Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
| 8 | * Copyright(c) 2015 Intel Corporation. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of version 2 of the GNU General Public License as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but |
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * General Public License for more details. |
| 18 | * |
| 19 | * BSD LICENSE |
| 20 | * |
| 21 | * Copyright(c) 2015 Intel Corporation. |
| 22 | * |
| 23 | * Redistribution and use in source and binary forms, with or without |
| 24 | * modification, are permitted provided that the following conditions |
| 25 | * are met: |
| 26 | * |
| 27 | * - Redistributions of source code must retain the above copyright |
| 28 | * notice, this list of conditions and the following disclaimer. |
| 29 | * - Redistributions in binary form must reproduce the above copyright |
| 30 | * notice, this list of conditions and the following disclaimer in |
| 31 | * the documentation and/or other materials provided with the |
| 32 | * distribution. |
| 33 | * - Neither the name of Intel Corporation nor the names of its |
| 34 | * contributors may be used to endorse or promote products derived |
| 35 | * from this software without specific prior written permission. |
| 36 | * |
| 37 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 38 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 39 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 40 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 41 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 42 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 43 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 44 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 45 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 46 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 48 | * |
| 49 | */ |
| 50 | |
| 51 | #include <linux/spinlock.h> |
| 52 | #include <linux/seqlock.h> |
| 53 | #include <linux/netdevice.h> |
| 54 | #include <linux/moduleparam.h> |
| 55 | #include <linux/bitops.h> |
| 56 | #include <linux/timer.h> |
| 57 | #include <linux/vmalloc.h> |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 58 | #include <linux/highmem.h> |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 59 | |
| 60 | #include "hfi.h" |
| 61 | #include "common.h" |
| 62 | #include "qp.h" |
| 63 | #include "sdma.h" |
| 64 | #include "iowait.h" |
| 65 | #include "trace.h" |
| 66 | |
| 67 | /* must be a power of 2 >= 64 <= 32768 */ |
Ignacio Hernandez | 028d725 | 2015-10-26 10:28:42 -0400 | [diff] [blame] | 68 | #define SDMA_DESCQ_CNT 2048 |
Mitko Haralanov | ee94785 | 2015-10-26 10:28:41 -0400 | [diff] [blame] | 69 | #define SDMA_DESC_INTR 64 |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 70 | #define INVALID_TAIL 0xffff |
| 71 | |
| 72 | static uint sdma_descq_cnt = SDMA_DESCQ_CNT; |
| 73 | module_param(sdma_descq_cnt, uint, S_IRUGO); |
| 74 | MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries"); |
| 75 | |
| 76 | static uint sdma_idle_cnt = 250; |
| 77 | module_param(sdma_idle_cnt, uint, S_IRUGO); |
| 78 | MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)"); |
| 79 | |
| 80 | uint mod_num_sdma; |
| 81 | module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO); |
| 82 | MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use"); |
| 83 | |
Mitko Haralanov | ee94785 | 2015-10-26 10:28:41 -0400 | [diff] [blame] | 84 | static uint sdma_desct_intr = SDMA_DESC_INTR; |
| 85 | module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR); |
| 86 | MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt"); |
| 87 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 88 | #define SDMA_WAIT_BATCH_SIZE 20 |
| 89 | /* max wait time for a SDMA engine to indicate it has halted */ |
| 90 | #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */ |
| 91 | /* all SDMA engine errors that cause a halt */ |
| 92 | |
| 93 | #define SD(name) SEND_DMA_##name |
| 94 | #define ALL_SDMA_ENG_HALT_ERRS \ |
| 95 | (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \ |
| 96 | | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \ |
| 97 | | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \ |
| 98 | | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \ |
| 99 | | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \ |
| 100 | | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \ |
| 101 | | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \ |
| 102 | | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \ |
| 103 | | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \ |
| 104 | | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \ |
| 105 | | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \ |
| 106 | | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \ |
| 107 | | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \ |
| 108 | | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \ |
| 109 | | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \ |
| 110 | | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \ |
| 111 | | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \ |
| 112 | | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK)) |
| 113 | |
| 114 | /* sdma_sendctrl operations */ |
jubin.john@intel.com | 349ac71 | 2016-01-11 18:30:52 -0500 | [diff] [blame] | 115 | #define SDMA_SENDCTRL_OP_ENABLE BIT(0) |
| 116 | #define SDMA_SENDCTRL_OP_INTENABLE BIT(1) |
| 117 | #define SDMA_SENDCTRL_OP_HALT BIT(2) |
| 118 | #define SDMA_SENDCTRL_OP_CLEANUP BIT(3) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 119 | |
| 120 | /* handle long defines */ |
| 121 | #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \ |
| 122 | SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK |
| 123 | #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \ |
| 124 | SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT |
| 125 | |
| 126 | static const char * const sdma_state_names[] = { |
| 127 | [sdma_state_s00_hw_down] = "s00_HwDown", |
| 128 | [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait", |
| 129 | [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait", |
| 130 | [sdma_state_s20_idle] = "s20_Idle", |
| 131 | [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait", |
| 132 | [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait", |
| 133 | [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait", |
| 134 | [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait", |
| 135 | [sdma_state_s80_hw_freeze] = "s80_HwFreeze", |
| 136 | [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean", |
| 137 | [sdma_state_s99_running] = "s99_Running", |
| 138 | }; |
| 139 | |
| 140 | static const char * const sdma_event_names[] = { |
| 141 | [sdma_event_e00_go_hw_down] = "e00_GoHwDown", |
| 142 | [sdma_event_e10_go_hw_start] = "e10_GoHwStart", |
| 143 | [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone", |
| 144 | [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone", |
| 145 | [sdma_event_e30_go_running] = "e30_GoRunning", |
| 146 | [sdma_event_e40_sw_cleaned] = "e40_SwCleaned", |
| 147 | [sdma_event_e50_hw_cleaned] = "e50_HwCleaned", |
| 148 | [sdma_event_e60_hw_halted] = "e60_HwHalted", |
| 149 | [sdma_event_e70_go_idle] = "e70_GoIdle", |
| 150 | [sdma_event_e80_hw_freeze] = "e80_HwFreeze", |
| 151 | [sdma_event_e81_hw_frozen] = "e81_HwFrozen", |
| 152 | [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze", |
| 153 | [sdma_event_e85_link_down] = "e85_LinkDown", |
| 154 | [sdma_event_e90_sw_halted] = "e90_SwHalted", |
| 155 | }; |
| 156 | |
| 157 | static const struct sdma_set_state_action sdma_action_table[] = { |
| 158 | [sdma_state_s00_hw_down] = { |
| 159 | .go_s99_running_tofalse = 1, |
| 160 | .op_enable = 0, |
| 161 | .op_intenable = 0, |
| 162 | .op_halt = 0, |
| 163 | .op_cleanup = 0, |
| 164 | }, |
| 165 | [sdma_state_s10_hw_start_up_halt_wait] = { |
| 166 | .op_enable = 0, |
| 167 | .op_intenable = 0, |
| 168 | .op_halt = 1, |
| 169 | .op_cleanup = 0, |
| 170 | }, |
| 171 | [sdma_state_s15_hw_start_up_clean_wait] = { |
| 172 | .op_enable = 0, |
| 173 | .op_intenable = 1, |
| 174 | .op_halt = 0, |
| 175 | .op_cleanup = 1, |
| 176 | }, |
| 177 | [sdma_state_s20_idle] = { |
| 178 | .op_enable = 0, |
| 179 | .op_intenable = 1, |
| 180 | .op_halt = 0, |
| 181 | .op_cleanup = 0, |
| 182 | }, |
| 183 | [sdma_state_s30_sw_clean_up_wait] = { |
| 184 | .op_enable = 0, |
| 185 | .op_intenable = 0, |
| 186 | .op_halt = 0, |
| 187 | .op_cleanup = 0, |
| 188 | }, |
| 189 | [sdma_state_s40_hw_clean_up_wait] = { |
| 190 | .op_enable = 0, |
| 191 | .op_intenable = 0, |
| 192 | .op_halt = 0, |
| 193 | .op_cleanup = 1, |
| 194 | }, |
| 195 | [sdma_state_s50_hw_halt_wait] = { |
| 196 | .op_enable = 0, |
| 197 | .op_intenable = 0, |
| 198 | .op_halt = 0, |
| 199 | .op_cleanup = 0, |
| 200 | }, |
| 201 | [sdma_state_s60_idle_halt_wait] = { |
| 202 | .go_s99_running_tofalse = 1, |
| 203 | .op_enable = 0, |
| 204 | .op_intenable = 0, |
| 205 | .op_halt = 1, |
| 206 | .op_cleanup = 0, |
| 207 | }, |
| 208 | [sdma_state_s80_hw_freeze] = { |
| 209 | .op_enable = 0, |
| 210 | .op_intenable = 0, |
| 211 | .op_halt = 0, |
| 212 | .op_cleanup = 0, |
| 213 | }, |
| 214 | [sdma_state_s82_freeze_sw_clean] = { |
| 215 | .op_enable = 0, |
| 216 | .op_intenable = 0, |
| 217 | .op_halt = 0, |
| 218 | .op_cleanup = 0, |
| 219 | }, |
| 220 | [sdma_state_s99_running] = { |
| 221 | .op_enable = 1, |
| 222 | .op_intenable = 1, |
| 223 | .op_halt = 0, |
| 224 | .op_cleanup = 0, |
| 225 | .go_s99_running_totrue = 1, |
| 226 | }, |
| 227 | }; |
| 228 | |
| 229 | #define SDMA_TAIL_UPDATE_THRESH 0x1F |
| 230 | |
| 231 | /* declare all statics here rather than keep sorting */ |
| 232 | static void sdma_complete(struct kref *); |
| 233 | static void sdma_finalput(struct sdma_state *); |
| 234 | static void sdma_get(struct sdma_state *); |
| 235 | static void sdma_hw_clean_up_task(unsigned long); |
| 236 | static void sdma_put(struct sdma_state *); |
| 237 | static void sdma_set_state(struct sdma_engine *, enum sdma_states); |
| 238 | static void sdma_start_hw_clean_up(struct sdma_engine *); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 239 | static void sdma_sw_clean_up_task(unsigned long); |
| 240 | static void sdma_sendctrl(struct sdma_engine *, unsigned); |
| 241 | static void init_sdma_regs(struct sdma_engine *, u32, uint); |
| 242 | static void sdma_process_event( |
| 243 | struct sdma_engine *sde, |
| 244 | enum sdma_events event); |
| 245 | static void __sdma_process_event( |
| 246 | struct sdma_engine *sde, |
| 247 | enum sdma_events event); |
| 248 | static void dump_sdma_state(struct sdma_engine *sde); |
| 249 | static void sdma_make_progress(struct sdma_engine *sde, u64 status); |
| 250 | static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail); |
| 251 | static void sdma_flush_descq(struct sdma_engine *sde); |
| 252 | |
| 253 | /** |
| 254 | * sdma_state_name() - return state string from enum |
| 255 | * @state: state |
| 256 | */ |
| 257 | static const char *sdma_state_name(enum sdma_states state) |
| 258 | { |
| 259 | return sdma_state_names[state]; |
| 260 | } |
| 261 | |
| 262 | static void sdma_get(struct sdma_state *ss) |
| 263 | { |
| 264 | kref_get(&ss->kref); |
| 265 | } |
| 266 | |
| 267 | static void sdma_complete(struct kref *kref) |
| 268 | { |
| 269 | struct sdma_state *ss = |
| 270 | container_of(kref, struct sdma_state, kref); |
| 271 | |
| 272 | complete(&ss->comp); |
| 273 | } |
| 274 | |
| 275 | static void sdma_put(struct sdma_state *ss) |
| 276 | { |
| 277 | kref_put(&ss->kref, sdma_complete); |
| 278 | } |
| 279 | |
| 280 | static void sdma_finalput(struct sdma_state *ss) |
| 281 | { |
| 282 | sdma_put(ss); |
| 283 | wait_for_completion(&ss->comp); |
| 284 | } |
| 285 | |
| 286 | static inline void write_sde_csr( |
| 287 | struct sdma_engine *sde, |
| 288 | u32 offset0, |
| 289 | u64 value) |
| 290 | { |
| 291 | write_kctxt_csr(sde->dd, sde->this_idx, offset0, value); |
| 292 | } |
| 293 | |
| 294 | static inline u64 read_sde_csr( |
| 295 | struct sdma_engine *sde, |
| 296 | u32 offset0) |
| 297 | { |
| 298 | return read_kctxt_csr(sde->dd, sde->this_idx, offset0); |
| 299 | } |
| 300 | |
| 301 | /* |
| 302 | * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for |
| 303 | * sdma engine 'sde' to drop to 0. |
| 304 | */ |
| 305 | static void sdma_wait_for_packet_egress(struct sdma_engine *sde, |
| 306 | int pause) |
| 307 | { |
| 308 | u64 off = 8 * sde->this_idx; |
| 309 | struct hfi1_devdata *dd = sde->dd; |
| 310 | int lcnt = 0; |
Vennila Megavannan | 25d97dd | 2015-10-26 10:28:30 -0400 | [diff] [blame] | 311 | u64 reg_prev; |
| 312 | u64 reg = 0; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 313 | |
| 314 | while (1) { |
Vennila Megavannan | 25d97dd | 2015-10-26 10:28:30 -0400 | [diff] [blame] | 315 | reg_prev = reg; |
| 316 | reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 317 | |
| 318 | reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK; |
| 319 | reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT; |
| 320 | if (reg == 0) |
| 321 | break; |
Vennila Megavannan | 25d97dd | 2015-10-26 10:28:30 -0400 | [diff] [blame] | 322 | /* counter is reest if accupancy count changes */ |
| 323 | if (reg != reg_prev) |
| 324 | lcnt = 0; |
| 325 | if (lcnt++ > 500) { |
| 326 | /* timed out - bounce the link */ |
| 327 | dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n", |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 328 | __func__, sde->this_idx, (u32)reg); |
Vennila Megavannan | 25d97dd | 2015-10-26 10:28:30 -0400 | [diff] [blame] | 329 | queue_work(dd->pport->hfi1_wq, |
| 330 | &dd->pport->link_bounce_work); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 331 | break; |
| 332 | } |
| 333 | udelay(1); |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | /* |
| 338 | * sdma_wait() - wait for packet egress to complete for all SDMA engines, |
| 339 | * and pause for credit return. |
| 340 | */ |
| 341 | void sdma_wait(struct hfi1_devdata *dd) |
| 342 | { |
| 343 | int i; |
| 344 | |
| 345 | for (i = 0; i < dd->num_sdma; i++) { |
| 346 | struct sdma_engine *sde = &dd->per_sdma[i]; |
| 347 | |
| 348 | sdma_wait_for_packet_egress(sde, 0); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt) |
| 353 | { |
| 354 | u64 reg; |
| 355 | |
| 356 | if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT)) |
| 357 | return; |
| 358 | reg = cnt; |
| 359 | reg &= SD(DESC_CNT_CNT_MASK); |
| 360 | reg <<= SD(DESC_CNT_CNT_SHIFT); |
| 361 | write_sde_csr(sde, SD(DESC_CNT), reg); |
| 362 | } |
| 363 | |
| 364 | /* |
| 365 | * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status |
| 366 | * |
| 367 | * Depending on timing there can be txreqs in two places: |
| 368 | * - in the descq ring |
| 369 | * - in the flush list |
| 370 | * |
| 371 | * To avoid ordering issues the descq ring needs to be flushed |
| 372 | * first followed by the flush list. |
| 373 | * |
| 374 | * This routine is called from two places |
| 375 | * - From a work queue item |
| 376 | * - Directly from the state machine just before setting the |
| 377 | * state to running |
| 378 | * |
| 379 | * Must be called with head_lock held |
| 380 | * |
| 381 | */ |
| 382 | static void sdma_flush(struct sdma_engine *sde) |
| 383 | { |
| 384 | struct sdma_txreq *txp, *txp_next; |
| 385 | LIST_HEAD(flushlist); |
Dean Luick | b77d713 | 2015-10-26 10:28:43 -0400 | [diff] [blame] | 386 | unsigned long flags; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 387 | |
| 388 | /* flush from head to tail */ |
| 389 | sdma_flush_descq(sde); |
Dean Luick | b77d713 | 2015-10-26 10:28:43 -0400 | [diff] [blame] | 390 | spin_lock_irqsave(&sde->flushlist_lock, flags); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 391 | /* copy flush list */ |
| 392 | list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) { |
| 393 | list_del_init(&txp->list); |
| 394 | list_add_tail(&txp->list, &flushlist); |
| 395 | } |
Dean Luick | b77d713 | 2015-10-26 10:28:43 -0400 | [diff] [blame] | 396 | spin_unlock_irqrestore(&sde->flushlist_lock, flags); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 397 | /* flush from flush list */ |
| 398 | list_for_each_entry_safe(txp, txp_next, &flushlist, list) { |
| 399 | int drained = 0; |
| 400 | /* protect against complete modifying */ |
| 401 | struct iowait *wait = txp->wait; |
| 402 | |
| 403 | list_del_init(&txp->list); |
| 404 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER |
| 405 | trace_hfi1_sdma_out_sn(sde, txp->sn); |
| 406 | if (WARN_ON_ONCE(sde->head_sn != txp->sn)) |
| 407 | dd_dev_err(sde->dd, "expected %llu got %llu\n", |
| 408 | sde->head_sn, txp->sn); |
| 409 | sde->head_sn++; |
| 410 | #endif |
| 411 | sdma_txclean(sde->dd, txp); |
| 412 | if (wait) |
| 413 | drained = atomic_dec_and_test(&wait->sdma_busy); |
| 414 | if (txp->complete) |
| 415 | (*txp->complete)(txp, SDMA_TXREQ_S_ABORTED, drained); |
| 416 | if (wait && drained) |
| 417 | iowait_drain_wakeup(wait); |
| 418 | } |
| 419 | } |
| 420 | |
| 421 | /* |
| 422 | * Fields a work request for flushing the descq ring |
| 423 | * and the flush list |
| 424 | * |
| 425 | * If the engine has been brought to running during |
| 426 | * the scheduling delay, the flush is ignored, assuming |
| 427 | * that the process of bringing the engine to running |
| 428 | * would have done this flush prior to going to running. |
| 429 | * |
| 430 | */ |
| 431 | static void sdma_field_flush(struct work_struct *work) |
| 432 | { |
| 433 | unsigned long flags; |
| 434 | struct sdma_engine *sde = |
| 435 | container_of(work, struct sdma_engine, flush_worker); |
| 436 | |
| 437 | write_seqlock_irqsave(&sde->head_lock, flags); |
| 438 | if (!__sdma_running(sde)) |
| 439 | sdma_flush(sde); |
| 440 | write_sequnlock_irqrestore(&sde->head_lock, flags); |
| 441 | } |
| 442 | |
| 443 | static void sdma_err_halt_wait(struct work_struct *work) |
| 444 | { |
| 445 | struct sdma_engine *sde = container_of(work, struct sdma_engine, |
| 446 | err_halt_worker); |
| 447 | u64 statuscsr; |
| 448 | unsigned long timeout; |
| 449 | |
| 450 | timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT); |
| 451 | while (1) { |
| 452 | statuscsr = read_sde_csr(sde, SD(STATUS)); |
| 453 | statuscsr &= SD(STATUS_ENG_HALTED_SMASK); |
| 454 | if (statuscsr) |
| 455 | break; |
| 456 | if (time_after(jiffies, timeout)) { |
| 457 | dd_dev_err(sde->dd, |
| 458 | "SDMA engine %d - timeout waiting for engine to halt\n", |
| 459 | sde->this_idx); |
| 460 | /* |
| 461 | * Continue anyway. This could happen if there was |
| 462 | * an uncorrectable error in the wrong spot. |
| 463 | */ |
| 464 | break; |
| 465 | } |
| 466 | usleep_range(80, 120); |
| 467 | } |
| 468 | |
| 469 | sdma_process_event(sde, sdma_event_e15_hw_halt_done); |
| 470 | } |
| 471 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 472 | static void sdma_err_progress_check_schedule(struct sdma_engine *sde) |
| 473 | { |
| 474 | if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) { |
| 475 | |
| 476 | unsigned index; |
| 477 | struct hfi1_devdata *dd = sde->dd; |
| 478 | |
| 479 | for (index = 0; index < dd->num_sdma; index++) { |
| 480 | struct sdma_engine *curr_sdma = &dd->per_sdma[index]; |
| 481 | |
| 482 | if (curr_sdma != sde) |
| 483 | curr_sdma->progress_check_head = |
| 484 | curr_sdma->descq_head; |
| 485 | } |
| 486 | dd_dev_err(sde->dd, |
| 487 | "SDMA engine %d - check scheduled\n", |
| 488 | sde->this_idx); |
| 489 | mod_timer(&sde->err_progress_check_timer, jiffies + 10); |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | static void sdma_err_progress_check(unsigned long data) |
| 494 | { |
| 495 | unsigned index; |
| 496 | struct sdma_engine *sde = (struct sdma_engine *)data; |
| 497 | |
| 498 | dd_dev_err(sde->dd, "SDE progress check event\n"); |
| 499 | for (index = 0; index < sde->dd->num_sdma; index++) { |
| 500 | struct sdma_engine *curr_sde = &sde->dd->per_sdma[index]; |
| 501 | unsigned long flags; |
| 502 | |
| 503 | /* check progress on each engine except the current one */ |
| 504 | if (curr_sde == sde) |
| 505 | continue; |
| 506 | /* |
| 507 | * We must lock interrupts when acquiring sde->lock, |
| 508 | * to avoid a deadlock if interrupt triggers and spins on |
| 509 | * the same lock on same CPU |
| 510 | */ |
| 511 | spin_lock_irqsave(&curr_sde->tail_lock, flags); |
| 512 | write_seqlock(&curr_sde->head_lock); |
| 513 | |
| 514 | /* skip non-running queues */ |
| 515 | if (curr_sde->state.current_state != sdma_state_s99_running) { |
| 516 | write_sequnlock(&curr_sde->head_lock); |
| 517 | spin_unlock_irqrestore(&curr_sde->tail_lock, flags); |
| 518 | continue; |
| 519 | } |
| 520 | |
| 521 | if ((curr_sde->descq_head != curr_sde->descq_tail) && |
| 522 | (curr_sde->descq_head == |
| 523 | curr_sde->progress_check_head)) |
| 524 | __sdma_process_event(curr_sde, |
| 525 | sdma_event_e90_sw_halted); |
| 526 | write_sequnlock(&curr_sde->head_lock); |
| 527 | spin_unlock_irqrestore(&curr_sde->tail_lock, flags); |
| 528 | } |
| 529 | schedule_work(&sde->err_halt_worker); |
| 530 | } |
| 531 | |
| 532 | static void sdma_hw_clean_up_task(unsigned long opaque) |
| 533 | { |
| 534 | struct sdma_engine *sde = (struct sdma_engine *) opaque; |
| 535 | u64 statuscsr; |
| 536 | |
| 537 | while (1) { |
| 538 | #ifdef CONFIG_SDMA_VERBOSITY |
| 539 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", |
| 540 | sde->this_idx, slashstrip(__FILE__), __LINE__, |
| 541 | __func__); |
| 542 | #endif |
| 543 | statuscsr = read_sde_csr(sde, SD(STATUS)); |
| 544 | statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK); |
| 545 | if (statuscsr) |
| 546 | break; |
| 547 | udelay(10); |
| 548 | } |
| 549 | |
| 550 | sdma_process_event(sde, sdma_event_e25_hw_clean_up_done); |
| 551 | } |
| 552 | |
| 553 | static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde) |
| 554 | { |
| 555 | smp_read_barrier_depends(); /* see sdma_update_tail() */ |
| 556 | return sde->tx_ring[sde->tx_head & sde->sdma_mask]; |
| 557 | } |
| 558 | |
| 559 | /* |
| 560 | * flush ring for recovery |
| 561 | */ |
| 562 | static void sdma_flush_descq(struct sdma_engine *sde) |
| 563 | { |
| 564 | u16 head, tail; |
| 565 | int progress = 0; |
| 566 | struct sdma_txreq *txp = get_txhead(sde); |
| 567 | |
| 568 | /* The reason for some of the complexity of this code is that |
| 569 | * not all descriptors have corresponding txps. So, we have to |
| 570 | * be able to skip over descs until we wander into the range of |
| 571 | * the next txp on the list. |
| 572 | */ |
| 573 | head = sde->descq_head & sde->sdma_mask; |
| 574 | tail = sde->descq_tail & sde->sdma_mask; |
| 575 | while (head != tail) { |
| 576 | /* advance head, wrap if needed */ |
| 577 | head = ++sde->descq_head & sde->sdma_mask; |
| 578 | /* if now past this txp's descs, do the callback */ |
| 579 | if (txp && txp->next_descq_idx == head) { |
| 580 | int drained = 0; |
| 581 | /* protect against complete modifying */ |
| 582 | struct iowait *wait = txp->wait; |
| 583 | |
| 584 | /* remove from list */ |
| 585 | sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; |
| 586 | if (wait) |
| 587 | drained = atomic_dec_and_test(&wait->sdma_busy); |
| 588 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER |
| 589 | trace_hfi1_sdma_out_sn(sde, txp->sn); |
| 590 | if (WARN_ON_ONCE(sde->head_sn != txp->sn)) |
| 591 | dd_dev_err(sde->dd, "expected %llu got %llu\n", |
| 592 | sde->head_sn, txp->sn); |
| 593 | sde->head_sn++; |
| 594 | #endif |
| 595 | sdma_txclean(sde->dd, txp); |
| 596 | trace_hfi1_sdma_progress(sde, head, tail, txp); |
| 597 | if (txp->complete) |
| 598 | (*txp->complete)( |
| 599 | txp, |
| 600 | SDMA_TXREQ_S_ABORTED, |
| 601 | drained); |
| 602 | if (wait && drained) |
| 603 | iowait_drain_wakeup(wait); |
| 604 | /* see if there is another txp */ |
| 605 | txp = get_txhead(sde); |
| 606 | } |
| 607 | progress++; |
| 608 | } |
| 609 | if (progress) |
| 610 | sdma_desc_avail(sde, sdma_descq_freecnt(sde)); |
| 611 | } |
| 612 | |
| 613 | static void sdma_sw_clean_up_task(unsigned long opaque) |
| 614 | { |
| 615 | struct sdma_engine *sde = (struct sdma_engine *) opaque; |
| 616 | unsigned long flags; |
| 617 | |
| 618 | spin_lock_irqsave(&sde->tail_lock, flags); |
| 619 | write_seqlock(&sde->head_lock); |
| 620 | |
| 621 | /* |
| 622 | * At this point, the following should always be true: |
| 623 | * - We are halted, so no more descriptors are getting retired. |
| 624 | * - We are not running, so no one is submitting new work. |
| 625 | * - Only we can send the e40_sw_cleaned, so we can't start |
| 626 | * running again until we say so. So, the active list and |
| 627 | * descq are ours to play with. |
| 628 | */ |
| 629 | |
| 630 | |
| 631 | /* |
| 632 | * In the error clean up sequence, software clean must be called |
| 633 | * before the hardware clean so we can use the hardware head in |
| 634 | * the progress routine. A hardware clean or SPC unfreeze will |
| 635 | * reset the hardware head. |
| 636 | * |
| 637 | * Process all retired requests. The progress routine will use the |
| 638 | * latest physical hardware head - we are not running so speed does |
| 639 | * not matter. |
| 640 | */ |
| 641 | sdma_make_progress(sde, 0); |
| 642 | |
| 643 | sdma_flush(sde); |
| 644 | |
| 645 | /* |
| 646 | * Reset our notion of head and tail. |
| 647 | * Note that the HW registers have been reset via an earlier |
| 648 | * clean up. |
| 649 | */ |
| 650 | sde->descq_tail = 0; |
| 651 | sde->descq_head = 0; |
| 652 | sde->desc_avail = sdma_descq_freecnt(sde); |
| 653 | *sde->head_dma = 0; |
| 654 | |
| 655 | __sdma_process_event(sde, sdma_event_e40_sw_cleaned); |
| 656 | |
| 657 | write_sequnlock(&sde->head_lock); |
| 658 | spin_unlock_irqrestore(&sde->tail_lock, flags); |
| 659 | } |
| 660 | |
| 661 | static void sdma_sw_tear_down(struct sdma_engine *sde) |
| 662 | { |
| 663 | struct sdma_state *ss = &sde->state; |
| 664 | |
| 665 | /* Releasing this reference means the state machine has stopped. */ |
| 666 | sdma_put(ss); |
| 667 | |
| 668 | /* stop waiting for all unfreeze events to complete */ |
| 669 | atomic_set(&sde->dd->sdma_unfreeze_count, -1); |
| 670 | wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); |
| 671 | } |
| 672 | |
| 673 | static void sdma_start_hw_clean_up(struct sdma_engine *sde) |
| 674 | { |
| 675 | tasklet_hi_schedule(&sde->sdma_hw_clean_up_task); |
| 676 | } |
| 677 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 678 | static void sdma_set_state(struct sdma_engine *sde, |
| 679 | enum sdma_states next_state) |
| 680 | { |
| 681 | struct sdma_state *ss = &sde->state; |
| 682 | const struct sdma_set_state_action *action = sdma_action_table; |
| 683 | unsigned op = 0; |
| 684 | |
| 685 | trace_hfi1_sdma_state( |
| 686 | sde, |
| 687 | sdma_state_names[ss->current_state], |
| 688 | sdma_state_names[next_state]); |
| 689 | |
| 690 | /* debugging bookkeeping */ |
| 691 | ss->previous_state = ss->current_state; |
| 692 | ss->previous_op = ss->current_op; |
| 693 | ss->current_state = next_state; |
| 694 | |
| 695 | if (ss->previous_state != sdma_state_s99_running |
| 696 | && next_state == sdma_state_s99_running) |
| 697 | sdma_flush(sde); |
| 698 | |
| 699 | if (action[next_state].op_enable) |
| 700 | op |= SDMA_SENDCTRL_OP_ENABLE; |
| 701 | |
| 702 | if (action[next_state].op_intenable) |
| 703 | op |= SDMA_SENDCTRL_OP_INTENABLE; |
| 704 | |
| 705 | if (action[next_state].op_halt) |
| 706 | op |= SDMA_SENDCTRL_OP_HALT; |
| 707 | |
| 708 | if (action[next_state].op_cleanup) |
| 709 | op |= SDMA_SENDCTRL_OP_CLEANUP; |
| 710 | |
| 711 | if (action[next_state].go_s99_running_tofalse) |
| 712 | ss->go_s99_running = 0; |
| 713 | |
| 714 | if (action[next_state].go_s99_running_totrue) |
| 715 | ss->go_s99_running = 1; |
| 716 | |
| 717 | ss->current_op = op; |
| 718 | sdma_sendctrl(sde, ss->current_op); |
| 719 | } |
| 720 | |
| 721 | /** |
| 722 | * sdma_get_descq_cnt() - called when device probed |
| 723 | * |
| 724 | * Return a validated descq count. |
| 725 | * |
| 726 | * This is currently only used in the verbs initialization to build the tx |
| 727 | * list. |
| 728 | * |
| 729 | * This will probably be deleted in favor of a more scalable approach to |
| 730 | * alloc tx's. |
| 731 | * |
| 732 | */ |
| 733 | u16 sdma_get_descq_cnt(void) |
| 734 | { |
| 735 | u16 count = sdma_descq_cnt; |
| 736 | |
| 737 | if (!count) |
| 738 | return SDMA_DESCQ_CNT; |
| 739 | /* count must be a power of 2 greater than 64 and less than |
| 740 | * 32768. Otherwise return default. |
| 741 | */ |
| 742 | if (!is_power_of_2(count)) |
| 743 | return SDMA_DESCQ_CNT; |
Mike Marciniszyn | aeef010 | 2015-09-15 10:19:27 -0400 | [diff] [blame] | 744 | if (count < 64 || count > 32768) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 745 | return SDMA_DESCQ_CNT; |
| 746 | return count; |
| 747 | } |
Geliang Tang | b91cc57 | 2015-09-21 23:39:08 +0800 | [diff] [blame] | 748 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 749 | /** |
| 750 | * sdma_select_engine_vl() - select sdma engine |
| 751 | * @dd: devdata |
| 752 | * @selector: a spreading factor |
| 753 | * @vl: this vl |
| 754 | * |
| 755 | * |
| 756 | * This function returns an engine based on the selector and a vl. The |
| 757 | * mapping fields are protected by RCU. |
| 758 | */ |
| 759 | struct sdma_engine *sdma_select_engine_vl( |
| 760 | struct hfi1_devdata *dd, |
| 761 | u32 selector, |
| 762 | u8 vl) |
| 763 | { |
| 764 | struct sdma_vl_map *m; |
| 765 | struct sdma_map_elem *e; |
| 766 | struct sdma_engine *rval; |
| 767 | |
Ira Weiny | 4be8199 | 2015-11-20 19:43:47 -0500 | [diff] [blame] | 768 | /* NOTE This should only happen if SC->VL changed after the initial |
| 769 | * checks on the QP/AH |
| 770 | * Default will return engine 0 below |
| 771 | */ |
| 772 | if (vl >= num_vls) { |
| 773 | rval = NULL; |
| 774 | goto done; |
| 775 | } |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 776 | |
| 777 | rcu_read_lock(); |
| 778 | m = rcu_dereference(dd->sdma_map); |
| 779 | if (unlikely(!m)) { |
| 780 | rcu_read_unlock(); |
Mike Marciniszyn | 0a226ed | 2015-11-09 19:13:58 -0500 | [diff] [blame] | 781 | return &dd->per_sdma[0]; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 782 | } |
| 783 | e = m->map[vl & m->mask]; |
| 784 | rval = e->sde[selector & e->mask]; |
| 785 | rcu_read_unlock(); |
| 786 | |
Ira Weiny | 4be8199 | 2015-11-20 19:43:47 -0500 | [diff] [blame] | 787 | done: |
Mike Marciniszyn | 0a226ed | 2015-11-09 19:13:58 -0500 | [diff] [blame] | 788 | rval = !rval ? &dd->per_sdma[0] : rval; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 789 | trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx); |
| 790 | return rval; |
| 791 | } |
| 792 | |
| 793 | /** |
| 794 | * sdma_select_engine_sc() - select sdma engine |
| 795 | * @dd: devdata |
| 796 | * @selector: a spreading factor |
| 797 | * @sc5: the 5 bit sc |
| 798 | * |
| 799 | * |
| 800 | * This function returns an engine based on the selector and an sc. |
| 801 | */ |
| 802 | struct sdma_engine *sdma_select_engine_sc( |
| 803 | struct hfi1_devdata *dd, |
| 804 | u32 selector, |
| 805 | u8 sc5) |
| 806 | { |
| 807 | u8 vl = sc_to_vlt(dd, sc5); |
| 808 | |
| 809 | return sdma_select_engine_vl(dd, selector, vl); |
| 810 | } |
| 811 | |
| 812 | /* |
| 813 | * Free the indicated map struct |
| 814 | */ |
| 815 | static void sdma_map_free(struct sdma_vl_map *m) |
| 816 | { |
| 817 | int i; |
| 818 | |
| 819 | for (i = 0; m && i < m->actual_vls; i++) |
| 820 | kfree(m->map[i]); |
| 821 | kfree(m); |
| 822 | } |
| 823 | |
| 824 | /* |
| 825 | * Handle RCU callback |
| 826 | */ |
| 827 | static void sdma_map_rcu_callback(struct rcu_head *list) |
| 828 | { |
| 829 | struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list); |
| 830 | |
| 831 | sdma_map_free(m); |
| 832 | } |
| 833 | |
| 834 | /** |
| 835 | * sdma_map_init - called when # vls change |
| 836 | * @dd: hfi1_devdata |
| 837 | * @port: port number |
| 838 | * @num_vls: number of vls |
| 839 | * @vl_engines: per vl engine mapping (optional) |
| 840 | * |
| 841 | * This routine changes the mapping based on the number of vls. |
| 842 | * |
| 843 | * vl_engines is used to specify a non-uniform vl/engine loading. NULL |
| 844 | * implies auto computing the loading and giving each VLs a uniform |
| 845 | * distribution of engines per VL. |
| 846 | * |
| 847 | * The auto algorithm computes the sde_per_vl and the number of extra |
| 848 | * engines. Any extra engines are added from the last VL on down. |
| 849 | * |
| 850 | * rcu locking is used here to control access to the mapping fields. |
| 851 | * |
| 852 | * If either the num_vls or num_sdma are non-power of 2, the array sizes |
| 853 | * in the struct sdma_vl_map and the struct sdma_map_elem are rounded |
| 854 | * up to the next highest power of 2 and the first entry is reused |
| 855 | * in a round robin fashion. |
| 856 | * |
| 857 | * If an error occurs the map change is not done and the mapping is |
| 858 | * not changed. |
| 859 | * |
| 860 | */ |
| 861 | int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines) |
| 862 | { |
| 863 | int i, j; |
| 864 | int extra, sde_per_vl; |
| 865 | int engine = 0; |
| 866 | u8 lvl_engines[OPA_MAX_VLS]; |
| 867 | struct sdma_vl_map *oldmap, *newmap; |
| 868 | |
| 869 | if (!(dd->flags & HFI1_HAS_SEND_DMA)) |
| 870 | return 0; |
| 871 | |
| 872 | if (!vl_engines) { |
| 873 | /* truncate divide */ |
| 874 | sde_per_vl = dd->num_sdma / num_vls; |
| 875 | /* extras */ |
| 876 | extra = dd->num_sdma % num_vls; |
| 877 | vl_engines = lvl_engines; |
| 878 | /* add extras from last vl down */ |
| 879 | for (i = num_vls - 1; i >= 0; i--, extra--) |
| 880 | vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0); |
| 881 | } |
| 882 | /* build new map */ |
| 883 | newmap = kzalloc( |
| 884 | sizeof(struct sdma_vl_map) + |
| 885 | roundup_pow_of_two(num_vls) * |
| 886 | sizeof(struct sdma_map_elem *), |
| 887 | GFP_KERNEL); |
| 888 | if (!newmap) |
| 889 | goto bail; |
| 890 | newmap->actual_vls = num_vls; |
| 891 | newmap->vls = roundup_pow_of_two(num_vls); |
| 892 | newmap->mask = (1 << ilog2(newmap->vls)) - 1; |
| 893 | for (i = 0; i < newmap->vls; i++) { |
| 894 | /* save for wrap around */ |
| 895 | int first_engine = engine; |
| 896 | |
| 897 | if (i < newmap->actual_vls) { |
| 898 | int sz = roundup_pow_of_two(vl_engines[i]); |
| 899 | |
| 900 | /* only allocate once */ |
| 901 | newmap->map[i] = kzalloc( |
| 902 | sizeof(struct sdma_map_elem) + |
| 903 | sz * sizeof(struct sdma_engine *), |
| 904 | GFP_KERNEL); |
| 905 | if (!newmap->map[i]) |
| 906 | goto bail; |
| 907 | newmap->map[i]->mask = (1 << ilog2(sz)) - 1; |
| 908 | /* assign engines */ |
| 909 | for (j = 0; j < sz; j++) { |
| 910 | newmap->map[i]->sde[j] = |
| 911 | &dd->per_sdma[engine]; |
| 912 | if (++engine >= first_engine + vl_engines[i]) |
| 913 | /* wrap back to first engine */ |
| 914 | engine = first_engine; |
| 915 | } |
| 916 | } else { |
| 917 | /* just re-use entry without allocating */ |
| 918 | newmap->map[i] = newmap->map[i % num_vls]; |
| 919 | } |
| 920 | engine = first_engine + vl_engines[i]; |
| 921 | } |
| 922 | /* newmap in hand, save old map */ |
| 923 | spin_lock_irq(&dd->sde_map_lock); |
| 924 | oldmap = rcu_dereference_protected(dd->sdma_map, |
| 925 | lockdep_is_held(&dd->sde_map_lock)); |
| 926 | |
| 927 | /* publish newmap */ |
| 928 | rcu_assign_pointer(dd->sdma_map, newmap); |
| 929 | |
| 930 | spin_unlock_irq(&dd->sde_map_lock); |
| 931 | /* success, free any old map after grace period */ |
| 932 | if (oldmap) |
| 933 | call_rcu(&oldmap->list, sdma_map_rcu_callback); |
| 934 | return 0; |
| 935 | bail: |
| 936 | /* free any partial allocation */ |
| 937 | sdma_map_free(newmap); |
| 938 | return -ENOMEM; |
| 939 | } |
| 940 | |
| 941 | /* |
| 942 | * Clean up allocated memory. |
| 943 | * |
| 944 | * This routine is can be called regardless of the success of sdma_init() |
| 945 | * |
| 946 | */ |
| 947 | static void sdma_clean(struct hfi1_devdata *dd, size_t num_engines) |
| 948 | { |
| 949 | size_t i; |
| 950 | struct sdma_engine *sde; |
| 951 | |
| 952 | if (dd->sdma_pad_dma) { |
| 953 | dma_free_coherent(&dd->pcidev->dev, 4, |
| 954 | (void *)dd->sdma_pad_dma, |
| 955 | dd->sdma_pad_phys); |
| 956 | dd->sdma_pad_dma = NULL; |
| 957 | dd->sdma_pad_phys = 0; |
| 958 | } |
| 959 | if (dd->sdma_heads_dma) { |
| 960 | dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size, |
| 961 | (void *)dd->sdma_heads_dma, |
| 962 | dd->sdma_heads_phys); |
| 963 | dd->sdma_heads_dma = NULL; |
| 964 | dd->sdma_heads_phys = 0; |
| 965 | } |
| 966 | for (i = 0; dd->per_sdma && i < num_engines; ++i) { |
| 967 | sde = &dd->per_sdma[i]; |
| 968 | |
| 969 | sde->head_dma = NULL; |
| 970 | sde->head_phys = 0; |
| 971 | |
| 972 | if (sde->descq) { |
| 973 | dma_free_coherent( |
| 974 | &dd->pcidev->dev, |
| 975 | sde->descq_cnt * sizeof(u64[2]), |
| 976 | sde->descq, |
| 977 | sde->descq_phys |
| 978 | ); |
| 979 | sde->descq = NULL; |
| 980 | sde->descq_phys = 0; |
| 981 | } |
Geliang Tang | 60f57ec | 2015-09-21 04:43:05 -0700 | [diff] [blame] | 982 | kvfree(sde->tx_ring); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 983 | sde->tx_ring = NULL; |
| 984 | } |
| 985 | spin_lock_irq(&dd->sde_map_lock); |
| 986 | kfree(rcu_access_pointer(dd->sdma_map)); |
| 987 | RCU_INIT_POINTER(dd->sdma_map, NULL); |
| 988 | spin_unlock_irq(&dd->sde_map_lock); |
| 989 | synchronize_rcu(); |
| 990 | kfree(dd->per_sdma); |
| 991 | dd->per_sdma = NULL; |
| 992 | } |
| 993 | |
| 994 | /** |
| 995 | * sdma_init() - called when device probed |
| 996 | * @dd: hfi1_devdata |
| 997 | * @port: port number (currently only zero) |
| 998 | * |
| 999 | * sdma_init initializes the specified number of engines. |
| 1000 | * |
| 1001 | * The code initializes each sde, its csrs. Interrupts |
| 1002 | * are not required to be enabled. |
| 1003 | * |
| 1004 | * Returns: |
| 1005 | * 0 - success, -errno on failure |
| 1006 | */ |
| 1007 | int sdma_init(struct hfi1_devdata *dd, u8 port) |
| 1008 | { |
| 1009 | unsigned this_idx; |
| 1010 | struct sdma_engine *sde; |
| 1011 | u16 descq_cnt; |
| 1012 | void *curr_head; |
| 1013 | struct hfi1_pportdata *ppd = dd->pport + port; |
| 1014 | u32 per_sdma_credits; |
| 1015 | uint idle_cnt = sdma_idle_cnt; |
| 1016 | size_t num_engines = dd->chip_sdma_engines; |
| 1017 | |
| 1018 | if (!HFI1_CAP_IS_KSET(SDMA)) { |
| 1019 | HFI1_CAP_CLEAR(SDMA_AHG); |
| 1020 | return 0; |
| 1021 | } |
| 1022 | if (mod_num_sdma && |
| 1023 | /* can't exceed chip support */ |
| 1024 | mod_num_sdma <= dd->chip_sdma_engines && |
| 1025 | /* count must be >= vls */ |
| 1026 | mod_num_sdma >= num_vls) |
| 1027 | num_engines = mod_num_sdma; |
| 1028 | |
| 1029 | dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma); |
| 1030 | dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines); |
| 1031 | dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n", |
| 1032 | dd->chip_sdma_mem_size); |
| 1033 | |
| 1034 | per_sdma_credits = |
| 1035 | dd->chip_sdma_mem_size/(num_engines * SDMA_BLOCK_SIZE); |
| 1036 | |
| 1037 | /* set up freeze waitqueue */ |
| 1038 | init_waitqueue_head(&dd->sdma_unfreeze_wq); |
| 1039 | atomic_set(&dd->sdma_unfreeze_count, 0); |
| 1040 | |
| 1041 | descq_cnt = sdma_get_descq_cnt(); |
| 1042 | dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n", |
| 1043 | num_engines, descq_cnt); |
| 1044 | |
| 1045 | /* alloc memory for array of send engines */ |
| 1046 | dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL); |
| 1047 | if (!dd->per_sdma) |
| 1048 | return -ENOMEM; |
| 1049 | |
| 1050 | idle_cnt = ns_to_cclock(dd, idle_cnt); |
Mitko Haralanov | ee94785 | 2015-10-26 10:28:41 -0400 | [diff] [blame] | 1051 | if (!sdma_desct_intr) |
| 1052 | sdma_desct_intr = SDMA_DESC_INTR; |
| 1053 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1054 | /* Allocate memory for SendDMA descriptor FIFOs */ |
| 1055 | for (this_idx = 0; this_idx < num_engines; ++this_idx) { |
| 1056 | sde = &dd->per_sdma[this_idx]; |
| 1057 | sde->dd = dd; |
| 1058 | sde->ppd = ppd; |
| 1059 | sde->this_idx = this_idx; |
| 1060 | sde->descq_cnt = descq_cnt; |
| 1061 | sde->desc_avail = sdma_descq_freecnt(sde); |
| 1062 | sde->sdma_shift = ilog2(descq_cnt); |
| 1063 | sde->sdma_mask = (1 << sde->sdma_shift) - 1; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1064 | |
Vennila Megavannan | a699c6c | 2016-01-11 18:30:56 -0500 | [diff] [blame] | 1065 | /* Create a mask specifically for each interrupt source */ |
| 1066 | sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES + |
| 1067 | this_idx); |
| 1068 | sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES + |
| 1069 | this_idx); |
| 1070 | sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES + |
| 1071 | this_idx); |
| 1072 | /* Create a combined mask to cover all 3 interrupt sources */ |
| 1073 | sde->imask = sde->int_mask | sde->progress_mask | |
| 1074 | sde->idle_mask; |
| 1075 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1076 | spin_lock_init(&sde->tail_lock); |
| 1077 | seqlock_init(&sde->head_lock); |
| 1078 | spin_lock_init(&sde->senddmactrl_lock); |
| 1079 | spin_lock_init(&sde->flushlist_lock); |
| 1080 | /* insure there is always a zero bit */ |
| 1081 | sde->ahg_bits = 0xfffffffe00000000ULL; |
| 1082 | |
| 1083 | sdma_set_state(sde, sdma_state_s00_hw_down); |
| 1084 | |
| 1085 | /* set up reference counting */ |
| 1086 | kref_init(&sde->state.kref); |
| 1087 | init_completion(&sde->state.comp); |
| 1088 | |
| 1089 | INIT_LIST_HEAD(&sde->flushlist); |
| 1090 | INIT_LIST_HEAD(&sde->dmawait); |
| 1091 | |
| 1092 | sde->tail_csr = |
| 1093 | get_kctxt_csr_addr(dd, this_idx, SD(TAIL)); |
| 1094 | |
| 1095 | if (idle_cnt) |
| 1096 | dd->default_desc1 = |
| 1097 | SDMA_DESC1_HEAD_TO_HOST_FLAG; |
| 1098 | else |
| 1099 | dd->default_desc1 = |
| 1100 | SDMA_DESC1_INT_REQ_FLAG; |
| 1101 | |
| 1102 | tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task, |
| 1103 | (unsigned long)sde); |
| 1104 | |
| 1105 | tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task, |
| 1106 | (unsigned long)sde); |
| 1107 | INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait); |
| 1108 | INIT_WORK(&sde->flush_worker, sdma_field_flush); |
| 1109 | |
| 1110 | sde->progress_check_head = 0; |
| 1111 | |
Muhammad Falak R Wani | daac731 | 2015-10-25 16:13:25 +0530 | [diff] [blame] | 1112 | setup_timer(&sde->err_progress_check_timer, |
| 1113 | sdma_err_progress_check, (unsigned long)sde); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1114 | |
| 1115 | sde->descq = dma_zalloc_coherent( |
| 1116 | &dd->pcidev->dev, |
| 1117 | descq_cnt * sizeof(u64[2]), |
| 1118 | &sde->descq_phys, |
| 1119 | GFP_KERNEL |
| 1120 | ); |
| 1121 | if (!sde->descq) |
| 1122 | goto bail; |
| 1123 | sde->tx_ring = |
| 1124 | kcalloc(descq_cnt, sizeof(struct sdma_txreq *), |
| 1125 | GFP_KERNEL); |
| 1126 | if (!sde->tx_ring) |
| 1127 | sde->tx_ring = |
| 1128 | vzalloc( |
| 1129 | sizeof(struct sdma_txreq *) * |
| 1130 | descq_cnt); |
| 1131 | if (!sde->tx_ring) |
| 1132 | goto bail; |
| 1133 | } |
| 1134 | |
| 1135 | dd->sdma_heads_size = L1_CACHE_BYTES * num_engines; |
| 1136 | /* Allocate memory for DMA of head registers to memory */ |
| 1137 | dd->sdma_heads_dma = dma_zalloc_coherent( |
| 1138 | &dd->pcidev->dev, |
| 1139 | dd->sdma_heads_size, |
| 1140 | &dd->sdma_heads_phys, |
| 1141 | GFP_KERNEL |
| 1142 | ); |
| 1143 | if (!dd->sdma_heads_dma) { |
| 1144 | dd_dev_err(dd, "failed to allocate SendDMA head memory\n"); |
| 1145 | goto bail; |
| 1146 | } |
| 1147 | |
| 1148 | /* Allocate memory for pad */ |
| 1149 | dd->sdma_pad_dma = dma_zalloc_coherent( |
| 1150 | &dd->pcidev->dev, |
| 1151 | sizeof(u32), |
| 1152 | &dd->sdma_pad_phys, |
| 1153 | GFP_KERNEL |
| 1154 | ); |
| 1155 | if (!dd->sdma_pad_dma) { |
| 1156 | dd_dev_err(dd, "failed to allocate SendDMA pad memory\n"); |
| 1157 | goto bail; |
| 1158 | } |
| 1159 | |
| 1160 | /* assign each engine to different cacheline and init registers */ |
| 1161 | curr_head = (void *)dd->sdma_heads_dma; |
| 1162 | for (this_idx = 0; this_idx < num_engines; ++this_idx) { |
| 1163 | unsigned long phys_offset; |
| 1164 | |
| 1165 | sde = &dd->per_sdma[this_idx]; |
| 1166 | |
| 1167 | sde->head_dma = curr_head; |
| 1168 | curr_head += L1_CACHE_BYTES; |
| 1169 | phys_offset = (unsigned long)sde->head_dma - |
| 1170 | (unsigned long)dd->sdma_heads_dma; |
| 1171 | sde->head_phys = dd->sdma_heads_phys + phys_offset; |
| 1172 | init_sdma_regs(sde, per_sdma_credits, idle_cnt); |
| 1173 | } |
| 1174 | dd->flags |= HFI1_HAS_SEND_DMA; |
| 1175 | dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0; |
| 1176 | dd->num_sdma = num_engines; |
| 1177 | if (sdma_map_init(dd, port, ppd->vls_operational, NULL)) |
| 1178 | goto bail; |
| 1179 | dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma); |
| 1180 | return 0; |
| 1181 | |
| 1182 | bail: |
| 1183 | sdma_clean(dd, num_engines); |
| 1184 | return -ENOMEM; |
| 1185 | } |
| 1186 | |
| 1187 | /** |
| 1188 | * sdma_all_running() - called when the link goes up |
| 1189 | * @dd: hfi1_devdata |
| 1190 | * |
| 1191 | * This routine moves all engines to the running state. |
| 1192 | */ |
| 1193 | void sdma_all_running(struct hfi1_devdata *dd) |
| 1194 | { |
| 1195 | struct sdma_engine *sde; |
| 1196 | unsigned int i; |
| 1197 | |
| 1198 | /* move all engines to running */ |
| 1199 | for (i = 0; i < dd->num_sdma; ++i) { |
| 1200 | sde = &dd->per_sdma[i]; |
| 1201 | sdma_process_event(sde, sdma_event_e30_go_running); |
| 1202 | } |
| 1203 | } |
| 1204 | |
| 1205 | /** |
| 1206 | * sdma_all_idle() - called when the link goes down |
| 1207 | * @dd: hfi1_devdata |
| 1208 | * |
| 1209 | * This routine moves all engines to the idle state. |
| 1210 | */ |
| 1211 | void sdma_all_idle(struct hfi1_devdata *dd) |
| 1212 | { |
| 1213 | struct sdma_engine *sde; |
| 1214 | unsigned int i; |
| 1215 | |
| 1216 | /* idle all engines */ |
| 1217 | for (i = 0; i < dd->num_sdma; ++i) { |
| 1218 | sde = &dd->per_sdma[i]; |
| 1219 | sdma_process_event(sde, sdma_event_e70_go_idle); |
| 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | /** |
| 1224 | * sdma_start() - called to kick off state processing for all engines |
| 1225 | * @dd: hfi1_devdata |
| 1226 | * |
| 1227 | * This routine is for kicking off the state processing for all required |
| 1228 | * sdma engines. Interrupts need to be working at this point. |
| 1229 | * |
| 1230 | */ |
| 1231 | void sdma_start(struct hfi1_devdata *dd) |
| 1232 | { |
| 1233 | unsigned i; |
| 1234 | struct sdma_engine *sde; |
| 1235 | |
| 1236 | /* kick off the engines state processing */ |
| 1237 | for (i = 0; i < dd->num_sdma; ++i) { |
| 1238 | sde = &dd->per_sdma[i]; |
| 1239 | sdma_process_event(sde, sdma_event_e10_go_hw_start); |
| 1240 | } |
| 1241 | } |
| 1242 | |
| 1243 | /** |
| 1244 | * sdma_exit() - used when module is removed |
| 1245 | * @dd: hfi1_devdata |
| 1246 | */ |
| 1247 | void sdma_exit(struct hfi1_devdata *dd) |
| 1248 | { |
| 1249 | unsigned this_idx; |
| 1250 | struct sdma_engine *sde; |
| 1251 | |
| 1252 | for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma; |
| 1253 | ++this_idx) { |
| 1254 | |
| 1255 | sde = &dd->per_sdma[this_idx]; |
| 1256 | if (!list_empty(&sde->dmawait)) |
| 1257 | dd_dev_err(dd, "sde %u: dmawait list not empty!\n", |
| 1258 | sde->this_idx); |
| 1259 | sdma_process_event(sde, sdma_event_e00_go_hw_down); |
| 1260 | |
| 1261 | del_timer_sync(&sde->err_progress_check_timer); |
| 1262 | |
| 1263 | /* |
| 1264 | * This waits for the state machine to exit so it is not |
| 1265 | * necessary to kill the sdma_sw_clean_up_task to make sure |
| 1266 | * it is not running. |
| 1267 | */ |
| 1268 | sdma_finalput(&sde->state); |
| 1269 | } |
| 1270 | sdma_clean(dd, dd->num_sdma); |
| 1271 | } |
| 1272 | |
| 1273 | /* |
| 1274 | * unmap the indicated descriptor |
| 1275 | */ |
| 1276 | static inline void sdma_unmap_desc( |
| 1277 | struct hfi1_devdata *dd, |
| 1278 | struct sdma_desc *descp) |
| 1279 | { |
| 1280 | switch (sdma_mapping_type(descp)) { |
| 1281 | case SDMA_MAP_SINGLE: |
| 1282 | dma_unmap_single( |
| 1283 | &dd->pcidev->dev, |
| 1284 | sdma_mapping_addr(descp), |
| 1285 | sdma_mapping_len(descp), |
| 1286 | DMA_TO_DEVICE); |
| 1287 | break; |
| 1288 | case SDMA_MAP_PAGE: |
| 1289 | dma_unmap_page( |
| 1290 | &dd->pcidev->dev, |
| 1291 | sdma_mapping_addr(descp), |
| 1292 | sdma_mapping_len(descp), |
| 1293 | DMA_TO_DEVICE); |
| 1294 | break; |
| 1295 | } |
| 1296 | } |
| 1297 | |
| 1298 | /* |
| 1299 | * return the mode as indicated by the first |
| 1300 | * descriptor in the tx. |
| 1301 | */ |
| 1302 | static inline u8 ahg_mode(struct sdma_txreq *tx) |
| 1303 | { |
| 1304 | return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK) |
| 1305 | >> SDMA_DESC1_HEADER_MODE_SHIFT; |
| 1306 | } |
| 1307 | |
| 1308 | /** |
| 1309 | * sdma_txclean() - clean tx of mappings, descp *kmalloc's |
| 1310 | * @dd: hfi1_devdata for unmapping |
| 1311 | * @tx: tx request to clean |
| 1312 | * |
| 1313 | * This is used in the progress routine to clean the tx or |
| 1314 | * by the ULP to toss an in-process tx build. |
| 1315 | * |
| 1316 | * The code can be called multiple times without issue. |
| 1317 | * |
| 1318 | */ |
| 1319 | void sdma_txclean( |
| 1320 | struct hfi1_devdata *dd, |
| 1321 | struct sdma_txreq *tx) |
| 1322 | { |
| 1323 | u16 i; |
| 1324 | |
| 1325 | if (tx->num_desc) { |
| 1326 | u8 skip = 0, mode = ahg_mode(tx); |
| 1327 | |
| 1328 | /* unmap first */ |
| 1329 | sdma_unmap_desc(dd, &tx->descp[0]); |
| 1330 | /* determine number of AHG descriptors to skip */ |
| 1331 | if (mode > SDMA_AHG_APPLY_UPDATE1) |
| 1332 | skip = mode >> 1; |
| 1333 | for (i = 1 + skip; i < tx->num_desc; i++) |
| 1334 | sdma_unmap_desc(dd, &tx->descp[i]); |
| 1335 | tx->num_desc = 0; |
| 1336 | } |
| 1337 | kfree(tx->coalesce_buf); |
| 1338 | tx->coalesce_buf = NULL; |
| 1339 | /* kmalloc'ed descp */ |
| 1340 | if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) { |
| 1341 | tx->desc_limit = ARRAY_SIZE(tx->descs); |
| 1342 | kfree(tx->descp); |
| 1343 | } |
| 1344 | } |
| 1345 | |
| 1346 | static inline u16 sdma_gethead(struct sdma_engine *sde) |
| 1347 | { |
| 1348 | struct hfi1_devdata *dd = sde->dd; |
| 1349 | int use_dmahead; |
| 1350 | u16 hwhead; |
| 1351 | |
| 1352 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1353 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", |
| 1354 | sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); |
| 1355 | #endif |
| 1356 | |
| 1357 | retry: |
| 1358 | use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) && |
| 1359 | (dd->flags & HFI1_HAS_SDMA_TIMEOUT); |
| 1360 | hwhead = use_dmahead ? |
| 1361 | (u16) le64_to_cpu(*sde->head_dma) : |
| 1362 | (u16) read_sde_csr(sde, SD(HEAD)); |
| 1363 | |
| 1364 | if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) { |
| 1365 | u16 cnt; |
| 1366 | u16 swtail; |
| 1367 | u16 swhead; |
| 1368 | int sane; |
| 1369 | |
| 1370 | swhead = sde->descq_head & sde->sdma_mask; |
| 1371 | /* this code is really bad for cache line trading */ |
| 1372 | swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask; |
| 1373 | cnt = sde->descq_cnt; |
| 1374 | |
| 1375 | if (swhead < swtail) |
| 1376 | /* not wrapped */ |
| 1377 | sane = (hwhead >= swhead) & (hwhead <= swtail); |
| 1378 | else if (swhead > swtail) |
| 1379 | /* wrapped around */ |
| 1380 | sane = ((hwhead >= swhead) && (hwhead < cnt)) || |
| 1381 | (hwhead <= swtail); |
| 1382 | else |
| 1383 | /* empty */ |
| 1384 | sane = (hwhead == swhead); |
| 1385 | |
| 1386 | if (unlikely(!sane)) { |
| 1387 | dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n", |
| 1388 | sde->this_idx, |
| 1389 | use_dmahead ? "dma" : "kreg", |
| 1390 | hwhead, swhead, swtail, cnt); |
| 1391 | if (use_dmahead) { |
| 1392 | /* try one more time, using csr */ |
| 1393 | use_dmahead = 0; |
| 1394 | goto retry; |
| 1395 | } |
| 1396 | /* proceed as if no progress */ |
| 1397 | hwhead = swhead; |
| 1398 | } |
| 1399 | } |
| 1400 | return hwhead; |
| 1401 | } |
| 1402 | |
| 1403 | /* |
| 1404 | * This is called when there are send DMA descriptors that might be |
| 1405 | * available. |
| 1406 | * |
| 1407 | * This is called with head_lock held. |
| 1408 | */ |
| 1409 | static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail) |
| 1410 | { |
| 1411 | struct iowait *wait, *nw; |
| 1412 | struct iowait *waits[SDMA_WAIT_BATCH_SIZE]; |
| 1413 | unsigned i, n = 0, seq; |
| 1414 | struct sdma_txreq *stx; |
| 1415 | struct hfi1_ibdev *dev = &sde->dd->verbs_dev; |
| 1416 | |
| 1417 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1418 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx, |
| 1419 | slashstrip(__FILE__), __LINE__, __func__); |
| 1420 | dd_dev_err(sde->dd, "avail: %u\n", avail); |
| 1421 | #endif |
| 1422 | |
| 1423 | do { |
| 1424 | seq = read_seqbegin(&dev->iowait_lock); |
| 1425 | if (!list_empty(&sde->dmawait)) { |
| 1426 | /* at least one item */ |
| 1427 | write_seqlock(&dev->iowait_lock); |
| 1428 | /* Harvest waiters wanting DMA descriptors */ |
| 1429 | list_for_each_entry_safe( |
| 1430 | wait, |
| 1431 | nw, |
| 1432 | &sde->dmawait, |
| 1433 | list) { |
| 1434 | u16 num_desc = 0; |
| 1435 | |
| 1436 | if (!wait->wakeup) |
| 1437 | continue; |
| 1438 | if (n == ARRAY_SIZE(waits)) |
| 1439 | break; |
| 1440 | if (!list_empty(&wait->tx_head)) { |
| 1441 | stx = list_first_entry( |
| 1442 | &wait->tx_head, |
| 1443 | struct sdma_txreq, |
| 1444 | list); |
| 1445 | num_desc = stx->num_desc; |
| 1446 | } |
| 1447 | if (num_desc > avail) |
| 1448 | break; |
| 1449 | avail -= num_desc; |
| 1450 | list_del_init(&wait->list); |
| 1451 | waits[n++] = wait; |
| 1452 | } |
| 1453 | write_sequnlock(&dev->iowait_lock); |
| 1454 | break; |
| 1455 | } |
| 1456 | } while (read_seqretry(&dev->iowait_lock, seq)); |
| 1457 | |
| 1458 | for (i = 0; i < n; i++) |
| 1459 | waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON); |
| 1460 | } |
| 1461 | |
| 1462 | /* head_lock must be held */ |
| 1463 | static void sdma_make_progress(struct sdma_engine *sde, u64 status) |
| 1464 | { |
| 1465 | struct sdma_txreq *txp = NULL; |
| 1466 | int progress = 0; |
| 1467 | u16 hwhead, swhead, swtail; |
| 1468 | int idle_check_done = 0; |
| 1469 | |
| 1470 | hwhead = sdma_gethead(sde); |
| 1471 | |
| 1472 | /* The reason for some of the complexity of this code is that |
| 1473 | * not all descriptors have corresponding txps. So, we have to |
| 1474 | * be able to skip over descs until we wander into the range of |
| 1475 | * the next txp on the list. |
| 1476 | */ |
| 1477 | |
| 1478 | retry: |
| 1479 | txp = get_txhead(sde); |
| 1480 | swhead = sde->descq_head & sde->sdma_mask; |
| 1481 | trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); |
| 1482 | while (swhead != hwhead) { |
| 1483 | /* advance head, wrap if needed */ |
| 1484 | swhead = ++sde->descq_head & sde->sdma_mask; |
| 1485 | |
| 1486 | /* if now past this txp's descs, do the callback */ |
| 1487 | if (txp && txp->next_descq_idx == swhead) { |
| 1488 | int drained = 0; |
| 1489 | /* protect against complete modifying */ |
| 1490 | struct iowait *wait = txp->wait; |
| 1491 | |
| 1492 | /* remove from list */ |
| 1493 | sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL; |
| 1494 | if (wait) |
| 1495 | drained = atomic_dec_and_test(&wait->sdma_busy); |
| 1496 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER |
| 1497 | trace_hfi1_sdma_out_sn(sde, txp->sn); |
| 1498 | if (WARN_ON_ONCE(sde->head_sn != txp->sn)) |
| 1499 | dd_dev_err(sde->dd, "expected %llu got %llu\n", |
| 1500 | sde->head_sn, txp->sn); |
| 1501 | sde->head_sn++; |
| 1502 | #endif |
| 1503 | sdma_txclean(sde->dd, txp); |
| 1504 | if (txp->complete) |
| 1505 | (*txp->complete)( |
| 1506 | txp, |
| 1507 | SDMA_TXREQ_S_OK, |
| 1508 | drained); |
| 1509 | if (wait && drained) |
| 1510 | iowait_drain_wakeup(wait); |
| 1511 | /* see if there is another txp */ |
| 1512 | txp = get_txhead(sde); |
| 1513 | } |
| 1514 | trace_hfi1_sdma_progress(sde, hwhead, swhead, txp); |
| 1515 | progress++; |
| 1516 | } |
| 1517 | |
| 1518 | /* |
| 1519 | * The SDMA idle interrupt is not guaranteed to be ordered with respect |
| 1520 | * to updates to the the dma_head location in host memory. The head |
| 1521 | * value read might not be fully up to date. If there are pending |
| 1522 | * descriptors and the SDMA idle interrupt fired then read from the |
| 1523 | * CSR SDMA head instead to get the latest value from the hardware. |
| 1524 | * The hardware SDMA head should be read at most once in this invocation |
| 1525 | * of sdma_make_progress(..) which is ensured by idle_check_done flag |
| 1526 | */ |
| 1527 | if ((status & sde->idle_mask) && !idle_check_done) { |
| 1528 | swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask; |
| 1529 | if (swtail != hwhead) { |
| 1530 | hwhead = (u16)read_sde_csr(sde, SD(HEAD)); |
| 1531 | idle_check_done = 1; |
| 1532 | goto retry; |
| 1533 | } |
| 1534 | } |
| 1535 | |
| 1536 | sde->last_status = status; |
| 1537 | if (progress) |
| 1538 | sdma_desc_avail(sde, sdma_descq_freecnt(sde)); |
| 1539 | } |
| 1540 | |
| 1541 | /* |
| 1542 | * sdma_engine_interrupt() - interrupt handler for engine |
| 1543 | * @sde: sdma engine |
| 1544 | * @status: sdma interrupt reason |
| 1545 | * |
| 1546 | * Status is a mask of the 3 possible interrupts for this engine. It will |
| 1547 | * contain bits _only_ for this SDMA engine. It will contain at least one |
| 1548 | * bit, it may contain more. |
| 1549 | */ |
| 1550 | void sdma_engine_interrupt(struct sdma_engine *sde, u64 status) |
| 1551 | { |
| 1552 | trace_hfi1_sdma_engine_interrupt(sde, status); |
| 1553 | write_seqlock(&sde->head_lock); |
Mitko Haralanov | ee94785 | 2015-10-26 10:28:41 -0400 | [diff] [blame] | 1554 | sdma_set_desc_cnt(sde, sdma_desct_intr); |
Vennila Megavannan | a699c6c | 2016-01-11 18:30:56 -0500 | [diff] [blame] | 1555 | if (status & sde->idle_mask) |
| 1556 | sde->idle_int_cnt++; |
| 1557 | else if (status & sde->progress_mask) |
| 1558 | sde->progress_int_cnt++; |
| 1559 | else if (status & sde->int_mask) |
| 1560 | sde->sdma_int_cnt++; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1561 | sdma_make_progress(sde, status); |
| 1562 | write_sequnlock(&sde->head_lock); |
| 1563 | } |
| 1564 | |
| 1565 | /** |
| 1566 | * sdma_engine_error() - error handler for engine |
| 1567 | * @sde: sdma engine |
| 1568 | * @status: sdma interrupt reason |
| 1569 | */ |
| 1570 | void sdma_engine_error(struct sdma_engine *sde, u64 status) |
| 1571 | { |
| 1572 | unsigned long flags; |
| 1573 | |
| 1574 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1575 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n", |
| 1576 | sde->this_idx, |
| 1577 | (unsigned long long)status, |
| 1578 | sdma_state_names[sde->state.current_state]); |
| 1579 | #endif |
| 1580 | spin_lock_irqsave(&sde->tail_lock, flags); |
| 1581 | write_seqlock(&sde->head_lock); |
| 1582 | if (status & ALL_SDMA_ENG_HALT_ERRS) |
| 1583 | __sdma_process_event(sde, sdma_event_e60_hw_halted); |
| 1584 | if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) { |
| 1585 | dd_dev_err(sde->dd, |
| 1586 | "SDMA (%u) engine error: 0x%llx state %s\n", |
| 1587 | sde->this_idx, |
| 1588 | (unsigned long long)status, |
| 1589 | sdma_state_names[sde->state.current_state]); |
| 1590 | dump_sdma_state(sde); |
| 1591 | } |
| 1592 | write_sequnlock(&sde->head_lock); |
| 1593 | spin_unlock_irqrestore(&sde->tail_lock, flags); |
| 1594 | } |
| 1595 | |
| 1596 | static void sdma_sendctrl(struct sdma_engine *sde, unsigned op) |
| 1597 | { |
| 1598 | u64 set_senddmactrl = 0; |
| 1599 | u64 clr_senddmactrl = 0; |
| 1600 | unsigned long flags; |
| 1601 | |
| 1602 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1603 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n", |
| 1604 | sde->this_idx, |
| 1605 | (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0, |
| 1606 | (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0, |
| 1607 | (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0, |
| 1608 | (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0); |
| 1609 | #endif |
| 1610 | |
| 1611 | if (op & SDMA_SENDCTRL_OP_ENABLE) |
| 1612 | set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); |
| 1613 | else |
| 1614 | clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK); |
| 1615 | |
| 1616 | if (op & SDMA_SENDCTRL_OP_INTENABLE) |
| 1617 | set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); |
| 1618 | else |
| 1619 | clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK); |
| 1620 | |
| 1621 | if (op & SDMA_SENDCTRL_OP_HALT) |
| 1622 | set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); |
| 1623 | else |
| 1624 | clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK); |
| 1625 | |
| 1626 | spin_lock_irqsave(&sde->senddmactrl_lock, flags); |
| 1627 | |
| 1628 | sde->p_senddmactrl |= set_senddmactrl; |
| 1629 | sde->p_senddmactrl &= ~clr_senddmactrl; |
| 1630 | |
| 1631 | if (op & SDMA_SENDCTRL_OP_CLEANUP) |
| 1632 | write_sde_csr(sde, SD(CTRL), |
| 1633 | sde->p_senddmactrl | |
| 1634 | SD(CTRL_SDMA_CLEANUP_SMASK)); |
| 1635 | else |
| 1636 | write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl); |
| 1637 | |
| 1638 | spin_unlock_irqrestore(&sde->senddmactrl_lock, flags); |
| 1639 | |
| 1640 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1641 | sdma_dumpstate(sde); |
| 1642 | #endif |
| 1643 | } |
| 1644 | |
| 1645 | static void sdma_setlengen(struct sdma_engine *sde) |
| 1646 | { |
| 1647 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1648 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", |
| 1649 | sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); |
| 1650 | #endif |
| 1651 | |
| 1652 | /* |
| 1653 | * Set SendDmaLenGen and clear-then-set the MSB of the generation |
| 1654 | * count to enable generation checking and load the internal |
| 1655 | * generation counter. |
| 1656 | */ |
| 1657 | write_sde_csr(sde, SD(LEN_GEN), |
| 1658 | (sde->descq_cnt/64) << SD(LEN_GEN_LENGTH_SHIFT) |
| 1659 | ); |
| 1660 | write_sde_csr(sde, SD(LEN_GEN), |
| 1661 | ((sde->descq_cnt/64) << SD(LEN_GEN_LENGTH_SHIFT)) |
| 1662 | | (4ULL << SD(LEN_GEN_GENERATION_SHIFT)) |
| 1663 | ); |
| 1664 | } |
| 1665 | |
| 1666 | static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail) |
| 1667 | { |
| 1668 | /* Commit writes to memory and advance the tail on the chip */ |
| 1669 | smp_wmb(); /* see get_txhead() */ |
| 1670 | writeq(tail, sde->tail_csr); |
| 1671 | } |
| 1672 | |
| 1673 | /* |
| 1674 | * This is called when changing to state s10_hw_start_up_halt_wait as |
| 1675 | * a result of send buffer errors or send DMA descriptor errors. |
| 1676 | */ |
| 1677 | static void sdma_hw_start_up(struct sdma_engine *sde) |
| 1678 | { |
| 1679 | u64 reg; |
| 1680 | |
| 1681 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1682 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", |
| 1683 | sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); |
| 1684 | #endif |
| 1685 | |
| 1686 | sdma_setlengen(sde); |
| 1687 | sdma_update_tail(sde, 0); /* Set SendDmaTail */ |
| 1688 | *sde->head_dma = 0; |
| 1689 | |
| 1690 | reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) << |
| 1691 | SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT); |
| 1692 | write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg); |
| 1693 | } |
| 1694 | |
| 1695 | #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ |
| 1696 | (r &= ~SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) |
| 1697 | |
| 1698 | #define SET_STATIC_RATE_CONTROL_SMASK(r) \ |
| 1699 | (r |= SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) |
| 1700 | /* |
| 1701 | * set_sdma_integrity |
| 1702 | * |
| 1703 | * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'. |
| 1704 | */ |
| 1705 | static void set_sdma_integrity(struct sdma_engine *sde) |
| 1706 | { |
| 1707 | struct hfi1_devdata *dd = sde->dd; |
| 1708 | u64 reg; |
| 1709 | |
| 1710 | if (unlikely(HFI1_CAP_IS_KSET(NO_INTEGRITY))) |
| 1711 | return; |
| 1712 | |
| 1713 | reg = hfi1_pkt_base_sdma_integrity(dd); |
| 1714 | |
| 1715 | if (HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) |
| 1716 | CLEAR_STATIC_RATE_CONTROL_SMASK(reg); |
| 1717 | else |
| 1718 | SET_STATIC_RATE_CONTROL_SMASK(reg); |
| 1719 | |
| 1720 | write_sde_csr(sde, SD(CHECK_ENABLE), reg); |
| 1721 | } |
| 1722 | |
| 1723 | |
| 1724 | static void init_sdma_regs( |
| 1725 | struct sdma_engine *sde, |
| 1726 | u32 credits, |
| 1727 | uint idle_cnt) |
| 1728 | { |
| 1729 | u8 opval, opmask; |
| 1730 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1731 | struct hfi1_devdata *dd = sde->dd; |
| 1732 | |
| 1733 | dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", |
| 1734 | sde->this_idx, slashstrip(__FILE__), __LINE__, __func__); |
| 1735 | #endif |
| 1736 | |
| 1737 | write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys); |
| 1738 | sdma_setlengen(sde); |
| 1739 | sdma_update_tail(sde, 0); /* Set SendDmaTail */ |
| 1740 | write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt); |
| 1741 | write_sde_csr(sde, SD(DESC_CNT), 0); |
| 1742 | write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys); |
| 1743 | write_sde_csr(sde, SD(MEMORY), |
| 1744 | ((u64)credits << |
| 1745 | SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) | |
| 1746 | ((u64)(credits * sde->this_idx) << |
| 1747 | SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT))); |
| 1748 | write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull); |
| 1749 | set_sdma_integrity(sde); |
| 1750 | opmask = OPCODE_CHECK_MASK_DISABLED; |
| 1751 | opval = OPCODE_CHECK_VAL_DISABLED; |
| 1752 | write_sde_csr(sde, SD(CHECK_OPCODE), |
| 1753 | (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) | |
| 1754 | (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT)); |
| 1755 | } |
| 1756 | |
| 1757 | #ifdef CONFIG_SDMA_VERBOSITY |
| 1758 | |
| 1759 | #define sdma_dumpstate_helper0(reg) do { \ |
| 1760 | csr = read_csr(sde->dd, reg); \ |
| 1761 | dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \ |
| 1762 | } while (0) |
| 1763 | |
| 1764 | #define sdma_dumpstate_helper(reg) do { \ |
| 1765 | csr = read_sde_csr(sde, reg); \ |
| 1766 | dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \ |
| 1767 | #reg, sde->this_idx, csr); \ |
| 1768 | } while (0) |
| 1769 | |
| 1770 | #define sdma_dumpstate_helper2(reg) do { \ |
| 1771 | csr = read_csr(sde->dd, reg + (8 * i)); \ |
| 1772 | dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \ |
| 1773 | #reg, i, csr); \ |
| 1774 | } while (0) |
| 1775 | |
| 1776 | void sdma_dumpstate(struct sdma_engine *sde) |
| 1777 | { |
| 1778 | u64 csr; |
| 1779 | unsigned i; |
| 1780 | |
| 1781 | sdma_dumpstate_helper(SD(CTRL)); |
| 1782 | sdma_dumpstate_helper(SD(STATUS)); |
| 1783 | sdma_dumpstate_helper0(SD(ERR_STATUS)); |
| 1784 | sdma_dumpstate_helper0(SD(ERR_MASK)); |
| 1785 | sdma_dumpstate_helper(SD(ENG_ERR_STATUS)); |
| 1786 | sdma_dumpstate_helper(SD(ENG_ERR_MASK)); |
| 1787 | |
| 1788 | for (i = 0; i < CCE_NUM_INT_CSRS; ++i) { |
Jubin John | 6fd8eda | 2015-09-02 10:43:24 -0400 | [diff] [blame] | 1789 | sdma_dumpstate_helper2(CCE_INT_STATUS); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1790 | sdma_dumpstate_helper2(CCE_INT_MASK); |
| 1791 | sdma_dumpstate_helper2(CCE_INT_BLOCKED); |
| 1792 | } |
| 1793 | |
| 1794 | sdma_dumpstate_helper(SD(TAIL)); |
| 1795 | sdma_dumpstate_helper(SD(HEAD)); |
| 1796 | sdma_dumpstate_helper(SD(PRIORITY_THLD)); |
Jubin John | 6fd8eda | 2015-09-02 10:43:24 -0400 | [diff] [blame] | 1797 | sdma_dumpstate_helper(SD(IDLE_CNT)); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1798 | sdma_dumpstate_helper(SD(RELOAD_CNT)); |
| 1799 | sdma_dumpstate_helper(SD(DESC_CNT)); |
| 1800 | sdma_dumpstate_helper(SD(DESC_FETCHED_CNT)); |
| 1801 | sdma_dumpstate_helper(SD(MEMORY)); |
| 1802 | sdma_dumpstate_helper0(SD(ENGINES)); |
| 1803 | sdma_dumpstate_helper0(SD(MEM_SIZE)); |
| 1804 | /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */ |
| 1805 | sdma_dumpstate_helper(SD(BASE_ADDR)); |
| 1806 | sdma_dumpstate_helper(SD(LEN_GEN)); |
| 1807 | sdma_dumpstate_helper(SD(HEAD_ADDR)); |
| 1808 | sdma_dumpstate_helper(SD(CHECK_ENABLE)); |
| 1809 | sdma_dumpstate_helper(SD(CHECK_VL)); |
| 1810 | sdma_dumpstate_helper(SD(CHECK_JOB_KEY)); |
| 1811 | sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY)); |
| 1812 | sdma_dumpstate_helper(SD(CHECK_SLID)); |
| 1813 | sdma_dumpstate_helper(SD(CHECK_OPCODE)); |
| 1814 | } |
| 1815 | #endif |
| 1816 | |
| 1817 | static void dump_sdma_state(struct sdma_engine *sde) |
| 1818 | { |
| 1819 | struct hw_sdma_desc *descq; |
| 1820 | struct hw_sdma_desc *descqp; |
| 1821 | u64 desc[2]; |
| 1822 | u64 addr; |
| 1823 | u8 gen; |
| 1824 | u16 len; |
| 1825 | u16 head, tail, cnt; |
| 1826 | |
| 1827 | head = sde->descq_head & sde->sdma_mask; |
| 1828 | tail = sde->descq_tail & sde->sdma_mask; |
| 1829 | cnt = sdma_descq_freecnt(sde); |
| 1830 | descq = sde->descq; |
| 1831 | |
| 1832 | dd_dev_err(sde->dd, |
| 1833 | "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n", |
| 1834 | sde->this_idx, |
| 1835 | head, |
| 1836 | tail, |
| 1837 | cnt, |
| 1838 | !list_empty(&sde->flushlist)); |
| 1839 | |
| 1840 | /* print info for each entry in the descriptor queue */ |
| 1841 | while (head != tail) { |
| 1842 | char flags[6] = { 'x', 'x', 'x', 'x', 0 }; |
| 1843 | |
| 1844 | descqp = &sde->descq[head]; |
| 1845 | desc[0] = le64_to_cpu(descqp->qw[0]); |
| 1846 | desc[1] = le64_to_cpu(descqp->qw[1]); |
| 1847 | flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; |
| 1848 | flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? |
| 1849 | 'H' : '-'; |
| 1850 | flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; |
| 1851 | flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; |
| 1852 | addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) |
| 1853 | & SDMA_DESC0_PHY_ADDR_MASK; |
| 1854 | gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) |
| 1855 | & SDMA_DESC1_GENERATION_MASK; |
| 1856 | len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) |
| 1857 | & SDMA_DESC0_BYTE_COUNT_MASK; |
| 1858 | dd_dev_err(sde->dd, |
| 1859 | "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", |
| 1860 | head, flags, addr, gen, len); |
| 1861 | dd_dev_err(sde->dd, |
| 1862 | "\tdesc0:0x%016llx desc1 0x%016llx\n", |
| 1863 | desc[0], desc[1]); |
| 1864 | if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) |
| 1865 | dd_dev_err(sde->dd, |
| 1866 | "\taidx: %u amode: %u alen: %u\n", |
| 1867 | (u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK) |
Dan Carpenter | 7d63046 | 2015-09-16 19:03:45 +0300 | [diff] [blame] | 1868 | >> SDMA_DESC1_HEADER_INDEX_SHIFT), |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1869 | (u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK) |
| 1870 | >> SDMA_DESC1_HEADER_MODE_SHIFT), |
| 1871 | (u8)((desc[1] & SDMA_DESC1_HEADER_DWS_SMASK) |
| 1872 | >> SDMA_DESC1_HEADER_DWS_SHIFT)); |
| 1873 | head++; |
| 1874 | head &= sde->sdma_mask; |
| 1875 | } |
| 1876 | } |
| 1877 | |
| 1878 | #define SDE_FMT \ |
Mike Marciniszyn | 0a226ed | 2015-11-09 19:13:58 -0500 | [diff] [blame] | 1879 | "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n" |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1880 | /** |
| 1881 | * sdma_seqfile_dump_sde() - debugfs dump of sde |
| 1882 | * @s: seq file |
| 1883 | * @sde: send dma engine to dump |
| 1884 | * |
| 1885 | * This routine dumps the sde to the indicated seq file. |
| 1886 | */ |
| 1887 | void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde) |
| 1888 | { |
| 1889 | u16 head, tail; |
| 1890 | struct hw_sdma_desc *descqp; |
| 1891 | u64 desc[2]; |
| 1892 | u64 addr; |
| 1893 | u8 gen; |
| 1894 | u16 len; |
| 1895 | |
| 1896 | head = sde->descq_head & sde->sdma_mask; |
| 1897 | tail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask; |
| 1898 | seq_printf(s, SDE_FMT, sde->this_idx, |
Mike Marciniszyn | 0a226ed | 2015-11-09 19:13:58 -0500 | [diff] [blame] | 1899 | sde->cpu, |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1900 | sdma_state_name(sde->state.current_state), |
| 1901 | (unsigned long long)read_sde_csr(sde, SD(CTRL)), |
| 1902 | (unsigned long long)read_sde_csr(sde, SD(STATUS)), |
| 1903 | (unsigned long long)read_sde_csr(sde, |
| 1904 | SD(ENG_ERR_STATUS)), |
| 1905 | (unsigned long long)read_sde_csr(sde, SD(TAIL)), |
| 1906 | tail, |
| 1907 | (unsigned long long)read_sde_csr(sde, SD(HEAD)), |
| 1908 | head, |
| 1909 | (unsigned long long)le64_to_cpu(*sde->head_dma), |
| 1910 | (unsigned long long)read_sde_csr(sde, SD(MEMORY)), |
| 1911 | (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)), |
| 1912 | (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)), |
| 1913 | (unsigned long long)sde->last_status, |
| 1914 | (unsigned long long)sde->ahg_bits, |
| 1915 | sde->tx_tail, |
| 1916 | sde->tx_head, |
| 1917 | sde->descq_tail, |
| 1918 | sde->descq_head, |
| 1919 | !list_empty(&sde->flushlist), |
| 1920 | sde->descq_full_count, |
| 1921 | (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID)); |
| 1922 | |
| 1923 | /* print info for each entry in the descriptor queue */ |
| 1924 | while (head != tail) { |
| 1925 | char flags[6] = { 'x', 'x', 'x', 'x', 0 }; |
| 1926 | |
| 1927 | descqp = &sde->descq[head]; |
| 1928 | desc[0] = le64_to_cpu(descqp->qw[0]); |
| 1929 | desc[1] = le64_to_cpu(descqp->qw[1]); |
| 1930 | flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-'; |
| 1931 | flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? |
| 1932 | 'H' : '-'; |
| 1933 | flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-'; |
| 1934 | flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-'; |
| 1935 | addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT) |
| 1936 | & SDMA_DESC0_PHY_ADDR_MASK; |
| 1937 | gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT) |
| 1938 | & SDMA_DESC1_GENERATION_MASK; |
| 1939 | len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT) |
| 1940 | & SDMA_DESC0_BYTE_COUNT_MASK; |
| 1941 | seq_printf(s, |
| 1942 | "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n", |
| 1943 | head, flags, addr, gen, len); |
| 1944 | if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) |
| 1945 | seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n", |
| 1946 | (u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK) |
Dan Carpenter | 7d63046 | 2015-09-16 19:03:45 +0300 | [diff] [blame] | 1947 | >> SDMA_DESC1_HEADER_INDEX_SHIFT), |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1948 | (u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK) |
| 1949 | >> SDMA_DESC1_HEADER_MODE_SHIFT)); |
| 1950 | head = (head + 1) & sde->sdma_mask; |
| 1951 | } |
| 1952 | } |
| 1953 | |
| 1954 | /* |
| 1955 | * add the generation number into |
| 1956 | * the qw1 and return |
| 1957 | */ |
| 1958 | static inline u64 add_gen(struct sdma_engine *sde, u64 qw1) |
| 1959 | { |
| 1960 | u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3; |
| 1961 | |
| 1962 | qw1 &= ~SDMA_DESC1_GENERATION_SMASK; |
| 1963 | qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK) |
| 1964 | << SDMA_DESC1_GENERATION_SHIFT; |
| 1965 | return qw1; |
| 1966 | } |
| 1967 | |
| 1968 | /* |
| 1969 | * This routine submits the indicated tx |
| 1970 | * |
| 1971 | * Space has already been guaranteed and |
| 1972 | * tail side of ring is locked. |
| 1973 | * |
| 1974 | * The hardware tail update is done |
| 1975 | * in the caller and that is facilitated |
| 1976 | * by returning the new tail. |
| 1977 | * |
| 1978 | * There is special case logic for ahg |
| 1979 | * to not add the generation number for |
| 1980 | * up to 2 descriptors that follow the |
| 1981 | * first descriptor. |
| 1982 | * |
| 1983 | */ |
| 1984 | static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx) |
| 1985 | { |
| 1986 | int i; |
| 1987 | u16 tail; |
| 1988 | struct sdma_desc *descp = tx->descp; |
| 1989 | u8 skip = 0, mode = ahg_mode(tx); |
| 1990 | |
| 1991 | tail = sde->descq_tail & sde->sdma_mask; |
| 1992 | sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); |
| 1993 | sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1])); |
| 1994 | trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1], |
| 1995 | tail, &sde->descq[tail]); |
| 1996 | tail = ++sde->descq_tail & sde->sdma_mask; |
| 1997 | descp++; |
| 1998 | if (mode > SDMA_AHG_APPLY_UPDATE1) |
| 1999 | skip = mode >> 1; |
| 2000 | for (i = 1; i < tx->num_desc; i++, descp++) { |
| 2001 | u64 qw1; |
| 2002 | |
| 2003 | sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]); |
| 2004 | if (skip) { |
| 2005 | /* edits don't have generation */ |
| 2006 | qw1 = descp->qw[1]; |
| 2007 | skip--; |
| 2008 | } else { |
| 2009 | /* replace generation with real one for non-edits */ |
| 2010 | qw1 = add_gen(sde, descp->qw[1]); |
| 2011 | } |
| 2012 | sde->descq[tail].qw[1] = cpu_to_le64(qw1); |
| 2013 | trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1, |
| 2014 | tail, &sde->descq[tail]); |
| 2015 | tail = ++sde->descq_tail & sde->sdma_mask; |
| 2016 | } |
| 2017 | tx->next_descq_idx = tail; |
| 2018 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER |
| 2019 | tx->sn = sde->tail_sn++; |
| 2020 | trace_hfi1_sdma_in_sn(sde, tx->sn); |
| 2021 | WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]); |
| 2022 | #endif |
| 2023 | sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx; |
| 2024 | sde->desc_avail -= tx->num_desc; |
| 2025 | return tail; |
| 2026 | } |
| 2027 | |
| 2028 | /* |
| 2029 | * Check for progress |
| 2030 | */ |
| 2031 | static int sdma_check_progress( |
| 2032 | struct sdma_engine *sde, |
| 2033 | struct iowait *wait, |
| 2034 | struct sdma_txreq *tx) |
| 2035 | { |
| 2036 | int ret; |
| 2037 | |
| 2038 | sde->desc_avail = sdma_descq_freecnt(sde); |
| 2039 | if (tx->num_desc <= sde->desc_avail) |
| 2040 | return -EAGAIN; |
| 2041 | /* pulse the head_lock */ |
| 2042 | if (wait && wait->sleep) { |
| 2043 | unsigned seq; |
| 2044 | |
| 2045 | seq = raw_seqcount_begin( |
| 2046 | (const seqcount_t *)&sde->head_lock.seqcount); |
| 2047 | ret = wait->sleep(sde, wait, tx, seq); |
| 2048 | if (ret == -EAGAIN) |
| 2049 | sde->desc_avail = sdma_descq_freecnt(sde); |
| 2050 | } else |
| 2051 | ret = -EBUSY; |
| 2052 | return ret; |
| 2053 | } |
| 2054 | |
| 2055 | /** |
| 2056 | * sdma_send_txreq() - submit a tx req to ring |
| 2057 | * @sde: sdma engine to use |
| 2058 | * @wait: wait structure to use when full (may be NULL) |
| 2059 | * @tx: sdma_txreq to submit |
| 2060 | * |
| 2061 | * The call submits the tx into the ring. If a iowait structure is non-NULL |
| 2062 | * the packet will be queued to the list in wait. |
| 2063 | * |
| 2064 | * Return: |
| 2065 | * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in |
| 2066 | * ring (wait == NULL) |
| 2067 | * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state |
| 2068 | */ |
| 2069 | int sdma_send_txreq(struct sdma_engine *sde, |
| 2070 | struct iowait *wait, |
| 2071 | struct sdma_txreq *tx) |
| 2072 | { |
| 2073 | int ret = 0; |
| 2074 | u16 tail; |
| 2075 | unsigned long flags; |
| 2076 | |
| 2077 | /* user should have supplied entire packet */ |
| 2078 | if (unlikely(tx->tlen)) |
| 2079 | return -EINVAL; |
| 2080 | tx->wait = wait; |
| 2081 | spin_lock_irqsave(&sde->tail_lock, flags); |
| 2082 | retry: |
| 2083 | if (unlikely(!__sdma_running(sde))) |
| 2084 | goto unlock_noconn; |
| 2085 | if (unlikely(tx->num_desc > sde->desc_avail)) |
| 2086 | goto nodesc; |
| 2087 | tail = submit_tx(sde, tx); |
| 2088 | if (wait) |
| 2089 | atomic_inc(&wait->sdma_busy); |
| 2090 | sdma_update_tail(sde, tail); |
| 2091 | unlock: |
| 2092 | spin_unlock_irqrestore(&sde->tail_lock, flags); |
| 2093 | return ret; |
| 2094 | unlock_noconn: |
| 2095 | if (wait) |
| 2096 | atomic_inc(&wait->sdma_busy); |
| 2097 | tx->next_descq_idx = 0; |
| 2098 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER |
| 2099 | tx->sn = sde->tail_sn++; |
| 2100 | trace_hfi1_sdma_in_sn(sde, tx->sn); |
| 2101 | #endif |
Dean Luick | f4f30031c | 2015-10-26 10:28:44 -0400 | [diff] [blame] | 2102 | spin_lock(&sde->flushlist_lock); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2103 | list_add_tail(&tx->list, &sde->flushlist); |
Dean Luick | f4f30031c | 2015-10-26 10:28:44 -0400 | [diff] [blame] | 2104 | spin_unlock(&sde->flushlist_lock); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2105 | if (wait) { |
| 2106 | wait->tx_count++; |
| 2107 | wait->count += tx->num_desc; |
| 2108 | } |
| 2109 | schedule_work(&sde->flush_worker); |
| 2110 | ret = -ECOMM; |
| 2111 | goto unlock; |
| 2112 | nodesc: |
| 2113 | ret = sdma_check_progress(sde, wait, tx); |
| 2114 | if (ret == -EAGAIN) { |
| 2115 | ret = 0; |
| 2116 | goto retry; |
| 2117 | } |
| 2118 | sde->descq_full_count++; |
| 2119 | goto unlock; |
| 2120 | } |
| 2121 | |
| 2122 | /** |
| 2123 | * sdma_send_txlist() - submit a list of tx req to ring |
| 2124 | * @sde: sdma engine to use |
| 2125 | * @wait: wait structure to use when full (may be NULL) |
| 2126 | * @tx_list: list of sdma_txreqs to submit |
| 2127 | * |
| 2128 | * The call submits the list into the ring. |
| 2129 | * |
| 2130 | * If the iowait structure is non-NULL and not equal to the iowait list |
| 2131 | * the unprocessed part of the list will be appended to the list in wait. |
| 2132 | * |
| 2133 | * In all cases, the tx_list will be updated so the head of the tx_list is |
| 2134 | * the list of descriptors that have yet to be transmitted. |
| 2135 | * |
| 2136 | * The intent of this call is to provide a more efficient |
| 2137 | * way of submitting multiple packets to SDMA while holding the tail |
| 2138 | * side locking. |
| 2139 | * |
| 2140 | * Return: |
| 2141 | * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring |
| 2142 | * (wait == NULL) |
| 2143 | * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state |
| 2144 | */ |
| 2145 | int sdma_send_txlist(struct sdma_engine *sde, |
| 2146 | struct iowait *wait, |
| 2147 | struct list_head *tx_list) |
| 2148 | { |
| 2149 | struct sdma_txreq *tx, *tx_next; |
| 2150 | int ret = 0; |
| 2151 | unsigned long flags; |
| 2152 | u16 tail = INVALID_TAIL; |
| 2153 | int count = 0; |
| 2154 | |
| 2155 | spin_lock_irqsave(&sde->tail_lock, flags); |
| 2156 | retry: |
| 2157 | list_for_each_entry_safe(tx, tx_next, tx_list, list) { |
| 2158 | tx->wait = wait; |
| 2159 | if (unlikely(!__sdma_running(sde))) |
| 2160 | goto unlock_noconn; |
| 2161 | if (unlikely(tx->num_desc > sde->desc_avail)) |
| 2162 | goto nodesc; |
| 2163 | if (unlikely(tx->tlen)) { |
| 2164 | ret = -EINVAL; |
| 2165 | goto update_tail; |
| 2166 | } |
| 2167 | list_del_init(&tx->list); |
| 2168 | tail = submit_tx(sde, tx); |
| 2169 | count++; |
| 2170 | if (tail != INVALID_TAIL && |
| 2171 | (count & SDMA_TAIL_UPDATE_THRESH) == 0) { |
| 2172 | sdma_update_tail(sde, tail); |
| 2173 | tail = INVALID_TAIL; |
| 2174 | } |
| 2175 | } |
| 2176 | update_tail: |
| 2177 | if (wait) |
| 2178 | atomic_add(count, &wait->sdma_busy); |
| 2179 | if (tail != INVALID_TAIL) |
| 2180 | sdma_update_tail(sde, tail); |
| 2181 | spin_unlock_irqrestore(&sde->tail_lock, flags); |
| 2182 | return ret; |
| 2183 | unlock_noconn: |
| 2184 | spin_lock(&sde->flushlist_lock); |
| 2185 | list_for_each_entry_safe(tx, tx_next, tx_list, list) { |
| 2186 | tx->wait = wait; |
| 2187 | list_del_init(&tx->list); |
| 2188 | if (wait) |
| 2189 | atomic_inc(&wait->sdma_busy); |
| 2190 | tx->next_descq_idx = 0; |
| 2191 | #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER |
| 2192 | tx->sn = sde->tail_sn++; |
| 2193 | trace_hfi1_sdma_in_sn(sde, tx->sn); |
| 2194 | #endif |
| 2195 | list_add_tail(&tx->list, &sde->flushlist); |
| 2196 | if (wait) { |
| 2197 | wait->tx_count++; |
| 2198 | wait->count += tx->num_desc; |
| 2199 | } |
| 2200 | } |
| 2201 | spin_unlock(&sde->flushlist_lock); |
| 2202 | schedule_work(&sde->flush_worker); |
| 2203 | ret = -ECOMM; |
| 2204 | goto update_tail; |
| 2205 | nodesc: |
| 2206 | ret = sdma_check_progress(sde, wait, tx); |
| 2207 | if (ret == -EAGAIN) { |
| 2208 | ret = 0; |
| 2209 | goto retry; |
| 2210 | } |
| 2211 | sde->descq_full_count++; |
| 2212 | goto update_tail; |
| 2213 | } |
| 2214 | |
| 2215 | static void sdma_process_event(struct sdma_engine *sde, |
| 2216 | enum sdma_events event) |
| 2217 | { |
| 2218 | unsigned long flags; |
| 2219 | |
| 2220 | spin_lock_irqsave(&sde->tail_lock, flags); |
| 2221 | write_seqlock(&sde->head_lock); |
| 2222 | |
| 2223 | __sdma_process_event(sde, event); |
| 2224 | |
| 2225 | if (sde->state.current_state == sdma_state_s99_running) |
| 2226 | sdma_desc_avail(sde, sdma_descq_freecnt(sde)); |
| 2227 | |
| 2228 | write_sequnlock(&sde->head_lock); |
| 2229 | spin_unlock_irqrestore(&sde->tail_lock, flags); |
| 2230 | } |
| 2231 | |
| 2232 | static void __sdma_process_event(struct sdma_engine *sde, |
| 2233 | enum sdma_events event) |
| 2234 | { |
| 2235 | struct sdma_state *ss = &sde->state; |
| 2236 | int need_progress = 0; |
| 2237 | |
| 2238 | /* CONFIG SDMA temporary */ |
| 2239 | #ifdef CONFIG_SDMA_VERBOSITY |
| 2240 | dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx, |
| 2241 | sdma_state_names[ss->current_state], |
| 2242 | sdma_event_names[event]); |
| 2243 | #endif |
| 2244 | |
| 2245 | switch (ss->current_state) { |
| 2246 | case sdma_state_s00_hw_down: |
| 2247 | switch (event) { |
| 2248 | case sdma_event_e00_go_hw_down: |
| 2249 | break; |
| 2250 | case sdma_event_e30_go_running: |
| 2251 | /* |
| 2252 | * If down, but running requested (usually result |
| 2253 | * of link up, then we need to start up. |
| 2254 | * This can happen when hw down is requested while |
| 2255 | * bringing the link up with traffic active on |
| 2256 | * 7220, e.g. */ |
| 2257 | ss->go_s99_running = 1; |
| 2258 | /* fall through and start dma engine */ |
| 2259 | case sdma_event_e10_go_hw_start: |
| 2260 | /* This reference means the state machine is started */ |
| 2261 | sdma_get(&sde->state); |
| 2262 | sdma_set_state(sde, |
| 2263 | sdma_state_s10_hw_start_up_halt_wait); |
| 2264 | break; |
| 2265 | case sdma_event_e15_hw_halt_done: |
| 2266 | break; |
| 2267 | case sdma_event_e25_hw_clean_up_done: |
| 2268 | break; |
| 2269 | case sdma_event_e40_sw_cleaned: |
| 2270 | sdma_sw_tear_down(sde); |
| 2271 | break; |
| 2272 | case sdma_event_e50_hw_cleaned: |
| 2273 | break; |
| 2274 | case sdma_event_e60_hw_halted: |
| 2275 | break; |
| 2276 | case sdma_event_e70_go_idle: |
| 2277 | break; |
| 2278 | case sdma_event_e80_hw_freeze: |
| 2279 | break; |
| 2280 | case sdma_event_e81_hw_frozen: |
| 2281 | break; |
| 2282 | case sdma_event_e82_hw_unfreeze: |
| 2283 | break; |
| 2284 | case sdma_event_e85_link_down: |
| 2285 | break; |
| 2286 | case sdma_event_e90_sw_halted: |
| 2287 | break; |
| 2288 | } |
| 2289 | break; |
| 2290 | |
| 2291 | case sdma_state_s10_hw_start_up_halt_wait: |
| 2292 | switch (event) { |
| 2293 | case sdma_event_e00_go_hw_down: |
| 2294 | sdma_set_state(sde, sdma_state_s00_hw_down); |
| 2295 | sdma_sw_tear_down(sde); |
| 2296 | break; |
| 2297 | case sdma_event_e10_go_hw_start: |
| 2298 | break; |
| 2299 | case sdma_event_e15_hw_halt_done: |
| 2300 | sdma_set_state(sde, |
| 2301 | sdma_state_s15_hw_start_up_clean_wait); |
| 2302 | sdma_start_hw_clean_up(sde); |
| 2303 | break; |
| 2304 | case sdma_event_e25_hw_clean_up_done: |
| 2305 | break; |
| 2306 | case sdma_event_e30_go_running: |
| 2307 | ss->go_s99_running = 1; |
| 2308 | break; |
| 2309 | case sdma_event_e40_sw_cleaned: |
| 2310 | break; |
| 2311 | case sdma_event_e50_hw_cleaned: |
| 2312 | break; |
| 2313 | case sdma_event_e60_hw_halted: |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2314 | schedule_work(&sde->err_halt_worker); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2315 | break; |
| 2316 | case sdma_event_e70_go_idle: |
| 2317 | ss->go_s99_running = 0; |
| 2318 | break; |
| 2319 | case sdma_event_e80_hw_freeze: |
| 2320 | break; |
| 2321 | case sdma_event_e81_hw_frozen: |
| 2322 | break; |
| 2323 | case sdma_event_e82_hw_unfreeze: |
| 2324 | break; |
| 2325 | case sdma_event_e85_link_down: |
| 2326 | break; |
| 2327 | case sdma_event_e90_sw_halted: |
| 2328 | break; |
| 2329 | } |
| 2330 | break; |
| 2331 | |
| 2332 | case sdma_state_s15_hw_start_up_clean_wait: |
| 2333 | switch (event) { |
| 2334 | case sdma_event_e00_go_hw_down: |
| 2335 | sdma_set_state(sde, sdma_state_s00_hw_down); |
| 2336 | sdma_sw_tear_down(sde); |
| 2337 | break; |
| 2338 | case sdma_event_e10_go_hw_start: |
| 2339 | break; |
| 2340 | case sdma_event_e15_hw_halt_done: |
| 2341 | break; |
| 2342 | case sdma_event_e25_hw_clean_up_done: |
| 2343 | sdma_hw_start_up(sde); |
| 2344 | sdma_set_state(sde, ss->go_s99_running ? |
| 2345 | sdma_state_s99_running : |
| 2346 | sdma_state_s20_idle); |
| 2347 | break; |
| 2348 | case sdma_event_e30_go_running: |
| 2349 | ss->go_s99_running = 1; |
| 2350 | break; |
| 2351 | case sdma_event_e40_sw_cleaned: |
| 2352 | break; |
| 2353 | case sdma_event_e50_hw_cleaned: |
| 2354 | break; |
| 2355 | case sdma_event_e60_hw_halted: |
| 2356 | break; |
| 2357 | case sdma_event_e70_go_idle: |
| 2358 | ss->go_s99_running = 0; |
| 2359 | break; |
| 2360 | case sdma_event_e80_hw_freeze: |
| 2361 | break; |
| 2362 | case sdma_event_e81_hw_frozen: |
| 2363 | break; |
| 2364 | case sdma_event_e82_hw_unfreeze: |
| 2365 | break; |
| 2366 | case sdma_event_e85_link_down: |
| 2367 | break; |
| 2368 | case sdma_event_e90_sw_halted: |
| 2369 | break; |
| 2370 | } |
| 2371 | break; |
| 2372 | |
| 2373 | case sdma_state_s20_idle: |
| 2374 | switch (event) { |
| 2375 | case sdma_event_e00_go_hw_down: |
| 2376 | sdma_set_state(sde, sdma_state_s00_hw_down); |
| 2377 | sdma_sw_tear_down(sde); |
| 2378 | break; |
| 2379 | case sdma_event_e10_go_hw_start: |
| 2380 | break; |
| 2381 | case sdma_event_e15_hw_halt_done: |
| 2382 | break; |
| 2383 | case sdma_event_e25_hw_clean_up_done: |
| 2384 | break; |
| 2385 | case sdma_event_e30_go_running: |
| 2386 | sdma_set_state(sde, sdma_state_s99_running); |
| 2387 | ss->go_s99_running = 1; |
| 2388 | break; |
| 2389 | case sdma_event_e40_sw_cleaned: |
| 2390 | break; |
| 2391 | case sdma_event_e50_hw_cleaned: |
| 2392 | break; |
| 2393 | case sdma_event_e60_hw_halted: |
| 2394 | sdma_set_state(sde, sdma_state_s50_hw_halt_wait); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2395 | schedule_work(&sde->err_halt_worker); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2396 | break; |
| 2397 | case sdma_event_e70_go_idle: |
| 2398 | break; |
| 2399 | case sdma_event_e85_link_down: |
| 2400 | /* fall through */ |
| 2401 | case sdma_event_e80_hw_freeze: |
| 2402 | sdma_set_state(sde, sdma_state_s80_hw_freeze); |
| 2403 | atomic_dec(&sde->dd->sdma_unfreeze_count); |
| 2404 | wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); |
| 2405 | break; |
| 2406 | case sdma_event_e81_hw_frozen: |
| 2407 | break; |
| 2408 | case sdma_event_e82_hw_unfreeze: |
| 2409 | break; |
| 2410 | case sdma_event_e90_sw_halted: |
| 2411 | break; |
| 2412 | } |
| 2413 | break; |
| 2414 | |
| 2415 | case sdma_state_s30_sw_clean_up_wait: |
| 2416 | switch (event) { |
| 2417 | case sdma_event_e00_go_hw_down: |
| 2418 | sdma_set_state(sde, sdma_state_s00_hw_down); |
| 2419 | break; |
| 2420 | case sdma_event_e10_go_hw_start: |
| 2421 | break; |
| 2422 | case sdma_event_e15_hw_halt_done: |
| 2423 | break; |
| 2424 | case sdma_event_e25_hw_clean_up_done: |
| 2425 | break; |
| 2426 | case sdma_event_e30_go_running: |
| 2427 | ss->go_s99_running = 1; |
| 2428 | break; |
| 2429 | case sdma_event_e40_sw_cleaned: |
| 2430 | sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait); |
| 2431 | sdma_start_hw_clean_up(sde); |
| 2432 | break; |
| 2433 | case sdma_event_e50_hw_cleaned: |
| 2434 | break; |
| 2435 | case sdma_event_e60_hw_halted: |
| 2436 | break; |
| 2437 | case sdma_event_e70_go_idle: |
| 2438 | ss->go_s99_running = 0; |
| 2439 | break; |
| 2440 | case sdma_event_e80_hw_freeze: |
| 2441 | break; |
| 2442 | case sdma_event_e81_hw_frozen: |
| 2443 | break; |
| 2444 | case sdma_event_e82_hw_unfreeze: |
| 2445 | break; |
| 2446 | case sdma_event_e85_link_down: |
| 2447 | ss->go_s99_running = 0; |
| 2448 | break; |
| 2449 | case sdma_event_e90_sw_halted: |
| 2450 | break; |
| 2451 | } |
| 2452 | break; |
| 2453 | |
| 2454 | case sdma_state_s40_hw_clean_up_wait: |
| 2455 | switch (event) { |
| 2456 | case sdma_event_e00_go_hw_down: |
| 2457 | sdma_set_state(sde, sdma_state_s00_hw_down); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2458 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2459 | break; |
| 2460 | case sdma_event_e10_go_hw_start: |
| 2461 | break; |
| 2462 | case sdma_event_e15_hw_halt_done: |
| 2463 | break; |
| 2464 | case sdma_event_e25_hw_clean_up_done: |
| 2465 | sdma_hw_start_up(sde); |
| 2466 | sdma_set_state(sde, ss->go_s99_running ? |
| 2467 | sdma_state_s99_running : |
| 2468 | sdma_state_s20_idle); |
| 2469 | break; |
| 2470 | case sdma_event_e30_go_running: |
| 2471 | ss->go_s99_running = 1; |
| 2472 | break; |
| 2473 | case sdma_event_e40_sw_cleaned: |
| 2474 | break; |
| 2475 | case sdma_event_e50_hw_cleaned: |
| 2476 | break; |
| 2477 | case sdma_event_e60_hw_halted: |
| 2478 | break; |
| 2479 | case sdma_event_e70_go_idle: |
| 2480 | ss->go_s99_running = 0; |
| 2481 | break; |
| 2482 | case sdma_event_e80_hw_freeze: |
| 2483 | break; |
| 2484 | case sdma_event_e81_hw_frozen: |
| 2485 | break; |
| 2486 | case sdma_event_e82_hw_unfreeze: |
| 2487 | break; |
| 2488 | case sdma_event_e85_link_down: |
| 2489 | ss->go_s99_running = 0; |
| 2490 | break; |
| 2491 | case sdma_event_e90_sw_halted: |
| 2492 | break; |
| 2493 | } |
| 2494 | break; |
| 2495 | |
| 2496 | case sdma_state_s50_hw_halt_wait: |
| 2497 | switch (event) { |
| 2498 | case sdma_event_e00_go_hw_down: |
| 2499 | sdma_set_state(sde, sdma_state_s00_hw_down); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2500 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2501 | break; |
| 2502 | case sdma_event_e10_go_hw_start: |
| 2503 | break; |
| 2504 | case sdma_event_e15_hw_halt_done: |
| 2505 | sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2506 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2507 | break; |
| 2508 | case sdma_event_e25_hw_clean_up_done: |
| 2509 | break; |
| 2510 | case sdma_event_e30_go_running: |
| 2511 | ss->go_s99_running = 1; |
| 2512 | break; |
| 2513 | case sdma_event_e40_sw_cleaned: |
| 2514 | break; |
| 2515 | case sdma_event_e50_hw_cleaned: |
| 2516 | break; |
| 2517 | case sdma_event_e60_hw_halted: |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2518 | schedule_work(&sde->err_halt_worker); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2519 | break; |
| 2520 | case sdma_event_e70_go_idle: |
| 2521 | ss->go_s99_running = 0; |
| 2522 | break; |
| 2523 | case sdma_event_e80_hw_freeze: |
| 2524 | break; |
| 2525 | case sdma_event_e81_hw_frozen: |
| 2526 | break; |
| 2527 | case sdma_event_e82_hw_unfreeze: |
| 2528 | break; |
| 2529 | case sdma_event_e85_link_down: |
| 2530 | ss->go_s99_running = 0; |
| 2531 | break; |
| 2532 | case sdma_event_e90_sw_halted: |
| 2533 | break; |
| 2534 | } |
| 2535 | break; |
| 2536 | |
| 2537 | case sdma_state_s60_idle_halt_wait: |
| 2538 | switch (event) { |
| 2539 | case sdma_event_e00_go_hw_down: |
| 2540 | sdma_set_state(sde, sdma_state_s00_hw_down); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2541 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2542 | break; |
| 2543 | case sdma_event_e10_go_hw_start: |
| 2544 | break; |
| 2545 | case sdma_event_e15_hw_halt_done: |
| 2546 | sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2547 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2548 | break; |
| 2549 | case sdma_event_e25_hw_clean_up_done: |
| 2550 | break; |
| 2551 | case sdma_event_e30_go_running: |
| 2552 | ss->go_s99_running = 1; |
| 2553 | break; |
| 2554 | case sdma_event_e40_sw_cleaned: |
| 2555 | break; |
| 2556 | case sdma_event_e50_hw_cleaned: |
| 2557 | break; |
| 2558 | case sdma_event_e60_hw_halted: |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2559 | schedule_work(&sde->err_halt_worker); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2560 | break; |
| 2561 | case sdma_event_e70_go_idle: |
| 2562 | ss->go_s99_running = 0; |
| 2563 | break; |
| 2564 | case sdma_event_e80_hw_freeze: |
| 2565 | break; |
| 2566 | case sdma_event_e81_hw_frozen: |
| 2567 | break; |
| 2568 | case sdma_event_e82_hw_unfreeze: |
| 2569 | break; |
| 2570 | case sdma_event_e85_link_down: |
| 2571 | break; |
| 2572 | case sdma_event_e90_sw_halted: |
| 2573 | break; |
| 2574 | } |
| 2575 | break; |
| 2576 | |
| 2577 | case sdma_state_s80_hw_freeze: |
| 2578 | switch (event) { |
| 2579 | case sdma_event_e00_go_hw_down: |
| 2580 | sdma_set_state(sde, sdma_state_s00_hw_down); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2581 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2582 | break; |
| 2583 | case sdma_event_e10_go_hw_start: |
| 2584 | break; |
| 2585 | case sdma_event_e15_hw_halt_done: |
| 2586 | break; |
| 2587 | case sdma_event_e25_hw_clean_up_done: |
| 2588 | break; |
| 2589 | case sdma_event_e30_go_running: |
| 2590 | ss->go_s99_running = 1; |
| 2591 | break; |
| 2592 | case sdma_event_e40_sw_cleaned: |
| 2593 | break; |
| 2594 | case sdma_event_e50_hw_cleaned: |
| 2595 | break; |
| 2596 | case sdma_event_e60_hw_halted: |
| 2597 | break; |
| 2598 | case sdma_event_e70_go_idle: |
| 2599 | ss->go_s99_running = 0; |
| 2600 | break; |
| 2601 | case sdma_event_e80_hw_freeze: |
| 2602 | break; |
| 2603 | case sdma_event_e81_hw_frozen: |
| 2604 | sdma_set_state(sde, sdma_state_s82_freeze_sw_clean); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2605 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2606 | break; |
| 2607 | case sdma_event_e82_hw_unfreeze: |
| 2608 | break; |
| 2609 | case sdma_event_e85_link_down: |
| 2610 | break; |
| 2611 | case sdma_event_e90_sw_halted: |
| 2612 | break; |
| 2613 | } |
| 2614 | break; |
| 2615 | |
| 2616 | case sdma_state_s82_freeze_sw_clean: |
| 2617 | switch (event) { |
| 2618 | case sdma_event_e00_go_hw_down: |
| 2619 | sdma_set_state(sde, sdma_state_s00_hw_down); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2620 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2621 | break; |
| 2622 | case sdma_event_e10_go_hw_start: |
| 2623 | break; |
| 2624 | case sdma_event_e15_hw_halt_done: |
| 2625 | break; |
| 2626 | case sdma_event_e25_hw_clean_up_done: |
| 2627 | break; |
| 2628 | case sdma_event_e30_go_running: |
| 2629 | ss->go_s99_running = 1; |
| 2630 | break; |
| 2631 | case sdma_event_e40_sw_cleaned: |
| 2632 | /* notify caller this engine is done cleaning */ |
| 2633 | atomic_dec(&sde->dd->sdma_unfreeze_count); |
| 2634 | wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); |
| 2635 | break; |
| 2636 | case sdma_event_e50_hw_cleaned: |
| 2637 | break; |
| 2638 | case sdma_event_e60_hw_halted: |
| 2639 | break; |
| 2640 | case sdma_event_e70_go_idle: |
| 2641 | ss->go_s99_running = 0; |
| 2642 | break; |
| 2643 | case sdma_event_e80_hw_freeze: |
| 2644 | break; |
| 2645 | case sdma_event_e81_hw_frozen: |
| 2646 | break; |
| 2647 | case sdma_event_e82_hw_unfreeze: |
| 2648 | sdma_hw_start_up(sde); |
| 2649 | sdma_set_state(sde, ss->go_s99_running ? |
| 2650 | sdma_state_s99_running : |
| 2651 | sdma_state_s20_idle); |
| 2652 | break; |
| 2653 | case sdma_event_e85_link_down: |
| 2654 | break; |
| 2655 | case sdma_event_e90_sw_halted: |
| 2656 | break; |
| 2657 | } |
| 2658 | break; |
| 2659 | |
| 2660 | case sdma_state_s99_running: |
| 2661 | switch (event) { |
| 2662 | case sdma_event_e00_go_hw_down: |
| 2663 | sdma_set_state(sde, sdma_state_s00_hw_down); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2664 | tasklet_hi_schedule(&sde->sdma_sw_clean_up_task); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2665 | break; |
| 2666 | case sdma_event_e10_go_hw_start: |
| 2667 | break; |
| 2668 | case sdma_event_e15_hw_halt_done: |
| 2669 | break; |
| 2670 | case sdma_event_e25_hw_clean_up_done: |
| 2671 | break; |
| 2672 | case sdma_event_e30_go_running: |
| 2673 | break; |
| 2674 | case sdma_event_e40_sw_cleaned: |
| 2675 | break; |
| 2676 | case sdma_event_e50_hw_cleaned: |
| 2677 | break; |
| 2678 | case sdma_event_e60_hw_halted: |
| 2679 | need_progress = 1; |
| 2680 | sdma_err_progress_check_schedule(sde); |
| 2681 | case sdma_event_e90_sw_halted: |
| 2682 | /* |
| 2683 | * SW initiated halt does not perform engines |
| 2684 | * progress check |
| 2685 | */ |
| 2686 | sdma_set_state(sde, sdma_state_s50_hw_halt_wait); |
Amitoj Kaur Chawla | 8edf750 | 2015-11-01 16:16:40 +0530 | [diff] [blame] | 2687 | schedule_work(&sde->err_halt_worker); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2688 | break; |
| 2689 | case sdma_event_e70_go_idle: |
| 2690 | sdma_set_state(sde, sdma_state_s60_idle_halt_wait); |
| 2691 | break; |
| 2692 | case sdma_event_e85_link_down: |
| 2693 | ss->go_s99_running = 0; |
| 2694 | /* fall through */ |
| 2695 | case sdma_event_e80_hw_freeze: |
| 2696 | sdma_set_state(sde, sdma_state_s80_hw_freeze); |
| 2697 | atomic_dec(&sde->dd->sdma_unfreeze_count); |
| 2698 | wake_up_interruptible(&sde->dd->sdma_unfreeze_wq); |
| 2699 | break; |
| 2700 | case sdma_event_e81_hw_frozen: |
| 2701 | break; |
| 2702 | case sdma_event_e82_hw_unfreeze: |
| 2703 | break; |
| 2704 | } |
| 2705 | break; |
| 2706 | } |
| 2707 | |
| 2708 | ss->last_event = event; |
| 2709 | if (need_progress) |
| 2710 | sdma_make_progress(sde, 0); |
| 2711 | } |
| 2712 | |
| 2713 | /* |
| 2714 | * _extend_sdma_tx_descs() - helper to extend txreq |
| 2715 | * |
| 2716 | * This is called once the initial nominal allocation |
| 2717 | * of descriptors in the sdma_txreq is exhausted. |
| 2718 | * |
| 2719 | * The code will bump the allocation up to the max |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2720 | * of MAX_DESC (64) descriptors. There doesn't seem |
| 2721 | * much point in an interim step. The last descriptor |
| 2722 | * is reserved for coalesce buffer in order to support |
| 2723 | * cases where input packet has >MAX_DESC iovecs. |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2724 | * |
| 2725 | */ |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2726 | static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2727 | { |
| 2728 | int i; |
| 2729 | |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2730 | /* Handle last descriptor */ |
| 2731 | if (unlikely((tx->num_desc == (MAX_DESC - 1)))) { |
| 2732 | /* if tlen is 0, it is for padding, release last descriptor */ |
| 2733 | if (!tx->tlen) { |
| 2734 | tx->desc_limit = MAX_DESC; |
| 2735 | } else if (!tx->coalesce_buf) { |
| 2736 | /* allocate coalesce buffer with space for padding */ |
| 2737 | tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32), |
| 2738 | GFP_ATOMIC); |
| 2739 | if (!tx->coalesce_buf) |
Mike Marciniszyn | a5a9e8c | 2015-12-03 16:41:05 -0500 | [diff] [blame] | 2740 | goto enomem; |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2741 | tx->coalesce_idx = 0; |
| 2742 | } |
| 2743 | return 0; |
| 2744 | } |
| 2745 | |
| 2746 | if (unlikely(tx->num_desc == MAX_DESC)) |
Mike Marciniszyn | a5a9e8c | 2015-12-03 16:41:05 -0500 | [diff] [blame] | 2747 | goto enomem; |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2748 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2749 | tx->descp = kmalloc_array( |
| 2750 | MAX_DESC, |
| 2751 | sizeof(struct sdma_desc), |
| 2752 | GFP_ATOMIC); |
| 2753 | if (!tx->descp) |
Mike Marciniszyn | a5a9e8c | 2015-12-03 16:41:05 -0500 | [diff] [blame] | 2754 | goto enomem; |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2755 | |
| 2756 | /* reserve last descriptor for coalescing */ |
| 2757 | tx->desc_limit = MAX_DESC - 1; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2758 | /* copy ones already built */ |
| 2759 | for (i = 0; i < tx->num_desc; i++) |
| 2760 | tx->descp[i] = tx->descs[i]; |
| 2761 | return 0; |
Mike Marciniszyn | a5a9e8c | 2015-12-03 16:41:05 -0500 | [diff] [blame] | 2762 | enomem: |
| 2763 | sdma_txclean(dd, tx); |
| 2764 | return -ENOMEM; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2765 | } |
| 2766 | |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2767 | /* |
| 2768 | * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors |
| 2769 | * |
| 2770 | * This is called once the initial nominal allocation of descriptors |
| 2771 | * in the sdma_txreq is exhausted. |
| 2772 | * |
| 2773 | * This function calls _extend_sdma_tx_descs to extend or allocate |
| 2774 | * coalesce buffer. If there is a allocated coalesce buffer, it will |
| 2775 | * copy the input packet data into the coalesce buffer. It also adds |
| 2776 | * coalesce buffer descriptor once whe whole packet is received. |
| 2777 | * |
| 2778 | * Return: |
| 2779 | * <0 - error |
| 2780 | * 0 - coalescing, don't populate descriptor |
| 2781 | * 1 - continue with populating descriptor |
| 2782 | */ |
| 2783 | int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx, |
| 2784 | int type, void *kvaddr, struct page *page, |
| 2785 | unsigned long offset, u16 len) |
| 2786 | { |
| 2787 | int pad_len, rval; |
| 2788 | dma_addr_t addr; |
| 2789 | |
| 2790 | rval = _extend_sdma_tx_descs(dd, tx); |
| 2791 | if (rval) { |
| 2792 | sdma_txclean(dd, tx); |
| 2793 | return rval; |
| 2794 | } |
| 2795 | |
| 2796 | /* If coalesce buffer is allocated, copy data into it */ |
| 2797 | if (tx->coalesce_buf) { |
| 2798 | if (type == SDMA_MAP_NONE) { |
| 2799 | sdma_txclean(dd, tx); |
| 2800 | return -EINVAL; |
| 2801 | } |
| 2802 | |
| 2803 | if (type == SDMA_MAP_PAGE) { |
| 2804 | kvaddr = kmap(page); |
| 2805 | kvaddr += offset; |
| 2806 | } else if (WARN_ON(!kvaddr)) { |
| 2807 | sdma_txclean(dd, tx); |
| 2808 | return -EINVAL; |
| 2809 | } |
| 2810 | |
| 2811 | memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len); |
| 2812 | tx->coalesce_idx += len; |
| 2813 | if (type == SDMA_MAP_PAGE) |
| 2814 | kunmap(page); |
| 2815 | |
| 2816 | /* If there is more data, return */ |
| 2817 | if (tx->tlen - tx->coalesce_idx) |
| 2818 | return 0; |
| 2819 | |
| 2820 | /* Whole packet is received; add any padding */ |
| 2821 | pad_len = tx->packet_len & (sizeof(u32) - 1); |
| 2822 | if (pad_len) { |
| 2823 | pad_len = sizeof(u32) - pad_len; |
| 2824 | memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len); |
| 2825 | /* padding is taken care of for coalescing case */ |
| 2826 | tx->packet_len += pad_len; |
| 2827 | tx->tlen += pad_len; |
| 2828 | } |
| 2829 | |
| 2830 | /* dma map the coalesce buffer */ |
| 2831 | addr = dma_map_single(&dd->pcidev->dev, |
| 2832 | tx->coalesce_buf, |
| 2833 | tx->tlen, |
| 2834 | DMA_TO_DEVICE); |
| 2835 | |
| 2836 | if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { |
| 2837 | sdma_txclean(dd, tx); |
| 2838 | return -ENOSPC; |
| 2839 | } |
| 2840 | |
| 2841 | /* Add descriptor for coalesce buffer */ |
| 2842 | tx->desc_limit = MAX_DESC; |
| 2843 | return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx, |
| 2844 | addr, tx->tlen); |
| 2845 | } |
| 2846 | |
| 2847 | return 1; |
| 2848 | } |
| 2849 | |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2850 | /* Update sdes when the lmc changes */ |
| 2851 | void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid) |
| 2852 | { |
| 2853 | struct sdma_engine *sde; |
| 2854 | int i; |
| 2855 | u64 sreg; |
| 2856 | |
| 2857 | sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) << |
| 2858 | SD(CHECK_SLID_MASK_SHIFT)) | |
| 2859 | (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) << |
| 2860 | SD(CHECK_SLID_VALUE_SHIFT)); |
| 2861 | |
| 2862 | for (i = 0; i < dd->num_sdma; i++) { |
| 2863 | hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x", |
| 2864 | i, (u32)sreg); |
| 2865 | sde = &dd->per_sdma[i]; |
| 2866 | write_sde_csr(sde, SD(CHECK_SLID), sreg); |
| 2867 | } |
| 2868 | } |
| 2869 | |
| 2870 | /* tx not dword sized - pad */ |
| 2871 | int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) |
| 2872 | { |
| 2873 | int rval = 0; |
| 2874 | |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2875 | tx->num_desc++; |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2876 | if ((unlikely(tx->num_desc == tx->desc_limit))) { |
| 2877 | rval = _extend_sdma_tx_descs(dd, tx); |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2878 | if (rval) { |
| 2879 | sdma_txclean(dd, tx); |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2880 | return rval; |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2881 | } |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2882 | } |
Niranjana Vishwanathapura | f4d26d8 | 2015-10-26 10:28:32 -0400 | [diff] [blame] | 2883 | /* finish the one just added */ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 2884 | make_tx_sdma_desc( |
| 2885 | tx, |
| 2886 | SDMA_MAP_NONE, |
| 2887 | dd->sdma_pad_phys, |
| 2888 | sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1))); |
| 2889 | _sdma_close_tx(dd, tx); |
| 2890 | return rval; |
| 2891 | } |
| 2892 | |
| 2893 | /* |
| 2894 | * Add ahg to the sdma_txreq |
| 2895 | * |
| 2896 | * The logic will consume up to 3 |
| 2897 | * descriptors at the beginning of |
| 2898 | * sdma_txreq. |
| 2899 | */ |
| 2900 | void _sdma_txreq_ahgadd( |
| 2901 | struct sdma_txreq *tx, |
| 2902 | u8 num_ahg, |
| 2903 | u8 ahg_entry, |
| 2904 | u32 *ahg, |
| 2905 | u8 ahg_hlen) |
| 2906 | { |
| 2907 | u32 i, shift = 0, desc = 0; |
| 2908 | u8 mode; |
| 2909 | |
| 2910 | WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4); |
| 2911 | /* compute mode */ |
| 2912 | if (num_ahg == 1) |
| 2913 | mode = SDMA_AHG_APPLY_UPDATE1; |
| 2914 | else if (num_ahg <= 5) |
| 2915 | mode = SDMA_AHG_APPLY_UPDATE2; |
| 2916 | else |
| 2917 | mode = SDMA_AHG_APPLY_UPDATE3; |
| 2918 | tx->num_desc++; |
| 2919 | /* initialize to consumed descriptors to zero */ |
| 2920 | switch (mode) { |
| 2921 | case SDMA_AHG_APPLY_UPDATE3: |
| 2922 | tx->num_desc++; |
| 2923 | tx->descs[2].qw[0] = 0; |
| 2924 | tx->descs[2].qw[1] = 0; |
| 2925 | /* FALLTHROUGH */ |
| 2926 | case SDMA_AHG_APPLY_UPDATE2: |
| 2927 | tx->num_desc++; |
| 2928 | tx->descs[1].qw[0] = 0; |
| 2929 | tx->descs[1].qw[1] = 0; |
| 2930 | break; |
| 2931 | } |
| 2932 | ahg_hlen >>= 2; |
| 2933 | tx->descs[0].qw[1] |= |
| 2934 | (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK) |
| 2935 | << SDMA_DESC1_HEADER_INDEX_SHIFT) | |
| 2936 | (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK) |
| 2937 | << SDMA_DESC1_HEADER_DWS_SHIFT) | |
| 2938 | (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK) |
| 2939 | << SDMA_DESC1_HEADER_MODE_SHIFT) | |
| 2940 | (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK) |
| 2941 | << SDMA_DESC1_HEADER_UPDATE1_SHIFT); |
| 2942 | for (i = 0; i < (num_ahg - 1); i++) { |
| 2943 | if (!shift && !(i & 2)) |
| 2944 | desc++; |
| 2945 | tx->descs[desc].qw[!!(i & 2)] |= |
| 2946 | (((u64)ahg[i + 1]) |
| 2947 | << shift); |
| 2948 | shift = (shift + 32) & 63; |
| 2949 | } |
| 2950 | } |
| 2951 | |
| 2952 | /** |
| 2953 | * sdma_ahg_alloc - allocate an AHG entry |
| 2954 | * @sde: engine to allocate from |
| 2955 | * |
| 2956 | * Return: |
| 2957 | * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled, |
| 2958 | * -ENOSPC if an entry is not available |
| 2959 | */ |
| 2960 | int sdma_ahg_alloc(struct sdma_engine *sde) |
| 2961 | { |
| 2962 | int nr; |
| 2963 | int oldbit; |
| 2964 | |
| 2965 | if (!sde) { |
| 2966 | trace_hfi1_ahg_allocate(sde, -EINVAL); |
| 2967 | return -EINVAL; |
| 2968 | } |
| 2969 | while (1) { |
| 2970 | nr = ffz(ACCESS_ONCE(sde->ahg_bits)); |
| 2971 | if (nr > 31) { |
| 2972 | trace_hfi1_ahg_allocate(sde, -ENOSPC); |
| 2973 | return -ENOSPC; |
| 2974 | } |
| 2975 | oldbit = test_and_set_bit(nr, &sde->ahg_bits); |
| 2976 | if (!oldbit) |
| 2977 | break; |
| 2978 | cpu_relax(); |
| 2979 | } |
| 2980 | trace_hfi1_ahg_allocate(sde, nr); |
| 2981 | return nr; |
| 2982 | } |
| 2983 | |
| 2984 | /** |
| 2985 | * sdma_ahg_free - free an AHG entry |
| 2986 | * @sde: engine to return AHG entry |
| 2987 | * @ahg_index: index to free |
| 2988 | * |
| 2989 | * This routine frees the indicate AHG entry. |
| 2990 | */ |
| 2991 | void sdma_ahg_free(struct sdma_engine *sde, int ahg_index) |
| 2992 | { |
| 2993 | if (!sde) |
| 2994 | return; |
| 2995 | trace_hfi1_ahg_deallocate(sde, ahg_index); |
| 2996 | if (ahg_index < 0 || ahg_index > 31) |
| 2997 | return; |
| 2998 | clear_bit(ahg_index, &sde->ahg_bits); |
| 2999 | } |
| 3000 | |
| 3001 | /* |
| 3002 | * SPC freeze handling for SDMA engines. Called when the driver knows |
| 3003 | * the SPC is going into a freeze but before the freeze is fully |
| 3004 | * settled. Generally an error interrupt. |
| 3005 | * |
| 3006 | * This event will pull the engine out of running so no more entries can be |
| 3007 | * added to the engine's queue. |
| 3008 | */ |
| 3009 | void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down) |
| 3010 | { |
| 3011 | int i; |
| 3012 | enum sdma_events event = link_down ? sdma_event_e85_link_down : |
| 3013 | sdma_event_e80_hw_freeze; |
| 3014 | |
| 3015 | /* set up the wait but do not wait here */ |
| 3016 | atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); |
| 3017 | |
| 3018 | /* tell all engines to stop running and wait */ |
| 3019 | for (i = 0; i < dd->num_sdma; i++) |
| 3020 | sdma_process_event(&dd->per_sdma[i], event); |
| 3021 | |
| 3022 | /* sdma_freeze() will wait for all engines to have stopped */ |
| 3023 | } |
| 3024 | |
| 3025 | /* |
| 3026 | * SPC freeze handling for SDMA engines. Called when the driver knows |
| 3027 | * the SPC is fully frozen. |
| 3028 | */ |
| 3029 | void sdma_freeze(struct hfi1_devdata *dd) |
| 3030 | { |
| 3031 | int i; |
| 3032 | int ret; |
| 3033 | |
| 3034 | /* |
| 3035 | * Make sure all engines have moved out of the running state before |
| 3036 | * continuing. |
| 3037 | */ |
| 3038 | ret = wait_event_interruptible(dd->sdma_unfreeze_wq, |
| 3039 | atomic_read(&dd->sdma_unfreeze_count) <= 0); |
| 3040 | /* interrupted or count is negative, then unloading - just exit */ |
| 3041 | if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0) |
| 3042 | return; |
| 3043 | |
| 3044 | /* set up the count for the next wait */ |
| 3045 | atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma); |
| 3046 | |
| 3047 | /* tell all engines that the SPC is frozen, they can start cleaning */ |
| 3048 | for (i = 0; i < dd->num_sdma; i++) |
| 3049 | sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen); |
| 3050 | |
| 3051 | /* |
| 3052 | * Wait for everyone to finish software clean before exiting. The |
| 3053 | * software clean will read engine CSRs, so must be completed before |
| 3054 | * the next step, which will clear the engine CSRs. |
| 3055 | */ |
| 3056 | (void) wait_event_interruptible(dd->sdma_unfreeze_wq, |
| 3057 | atomic_read(&dd->sdma_unfreeze_count) <= 0); |
| 3058 | /* no need to check results - done no matter what */ |
| 3059 | } |
| 3060 | |
| 3061 | /* |
| 3062 | * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen. |
| 3063 | * |
| 3064 | * The SPC freeze acts like a SDMA halt and a hardware clean combined. All |
| 3065 | * that is left is a software clean. We could do it after the SPC is fully |
| 3066 | * frozen, but then we'd have to add another state to wait for the unfreeze. |
| 3067 | * Instead, just defer the software clean until the unfreeze step. |
| 3068 | */ |
| 3069 | void sdma_unfreeze(struct hfi1_devdata *dd) |
| 3070 | { |
| 3071 | int i; |
| 3072 | |
| 3073 | /* tell all engines start freeze clean up */ |
| 3074 | for (i = 0; i < dd->num_sdma; i++) |
| 3075 | sdma_process_event(&dd->per_sdma[i], |
| 3076 | sdma_event_e82_hw_unfreeze); |
| 3077 | } |
| 3078 | |
| 3079 | /** |
| 3080 | * _sdma_engine_progress_schedule() - schedule progress on engine |
| 3081 | * @sde: sdma_engine to schedule progress |
| 3082 | * |
| 3083 | */ |
| 3084 | void _sdma_engine_progress_schedule( |
| 3085 | struct sdma_engine *sde) |
| 3086 | { |
| 3087 | trace_hfi1_sdma_engine_progress(sde, sde->progress_mask); |
| 3088 | /* assume we have selected a good cpu */ |
| 3089 | write_csr(sde->dd, |
| 3090 | CCE_INT_FORCE + (8*(IS_SDMA_START/64)), sde->progress_mask); |
| 3091 | } |