Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson AB 2010 |
| 3 | * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com |
| 4 | * Author: Daniel Martensson / daniel.martensson@stericsson.com |
| 5 | * Dmitry.Tarnyagin / dmitry.tarnyagin@stericsson.com |
| 6 | * License terms: GNU General Public License (GPL) version 2 |
| 7 | */ |
| 8 | |
| 9 | #ifndef CAIF_HSI_H_ |
| 10 | #define CAIF_HSI_H_ |
| 11 | |
| 12 | #include <net/caif/caif_layer.h> |
| 13 | #include <net/caif/caif_device.h> |
| 14 | #include <linux/atomic.h> |
| 15 | |
| 16 | /* |
| 17 | * Maximum number of CAIF frames that can reside in the same HSI frame. |
| 18 | */ |
| 19 | #define CFHSI_MAX_PKTS 15 |
| 20 | |
| 21 | /* |
| 22 | * Maximum number of bytes used for the frame that can be embedded in the |
| 23 | * HSI descriptor. |
| 24 | */ |
| 25 | #define CFHSI_MAX_EMB_FRM_SZ 96 |
| 26 | |
| 27 | /* |
| 28 | * Decides if HSI buffers should be prefilled with 0xFF pattern for easier |
| 29 | * debugging. Both TX and RX buffers will be filled before the transfer. |
| 30 | */ |
| 31 | #define CFHSI_DBG_PREFILL 0 |
| 32 | |
| 33 | /* Structure describing a HSI packet descriptor. */ |
| 34 | #pragma pack(1) /* Byte alignment. */ |
| 35 | struct cfhsi_desc { |
| 36 | u8 header; |
| 37 | u8 offset; |
| 38 | u16 cffrm_len[CFHSI_MAX_PKTS]; |
| 39 | u8 emb_frm[CFHSI_MAX_EMB_FRM_SZ]; |
| 40 | }; |
| 41 | #pragma pack() /* Default alignment. */ |
| 42 | |
| 43 | /* Size of the complete HSI packet descriptor. */ |
| 44 | #define CFHSI_DESC_SZ (sizeof(struct cfhsi_desc)) |
| 45 | |
| 46 | /* |
| 47 | * Size of the complete HSI packet descriptor excluding the optional embedded |
| 48 | * CAIF frame. |
| 49 | */ |
| 50 | #define CFHSI_DESC_SHORT_SZ (CFHSI_DESC_SZ - CFHSI_MAX_EMB_FRM_SZ) |
| 51 | |
| 52 | /* |
| 53 | * Maximum bytes transferred in one transfer. |
| 54 | */ |
Daniel Martensson | 5bbed92 | 2011-10-13 11:29:28 +0000 | [diff] [blame] | 55 | #define CFHSI_MAX_CAIF_FRAME_SZ 4096 |
| 56 | |
| 57 | #define CFHSI_MAX_PAYLOAD_SZ (CFHSI_MAX_PKTS * CFHSI_MAX_CAIF_FRAME_SZ) |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 58 | |
| 59 | /* Size of the complete HSI TX buffer. */ |
| 60 | #define CFHSI_BUF_SZ_TX (CFHSI_DESC_SZ + CFHSI_MAX_PAYLOAD_SZ) |
| 61 | |
| 62 | /* Size of the complete HSI RX buffer. */ |
| 63 | #define CFHSI_BUF_SZ_RX ((2 * CFHSI_DESC_SZ) + CFHSI_MAX_PAYLOAD_SZ) |
| 64 | |
| 65 | /* Bitmasks for the HSI descriptor. */ |
| 66 | #define CFHSI_PIGGY_DESC (0x01 << 7) |
| 67 | |
| 68 | #define CFHSI_TX_STATE_IDLE 0 |
| 69 | #define CFHSI_TX_STATE_XFER 1 |
| 70 | |
| 71 | #define CFHSI_RX_STATE_DESC 0 |
| 72 | #define CFHSI_RX_STATE_PAYLOAD 1 |
| 73 | |
| 74 | /* Bitmasks for power management. */ |
| 75 | #define CFHSI_WAKE_UP 0 |
| 76 | #define CFHSI_WAKE_UP_ACK 1 |
| 77 | #define CFHSI_WAKE_DOWN_ACK 2 |
| 78 | #define CFHSI_AWAKE 3 |
Daniel Martensson | 687b13e | 2011-10-13 11:29:25 +0000 | [diff] [blame] | 79 | #define CFHSI_WAKELOCK_HELD 4 |
| 80 | #define CFHSI_SHUTDOWN 5 |
| 81 | #define CFHSI_FLUSH_FIFO 6 |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 82 | |
| 83 | #ifndef CFHSI_INACTIVITY_TOUT |
| 84 | #define CFHSI_INACTIVITY_TOUT (1 * HZ) |
| 85 | #endif /* CFHSI_INACTIVITY_TOUT */ |
| 86 | |
Daniel Martensson | 687b13e | 2011-10-13 11:29:25 +0000 | [diff] [blame] | 87 | #ifndef CFHSI_WAKE_TOUT |
| 88 | #define CFHSI_WAKE_TOUT (3 * HZ) |
| 89 | #endif /* CFHSI_WAKE_TOUT */ |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 90 | |
Daniel Martensson | 687b13e | 2011-10-13 11:29:25 +0000 | [diff] [blame] | 91 | #ifndef CFHSI_MAX_RX_RETRIES |
| 92 | #define CFHSI_MAX_RX_RETRIES (10 * HZ) |
| 93 | #endif |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 94 | |
| 95 | /* Structure implemented by the CAIF HSI driver. */ |
| 96 | struct cfhsi_drv { |
| 97 | void (*tx_done_cb) (struct cfhsi_drv *drv); |
| 98 | void (*rx_done_cb) (struct cfhsi_drv *drv); |
| 99 | void (*wake_up_cb) (struct cfhsi_drv *drv); |
| 100 | void (*wake_down_cb) (struct cfhsi_drv *drv); |
| 101 | }; |
| 102 | |
| 103 | /* Structure implemented by HSI device. */ |
| 104 | struct cfhsi_dev { |
| 105 | int (*cfhsi_up) (struct cfhsi_dev *dev); |
| 106 | int (*cfhsi_down) (struct cfhsi_dev *dev); |
| 107 | int (*cfhsi_tx) (u8 *ptr, int len, struct cfhsi_dev *dev); |
| 108 | int (*cfhsi_rx) (u8 *ptr, int len, struct cfhsi_dev *dev); |
| 109 | int (*cfhsi_wake_up) (struct cfhsi_dev *dev); |
| 110 | int (*cfhsi_wake_down) (struct cfhsi_dev *dev); |
Daniel Martensson | 5ea2ef5 | 2011-10-13 11:29:29 +0000 | [diff] [blame] | 111 | int (*cfhsi_get_peer_wake) (struct cfhsi_dev *dev, bool *status); |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 112 | int (*cfhsi_fifo_occupancy)(struct cfhsi_dev *dev, size_t *occupancy); |
| 113 | int (*cfhsi_rx_cancel)(struct cfhsi_dev *dev); |
| 114 | struct cfhsi_drv *drv; |
| 115 | }; |
| 116 | |
Daniel Martensson | 687b13e | 2011-10-13 11:29:25 +0000 | [diff] [blame] | 117 | /* Structure holds status of received CAIF frames processing */ |
| 118 | struct cfhsi_rx_state { |
| 119 | int state; |
| 120 | int nfrms; |
| 121 | int pld_len; |
| 122 | int retries; |
| 123 | bool piggy_desc; |
| 124 | }; |
| 125 | |
Dmitry Tarnyagin | ece367d | 2012-04-12 08:27:25 +0000 | [diff] [blame] | 126 | /* Priority mapping */ |
| 127 | enum { |
| 128 | CFHSI_PRIO_CTL = 0, |
| 129 | CFHSI_PRIO_VI, |
| 130 | CFHSI_PRIO_VO, |
| 131 | CFHSI_PRIO_BEBK, |
| 132 | CFHSI_PRIO_LAST, |
| 133 | }; |
| 134 | |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 135 | /* Structure implemented by CAIF HSI drivers. */ |
| 136 | struct cfhsi { |
| 137 | struct caif_dev_common cfdev; |
| 138 | struct net_device *ndev; |
| 139 | struct platform_device *pdev; |
Dmitry Tarnyagin | ece367d | 2012-04-12 08:27:25 +0000 | [diff] [blame] | 140 | struct sk_buff_head qhead[CFHSI_PRIO_LAST]; |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 141 | struct cfhsi_drv drv; |
| 142 | struct cfhsi_dev *dev; |
| 143 | int tx_state; |
Daniel Martensson | 687b13e | 2011-10-13 11:29:25 +0000 | [diff] [blame] | 144 | struct cfhsi_rx_state rx_state; |
Dmitry Tarnyagin | 28bd204 | 2011-10-13 11:29:27 +0000 | [diff] [blame] | 145 | unsigned long inactivity_timeout; |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 146 | int rx_len; |
| 147 | u8 *rx_ptr; |
| 148 | u8 *tx_buf; |
| 149 | u8 *rx_buf; |
sjur.brandeland@stericsson.com | 332ad43 | 2012-02-03 04:36:21 +0000 | [diff] [blame] | 150 | u8 *rx_flip_buf; |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 151 | spinlock_t lock; |
| 152 | int flow_off_sent; |
| 153 | u32 q_low_mark; |
| 154 | u32 q_high_mark; |
| 155 | struct list_head list; |
| 156 | struct work_struct wake_up_work; |
| 157 | struct work_struct wake_down_work; |
Daniel Martensson | 5bbed92 | 2011-10-13 11:29:28 +0000 | [diff] [blame] | 158 | struct work_struct out_of_sync_work; |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 159 | struct workqueue_struct *wq; |
| 160 | wait_queue_head_t wake_up_wait; |
| 161 | wait_queue_head_t wake_down_wait; |
| 162 | wait_queue_head_t flush_fifo_wait; |
Dmitry Tarnyagin | ece367d | 2012-04-12 08:27:25 +0000 | [diff] [blame] | 163 | struct timer_list inactivity_timer; |
Daniel Martensson | 687b13e | 2011-10-13 11:29:25 +0000 | [diff] [blame] | 164 | struct timer_list rx_slowpath_timer; |
Dmitry Tarnyagin | ece367d | 2012-04-12 08:27:25 +0000 | [diff] [blame] | 165 | |
| 166 | /* TX aggregation */ |
| 167 | unsigned long aggregation_timeout; |
| 168 | int aggregation_len; |
| 169 | struct timer_list aggregation_timer; |
| 170 | |
Dmitry.Tarnyagin | 40d6904 | 2011-06-01 03:29:18 +0000 | [diff] [blame] | 171 | unsigned long bits; |
| 172 | }; |
| 173 | |
| 174 | extern struct platform_driver cfhsi_driver; |
| 175 | |
| 176 | #endif /* CAIF_HSI_H_ */ |