Ajay Singh Parmar | 769215f | 2017-03-19 22:35:13 -0700 | [diff] [blame] | 1 | Qualcomm Technologies, Inc. |
| 2 | sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. |
| 3 | DP Controller: Required properties: |
| 4 | - compatible: Should be "qcom,dp-display". |
| 5 | - reg: Base address and length of DP hardware's memory mapped regions. |
| 6 | - reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. |
| 7 | "dp_phy" - DP PHY memory region. |
| 8 | "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. |
| 9 | "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. |
| 10 | "dp_mmss_cc" - Display Clock Control memory region. |
| 11 | "qfprom_physical" - QFPROM Phys memory region. |
| 12 | "dp_pll" - USB3 DP combo PLL memory region. |
Padmanabhan Komanduru | b6117bd | 2017-05-11 20:18:40 -0700 | [diff] [blame] | 13 | "usb3_dp_com" - USB3 DP PHY combo memory region. |
Ajay Singh Parmar | 769215f | 2017-03-19 22:35:13 -0700 | [diff] [blame] | 14 | "hdcp_physical" - DP HDCP memory region. |
| 15 | - cell-index: Specifies the controller instance. |
| 16 | - clocks: Clocks required for Display Port operation. |
| 17 | - clock-names: Names of the clocks corresponding to handles. Following clocks are required: |
| 18 | "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", |
| 19 | "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", |
| 20 | "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". |
| 21 | - gdsc-supply: phandle to gdsc regulator node. |
| 22 | - vdda-1p2-supply: phandle to vdda 1.2V regulator node. |
| 23 | - vdda-0p9-supply: phandle to vdda 0.9V regulator node. |
| 24 | - interrupt-parent phandle to the interrupt parent device node. |
| 25 | - interrupts: The interrupt signal from the DSI block. |
| 26 | - qcom,aux-en-gpio: Specifies the aux-channel enable gpio. |
| 27 | - qcom,aux-sel-gpio: Specifies the aux-channel select gpio. |
| 28 | - qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. |
Padmanabhan Komanduru | 20a21db | 2017-07-10 16:58:59 +0530 | [diff] [blame] | 29 | - qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first |
| 30 | entry in this array corresponds to the register offset |
| 31 | within DP AUX, while the remaining entries indicate the |
| 32 | programmable values. |
| 33 | - qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first |
| 34 | entry in this array corresponds to the register offset |
| 35 | within DP AUX, while the remaining entries indicate the |
| 36 | programmable values. |
| 37 | - qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first |
| 38 | entry in this array corresponds to the register offset |
| 39 | within DP AUX, while the remaining entries indicate the |
| 40 | programmable values. |
| 41 | - qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first |
| 42 | entry in this array corresponds to the register offset |
| 43 | within DP AUX, while the remaining entries indicate the |
| 44 | programmable values. |
| 45 | - qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first |
| 46 | entry in this array corresponds to the register offset |
| 47 | within DP AUX, while the remaining entries indicate the |
| 48 | programmable values. |
| 49 | - qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first |
| 50 | entry in this array corresponds to the register offset |
| 51 | within DP AUX, while the remaining entries indicate the |
| 52 | programmable values. |
| 53 | - qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first |
| 54 | entry in this array corresponds to the register offset |
| 55 | within DP AUX, while the remaining entries indicate the |
| 56 | programmable values. |
| 57 | - qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first |
| 58 | entry in this array corresponds to the register offset |
| 59 | within DP AUX, while the remaining entries indicate the |
| 60 | programmable values. |
| 61 | - qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first |
| 62 | entry in this array corresponds to the register offset |
| 63 | within DP AUX, while the remaining entries indicate the |
| 64 | programmable values. |
| 65 | - qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first |
| 66 | entry in this array corresponds to the register offset |
| 67 | within DP AUX, while the remaining entries indicate the |
| 68 | programmable values. |
Ajay Singh Parmar | 769215f | 2017-03-19 22:35:13 -0700 | [diff] [blame] | 69 | - qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. |
| 70 | - qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection. |
| 71 | - qcom,<type>-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types" |
| 72 | can be "core", "ctrl", and "phy". Within the same type, |
| 73 | there can be more than one instance of this binding, |
| 74 | in which case the entry would be appended with the |
| 75 | supply entry index. |
| 76 | e.g. qcom,ctrl-supply-entry@0 |
| 77 | -- qcom,supply-name: name of the supply (vdd/vdda/vddio) |
| 78 | -- qcom,supply-min-voltage: minimum voltage level (uV) |
| 79 | -- qcom,supply-max-voltage: maximum voltage level (uV) |
| 80 | -- qcom,supply-enable-load: load drawn (uA) from enabled supply |
| 81 | -- qcom,supply-disable-load: load drawn (uA) from disabled supply |
| 82 | -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on |
| 83 | -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on |
| 84 | -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off |
| 85 | -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off |
| 86 | - pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node |
| 87 | Refer to pinctrl-bindings.txt |
| 88 | - pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin |
| 89 | controller. These pin configurations are installed in the pinctrl |
| 90 | device node. Refer to pinctrl-bindings.txt |
| 91 | |
Tatenda Chipeperekwa | 326526e | 2017-04-24 16:51:50 -0700 | [diff] [blame] | 92 | msm_ext_disp is a device which manages the interaction between external |
| 93 | display interfaces, e.g. Display Port, and the audio subsystem. |
| 94 | |
| 95 | Optional properties: |
| 96 | - qcom,ext-disp: phandle for msm-ext-display module |
| 97 | - compatible: Must be "qcom,msm-ext-disp" |
| 98 | |
| 99 | [Optional child nodes]: These nodes are for devices which are |
| 100 | dependent on msm_ext_disp. If msm_ext_disp is disabled then |
| 101 | these devices will be disabled as well. Ex. Audio Codec device. |
| 102 | |
| 103 | - ext_disp_audio_codec: Node for Audio Codec. |
| 104 | - compatible : "qcom,msm-ext-disp-audio-codec-rx"; |
| 105 | |
Ajay Singh Parmar | 769215f | 2017-03-19 22:35:13 -0700 | [diff] [blame] | 106 | Example: |
Tatenda Chipeperekwa | 326526e | 2017-04-24 16:51:50 -0700 | [diff] [blame] | 107 | ext_disp: qcom,msm-ext-disp { |
| 108 | compatible = "qcom,msm-ext-disp"; |
| 109 | ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { |
| 110 | compatible = "qcom,msm-ext-disp-audio-codec-rx"; |
| 111 | }; |
| 112 | }; |
| 113 | |
Ajay Singh Parmar | 769215f | 2017-03-19 22:35:13 -0700 | [diff] [blame] | 114 | sde_dp: qcom,dp_display@0{ |
| 115 | cell-index = <0>; |
| 116 | compatible = "qcom,dp-display"; |
| 117 | |
| 118 | gdsc-supply = <&mdss_core_gdsc>; |
| 119 | vdda-1p2-supply = <&pm8998_l26>; |
| 120 | vdda-0p9-supply = <&pm8998_l1>; |
| 121 | |
| 122 | reg = <0xae90000 0xa84>, |
| 123 | <0x88eaa00 0x200>, |
| 124 | <0x88ea200 0x200>, |
| 125 | <0x88ea600 0x200>, |
| 126 | <0xaf02000 0x1a0>, |
| 127 | <0x780000 0x621c>, |
| 128 | <0x88ea030 0x10>, |
| 129 | <0x88e8000 0x621c>, |
| 130 | <0x0aee1000 0x034>; |
| 131 | reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", |
| 132 | "dp_mmss_cc", "qfprom_physical", "dp_pll", |
| 133 | "usb3_dp_com", "hdcp_physical"; |
| 134 | |
| 135 | interrupt-parent = <&mdss_mdp>; |
| 136 | interrupts = <12 0>; |
| 137 | |
| 138 | clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, |
| 139 | <&clock_rpmh RPMH_CXO_CLK>, |
| 140 | <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, |
| 141 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| 142 | <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, |
| 143 | <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, |
| 144 | <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, |
| 145 | <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, |
| 146 | <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, |
| 147 | <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, |
| 148 | <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>; |
| 149 | clock-names = "core_aux_clk", "core_usb_ref_clk_src", |
| 150 | "core_usb_ref_clk", "core_usb_cfg_ahb_clk", |
| 151 | "core_usb_pipe_clk", "ctrl_link_clk", |
| 152 | "ctrl_link_iface_clk", "ctrl_crypto_clk", |
| 153 | "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent"; |
| 154 | |
| 155 | qcom,dp-usbpd-detection = <&pmi8998_pdphy>; |
Tatenda Chipeperekwa | 326526e | 2017-04-24 16:51:50 -0700 | [diff] [blame] | 156 | qcom,ext-disp = <&ext_disp>; |
Ajay Singh Parmar | 769215f | 2017-03-19 22:35:13 -0700 | [diff] [blame] | 157 | |
Padmanabhan Komanduru | 20a21db | 2017-07-10 16:58:59 +0530 | [diff] [blame] | 158 | qcom,aux-cfg0-settings = [1c 00]; |
| 159 | qcom,aux-cfg1-settings = [20 13 23 1d]; |
| 160 | qcom,aux-cfg2-settings = [24 00]; |
| 161 | qcom,aux-cfg3-settings = [28 00]; |
| 162 | qcom,aux-cfg4-settings = [2c 0a]; |
| 163 | qcom,aux-cfg5-settings = [30 26]; |
| 164 | qcom,aux-cfg6-settings = [34 0a]; |
| 165 | qcom,aux-cfg7-settings = [38 03]; |
| 166 | qcom,aux-cfg8-settings = [3c bb]; |
| 167 | qcom,aux-cfg9-settings = [40 03]; |
Ajay Singh Parmar | 769215f | 2017-03-19 22:35:13 -0700 | [diff] [blame] | 168 | qcom,max-pclk-frequency-khz = <593470>; |
| 169 | pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; |
| 170 | pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; |
| 171 | pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; |
| 172 | qcom,aux-en-gpio = <&tlmm 43 0>; |
| 173 | qcom,aux-sel-gpio = <&tlmm 51 0>; |
| 174 | qcom,usbplug-cc-gpio = <&tlmm 38 0>; |
| 175 | qcom,core-supply-entries { |
| 176 | #address-cells = <1>; |
| 177 | #size-cells = <0>; |
| 178 | |
| 179 | qcom,core-supply-entry@0 { |
| 180 | reg = <0>; |
| 181 | qcom,supply-name = "gdsc"; |
| 182 | qcom,supply-min-voltage = <0>; |
| 183 | qcom,supply-max-voltage = <0>; |
| 184 | qcom,supply-enable-load = <0>; |
| 185 | qcom,supply-disable-load = <0>; |
| 186 | }; |
| 187 | }; |
| 188 | |
| 189 | qcom,ctrl-supply-entries { |
| 190 | #address-cells = <1>; |
| 191 | #size-cells = <0>; |
| 192 | |
| 193 | qcom,ctrl-supply-entry@0 { |
| 194 | reg = <0>; |
| 195 | qcom,supply-name = "vdda-1p2"; |
| 196 | qcom,supply-min-voltage = <1200000>; |
| 197 | qcom,supply-max-voltage = <1200000>; |
| 198 | qcom,supply-enable-load = <21800>; |
| 199 | qcom,supply-disable-load = <4>; |
| 200 | }; |
| 201 | }; |
| 202 | |
| 203 | qcom,phy-supply-entries { |
| 204 | #address-cells = <1>; |
| 205 | #size-cells = <0>; |
| 206 | |
| 207 | qcom,phy-supply-entry@0 { |
| 208 | reg = <0>; |
| 209 | qcom,supply-name = "vdda-0p9"; |
| 210 | qcom,supply-min-voltage = <880000>; |
| 211 | qcom,supply-max-voltage = <880000>; |
| 212 | qcom,supply-enable-load = <36000>; |
| 213 | qcom,supply-disable-load = <32>; |
| 214 | }; |
| 215 | }; |
| 216 | }; |
| 217 | }; |