Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1 | /* |
Vicky Wallace | 762dbc3 | 2018-01-25 17:21:13 -0800 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "clk: %s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/clk-provider.h> |
| 25 | #include <linux/regmap.h> |
| 26 | #include <linux/reset-controller.h> |
| 27 | |
| 28 | #include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h> |
| 29 | |
| 30 | #include "common.h" |
| 31 | #include "clk-regmap.h" |
| 32 | #include "clk-pll.h" |
| 33 | #include "clk-rcg.h" |
| 34 | #include "clk-branch.h" |
| 35 | #include "reset.h" |
| 36 | |
| 37 | #include "clk-alpha-pll.h" |
| 38 | #include "vdd-level-sdm845.h" |
| 39 | |
| 40 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
| 41 | |
| 42 | static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner); |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 43 | static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_CX_NUM, 1, vdd_corner); |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 44 | |
| 45 | enum { |
| 46 | P_BI_TCXO, |
| 47 | P_CORE_BI_PLL_TEST_SE, |
| 48 | P_GPLL0_OUT_EVEN, |
| 49 | P_GPLL0_OUT_MAIN, |
| 50 | P_GPLL4_OUT_EVEN, |
| 51 | P_SLEEP_CLK, |
| 52 | }; |
| 53 | |
| 54 | static const struct parent_map gcc_parent_map_0[] = { |
| 55 | { P_BI_TCXO, 0 }, |
| 56 | { P_GPLL0_OUT_MAIN, 1 }, |
| 57 | { P_GPLL0_OUT_EVEN, 6 }, |
| 58 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 59 | }; |
| 60 | |
| 61 | static const char * const gcc_parent_names_0[] = { |
| 62 | "bi_tcxo", |
| 63 | "gpll0", |
| 64 | "gpll0_out_even", |
| 65 | "core_bi_pll_test_se", |
| 66 | }; |
| 67 | |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 68 | static const char * const gcc_parent_names_ao_0[] = { |
| 69 | "bi_tcxo_ao", |
| 70 | "gpll0", |
| 71 | "gpll0_out_even", |
| 72 | "core_bi_pll_test_se", |
| 73 | }; |
| 74 | |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 75 | static const struct parent_map gcc_parent_map_1[] = { |
| 76 | { P_BI_TCXO, 0 }, |
| 77 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 78 | }; |
| 79 | |
| 80 | static const char * const gcc_parent_names_1[] = { |
| 81 | "bi_tcxo", |
| 82 | "core_bi_pll_test_se", |
| 83 | }; |
| 84 | |
| 85 | static const struct parent_map gcc_parent_map_2[] = { |
| 86 | { P_BI_TCXO, 0 }, |
| 87 | { P_GPLL0_OUT_MAIN, 1 }, |
| 88 | { P_SLEEP_CLK, 5 }, |
| 89 | { P_GPLL0_OUT_EVEN, 6 }, |
| 90 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 91 | }; |
| 92 | |
| 93 | static const char * const gcc_parent_names_2[] = { |
| 94 | "bi_tcxo", |
| 95 | "gpll0", |
| 96 | "core_pi_sleep_clk", |
| 97 | "gpll0_out_even", |
| 98 | "core_bi_pll_test_se", |
| 99 | }; |
| 100 | |
| 101 | static const struct parent_map gcc_parent_map_3[] = { |
| 102 | { P_BI_TCXO, 0 }, |
| 103 | { P_SLEEP_CLK, 5 }, |
| 104 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 105 | }; |
| 106 | |
| 107 | static const char * const gcc_parent_names_3[] = { |
| 108 | "bi_tcxo", |
| 109 | "core_pi_sleep_clk", |
| 110 | "core_bi_pll_test_se", |
| 111 | }; |
| 112 | |
| 113 | static const struct parent_map gcc_parent_map_4[] = { |
| 114 | { P_BI_TCXO, 0 }, |
| 115 | { P_GPLL0_OUT_MAIN, 1 }, |
| 116 | { P_GPLL4_OUT_EVEN, 2 }, |
| 117 | { P_GPLL0_OUT_EVEN, 6 }, |
| 118 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 119 | }; |
| 120 | |
| 121 | static const char * const gcc_parent_names_4[] = { |
| 122 | "bi_tcxo", |
| 123 | "gpll0", |
| 124 | "gpll4_out_even", |
| 125 | "gpll0_out_even", |
| 126 | "core_bi_pll_test_se", |
| 127 | }; |
| 128 | |
| 129 | static struct pll_vco trion_vco[] = { |
| 130 | { 249600000, 2000000000, 0 }, |
| 131 | }; |
| 132 | |
| 133 | static struct clk_alpha_pll gpll0 = { |
| 134 | .offset = 0x0, |
| 135 | .vco_table = trion_vco, |
| 136 | .num_vco = ARRAY_SIZE(trion_vco), |
| 137 | .type = TRION_PLL, |
| 138 | .clkr = { |
| 139 | .enable_reg = 0x6d000, |
| 140 | .enable_mask = BIT(0), |
| 141 | .hw.init = &(struct clk_init_data){ |
| 142 | .name = "gpll0", |
| 143 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 144 | .num_parents = 1, |
| 145 | .ops = &clk_trion_fixed_pll_ops, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 146 | }, |
| 147 | }, |
| 148 | }; |
| 149 | |
| 150 | static const struct clk_div_table post_div_table_trion_even[] = { |
| 151 | { 0x0, 1 }, |
| 152 | { 0x1, 2 }, |
| 153 | { 0x3, 4 }, |
| 154 | { 0x7, 8 }, |
| 155 | { } |
| 156 | }; |
| 157 | |
| 158 | static struct clk_alpha_pll_postdiv gpll0_out_even = { |
| 159 | .offset = 0x0, |
| 160 | .post_div_shift = 8, |
| 161 | .post_div_table = post_div_table_trion_even, |
| 162 | .num_post_div = ARRAY_SIZE(post_div_table_trion_even), |
| 163 | .width = 4, |
| 164 | .clkr.hw.init = &(struct clk_init_data){ |
| 165 | .name = "gpll0_out_even", |
| 166 | .parent_names = (const char *[]){ "gpll0" }, |
| 167 | .num_parents = 1, |
| 168 | .ops = &clk_trion_pll_postdiv_ops, |
| 169 | }, |
| 170 | }; |
| 171 | |
| 172 | static struct clk_alpha_pll gpll4 = { |
| 173 | .offset = 0x76000, |
| 174 | .vco_table = trion_vco, |
| 175 | .num_vco = ARRAY_SIZE(trion_vco), |
| 176 | .type = TRION_PLL, |
| 177 | .clkr = { |
| 178 | .enable_reg = 0x6d000, |
| 179 | .enable_mask = BIT(4), |
| 180 | .hw.init = &(struct clk_init_data){ |
| 181 | .name = "gpll4", |
| 182 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 183 | .num_parents = 1, |
| 184 | .ops = &clk_trion_fixed_pll_ops, |
| 185 | VDD_CX_FMAX_MAP4( |
| 186 | MIN, 615000000, |
| 187 | LOW, 1066000000, |
| 188 | LOW_L1, 1600000000, |
| 189 | NOMINAL, 2000000000), |
| 190 | }, |
| 191 | }, |
| 192 | }; |
| 193 | |
| 194 | static struct clk_alpha_pll_postdiv gpll4_out_even = { |
| 195 | .offset = 0x76000, |
| 196 | .post_div_shift = 8, |
| 197 | .post_div_table = post_div_table_trion_even, |
| 198 | .num_post_div = ARRAY_SIZE(post_div_table_trion_even), |
| 199 | .width = 4, |
| 200 | .clkr.hw.init = &(struct clk_init_data){ |
| 201 | .name = "gpll4_out_even", |
| 202 | .parent_names = (const char *[]){ "gpll4" }, |
| 203 | .num_parents = 1, |
| 204 | .ops = &clk_trion_pll_postdiv_ops, |
| 205 | }, |
| 206 | }; |
| 207 | |
| 208 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = { |
| 209 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 210 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 211 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 212 | { } |
| 213 | }; |
| 214 | |
| 215 | static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = { |
| 216 | .cmd_rcgr = 0x11024, |
| 217 | .mnd_width = 8, |
| 218 | .hid_width = 5, |
| 219 | .parent_map = gcc_parent_map_0, |
| 220 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 221 | .clkr.hw.init = &(struct clk_init_data){ |
| 222 | .name = "gcc_blsp1_qup1_i2c_apps_clk_src", |
| 223 | .parent_names = gcc_parent_names_0, |
| 224 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 225 | .ops = &clk_rcg2_ops, |
| 226 | VDD_CX_FMAX_MAP3( |
| 227 | MIN, 9600000, |
| 228 | LOWER, 19200000, |
| 229 | LOW, 50000000), |
| 230 | }, |
| 231 | }; |
| 232 | |
| 233 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = { |
| 234 | F(960000, P_BI_TCXO, 10, 1, 2), |
| 235 | F(4800000, P_BI_TCXO, 4, 0, 0), |
| 236 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 237 | F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4), |
| 238 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 239 | F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2), |
| 240 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), |
| 241 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 242 | { } |
| 243 | }; |
| 244 | |
| 245 | static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = { |
| 246 | .cmd_rcgr = 0x1100c, |
| 247 | .mnd_width = 8, |
| 248 | .hid_width = 5, |
| 249 | .parent_map = gcc_parent_map_0, |
| 250 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 251 | .clkr.hw.init = &(struct clk_init_data){ |
| 252 | .name = "gcc_blsp1_qup1_spi_apps_clk_src", |
| 253 | .parent_names = gcc_parent_names_0, |
| 254 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 255 | .ops = &clk_rcg2_ops, |
| 256 | VDD_CX_FMAX_MAP4( |
| 257 | MIN, 9600000, |
| 258 | LOWER, 19200000, |
| 259 | LOW, 25000000, |
| 260 | NOMINAL, 50000000), |
| 261 | }, |
| 262 | }; |
| 263 | |
| 264 | static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = { |
| 265 | .cmd_rcgr = 0x13024, |
| 266 | .mnd_width = 8, |
| 267 | .hid_width = 5, |
| 268 | .parent_map = gcc_parent_map_0, |
| 269 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 270 | .clkr.hw.init = &(struct clk_init_data){ |
| 271 | .name = "gcc_blsp1_qup2_i2c_apps_clk_src", |
| 272 | .parent_names = gcc_parent_names_0, |
| 273 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 274 | .ops = &clk_rcg2_ops, |
| 275 | VDD_CX_FMAX_MAP3( |
| 276 | MIN, 9600000, |
| 277 | LOWER, 19200000, |
| 278 | LOW, 50000000), |
| 279 | }, |
| 280 | }; |
| 281 | |
| 282 | static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = { |
| 283 | .cmd_rcgr = 0x1300c, |
| 284 | .mnd_width = 8, |
| 285 | .hid_width = 5, |
| 286 | .parent_map = gcc_parent_map_0, |
| 287 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 288 | .clkr.hw.init = &(struct clk_init_data){ |
| 289 | .name = "gcc_blsp1_qup2_spi_apps_clk_src", |
| 290 | .parent_names = gcc_parent_names_0, |
| 291 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 292 | .ops = &clk_rcg2_ops, |
| 293 | VDD_CX_FMAX_MAP4( |
| 294 | MIN, 9600000, |
| 295 | LOWER, 19200000, |
| 296 | LOW, 25000000, |
| 297 | NOMINAL, 50000000), |
| 298 | }, |
| 299 | }; |
| 300 | |
| 301 | static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = { |
| 302 | .cmd_rcgr = 0x15024, |
| 303 | .mnd_width = 8, |
| 304 | .hid_width = 5, |
| 305 | .parent_map = gcc_parent_map_0, |
| 306 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 307 | .clkr.hw.init = &(struct clk_init_data){ |
| 308 | .name = "gcc_blsp1_qup3_i2c_apps_clk_src", |
| 309 | .parent_names = gcc_parent_names_0, |
| 310 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 311 | .ops = &clk_rcg2_ops, |
| 312 | VDD_CX_FMAX_MAP3( |
| 313 | MIN, 9600000, |
| 314 | LOWER, 19200000, |
| 315 | LOW, 50000000), |
| 316 | }, |
| 317 | }; |
| 318 | |
| 319 | static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = { |
| 320 | .cmd_rcgr = 0x1500c, |
| 321 | .mnd_width = 8, |
| 322 | .hid_width = 5, |
| 323 | .parent_map = gcc_parent_map_0, |
| 324 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 325 | .clkr.hw.init = &(struct clk_init_data){ |
| 326 | .name = "gcc_blsp1_qup3_spi_apps_clk_src", |
| 327 | .parent_names = gcc_parent_names_0, |
| 328 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 329 | .ops = &clk_rcg2_ops, |
| 330 | VDD_CX_FMAX_MAP4( |
| 331 | MIN, 9600000, |
| 332 | LOWER, 19200000, |
| 333 | LOW, 25000000, |
| 334 | NOMINAL, 50000000), |
| 335 | }, |
| 336 | }; |
| 337 | |
| 338 | static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = { |
| 339 | .cmd_rcgr = 0x17024, |
| 340 | .mnd_width = 8, |
| 341 | .hid_width = 5, |
| 342 | .parent_map = gcc_parent_map_0, |
| 343 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 344 | .clkr.hw.init = &(struct clk_init_data){ |
| 345 | .name = "gcc_blsp1_qup4_i2c_apps_clk_src", |
| 346 | .parent_names = gcc_parent_names_0, |
| 347 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 348 | .ops = &clk_rcg2_ops, |
| 349 | VDD_CX_FMAX_MAP3( |
| 350 | MIN, 9600000, |
| 351 | LOWER, 19200000, |
| 352 | LOW, 50000000), |
| 353 | }, |
| 354 | }; |
| 355 | |
| 356 | static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = { |
| 357 | .cmd_rcgr = 0x1700c, |
| 358 | .mnd_width = 8, |
| 359 | .hid_width = 5, |
| 360 | .parent_map = gcc_parent_map_0, |
| 361 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 362 | .clkr.hw.init = &(struct clk_init_data){ |
| 363 | .name = "gcc_blsp1_qup4_spi_apps_clk_src", |
| 364 | .parent_names = gcc_parent_names_0, |
| 365 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 366 | .ops = &clk_rcg2_ops, |
| 367 | VDD_CX_FMAX_MAP4( |
| 368 | MIN, 9600000, |
| 369 | LOWER, 19200000, |
| 370 | LOW, 25000000, |
| 371 | NOMINAL, 50000000), |
| 372 | }, |
| 373 | }; |
| 374 | |
| 375 | static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = { |
| 376 | F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625), |
| 377 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), |
| 378 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 379 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), |
| 380 | F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75), |
| 381 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 382 | F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2), |
| 383 | F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), |
| 384 | F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2), |
| 385 | F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2), |
| 386 | F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2), |
| 387 | F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2), |
| 388 | F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), |
| 389 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), |
| 390 | F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2), |
| 391 | F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2), |
| 392 | F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2), |
| 393 | F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), |
| 394 | F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), |
| 395 | F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), |
| 396 | F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), |
| 397 | F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), |
| 398 | F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), |
| 399 | F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), |
| 400 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 401 | F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), |
| 402 | { } |
| 403 | }; |
| 404 | |
| 405 | |
| 406 | static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = { |
| 407 | .cmd_rcgr = 0x1200c, |
| 408 | .mnd_width = 16, |
| 409 | .hid_width = 5, |
| 410 | .parent_map = gcc_parent_map_0, |
| 411 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 412 | .clkr.hw.init = &(struct clk_init_data){ |
| 413 | .name = "gcc_blsp1_uart1_apps_clk_src", |
| 414 | .parent_names = gcc_parent_names_0, |
| 415 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 416 | .ops = &clk_rcg2_ops, |
| 417 | VDD_CX_FMAX_MAP4( |
| 418 | MIN, 9600000, |
| 419 | LOWER, 19200000, |
| 420 | LOW, 48000000, |
| 421 | NOMINAL, 63157895), |
| 422 | }, |
| 423 | }; |
| 424 | |
| 425 | static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = { |
| 426 | .cmd_rcgr = 0x1400c, |
| 427 | .mnd_width = 16, |
| 428 | .hid_width = 5, |
| 429 | .parent_map = gcc_parent_map_0, |
| 430 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 431 | .clkr.hw.init = &(struct clk_init_data){ |
| 432 | .name = "gcc_blsp1_uart2_apps_clk_src", |
| 433 | .parent_names = gcc_parent_names_0, |
| 434 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 435 | .ops = &clk_rcg2_ops, |
| 436 | VDD_CX_FMAX_MAP4( |
| 437 | MIN, 9600000, |
| 438 | LOWER, 19200000, |
| 439 | LOW, 48000000, |
| 440 | NOMINAL, 63157895), |
| 441 | }, |
| 442 | }; |
| 443 | |
| 444 | static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = { |
| 445 | .cmd_rcgr = 0x1600c, |
| 446 | .mnd_width = 16, |
| 447 | .hid_width = 5, |
| 448 | .parent_map = gcc_parent_map_0, |
| 449 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 450 | .clkr.hw.init = &(struct clk_init_data){ |
| 451 | .name = "gcc_blsp1_uart3_apps_clk_src", |
| 452 | .parent_names = gcc_parent_names_0, |
| 453 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 454 | .ops = &clk_rcg2_ops, |
| 455 | VDD_CX_FMAX_MAP4( |
| 456 | MIN, 9600000, |
| 457 | LOWER, 19200000, |
| 458 | LOW, 48000000, |
| 459 | NOMINAL, 63157895), |
| 460 | }, |
| 461 | }; |
| 462 | |
| 463 | static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = { |
| 464 | .cmd_rcgr = 0x1800c, |
| 465 | .mnd_width = 16, |
| 466 | .hid_width = 5, |
| 467 | .parent_map = gcc_parent_map_0, |
| 468 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 469 | .clkr.hw.init = &(struct clk_init_data){ |
| 470 | .name = "gcc_blsp1_uart4_apps_clk_src", |
| 471 | .parent_names = gcc_parent_names_0, |
| 472 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 473 | .ops = &clk_rcg2_ops, |
| 474 | VDD_CX_FMAX_MAP4( |
| 475 | MIN, 9600000, |
| 476 | LOWER, 19200000, |
| 477 | LOW, 48000000, |
| 478 | NOMINAL, 63157895), |
| 479 | }, |
| 480 | }; |
| 481 | |
| 482 | static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { |
| 483 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 484 | { } |
| 485 | }; |
| 486 | |
| 487 | static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { |
| 488 | .cmd_rcgr = 0x24010, |
| 489 | .mnd_width = 0, |
| 490 | .hid_width = 5, |
| 491 | .parent_map = gcc_parent_map_0, |
| 492 | .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, |
| 493 | .clkr.hw.init = &(struct clk_init_data){ |
| 494 | .name = "gcc_cpuss_ahb_clk_src", |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 495 | .parent_names = gcc_parent_names_ao_0, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 496 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 497 | .ops = &clk_rcg2_ops, |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 498 | VDD_CX_FMAX_MAP1_AO( |
| 499 | MIN, 19200000), |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 500 | }, |
| 501 | }; |
| 502 | |
| 503 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { |
| 504 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 505 | { } |
| 506 | }; |
| 507 | |
| 508 | static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { |
| 509 | .cmd_rcgr = 0x2402c, |
| 510 | .mnd_width = 0, |
| 511 | .hid_width = 5, |
| 512 | .parent_map = gcc_parent_map_0, |
| 513 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
| 514 | .clkr.hw.init = &(struct clk_init_data){ |
| 515 | .name = "gcc_cpuss_rbcpr_clk_src", |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 516 | .parent_names = gcc_parent_names_ao_0, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 517 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 518 | .ops = &clk_rcg2_ops, |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 519 | VDD_CX_FMAX_MAP1_AO( |
| 520 | MIN, 19200000), |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 521 | }, |
| 522 | }; |
| 523 | |
| 524 | static const struct freq_tbl ftbl_gcc_emac_clk_src[] = { |
Vicky Wallace | cbfd23e | 2017-12-07 18:05:34 -0800 | [diff] [blame] | 525 | F(2500000, P_BI_TCXO, 1, 25, 192), |
| 526 | F(5000000, P_BI_TCXO, 1, 25, 96), |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 527 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Vicky Wallace | cbfd23e | 2017-12-07 18:05:34 -0800 | [diff] [blame] | 528 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 529 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 530 | F(125000000, P_GPLL4_OUT_EVEN, 4, 0, 0), |
| 531 | F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0), |
| 532 | { } |
| 533 | }; |
| 534 | |
| 535 | static struct clk_rcg2 gcc_emac_clk_src = { |
| 536 | .cmd_rcgr = 0x47020, |
| 537 | .mnd_width = 8, |
| 538 | .hid_width = 5, |
| 539 | .parent_map = gcc_parent_map_4, |
| 540 | .freq_tbl = ftbl_gcc_emac_clk_src, |
| 541 | .clkr.hw.init = &(struct clk_init_data){ |
| 542 | .name = "gcc_emac_clk_src", |
| 543 | .parent_names = gcc_parent_names_4, |
| 544 | .num_parents = 5, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 545 | .ops = &clk_rcg2_ops, |
| 546 | VDD_CX_FMAX_MAP4( |
| 547 | MIN, 19200000, |
| 548 | LOWER, 50000000, |
| 549 | LOW, 125000000, |
| 550 | NOMINAL, 250000000), |
| 551 | }, |
| 552 | }; |
| 553 | |
Shefali Jain | 61b0182 | 2018-04-10 16:00:48 +0530 | [diff] [blame] | 554 | static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { |
| 555 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 556 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 557 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 558 | F(125000000, P_GPLL4_OUT_EVEN, 4, 0, 0), |
| 559 | F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0), |
| 560 | { } |
| 561 | }; |
| 562 | |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 563 | static struct clk_rcg2 gcc_emac_ptp_clk_src = { |
| 564 | .cmd_rcgr = 0x47038, |
| 565 | .mnd_width = 0, |
| 566 | .hid_width = 5, |
| 567 | .parent_map = gcc_parent_map_4, |
Shefali Jain | 61b0182 | 2018-04-10 16:00:48 +0530 | [diff] [blame] | 568 | .freq_tbl = ftbl_gcc_emac_ptp_clk_src, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 569 | .clkr.hw.init = &(struct clk_init_data){ |
| 570 | .name = "gcc_emac_ptp_clk_src", |
| 571 | .parent_names = gcc_parent_names_4, |
| 572 | .num_parents = 5, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 573 | .ops = &clk_rcg2_ops, |
| 574 | VDD_CX_FMAX_MAP4( |
| 575 | MIN, 19200000, |
| 576 | LOWER, 50000000, |
| 577 | LOW, 125000000, |
| 578 | NOMINAL, 250000000), |
| 579 | }, |
| 580 | }; |
| 581 | |
| 582 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { |
| 583 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 584 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 585 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 586 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 587 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 588 | { } |
| 589 | }; |
| 590 | |
| 591 | static struct clk_rcg2 gcc_gp1_clk_src = { |
| 592 | .cmd_rcgr = 0x2b004, |
| 593 | .mnd_width = 8, |
| 594 | .hid_width = 5, |
| 595 | .parent_map = gcc_parent_map_2, |
| 596 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 597 | .clkr.hw.init = &(struct clk_init_data){ |
| 598 | .name = "gcc_gp1_clk_src", |
| 599 | .parent_names = gcc_parent_names_2, |
| 600 | .num_parents = 5, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 601 | .ops = &clk_rcg2_ops, |
| 602 | VDD_CX_FMAX_MAP4( |
| 603 | MIN, 19200000, |
| 604 | LOWER, 50000000, |
| 605 | LOW, 100000000, |
| 606 | NOMINAL, 200000000), |
| 607 | }, |
| 608 | }; |
| 609 | |
| 610 | static struct clk_rcg2 gcc_gp2_clk_src = { |
| 611 | .cmd_rcgr = 0x2c004, |
| 612 | .mnd_width = 8, |
| 613 | .hid_width = 5, |
| 614 | .parent_map = gcc_parent_map_2, |
| 615 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 616 | .clkr.hw.init = &(struct clk_init_data){ |
| 617 | .name = "gcc_gp2_clk_src", |
| 618 | .parent_names = gcc_parent_names_2, |
| 619 | .num_parents = 5, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 620 | .ops = &clk_rcg2_ops, |
| 621 | VDD_CX_FMAX_MAP4( |
| 622 | MIN, 19200000, |
| 623 | LOWER, 50000000, |
| 624 | LOW, 100000000, |
| 625 | NOMINAL, 200000000), |
| 626 | }, |
| 627 | }; |
| 628 | |
| 629 | static struct clk_rcg2 gcc_gp3_clk_src = { |
| 630 | .cmd_rcgr = 0x2d004, |
| 631 | .mnd_width = 8, |
| 632 | .hid_width = 5, |
| 633 | .parent_map = gcc_parent_map_2, |
| 634 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 635 | .clkr.hw.init = &(struct clk_init_data){ |
| 636 | .name = "gcc_gp3_clk_src", |
| 637 | .parent_names = gcc_parent_names_2, |
| 638 | .num_parents = 5, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 639 | .ops = &clk_rcg2_ops, |
| 640 | VDD_CX_FMAX_MAP4( |
| 641 | MIN, 19200000, |
| 642 | LOWER, 50000000, |
| 643 | LOW, 100000000, |
| 644 | NOMINAL, 200000000), |
| 645 | }, |
| 646 | }; |
| 647 | |
| 648 | static const struct freq_tbl ftbl_gcc_pcie_aux_phy_clk_src[] = { |
| 649 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 650 | { } |
| 651 | }; |
| 652 | |
| 653 | static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { |
| 654 | .cmd_rcgr = 0x37030, |
| 655 | .mnd_width = 16, |
| 656 | .hid_width = 5, |
| 657 | .parent_map = gcc_parent_map_3, |
| 658 | .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src, |
| 659 | .clkr.hw.init = &(struct clk_init_data){ |
| 660 | .name = "gcc_pcie_aux_phy_clk_src", |
| 661 | .parent_names = gcc_parent_names_3, |
| 662 | .num_parents = 3, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 663 | .ops = &clk_rcg2_ops, |
| 664 | VDD_CX_FMAX_MAP1( |
| 665 | MIN, 19200000), |
| 666 | }, |
| 667 | }; |
| 668 | |
| 669 | static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { |
| 670 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 671 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 672 | { } |
| 673 | }; |
| 674 | |
| 675 | static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { |
| 676 | .cmd_rcgr = 0x39010, |
| 677 | .mnd_width = 0, |
| 678 | .hid_width = 5, |
| 679 | .parent_map = gcc_parent_map_0, |
| 680 | .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, |
| 681 | .clkr.hw.init = &(struct clk_init_data){ |
| 682 | .name = "gcc_pcie_phy_refgen_clk_src", |
| 683 | .parent_names = gcc_parent_names_0, |
| 684 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 685 | .ops = &clk_rcg2_ops, |
| 686 | VDD_CX_FMAX_MAP2( |
| 687 | MIN, 19200000, |
| 688 | LOW, 100000000), |
| 689 | }, |
| 690 | }; |
| 691 | |
| 692 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { |
| 693 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 694 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 695 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 696 | { } |
| 697 | }; |
| 698 | |
| 699 | static struct clk_rcg2 gcc_pdm2_clk_src = { |
| 700 | .cmd_rcgr = 0x19010, |
| 701 | .mnd_width = 0, |
| 702 | .hid_width = 5, |
| 703 | .parent_map = gcc_parent_map_0, |
| 704 | .freq_tbl = ftbl_gcc_pdm2_clk_src, |
| 705 | .clkr.hw.init = &(struct clk_init_data){ |
| 706 | .name = "gcc_pdm2_clk_src", |
| 707 | .parent_names = gcc_parent_names_0, |
| 708 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 709 | .ops = &clk_rcg2_ops, |
| 710 | VDD_CX_FMAX_MAP3( |
| 711 | MIN, 9600000, |
| 712 | LOWER, 19200000, |
| 713 | LOW, 60000000), |
| 714 | }, |
| 715 | }; |
| 716 | |
| 717 | static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { |
| 718 | .cmd_rcgr = 0xf00c, |
| 719 | .mnd_width = 8, |
| 720 | .hid_width = 5, |
| 721 | .parent_map = gcc_parent_map_0, |
| 722 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 723 | .clkr.hw.init = &(struct clk_init_data){ |
| 724 | .name = "gcc_sdcc1_apps_clk_src", |
| 725 | .parent_names = gcc_parent_names_0, |
| 726 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 727 | .ops = &clk_rcg2_ops, |
| 728 | VDD_CX_FMAX_MAP4( |
| 729 | MIN, 19200000, |
| 730 | LOWER, 50000000, |
| 731 | LOW, 100000000, |
| 732 | NOMINAL, 200000000), |
| 733 | }, |
| 734 | }; |
| 735 | |
| 736 | static struct clk_rcg2 gcc_spmi_fetcher_clk_src = { |
| 737 | .cmd_rcgr = 0x3f00c, |
| 738 | .mnd_width = 0, |
| 739 | .hid_width = 5, |
| 740 | .parent_map = gcc_parent_map_1, |
| 741 | .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src, |
| 742 | .clkr.hw.init = &(struct clk_init_data){ |
| 743 | .name = "gcc_spmi_fetcher_clk_src", |
| 744 | .parent_names = gcc_parent_names_1, |
| 745 | .num_parents = 2, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 746 | .ops = &clk_rcg2_ops, |
| 747 | VDD_CX_FMAX_MAP1( |
| 748 | MIN, 19200000), |
| 749 | }, |
| 750 | }; |
| 751 | |
| 752 | static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = { |
| 753 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 754 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), |
Shefali Jain | a52d7c7 | 2018-06-26 13:00:55 +0530 | [diff] [blame] | 755 | F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 756 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 757 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 758 | { } |
| 759 | }; |
| 760 | |
| 761 | static struct clk_rcg2 gcc_usb30_master_clk_src = { |
| 762 | .cmd_rcgr = 0xb01c, |
| 763 | .mnd_width = 8, |
| 764 | .hid_width = 5, |
| 765 | .parent_map = gcc_parent_map_0, |
| 766 | .freq_tbl = ftbl_gcc_usb30_master_clk_src, |
| 767 | .clkr.hw.init = &(struct clk_init_data){ |
| 768 | .name = "gcc_usb30_master_clk_src", |
| 769 | .parent_names = gcc_parent_names_0, |
| 770 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 771 | .ops = &clk_rcg2_ops, |
| 772 | VDD_CX_FMAX_MAP5( |
| 773 | MIN, 50000000, |
| 774 | LOWER, 75000000, |
Shefali Jain | a52d7c7 | 2018-06-26 13:00:55 +0530 | [diff] [blame] | 775 | LOW, 120000000, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 776 | NOMINAL, 200000000, |
| 777 | HIGH, 240000000), |
| 778 | }, |
| 779 | }; |
| 780 | |
| 781 | static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 782 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 783 | F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), |
| 784 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 785 | { } |
| 786 | }; |
| 787 | |
| 788 | static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = { |
| 789 | .cmd_rcgr = 0xb034, |
| 790 | .mnd_width = 0, |
| 791 | .hid_width = 5, |
| 792 | .parent_map = gcc_parent_map_0, |
| 793 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 794 | .clkr.hw.init = &(struct clk_init_data){ |
| 795 | .name = "gcc_usb30_mock_utmi_clk_src", |
| 796 | .parent_names = gcc_parent_names_0, |
| 797 | .num_parents = 4, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 798 | .ops = &clk_rcg2_ops, |
| 799 | VDD_CX_FMAX_MAP3( |
| 800 | MIN, 19200000, |
| 801 | LOWER, 40000000, |
| 802 | LOW, 60000000), |
| 803 | }, |
| 804 | }; |
| 805 | |
| 806 | static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = { |
| 807 | F(1000000, P_BI_TCXO, 1, 5, 96), |
| 808 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 809 | { } |
| 810 | }; |
| 811 | |
| 812 | static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = { |
| 813 | .cmd_rcgr = 0xb05c, |
| 814 | .mnd_width = 16, |
| 815 | .hid_width = 5, |
| 816 | .parent_map = gcc_parent_map_3, |
| 817 | .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src, |
| 818 | .clkr.hw.init = &(struct clk_init_data){ |
| 819 | .name = "gcc_usb3_phy_aux_clk_src", |
| 820 | .parent_names = gcc_parent_names_3, |
| 821 | .num_parents = 3, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 822 | .ops = &clk_rcg2_ops, |
| 823 | VDD_CX_FMAX_MAP1( |
| 824 | MIN, 19200000), |
| 825 | }, |
| 826 | }; |
| 827 | |
| 828 | static struct clk_branch gcc_blsp1_ahb_clk = { |
| 829 | .halt_reg = 0x10004, |
| 830 | .halt_check = BRANCH_HALT_VOTED, |
| 831 | .clkr = { |
| 832 | .enable_reg = 0x6d004, |
| 833 | .enable_mask = BIT(25), |
| 834 | .hw.init = &(struct clk_init_data){ |
| 835 | .name = "gcc_blsp1_ahb_clk", |
| 836 | .ops = &clk_branch2_ops, |
| 837 | }, |
| 838 | }, |
| 839 | }; |
| 840 | |
| 841 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { |
| 842 | .halt_reg = 0x11008, |
| 843 | .halt_check = BRANCH_HALT, |
| 844 | .clkr = { |
| 845 | .enable_reg = 0x11008, |
| 846 | .enable_mask = BIT(0), |
| 847 | .hw.init = &(struct clk_init_data){ |
| 848 | .name = "gcc_blsp1_qup1_i2c_apps_clk", |
| 849 | .parent_names = (const char *[]){ |
| 850 | "gcc_blsp1_qup1_i2c_apps_clk_src", |
| 851 | }, |
| 852 | .num_parents = 1, |
| 853 | .flags = CLK_SET_RATE_PARENT, |
| 854 | .ops = &clk_branch2_ops, |
| 855 | }, |
| 856 | }, |
| 857 | }; |
| 858 | |
| 859 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { |
| 860 | .halt_reg = 0x11004, |
| 861 | .halt_check = BRANCH_HALT, |
| 862 | .clkr = { |
| 863 | .enable_reg = 0x11004, |
| 864 | .enable_mask = BIT(0), |
| 865 | .hw.init = &(struct clk_init_data){ |
| 866 | .name = "gcc_blsp1_qup1_spi_apps_clk", |
| 867 | .parent_names = (const char *[]){ |
| 868 | "gcc_blsp1_qup1_spi_apps_clk_src", |
| 869 | }, |
| 870 | .num_parents = 1, |
| 871 | .flags = CLK_SET_RATE_PARENT, |
| 872 | .ops = &clk_branch2_ops, |
| 873 | }, |
| 874 | }, |
| 875 | }; |
| 876 | |
| 877 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { |
| 878 | .halt_reg = 0x13008, |
| 879 | .halt_check = BRANCH_HALT, |
| 880 | .clkr = { |
| 881 | .enable_reg = 0x13008, |
| 882 | .enable_mask = BIT(0), |
| 883 | .hw.init = &(struct clk_init_data){ |
| 884 | .name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 885 | .parent_names = (const char *[]){ |
| 886 | "gcc_blsp1_qup2_i2c_apps_clk_src", |
| 887 | }, |
| 888 | .num_parents = 1, |
| 889 | .flags = CLK_SET_RATE_PARENT, |
| 890 | .ops = &clk_branch2_ops, |
| 891 | }, |
| 892 | }, |
| 893 | }; |
| 894 | |
| 895 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { |
| 896 | .halt_reg = 0x13004, |
| 897 | .halt_check = BRANCH_HALT, |
| 898 | .clkr = { |
| 899 | .enable_reg = 0x13004, |
| 900 | .enable_mask = BIT(0), |
| 901 | .hw.init = &(struct clk_init_data){ |
| 902 | .name = "gcc_blsp1_qup2_spi_apps_clk", |
| 903 | .parent_names = (const char *[]){ |
| 904 | "gcc_blsp1_qup2_spi_apps_clk_src", |
| 905 | }, |
| 906 | .num_parents = 1, |
| 907 | .flags = CLK_SET_RATE_PARENT, |
| 908 | .ops = &clk_branch2_ops, |
| 909 | }, |
| 910 | }, |
| 911 | }; |
| 912 | |
| 913 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { |
| 914 | .halt_reg = 0x15008, |
| 915 | .halt_check = BRANCH_HALT, |
| 916 | .clkr = { |
| 917 | .enable_reg = 0x15008, |
| 918 | .enable_mask = BIT(0), |
| 919 | .hw.init = &(struct clk_init_data){ |
| 920 | .name = "gcc_blsp1_qup3_i2c_apps_clk", |
| 921 | .parent_names = (const char *[]){ |
| 922 | "gcc_blsp1_qup3_i2c_apps_clk_src", |
| 923 | }, |
| 924 | .num_parents = 1, |
| 925 | .flags = CLK_SET_RATE_PARENT, |
| 926 | .ops = &clk_branch2_ops, |
| 927 | }, |
| 928 | }, |
| 929 | }; |
| 930 | |
| 931 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { |
| 932 | .halt_reg = 0x15004, |
| 933 | .halt_check = BRANCH_HALT, |
| 934 | .clkr = { |
| 935 | .enable_reg = 0x15004, |
| 936 | .enable_mask = BIT(0), |
| 937 | .hw.init = &(struct clk_init_data){ |
| 938 | .name = "gcc_blsp1_qup3_spi_apps_clk", |
| 939 | .parent_names = (const char *[]){ |
| 940 | "gcc_blsp1_qup3_spi_apps_clk_src", |
| 941 | }, |
| 942 | .num_parents = 1, |
| 943 | .flags = CLK_SET_RATE_PARENT, |
| 944 | .ops = &clk_branch2_ops, |
| 945 | }, |
| 946 | }, |
| 947 | }; |
| 948 | |
| 949 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { |
| 950 | .halt_reg = 0x17008, |
| 951 | .halt_check = BRANCH_HALT, |
| 952 | .clkr = { |
| 953 | .enable_reg = 0x17008, |
| 954 | .enable_mask = BIT(0), |
| 955 | .hw.init = &(struct clk_init_data){ |
| 956 | .name = "gcc_blsp1_qup4_i2c_apps_clk", |
| 957 | .parent_names = (const char *[]){ |
| 958 | "gcc_blsp1_qup4_i2c_apps_clk_src", |
| 959 | }, |
| 960 | .num_parents = 1, |
| 961 | .flags = CLK_SET_RATE_PARENT, |
| 962 | .ops = &clk_branch2_ops, |
| 963 | }, |
| 964 | }, |
| 965 | }; |
| 966 | |
| 967 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { |
| 968 | .halt_reg = 0x17004, |
| 969 | .halt_check = BRANCH_HALT, |
| 970 | .clkr = { |
| 971 | .enable_reg = 0x17004, |
| 972 | .enable_mask = BIT(0), |
| 973 | .hw.init = &(struct clk_init_data){ |
| 974 | .name = "gcc_blsp1_qup4_spi_apps_clk", |
| 975 | .parent_names = (const char *[]){ |
| 976 | "gcc_blsp1_qup4_spi_apps_clk_src", |
| 977 | }, |
| 978 | .num_parents = 1, |
| 979 | .flags = CLK_SET_RATE_PARENT, |
| 980 | .ops = &clk_branch2_ops, |
| 981 | }, |
| 982 | }, |
| 983 | }; |
| 984 | |
| 985 | static struct clk_branch gcc_blsp1_sleep_clk = { |
| 986 | .halt_reg = 0x10008, |
| 987 | .halt_check = BRANCH_HALT_VOTED, |
| 988 | .clkr = { |
| 989 | .enable_reg = 0x6d004, |
| 990 | .enable_mask = BIT(26), |
| 991 | .hw.init = &(struct clk_init_data){ |
| 992 | .name = "gcc_blsp1_sleep_clk", |
| 993 | .ops = &clk_branch2_ops, |
| 994 | }, |
| 995 | }, |
| 996 | }; |
| 997 | |
| 998 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { |
| 999 | .halt_reg = 0x12004, |
| 1000 | .halt_check = BRANCH_HALT, |
| 1001 | .clkr = { |
| 1002 | .enable_reg = 0x12004, |
| 1003 | .enable_mask = BIT(0), |
| 1004 | .hw.init = &(struct clk_init_data){ |
| 1005 | .name = "gcc_blsp1_uart1_apps_clk", |
| 1006 | .parent_names = (const char *[]){ |
| 1007 | "gcc_blsp1_uart1_apps_clk_src", |
| 1008 | }, |
| 1009 | .num_parents = 1, |
| 1010 | .flags = CLK_SET_RATE_PARENT, |
| 1011 | .ops = &clk_branch2_ops, |
| 1012 | }, |
| 1013 | }, |
| 1014 | }; |
| 1015 | |
| 1016 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { |
| 1017 | .halt_reg = 0x14004, |
| 1018 | .halt_check = BRANCH_HALT, |
| 1019 | .clkr = { |
| 1020 | .enable_reg = 0x14004, |
| 1021 | .enable_mask = BIT(0), |
| 1022 | .hw.init = &(struct clk_init_data){ |
| 1023 | .name = "gcc_blsp1_uart2_apps_clk", |
| 1024 | .parent_names = (const char *[]){ |
| 1025 | "gcc_blsp1_uart2_apps_clk_src", |
| 1026 | }, |
| 1027 | .num_parents = 1, |
| 1028 | .flags = CLK_SET_RATE_PARENT, |
| 1029 | .ops = &clk_branch2_ops, |
| 1030 | }, |
| 1031 | }, |
| 1032 | }; |
| 1033 | |
| 1034 | static struct clk_branch gcc_blsp1_uart3_apps_clk = { |
| 1035 | .halt_reg = 0x16004, |
| 1036 | .halt_check = BRANCH_HALT, |
| 1037 | .clkr = { |
| 1038 | .enable_reg = 0x16004, |
| 1039 | .enable_mask = BIT(0), |
| 1040 | .hw.init = &(struct clk_init_data){ |
| 1041 | .name = "gcc_blsp1_uart3_apps_clk", |
| 1042 | .parent_names = (const char *[]){ |
| 1043 | "gcc_blsp1_uart3_apps_clk_src", |
| 1044 | }, |
| 1045 | .num_parents = 1, |
| 1046 | .flags = CLK_SET_RATE_PARENT, |
| 1047 | .ops = &clk_branch2_ops, |
| 1048 | }, |
| 1049 | }, |
| 1050 | }; |
| 1051 | |
| 1052 | static struct clk_branch gcc_blsp1_uart4_apps_clk = { |
| 1053 | .halt_reg = 0x18004, |
| 1054 | .halt_check = BRANCH_HALT, |
| 1055 | .clkr = { |
| 1056 | .enable_reg = 0x18004, |
| 1057 | .enable_mask = BIT(0), |
| 1058 | .hw.init = &(struct clk_init_data){ |
| 1059 | .name = "gcc_blsp1_uart4_apps_clk", |
| 1060 | .parent_names = (const char *[]){ |
| 1061 | "gcc_blsp1_uart4_apps_clk_src", |
| 1062 | }, |
| 1063 | .num_parents = 1, |
| 1064 | .flags = CLK_SET_RATE_PARENT, |
| 1065 | .ops = &clk_branch2_ops, |
| 1066 | }, |
| 1067 | }, |
| 1068 | }; |
| 1069 | |
| 1070 | static struct clk_branch gcc_boot_rom_ahb_clk = { |
| 1071 | .halt_reg = 0x1c004, |
| 1072 | .halt_check = BRANCH_HALT_VOTED, |
| 1073 | .hwcg_reg = 0x1c004, |
| 1074 | .hwcg_bit = 1, |
| 1075 | .clkr = { |
| 1076 | .enable_reg = 0x6d004, |
| 1077 | .enable_mask = BIT(10), |
| 1078 | .hw.init = &(struct clk_init_data){ |
| 1079 | .name = "gcc_boot_rom_ahb_clk", |
| 1080 | .ops = &clk_branch2_ops, |
| 1081 | }, |
| 1082 | }, |
| 1083 | }; |
| 1084 | |
| 1085 | static struct clk_branch gcc_ce1_ahb_clk = { |
| 1086 | .halt_reg = 0x2100c, |
| 1087 | .halt_check = BRANCH_HALT_VOTED, |
| 1088 | .hwcg_reg = 0x2100c, |
| 1089 | .hwcg_bit = 1, |
| 1090 | .clkr = { |
| 1091 | .enable_reg = 0x6d004, |
| 1092 | .enable_mask = BIT(3), |
| 1093 | .hw.init = &(struct clk_init_data){ |
| 1094 | .name = "gcc_ce1_ahb_clk", |
| 1095 | .ops = &clk_branch2_ops, |
| 1096 | }, |
| 1097 | }, |
| 1098 | }; |
| 1099 | |
| 1100 | static struct clk_branch gcc_ce1_axi_clk = { |
| 1101 | .halt_reg = 0x21008, |
| 1102 | .halt_check = BRANCH_HALT_VOTED, |
| 1103 | .clkr = { |
| 1104 | .enable_reg = 0x6d004, |
| 1105 | .enable_mask = BIT(4), |
| 1106 | .hw.init = &(struct clk_init_data){ |
| 1107 | .name = "gcc_ce1_axi_clk", |
| 1108 | .ops = &clk_branch2_ops, |
| 1109 | }, |
| 1110 | }, |
| 1111 | }; |
| 1112 | |
| 1113 | static struct clk_branch gcc_ce1_clk = { |
| 1114 | .halt_reg = 0x21004, |
| 1115 | .halt_check = BRANCH_HALT_VOTED, |
| 1116 | .clkr = { |
| 1117 | .enable_reg = 0x6d004, |
| 1118 | .enable_mask = BIT(5), |
| 1119 | .hw.init = &(struct clk_init_data){ |
| 1120 | .name = "gcc_ce1_clk", |
| 1121 | .ops = &clk_branch2_ops, |
| 1122 | }, |
| 1123 | }, |
| 1124 | }; |
| 1125 | |
| 1126 | static struct clk_branch gcc_cpuss_ahb_clk = { |
| 1127 | .halt_reg = 0x24000, |
| 1128 | .halt_check = BRANCH_HALT_VOTED, |
| 1129 | .clkr = { |
| 1130 | .enable_reg = 0x6d004, |
| 1131 | .enable_mask = BIT(21), |
| 1132 | .hw.init = &(struct clk_init_data){ |
| 1133 | .name = "gcc_cpuss_ahb_clk", |
| 1134 | .parent_names = (const char *[]){ |
| 1135 | "gcc_cpuss_ahb_clk_src", |
| 1136 | }, |
| 1137 | .num_parents = 1, |
| 1138 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
| 1139 | .ops = &clk_branch2_ops, |
| 1140 | }, |
| 1141 | }, |
| 1142 | }; |
| 1143 | |
| 1144 | static struct clk_branch gcc_cpuss_gnoc_clk = { |
| 1145 | .halt_reg = 0x24004, |
| 1146 | .halt_check = BRANCH_HALT_VOTED, |
| 1147 | .hwcg_reg = 0x24004, |
| 1148 | .hwcg_bit = 1, |
| 1149 | .clkr = { |
| 1150 | .enable_reg = 0x6d004, |
| 1151 | .enable_mask = BIT(22), |
| 1152 | .hw.init = &(struct clk_init_data){ |
| 1153 | .name = "gcc_cpuss_gnoc_clk", |
| 1154 | .flags = CLK_IS_CRITICAL, |
| 1155 | .ops = &clk_branch2_ops, |
| 1156 | }, |
| 1157 | }, |
| 1158 | }; |
| 1159 | |
| 1160 | static struct clk_branch gcc_cpuss_rbcpr_clk = { |
| 1161 | .halt_reg = 0x24008, |
| 1162 | .halt_check = BRANCH_HALT, |
| 1163 | .clkr = { |
| 1164 | .enable_reg = 0x24008, |
| 1165 | .enable_mask = BIT(0), |
| 1166 | .hw.init = &(struct clk_init_data){ |
| 1167 | .name = "gcc_cpuss_rbcpr_clk", |
| 1168 | .parent_names = (const char *[]){ |
| 1169 | "gcc_cpuss_rbcpr_clk_src", |
| 1170 | }, |
| 1171 | .num_parents = 1, |
| 1172 | .flags = CLK_SET_RATE_PARENT, |
| 1173 | .ops = &clk_branch2_ops, |
| 1174 | }, |
| 1175 | }, |
| 1176 | }; |
| 1177 | |
| 1178 | static struct clk_branch gcc_eth_axi_clk = { |
| 1179 | .halt_reg = 0x4701c, |
| 1180 | .halt_check = BRANCH_HALT, |
| 1181 | .clkr = { |
| 1182 | .enable_reg = 0x4701c, |
| 1183 | .enable_mask = BIT(0), |
| 1184 | .hw.init = &(struct clk_init_data){ |
| 1185 | .name = "gcc_eth_axi_clk", |
| 1186 | .ops = &clk_branch2_ops, |
| 1187 | }, |
| 1188 | }, |
| 1189 | }; |
| 1190 | |
| 1191 | static struct clk_branch gcc_eth_ptp_clk = { |
| 1192 | .halt_reg = 0x47018, |
| 1193 | .halt_check = BRANCH_HALT, |
| 1194 | .clkr = { |
| 1195 | .enable_reg = 0x47018, |
| 1196 | .enable_mask = BIT(0), |
| 1197 | .hw.init = &(struct clk_init_data){ |
| 1198 | .name = "gcc_eth_ptp_clk", |
| 1199 | .parent_names = (const char *[]){ |
| 1200 | "gcc_emac_ptp_clk_src", |
| 1201 | }, |
| 1202 | .num_parents = 1, |
| 1203 | .flags = CLK_SET_RATE_PARENT, |
| 1204 | .ops = &clk_branch2_ops, |
| 1205 | }, |
| 1206 | }, |
| 1207 | }; |
| 1208 | |
| 1209 | static struct clk_branch gcc_eth_rgmii_clk = { |
| 1210 | .halt_reg = 0x47010, |
| 1211 | .halt_check = BRANCH_HALT, |
| 1212 | .clkr = { |
| 1213 | .enable_reg = 0x47010, |
| 1214 | .enable_mask = BIT(0), |
| 1215 | .hw.init = &(struct clk_init_data){ |
| 1216 | .name = "gcc_eth_rgmii_clk", |
| 1217 | .parent_names = (const char *[]){ |
| 1218 | "gcc_emac_clk_src", |
| 1219 | }, |
| 1220 | .num_parents = 1, |
| 1221 | .flags = CLK_SET_RATE_PARENT, |
| 1222 | .ops = &clk_branch2_ops, |
| 1223 | }, |
| 1224 | }, |
| 1225 | }; |
| 1226 | |
| 1227 | static struct clk_branch gcc_eth_slave_ahb_clk = { |
| 1228 | .halt_reg = 0x47014, |
| 1229 | .halt_check = BRANCH_HALT, |
| 1230 | .hwcg_reg = 0x47014, |
| 1231 | .hwcg_bit = 1, |
| 1232 | .clkr = { |
| 1233 | .enable_reg = 0x47014, |
| 1234 | .enable_mask = BIT(0), |
| 1235 | .hw.init = &(struct clk_init_data){ |
| 1236 | .name = "gcc_eth_slave_ahb_clk", |
| 1237 | .ops = &clk_branch2_ops, |
| 1238 | }, |
| 1239 | }, |
| 1240 | }; |
| 1241 | |
| 1242 | static struct clk_branch gcc_gp1_clk = { |
| 1243 | .halt_reg = 0x2b000, |
| 1244 | .halt_check = BRANCH_HALT, |
| 1245 | .clkr = { |
| 1246 | .enable_reg = 0x2b000, |
| 1247 | .enable_mask = BIT(0), |
| 1248 | .hw.init = &(struct clk_init_data){ |
| 1249 | .name = "gcc_gp1_clk", |
| 1250 | .parent_names = (const char *[]){ |
| 1251 | "gcc_gp1_clk_src", |
| 1252 | }, |
| 1253 | .num_parents = 1, |
| 1254 | .flags = CLK_SET_RATE_PARENT, |
| 1255 | .ops = &clk_branch2_ops, |
| 1256 | }, |
| 1257 | }, |
| 1258 | }; |
| 1259 | |
| 1260 | static struct clk_branch gcc_gp2_clk = { |
| 1261 | .halt_reg = 0x2c000, |
| 1262 | .halt_check = BRANCH_HALT, |
| 1263 | .clkr = { |
| 1264 | .enable_reg = 0x2c000, |
| 1265 | .enable_mask = BIT(0), |
| 1266 | .hw.init = &(struct clk_init_data){ |
| 1267 | .name = "gcc_gp2_clk", |
| 1268 | .parent_names = (const char *[]){ |
| 1269 | "gcc_gp2_clk_src", |
| 1270 | }, |
| 1271 | .num_parents = 1, |
| 1272 | .flags = CLK_SET_RATE_PARENT, |
| 1273 | .ops = &clk_branch2_ops, |
| 1274 | }, |
| 1275 | }, |
| 1276 | }; |
| 1277 | |
| 1278 | static struct clk_branch gcc_gp3_clk = { |
| 1279 | .halt_reg = 0x2d000, |
| 1280 | .halt_check = BRANCH_HALT, |
| 1281 | .clkr = { |
| 1282 | .enable_reg = 0x2d000, |
| 1283 | .enable_mask = BIT(0), |
| 1284 | .hw.init = &(struct clk_init_data){ |
| 1285 | .name = "gcc_gp3_clk", |
| 1286 | .parent_names = (const char *[]){ |
| 1287 | "gcc_gp3_clk_src", |
| 1288 | }, |
| 1289 | .num_parents = 1, |
| 1290 | .flags = CLK_SET_RATE_PARENT, |
| 1291 | .ops = &clk_branch2_ops, |
| 1292 | }, |
| 1293 | }, |
| 1294 | }; |
| 1295 | |
Vicky Wallace | c0f0a6f | 2017-11-29 11:44:55 -0800 | [diff] [blame] | 1296 | static struct clk_branch gcc_pcie_0_clkref_clk = { |
| 1297 | .halt_reg = 0x88004, |
| 1298 | .halt_check = BRANCH_HALT, |
| 1299 | .clkr = { |
| 1300 | .enable_reg = 0x88004, |
| 1301 | .enable_mask = BIT(0), |
| 1302 | .hw.init = &(struct clk_init_data){ |
| 1303 | .name = "gcc_pcie_0_clkref_clk", |
| 1304 | .ops = &clk_branch2_ops, |
| 1305 | }, |
| 1306 | }, |
| 1307 | }; |
| 1308 | |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1309 | static struct clk_branch gcc_pcie_aux_clk = { |
| 1310 | .halt_reg = 0x37020, |
David Collins | 16fb752 | 2017-12-14 13:33:47 -0800 | [diff] [blame] | 1311 | .halt_check = BRANCH_HALT_DELAY, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1312 | .clkr = { |
| 1313 | .enable_reg = 0x6d00c, |
| 1314 | .enable_mask = BIT(3), |
| 1315 | .hw.init = &(struct clk_init_data){ |
| 1316 | .name = "gcc_pcie_aux_clk", |
| 1317 | .ops = &clk_branch2_ops, |
| 1318 | }, |
| 1319 | }, |
| 1320 | }; |
| 1321 | |
| 1322 | static struct clk_branch gcc_pcie_cfg_ahb_clk = { |
| 1323 | .halt_reg = 0x3701c, |
| 1324 | .halt_check = BRANCH_HALT_VOTED, |
| 1325 | .hwcg_reg = 0x3701c, |
| 1326 | .hwcg_bit = 1, |
| 1327 | .clkr = { |
| 1328 | .enable_reg = 0x6d00c, |
| 1329 | .enable_mask = BIT(2), |
| 1330 | .hw.init = &(struct clk_init_data){ |
| 1331 | .name = "gcc_pcie_cfg_ahb_clk", |
| 1332 | .ops = &clk_branch2_ops, |
| 1333 | }, |
| 1334 | }, |
| 1335 | }; |
| 1336 | |
| 1337 | static struct clk_branch gcc_pcie_mstr_axi_clk = { |
| 1338 | .halt_reg = 0x37018, |
| 1339 | .halt_check = BRANCH_HALT_VOTED, |
| 1340 | .clkr = { |
| 1341 | .enable_reg = 0x6d00c, |
| 1342 | .enable_mask = BIT(1), |
| 1343 | .hw.init = &(struct clk_init_data){ |
| 1344 | .name = "gcc_pcie_mstr_axi_clk", |
| 1345 | .ops = &clk_branch2_ops, |
| 1346 | }, |
| 1347 | }, |
| 1348 | }; |
| 1349 | |
| 1350 | static struct clk_branch gcc_pcie_phy_refgen_clk = { |
| 1351 | .halt_reg = 0x39028, |
| 1352 | .halt_check = BRANCH_HALT, |
| 1353 | .clkr = { |
| 1354 | .enable_reg = 0x39028, |
| 1355 | .enable_mask = BIT(0), |
| 1356 | .hw.init = &(struct clk_init_data){ |
| 1357 | .name = "gcc_pcie_phy_refgen_clk", |
| 1358 | .parent_names = (const char *[]){ |
| 1359 | "gcc_pcie_phy_refgen_clk_src", |
| 1360 | }, |
| 1361 | .num_parents = 1, |
| 1362 | .flags = CLK_SET_RATE_PARENT, |
| 1363 | .ops = &clk_branch2_ops, |
| 1364 | }, |
| 1365 | }, |
| 1366 | }; |
| 1367 | |
| 1368 | static struct clk_branch gcc_pcie_pipe_clk = { |
| 1369 | .halt_reg = 0x37028, |
David Collins | 16fb752 | 2017-12-14 13:33:47 -0800 | [diff] [blame] | 1370 | .halt_check = BRANCH_HALT_DELAY, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1371 | .clkr = { |
| 1372 | .enable_reg = 0x6d00c, |
| 1373 | .enable_mask = BIT(4), |
| 1374 | .hw.init = &(struct clk_init_data){ |
| 1375 | .name = "gcc_pcie_pipe_clk", |
| 1376 | .ops = &clk_branch2_ops, |
| 1377 | }, |
| 1378 | }, |
| 1379 | }; |
| 1380 | |
| 1381 | static struct clk_branch gcc_pcie_sleep_clk = { |
| 1382 | .halt_reg = 0x37024, |
| 1383 | .halt_check = BRANCH_HALT_VOTED, |
| 1384 | .clkr = { |
| 1385 | .enable_reg = 0x6d00c, |
| 1386 | .enable_mask = BIT(6), |
| 1387 | .hw.init = &(struct clk_init_data){ |
| 1388 | .name = "gcc_pcie_sleep_clk", |
| 1389 | .parent_names = (const char *[]){ |
| 1390 | "gcc_pcie_aux_phy_clk_src", |
| 1391 | }, |
| 1392 | .num_parents = 1, |
| 1393 | .flags = CLK_SET_RATE_PARENT, |
| 1394 | .ops = &clk_branch2_ops, |
| 1395 | }, |
| 1396 | }, |
| 1397 | }; |
| 1398 | |
| 1399 | static struct clk_branch gcc_pcie_slv_axi_clk = { |
| 1400 | .halt_reg = 0x37014, |
| 1401 | .halt_check = BRANCH_HALT_VOTED, |
| 1402 | .hwcg_reg = 0x37014, |
| 1403 | .hwcg_bit = 1, |
| 1404 | .clkr = { |
| 1405 | .enable_reg = 0x6d00c, |
| 1406 | .enable_mask = BIT(0), |
| 1407 | .hw.init = &(struct clk_init_data){ |
| 1408 | .name = "gcc_pcie_slv_axi_clk", |
| 1409 | .ops = &clk_branch2_ops, |
| 1410 | }, |
| 1411 | }, |
| 1412 | }; |
| 1413 | |
| 1414 | static struct clk_branch gcc_pcie_slv_q2a_axi_clk = { |
| 1415 | .halt_reg = 0x37010, |
| 1416 | .halt_check = BRANCH_HALT_VOTED, |
| 1417 | .clkr = { |
| 1418 | .enable_reg = 0x6d00c, |
| 1419 | .enable_mask = BIT(5), |
| 1420 | .hw.init = &(struct clk_init_data){ |
| 1421 | .name = "gcc_pcie_slv_q2a_axi_clk", |
| 1422 | .ops = &clk_branch2_ops, |
| 1423 | }, |
| 1424 | }, |
| 1425 | }; |
| 1426 | |
| 1427 | static struct clk_branch gcc_pdm2_clk = { |
| 1428 | .halt_reg = 0x1900c, |
| 1429 | .halt_check = BRANCH_HALT, |
| 1430 | .clkr = { |
| 1431 | .enable_reg = 0x1900c, |
| 1432 | .enable_mask = BIT(0), |
| 1433 | .hw.init = &(struct clk_init_data){ |
| 1434 | .name = "gcc_pdm2_clk", |
| 1435 | .parent_names = (const char *[]){ |
| 1436 | "gcc_pdm2_clk_src", |
| 1437 | }, |
| 1438 | .num_parents = 1, |
| 1439 | .flags = CLK_SET_RATE_PARENT, |
| 1440 | .ops = &clk_branch2_ops, |
| 1441 | }, |
| 1442 | }, |
| 1443 | }; |
| 1444 | |
| 1445 | static struct clk_branch gcc_pdm_ahb_clk = { |
| 1446 | .halt_reg = 0x19004, |
| 1447 | .halt_check = BRANCH_HALT, |
| 1448 | .hwcg_reg = 0x19004, |
| 1449 | .hwcg_bit = 1, |
| 1450 | .clkr = { |
| 1451 | .enable_reg = 0x19004, |
| 1452 | .enable_mask = BIT(0), |
| 1453 | .hw.init = &(struct clk_init_data){ |
| 1454 | .name = "gcc_pdm_ahb_clk", |
| 1455 | .ops = &clk_branch2_ops, |
| 1456 | }, |
| 1457 | }, |
| 1458 | }; |
| 1459 | |
| 1460 | static struct clk_branch gcc_pdm_xo4_clk = { |
| 1461 | .halt_reg = 0x19008, |
| 1462 | .halt_check = BRANCH_HALT, |
| 1463 | .clkr = { |
| 1464 | .enable_reg = 0x19008, |
| 1465 | .enable_mask = BIT(0), |
| 1466 | .hw.init = &(struct clk_init_data){ |
| 1467 | .name = "gcc_pdm_xo4_clk", |
| 1468 | .ops = &clk_branch2_ops, |
| 1469 | }, |
| 1470 | }, |
| 1471 | }; |
| 1472 | |
| 1473 | static struct clk_branch gcc_prng_ahb_clk = { |
| 1474 | .halt_reg = 0x1a004, |
| 1475 | .halt_check = BRANCH_HALT_VOTED, |
| 1476 | .clkr = { |
| 1477 | .enable_reg = 0x6d004, |
| 1478 | .enable_mask = BIT(13), |
| 1479 | .hw.init = &(struct clk_init_data){ |
| 1480 | .name = "gcc_prng_ahb_clk", |
| 1481 | .ops = &clk_branch2_ops, |
| 1482 | }, |
| 1483 | }, |
| 1484 | }; |
| 1485 | |
| 1486 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
| 1487 | .halt_reg = 0xf008, |
| 1488 | .halt_check = BRANCH_HALT, |
| 1489 | .clkr = { |
| 1490 | .enable_reg = 0xf008, |
| 1491 | .enable_mask = BIT(0), |
| 1492 | .hw.init = &(struct clk_init_data){ |
| 1493 | .name = "gcc_sdcc1_ahb_clk", |
| 1494 | .ops = &clk_branch2_ops, |
| 1495 | }, |
| 1496 | }, |
| 1497 | }; |
| 1498 | |
| 1499 | static struct clk_branch gcc_sdcc1_apps_clk = { |
| 1500 | .halt_reg = 0xf004, |
| 1501 | .halt_check = BRANCH_HALT, |
| 1502 | .clkr = { |
| 1503 | .enable_reg = 0xf004, |
| 1504 | .enable_mask = BIT(0), |
| 1505 | .hw.init = &(struct clk_init_data){ |
| 1506 | .name = "gcc_sdcc1_apps_clk", |
| 1507 | .parent_names = (const char *[]){ |
| 1508 | "gcc_sdcc1_apps_clk_src", |
| 1509 | }, |
| 1510 | .num_parents = 1, |
| 1511 | .flags = CLK_SET_RATE_PARENT, |
| 1512 | .ops = &clk_branch2_ops, |
| 1513 | }, |
| 1514 | }, |
| 1515 | }; |
| 1516 | |
| 1517 | static struct clk_branch gcc_spmi_fetcher_ahb_clk = { |
| 1518 | .halt_reg = 0x3f008, |
| 1519 | .halt_check = BRANCH_HALT, |
| 1520 | .clkr = { |
| 1521 | .enable_reg = 0x3f008, |
| 1522 | .enable_mask = BIT(0), |
| 1523 | .hw.init = &(struct clk_init_data){ |
| 1524 | .name = "gcc_spmi_fetcher_ahb_clk", |
| 1525 | .ops = &clk_branch2_ops, |
| 1526 | }, |
| 1527 | }, |
| 1528 | }; |
| 1529 | |
| 1530 | static struct clk_branch gcc_spmi_fetcher_clk = { |
| 1531 | .halt_reg = 0x3f004, |
| 1532 | .halt_check = BRANCH_HALT, |
| 1533 | .clkr = { |
| 1534 | .enable_reg = 0x3f004, |
| 1535 | .enable_mask = BIT(0), |
| 1536 | .hw.init = &(struct clk_init_data){ |
| 1537 | .name = "gcc_spmi_fetcher_clk", |
| 1538 | .parent_names = (const char *[]){ |
| 1539 | "gcc_spmi_fetcher_clk_src", |
| 1540 | }, |
| 1541 | .num_parents = 1, |
| 1542 | .flags = CLK_SET_RATE_PARENT, |
| 1543 | .ops = &clk_branch2_ops, |
| 1544 | }, |
| 1545 | }, |
| 1546 | }; |
| 1547 | |
| 1548 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { |
| 1549 | .halt_reg = 0x400c, |
| 1550 | .halt_check = BRANCH_HALT_VOTED, |
| 1551 | .clkr = { |
| 1552 | .enable_reg = 0x6d004, |
| 1553 | .enable_mask = BIT(0), |
| 1554 | .hw.init = &(struct clk_init_data){ |
| 1555 | .name = "gcc_sys_noc_cpuss_ahb_clk", |
| 1556 | .parent_names = (const char *[]){ |
| 1557 | "gcc_cpuss_ahb_clk_src", |
| 1558 | }, |
| 1559 | .num_parents = 1, |
| 1560 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
| 1561 | .ops = &clk_branch2_ops, |
| 1562 | }, |
| 1563 | }, |
| 1564 | }; |
| 1565 | |
| 1566 | static struct clk_branch gcc_sys_noc_usb3_clk = { |
| 1567 | .halt_reg = 0x4018, |
| 1568 | .halt_check = BRANCH_HALT, |
| 1569 | .clkr = { |
| 1570 | .enable_reg = 0x4018, |
| 1571 | .enable_mask = BIT(0), |
| 1572 | .hw.init = &(struct clk_init_data){ |
| 1573 | .name = "gcc_sys_noc_usb3_clk", |
| 1574 | .parent_names = (const char *[]){ |
| 1575 | "gcc_usb30_master_clk_src", |
| 1576 | }, |
| 1577 | .num_parents = 1, |
| 1578 | .flags = CLK_SET_RATE_PARENT, |
| 1579 | .ops = &clk_branch2_ops, |
| 1580 | }, |
| 1581 | }, |
| 1582 | }; |
| 1583 | |
| 1584 | static struct clk_branch gcc_usb30_master_clk = { |
| 1585 | .halt_reg = 0xb010, |
| 1586 | .halt_check = BRANCH_HALT, |
| 1587 | .clkr = { |
| 1588 | .enable_reg = 0xb010, |
| 1589 | .enable_mask = BIT(0), |
| 1590 | .hw.init = &(struct clk_init_data){ |
| 1591 | .name = "gcc_usb30_master_clk", |
| 1592 | .parent_names = (const char *[]){ |
| 1593 | "gcc_usb30_master_clk_src", |
| 1594 | }, |
| 1595 | .num_parents = 1, |
| 1596 | .flags = CLK_SET_RATE_PARENT, |
| 1597 | .ops = &clk_branch2_ops, |
| 1598 | }, |
| 1599 | }, |
| 1600 | }; |
| 1601 | |
| 1602 | static struct clk_branch gcc_usb30_mock_utmi_clk = { |
| 1603 | .halt_reg = 0xb018, |
| 1604 | .halt_check = BRANCH_HALT, |
| 1605 | .clkr = { |
| 1606 | .enable_reg = 0xb018, |
| 1607 | .enable_mask = BIT(0), |
| 1608 | .hw.init = &(struct clk_init_data){ |
| 1609 | .name = "gcc_usb30_mock_utmi_clk", |
| 1610 | .parent_names = (const char *[]){ |
| 1611 | "gcc_usb30_mock_utmi_clk_src", |
| 1612 | }, |
| 1613 | .num_parents = 1, |
| 1614 | .flags = CLK_SET_RATE_PARENT, |
| 1615 | .ops = &clk_branch2_ops, |
| 1616 | }, |
| 1617 | }, |
| 1618 | }; |
| 1619 | |
| 1620 | static struct clk_branch gcc_usb30_sleep_clk = { |
| 1621 | .halt_reg = 0xb014, |
| 1622 | .halt_check = BRANCH_HALT, |
| 1623 | .clkr = { |
| 1624 | .enable_reg = 0xb014, |
| 1625 | .enable_mask = BIT(0), |
| 1626 | .hw.init = &(struct clk_init_data){ |
| 1627 | .name = "gcc_usb30_sleep_clk", |
| 1628 | .ops = &clk_branch2_ops, |
| 1629 | }, |
| 1630 | }, |
| 1631 | }; |
| 1632 | |
| 1633 | static struct clk_branch gcc_usb3_phy_aux_clk = { |
| 1634 | .halt_reg = 0xb050, |
| 1635 | .halt_check = BRANCH_HALT, |
| 1636 | .clkr = { |
| 1637 | .enable_reg = 0xb050, |
| 1638 | .enable_mask = BIT(0), |
| 1639 | .hw.init = &(struct clk_init_data){ |
| 1640 | .name = "gcc_usb3_phy_aux_clk", |
| 1641 | .parent_names = (const char *[]){ |
| 1642 | "gcc_usb3_phy_aux_clk_src", |
| 1643 | }, |
| 1644 | .num_parents = 1, |
| 1645 | .flags = CLK_SET_RATE_PARENT, |
| 1646 | .ops = &clk_branch2_ops, |
| 1647 | }, |
| 1648 | }, |
| 1649 | }; |
| 1650 | |
Vicky Wallace | c0f0a6f | 2017-11-29 11:44:55 -0800 | [diff] [blame] | 1651 | static struct clk_gate2 gcc_usb3_phy_pipe_clk = { |
| 1652 | .udelay = 500, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1653 | .clkr = { |
| 1654 | .enable_reg = 0xb054, |
| 1655 | .enable_mask = BIT(0), |
| 1656 | .hw.init = &(struct clk_init_data){ |
| 1657 | .name = "gcc_usb3_phy_pipe_clk", |
Vicky Wallace | c0f0a6f | 2017-11-29 11:44:55 -0800 | [diff] [blame] | 1658 | .ops = &clk_gate2_ops, |
| 1659 | }, |
| 1660 | }, |
| 1661 | }; |
| 1662 | |
| 1663 | static struct clk_branch gcc_usb3_prim_clkref_clk = { |
| 1664 | .halt_reg = 0x88000, |
| 1665 | .halt_check = BRANCH_HALT, |
| 1666 | .clkr = { |
| 1667 | .enable_reg = 0x88000, |
| 1668 | .enable_mask = BIT(0), |
| 1669 | .hw.init = &(struct clk_init_data){ |
| 1670 | .name = "gcc_usb3_prim_clkref_clk", |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1671 | .ops = &clk_branch2_ops, |
| 1672 | }, |
| 1673 | }, |
| 1674 | }; |
| 1675 | |
| 1676 | static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { |
| 1677 | .halt_reg = 0xe004, |
| 1678 | .halt_check = BRANCH_HALT, |
| 1679 | .hwcg_reg = 0xe004, |
| 1680 | .hwcg_bit = 1, |
| 1681 | .clkr = { |
| 1682 | .enable_reg = 0xe004, |
| 1683 | .enable_mask = BIT(0), |
| 1684 | .hw.init = &(struct clk_init_data){ |
| 1685 | .name = "gcc_usb_phy_cfg_ahb2phy_clk", |
| 1686 | .ops = &clk_branch2_ops, |
| 1687 | }, |
| 1688 | }, |
| 1689 | }; |
| 1690 | |
Vicky Wallace | 46de8f4 | 2017-11-21 17:38:42 -0800 | [diff] [blame] | 1691 | /* Measure-only clock for gcc_ipa_2x_clk. */ |
| 1692 | static struct clk_dummy measure_only_ipa_2x_clk = { |
| 1693 | .rrate = 1000, |
| 1694 | .hw.init = &(struct clk_init_data){ |
| 1695 | .name = "measure_only_ipa_2x_clk", |
| 1696 | .ops = &clk_dummy_ops, |
| 1697 | }, |
| 1698 | }; |
| 1699 | |
| 1700 | static struct clk_hw *gcc_sdxpoorwills_hws[] = { |
| 1701 | [MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw, |
| 1702 | }; |
| 1703 | |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1704 | static struct clk_regmap *gcc_sdxpoorwills_clocks[] = { |
| 1705 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, |
| 1706 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, |
| 1707 | [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = |
| 1708 | &gcc_blsp1_qup1_i2c_apps_clk_src.clkr, |
| 1709 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, |
| 1710 | [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = |
| 1711 | &gcc_blsp1_qup1_spi_apps_clk_src.clkr, |
| 1712 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, |
| 1713 | [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = |
| 1714 | &gcc_blsp1_qup2_i2c_apps_clk_src.clkr, |
| 1715 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, |
| 1716 | [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = |
| 1717 | &gcc_blsp1_qup2_spi_apps_clk_src.clkr, |
| 1718 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, |
| 1719 | [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = |
| 1720 | &gcc_blsp1_qup3_i2c_apps_clk_src.clkr, |
| 1721 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, |
| 1722 | [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = |
| 1723 | &gcc_blsp1_qup3_spi_apps_clk_src.clkr, |
| 1724 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, |
| 1725 | [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = |
| 1726 | &gcc_blsp1_qup4_i2c_apps_clk_src.clkr, |
| 1727 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, |
| 1728 | [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = |
| 1729 | &gcc_blsp1_qup4_spi_apps_clk_src.clkr, |
| 1730 | [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, |
| 1731 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, |
| 1732 | [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr, |
| 1733 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, |
| 1734 | [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr, |
| 1735 | [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, |
| 1736 | [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr, |
| 1737 | [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, |
| 1738 | [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr, |
| 1739 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, |
| 1740 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, |
| 1741 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, |
| 1742 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, |
| 1743 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, |
| 1744 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, |
| 1745 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, |
| 1746 | [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, |
| 1747 | [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, |
| 1748 | [GCC_EMAC_CLK_SRC] = &gcc_emac_clk_src.clkr, |
| 1749 | [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, |
| 1750 | [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr, |
| 1751 | [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr, |
| 1752 | [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr, |
| 1753 | [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr, |
| 1754 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, |
| 1755 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, |
| 1756 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, |
| 1757 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, |
| 1758 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, |
| 1759 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, |
Vicky Wallace | c0f0a6f | 2017-11-29 11:44:55 -0800 | [diff] [blame] | 1760 | [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1761 | [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr, |
| 1762 | [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr, |
| 1763 | [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr, |
| 1764 | [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr, |
| 1765 | [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, |
| 1766 | [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, |
| 1767 | [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr, |
| 1768 | [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr, |
| 1769 | [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr, |
| 1770 | [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr, |
| 1771 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
| 1772 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, |
| 1773 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, |
| 1774 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, |
| 1775 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, |
| 1776 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, |
| 1777 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, |
| 1778 | [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, |
| 1779 | [GCC_SPMI_FETCHER_AHB_CLK] = &gcc_spmi_fetcher_ahb_clk.clkr, |
| 1780 | [GCC_SPMI_FETCHER_CLK] = &gcc_spmi_fetcher_clk.clkr, |
| 1781 | [GCC_SPMI_FETCHER_CLK_SRC] = &gcc_spmi_fetcher_clk_src.clkr, |
| 1782 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, |
| 1783 | [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr, |
| 1784 | [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, |
| 1785 | [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr, |
| 1786 | [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, |
| 1787 | [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr, |
| 1788 | [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, |
| 1789 | [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, |
| 1790 | [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr, |
| 1791 | [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, |
Vicky Wallace | c0f0a6f | 2017-11-29 11:44:55 -0800 | [diff] [blame] | 1792 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1793 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, |
| 1794 | [GPLL0] = &gpll0.clkr, |
| 1795 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, |
| 1796 | [GPLL4] = &gpll4.clkr, |
| 1797 | [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, |
| 1798 | }; |
| 1799 | |
| 1800 | static const struct qcom_reset_map gcc_sdxpoorwills_resets[] = { |
| 1801 | [GCC_BLSP1_QUP1_BCR] = { 0x11000 }, |
| 1802 | [GCC_BLSP1_QUP2_BCR] = { 0x13000 }, |
| 1803 | [GCC_BLSP1_QUP3_BCR] = { 0x15000 }, |
| 1804 | [GCC_BLSP1_QUP4_BCR] = { 0x17000 }, |
| 1805 | [GCC_BLSP1_UART2_BCR] = { 0x14000 }, |
| 1806 | [GCC_BLSP1_UART3_BCR] = { 0x16000 }, |
| 1807 | [GCC_BLSP1_UART4_BCR] = { 0x18000 }, |
| 1808 | [GCC_CE1_BCR] = { 0x21000 }, |
| 1809 | [GCC_EMAC_BCR] = { 0x47000 }, |
| 1810 | [GCC_PCIE_BCR] = { 0x37000 }, |
| 1811 | [GCC_PCIE_PHY_BCR] = { 0x39000 }, |
| 1812 | [GCC_PDM_BCR] = { 0x19000 }, |
| 1813 | [GCC_PRNG_BCR] = { 0x1a000 }, |
| 1814 | [GCC_SDCC1_BCR] = { 0xf000 }, |
| 1815 | [GCC_SPMI_FETCHER_BCR] = { 0x3f000 }, |
| 1816 | [GCC_USB30_BCR] = { 0xb000 }, |
Vicky Wallace | c0f0a6f | 2017-11-29 11:44:55 -0800 | [diff] [blame] | 1817 | [GCC_USB3_PHY_BCR] = { 0xc000 }, |
| 1818 | [GCC_USB3PHY_PHY_BCR] = { 0xc004 }, |
Hemant Kumar | 2d88c53 | 2018-02-16 15:01:24 -0800 | [diff] [blame] | 1819 | [GCC_QUSB2PHY_BCR] = { 0xd000 }, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1820 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 }, |
| 1821 | }; |
| 1822 | |
| 1823 | |
| 1824 | static const struct regmap_config gcc_sdxpoorwills_regmap_config = { |
| 1825 | .reg_bits = 32, |
| 1826 | .reg_stride = 4, |
| 1827 | .val_bits = 32, |
| 1828 | .max_register = 0x9b040, |
| 1829 | .fast_io = true, |
| 1830 | }; |
| 1831 | |
| 1832 | static const struct qcom_cc_desc gcc_sdxpoorwills_desc = { |
| 1833 | .config = &gcc_sdxpoorwills_regmap_config, |
| 1834 | .clks = gcc_sdxpoorwills_clocks, |
| 1835 | .num_clks = ARRAY_SIZE(gcc_sdxpoorwills_clocks), |
| 1836 | .resets = gcc_sdxpoorwills_resets, |
| 1837 | .num_resets = ARRAY_SIZE(gcc_sdxpoorwills_resets), |
| 1838 | }; |
| 1839 | |
| 1840 | static const struct of_device_id gcc_sdxpoorwills_match_table[] = { |
| 1841 | { .compatible = "qcom,gcc-sdxpoorwills" }, |
Shefali Jain | fca86a6 | 2018-08-28 15:52:12 +0530 | [diff] [blame] | 1842 | { .compatible = "qcom,gcc-sdxpoorwills-v2" }, |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1843 | { } |
| 1844 | }; |
| 1845 | MODULE_DEVICE_TABLE(of, gcc_sdxpoorwills_match_table); |
| 1846 | |
Shefali Jain | fca86a6 | 2018-08-28 15:52:12 +0530 | [diff] [blame] | 1847 | static void gcc_fixup_sdxpoorwillsv2(void) |
| 1848 | { |
| 1849 | gcc_blsp1_ahb_clk.clkr.enable_mask = BIT(14); |
| 1850 | gcc_blsp1_sleep_clk.clkr.enable_mask = BIT(15); |
| 1851 | } |
| 1852 | |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1853 | static int gcc_sdxpoorwills_probe(struct platform_device *pdev) |
| 1854 | { |
Shefali Jain | fca86a6 | 2018-08-28 15:52:12 +0530 | [diff] [blame] | 1855 | int i, ret = 0, compatlen; |
Vicky Wallace | 46de8f4 | 2017-11-21 17:38:42 -0800 | [diff] [blame] | 1856 | struct clk *clk; |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1857 | struct regmap *regmap; |
Shefali Jain | fca86a6 | 2018-08-28 15:52:12 +0530 | [diff] [blame] | 1858 | const char *compat = NULL; |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1859 | |
| 1860 | regmap = qcom_cc_map(pdev, &gcc_sdxpoorwills_desc); |
| 1861 | if (IS_ERR(regmap)) |
| 1862 | return PTR_ERR(regmap); |
| 1863 | |
| 1864 | vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); |
| 1865 | if (IS_ERR(vdd_cx.regulator[0])) { |
| 1866 | if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) |
| 1867 | dev_err(&pdev->dev, |
| 1868 | "Unable to get vdd_cx regulator\n"); |
| 1869 | return PTR_ERR(vdd_cx.regulator[0]); |
| 1870 | } |
| 1871 | |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 1872 | vdd_cx_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx_ao"); |
| 1873 | if (IS_ERR(vdd_cx_ao.regulator[0])) { |
| 1874 | if (!(PTR_ERR(vdd_cx_ao.regulator[0]) == -EPROBE_DEFER)) |
| 1875 | dev_err(&pdev->dev, |
| 1876 | "Unable to get vdd_cx_ao regulator\n"); |
| 1877 | return PTR_ERR(vdd_cx_ao.regulator[0]); |
| 1878 | } |
| 1879 | |
Shefali Jain | fca86a6 | 2018-08-28 15:52:12 +0530 | [diff] [blame] | 1880 | compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen); |
| 1881 | if (!compat || (compatlen <= 0)) |
| 1882 | return -EINVAL; |
| 1883 | |
| 1884 | if (!strcmp(compat, "qcom,gcc-sdxpoorwills-v2")) |
| 1885 | gcc_fixup_sdxpoorwillsv2(); |
| 1886 | |
Vicky Wallace | 46de8f4 | 2017-11-21 17:38:42 -0800 | [diff] [blame] | 1887 | /* Register the dummy measurement clocks */ |
| 1888 | for (i = 0; i < ARRAY_SIZE(gcc_sdxpoorwills_hws); i++) { |
| 1889 | clk = devm_clk_register(&pdev->dev, gcc_sdxpoorwills_hws[i]); |
| 1890 | if (IS_ERR(clk)) |
| 1891 | return PTR_ERR(clk); |
| 1892 | } |
| 1893 | |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1894 | ret = qcom_cc_really_probe(pdev, &gcc_sdxpoorwills_desc, regmap); |
| 1895 | if (ret) { |
| 1896 | dev_err(&pdev->dev, "Failed to register GCC clocks\n"); |
| 1897 | return ret; |
| 1898 | } |
| 1899 | |
| 1900 | dev_info(&pdev->dev, "Registered GCC clocks\n"); |
| 1901 | |
| 1902 | return ret; |
| 1903 | } |
| 1904 | |
| 1905 | static struct platform_driver gcc_sdxpoorwills_driver = { |
| 1906 | .probe = gcc_sdxpoorwills_probe, |
| 1907 | .driver = { |
| 1908 | .name = "gcc-sdxpoorwills", |
| 1909 | .of_match_table = gcc_sdxpoorwills_match_table, |
| 1910 | }, |
| 1911 | }; |
| 1912 | |
| 1913 | static int __init gcc_sdxpoorwills_init(void) |
| 1914 | { |
| 1915 | return platform_driver_register(&gcc_sdxpoorwills_driver); |
| 1916 | } |
David Dai | 961b2f3 | 2017-12-04 16:50:35 -0800 | [diff] [blame] | 1917 | subsys_initcall(gcc_sdxpoorwills_init); |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1918 | |
| 1919 | static void __exit gcc_sdxpoorwills_exit(void) |
| 1920 | { |
| 1921 | platform_driver_unregister(&gcc_sdxpoorwills_driver); |
| 1922 | } |
| 1923 | module_exit(gcc_sdxpoorwills_exit); |
| 1924 | |
Taniya Das | 998732d | 2018-04-06 12:10:34 +0530 | [diff] [blame] | 1925 | static int gcc_cpuss_ahb_clk_update_rate(void) |
| 1926 | { |
| 1927 | clk_set_rate(gcc_cpuss_ahb_clk.clkr.hw.clk, 19200000); |
| 1928 | clk_set_rate(gcc_sys_noc_cpuss_ahb_clk.clkr.hw.clk, 19200000); |
| 1929 | |
| 1930 | return 0; |
| 1931 | } |
| 1932 | late_initcall(gcc_cpuss_ahb_clk_update_rate); |
| 1933 | |
Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1934 | MODULE_DESCRIPTION("QTI GCC SDXPOORWILLS Driver"); |
| 1935 | MODULE_LICENSE("GPL v2"); |
| 1936 | MODULE_ALIAS("platform:gcc-sdxpoorwills"); |