Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1 | /* |
Pratham Pratap | 7a274cb | 2018-05-10 14:31:09 +0530 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/clk.h> |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 19 | #include <linux/delay.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/power_supply.h> |
| 24 | #include <linux/regulator/consumer.h> |
| 25 | #include <linux/regulator/driver.h> |
| 26 | #include <linux/regulator/machine.h> |
| 27 | #include <linux/usb/phy.h> |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 28 | #include <linux/reset.h> |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 29 | |
| 30 | #define QUSB2PHY_PLL_STATUS 0x38 |
| 31 | #define QUSB2PHY_PLL_LOCK BIT(5) |
| 32 | |
| 33 | #define QUSB2PHY_PORT_QC1 0x70 |
| 34 | #define VDM_SRC_EN BIT(4) |
| 35 | #define VDP_SRC_EN BIT(2) |
| 36 | |
| 37 | #define QUSB2PHY_PORT_QC2 0x74 |
| 38 | #define RDM_UP_EN BIT(1) |
| 39 | #define RDP_UP_EN BIT(3) |
| 40 | #define RPUM_LOW_EN BIT(4) |
| 41 | #define RPUP_LOW_EN BIT(5) |
| 42 | |
| 43 | #define QUSB2PHY_PORT_POWERDOWN 0xB4 |
| 44 | #define CLAMP_N_EN BIT(5) |
| 45 | #define FREEZIO_N BIT(1) |
| 46 | #define POWER_DOWN BIT(0) |
| 47 | |
Vijayavardhan Vennapusa | 5ad836f | 2017-01-03 12:25:36 +0530 | [diff] [blame] | 48 | #define QUSB2PHY_PORT_TEST_CTRL 0xB8 |
| 49 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 50 | #define QUSB2PHY_PWR_CTRL1 0x210 |
| 51 | #define PWR_CTRL1_CLAMP_N_EN BIT(1) |
| 52 | #define PWR_CTRL1_POWR_DOWN BIT(0) |
| 53 | |
| 54 | #define QUSB2PHY_PLL_COMMON_STATUS_ONE 0x1A0 |
| 55 | #define CORE_READY_STATUS BIT(0) |
| 56 | |
| 57 | #define QUSB2PHY_PORT_UTMI_CTRL1 0xC0 |
| 58 | #define TERM_SELECT BIT(4) |
| 59 | #define XCVR_SELECT_FS BIT(2) |
| 60 | #define OP_MODE_NON_DRIVE BIT(0) |
| 61 | |
| 62 | #define QUSB2PHY_PORT_UTMI_CTRL2 0xC4 |
| 63 | #define UTMI_ULPI_SEL BIT(7) |
| 64 | #define UTMI_TEST_MUX_SEL BIT(6) |
| 65 | |
| 66 | #define QUSB2PHY_PLL_TEST 0x04 |
| 67 | #define CLK_REF_SEL BIT(7) |
| 68 | |
| 69 | #define QUSB2PHY_PORT_TUNE1 0x80 |
| 70 | #define QUSB2PHY_PORT_TUNE2 0x84 |
| 71 | #define QUSB2PHY_PORT_TUNE3 0x88 |
| 72 | #define QUSB2PHY_PORT_TUNE4 0x8C |
Vijayavardhan Vennapusa | d51acfc | 2017-02-16 16:25:35 +0530 | [diff] [blame] | 73 | #define QUSB2PHY_PORT_TUNE5 0x90 |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 74 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 75 | /* Get TUNE2's high nibble value read from efuse */ |
| 76 | #define TUNE2_HIGH_NIBBLE_VAL(val, pos, mask) ((val >> pos) & mask) |
| 77 | |
| 78 | #define QUSB2PHY_PORT_INTR_CTRL 0xBC |
| 79 | #define CHG_DET_INTR_EN BIT(4) |
| 80 | #define DMSE_INTR_HIGH_SEL BIT(3) |
| 81 | #define DMSE_INTR_EN BIT(2) |
| 82 | #define DPSE_INTR_HIGH_SEL BIT(1) |
| 83 | #define DPSE_INTR_EN BIT(0) |
| 84 | |
| 85 | #define QUSB2PHY_PORT_UTMI_STATUS 0xF4 |
| 86 | #define LINESTATE_DP BIT(0) |
| 87 | #define LINESTATE_DM BIT(1) |
| 88 | |
| 89 | |
| 90 | #define QUSB2PHY_1P8_VOL_MIN 1800000 /* uV */ |
| 91 | #define QUSB2PHY_1P8_VOL_MAX 1800000 /* uV */ |
| 92 | #define QUSB2PHY_1P8_HPM_LOAD 30000 /* uA */ |
| 93 | |
| 94 | #define QUSB2PHY_3P3_VOL_MIN 3075000 /* uV */ |
| 95 | #define QUSB2PHY_3P3_VOL_MAX 3200000 /* uV */ |
| 96 | #define QUSB2PHY_3P3_HPM_LOAD 30000 /* uA */ |
| 97 | |
| 98 | #define QUSB2PHY_REFCLK_ENABLE BIT(0) |
| 99 | |
Vijayavardhan Vennapusa | d51acfc | 2017-02-16 16:25:35 +0530 | [diff] [blame] | 100 | static unsigned int tune1; |
| 101 | module_param(tune1, uint, 0644); |
| 102 | MODULE_PARM_DESC(tune1, "QUSB PHY TUNE1"); |
| 103 | |
| 104 | static unsigned int tune2; |
| 105 | module_param(tune2, uint, 0644); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 106 | MODULE_PARM_DESC(tune2, "QUSB PHY TUNE2"); |
| 107 | |
Vijayavardhan Vennapusa | d51acfc | 2017-02-16 16:25:35 +0530 | [diff] [blame] | 108 | static unsigned int tune3; |
| 109 | module_param(tune3, uint, 0644); |
| 110 | MODULE_PARM_DESC(tune3, "QUSB PHY TUNE3"); |
| 111 | |
| 112 | static unsigned int tune4; |
| 113 | module_param(tune4, uint, 0644); |
| 114 | MODULE_PARM_DESC(tune4, "QUSB PHY TUNE4"); |
| 115 | |
| 116 | static unsigned int tune5; |
| 117 | module_param(tune5, uint, 0644); |
| 118 | MODULE_PARM_DESC(tune5, "QUSB PHY TUNE5"); |
| 119 | |
| 120 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 121 | struct qusb_phy { |
| 122 | struct usb_phy phy; |
| 123 | void __iomem *base; |
| 124 | void __iomem *tune2_efuse_reg; |
| 125 | void __iomem *ref_clk_base; |
Chandana Kishori Chiluveru | 94bd075 | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 126 | void __iomem *tcsr_clamp_dig_n; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 127 | |
| 128 | struct clk *ref_clk_src; |
| 129 | struct clk *ref_clk; |
| 130 | struct clk *cfg_ahb_clk; |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 131 | struct reset_control *phy_reset; |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 132 | struct clk *iface_clk; |
| 133 | struct clk *core_clk; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 134 | |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 135 | struct regulator *gdsc; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 136 | struct regulator *vdd; |
| 137 | struct regulator *vdda33; |
| 138 | struct regulator *vdda18; |
| 139 | int vdd_levels[3]; /* none, low, high */ |
| 140 | int init_seq_len; |
| 141 | int *qusb_phy_init_seq; |
| 142 | u32 major_rev; |
| 143 | |
| 144 | u32 tune2_val; |
| 145 | int tune2_efuse_bit_pos; |
| 146 | int tune2_efuse_num_of_bits; |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 147 | int tune2_efuse_correction; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 148 | |
| 149 | bool power_enabled; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 150 | bool cable_connected; |
| 151 | bool suspended; |
| 152 | bool ulpi_mode; |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 153 | bool dpdm_enable; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 154 | bool is_se_clk; |
| 155 | |
| 156 | struct regulator_desc dpdm_rdesc; |
| 157 | struct regulator_dev *dpdm_rdev; |
| 158 | |
| 159 | /* emulation targets specific */ |
| 160 | void __iomem *emu_phy_base; |
| 161 | bool emulation; |
| 162 | int *emu_init_seq; |
| 163 | int emu_init_seq_len; |
| 164 | int *phy_pll_reset_seq; |
| 165 | int phy_pll_reset_seq_len; |
| 166 | int *emu_dcm_reset_seq; |
| 167 | int emu_dcm_reset_seq_len; |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 168 | bool put_into_high_z_state; |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 169 | struct mutex phy_lock; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 170 | }; |
| 171 | |
| 172 | static void qusb_phy_enable_clocks(struct qusb_phy *qphy, bool on) |
| 173 | { |
Pratham Pratap | 41b4418 | 2018-12-24 16:17:25 +0530 | [diff] [blame] | 174 | dev_dbg(qphy->phy.dev, "%s(): on:%d\n", __func__, on); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 175 | |
Pratham Pratap | 41b4418 | 2018-12-24 16:17:25 +0530 | [diff] [blame] | 176 | if (on) { |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 177 | clk_prepare_enable(qphy->ref_clk_src); |
| 178 | clk_prepare_enable(qphy->ref_clk); |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 179 | clk_prepare_enable(qphy->iface_clk); |
| 180 | clk_prepare_enable(qphy->core_clk); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 181 | clk_prepare_enable(qphy->cfg_ahb_clk); |
Pratham Pratap | 41b4418 | 2018-12-24 16:17:25 +0530 | [diff] [blame] | 182 | } else { |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 183 | clk_disable_unprepare(qphy->cfg_ahb_clk); |
| 184 | /* |
| 185 | * FSM depedency beween iface_clk and core_clk. |
| 186 | * Hence turned off core_clk before iface_clk. |
| 187 | */ |
| 188 | clk_disable_unprepare(qphy->core_clk); |
| 189 | clk_disable_unprepare(qphy->iface_clk); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 190 | clk_disable_unprepare(qphy->ref_clk); |
| 191 | clk_disable_unprepare(qphy->ref_clk_src); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 192 | } |
| 193 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 194 | } |
| 195 | |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 196 | static int qusb_phy_gdsc(struct qusb_phy *qphy, bool on) |
| 197 | { |
| 198 | int ret; |
| 199 | |
| 200 | if (IS_ERR_OR_NULL(qphy->gdsc)) |
| 201 | return -EPERM; |
| 202 | |
| 203 | if (on) { |
| 204 | dev_dbg(qphy->phy.dev, "TURNING ON GDSC\n"); |
| 205 | ret = regulator_enable(qphy->gdsc); |
| 206 | if (ret) { |
| 207 | dev_err(qphy->phy.dev, "unable to enable gdsc\n"); |
| 208 | return ret; |
| 209 | } |
| 210 | } else { |
| 211 | dev_dbg(qphy->phy.dev, "TURNING OFF GDSC\n"); |
| 212 | ret = regulator_disable(qphy->gdsc); |
| 213 | if (ret) { |
| 214 | dev_err(qphy->phy.dev, "unable to disable gdsc\n"); |
| 215 | return ret; |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | return ret; |
| 220 | } |
| 221 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 222 | static int qusb_phy_config_vdd(struct qusb_phy *qphy, int high) |
| 223 | { |
| 224 | int min, ret; |
| 225 | |
| 226 | min = high ? 1 : 0; /* low or none? */ |
| 227 | ret = regulator_set_voltage(qphy->vdd, qphy->vdd_levels[min], |
| 228 | qphy->vdd_levels[2]); |
| 229 | if (ret) { |
| 230 | dev_err(qphy->phy.dev, "unable to set voltage for qusb vdd\n"); |
| 231 | return ret; |
| 232 | } |
| 233 | |
| 234 | dev_dbg(qphy->phy.dev, "min_vol:%d max_vol:%d\n", |
| 235 | qphy->vdd_levels[min], qphy->vdd_levels[2]); |
| 236 | return ret; |
| 237 | } |
| 238 | |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 239 | static int qusb_phy_enable_power(struct qusb_phy *qphy, bool on) |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 240 | { |
| 241 | int ret = 0; |
| 242 | |
| 243 | dev_dbg(qphy->phy.dev, "%s turn %s regulators. power_enabled:%d\n", |
| 244 | __func__, on ? "on" : "off", qphy->power_enabled); |
| 245 | |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 246 | if (qphy->power_enabled == on) { |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 247 | dev_dbg(qphy->phy.dev, "PHYs' regulators are already ON.\n"); |
| 248 | return 0; |
| 249 | } |
| 250 | |
| 251 | if (!on) |
| 252 | goto disable_vdda33; |
| 253 | |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 254 | ret = qusb_phy_config_vdd(qphy, true); |
| 255 | if (ret) { |
| 256 | dev_err(qphy->phy.dev, "Unable to config VDD:%d\n", |
| 257 | ret); |
| 258 | goto err_vdd; |
| 259 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 260 | |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 261 | ret = regulator_enable(qphy->vdd); |
| 262 | if (ret) { |
| 263 | dev_err(qphy->phy.dev, "Unable to enable VDD\n"); |
| 264 | goto unconfig_vdd; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | ret = regulator_set_load(qphy->vdda18, QUSB2PHY_1P8_HPM_LOAD); |
| 268 | if (ret < 0) { |
| 269 | dev_err(qphy->phy.dev, "Unable to set HPM of vdda18:%d\n", ret); |
| 270 | goto disable_vdd; |
| 271 | } |
| 272 | |
| 273 | ret = regulator_set_voltage(qphy->vdda18, QUSB2PHY_1P8_VOL_MIN, |
| 274 | QUSB2PHY_1P8_VOL_MAX); |
| 275 | if (ret) { |
| 276 | dev_err(qphy->phy.dev, |
| 277 | "Unable to set voltage for vdda18:%d\n", ret); |
| 278 | goto put_vdda18_lpm; |
| 279 | } |
| 280 | |
| 281 | ret = regulator_enable(qphy->vdda18); |
| 282 | if (ret) { |
| 283 | dev_err(qphy->phy.dev, "Unable to enable vdda18:%d\n", ret); |
| 284 | goto unset_vdda18; |
| 285 | } |
| 286 | |
| 287 | ret = regulator_set_load(qphy->vdda33, QUSB2PHY_3P3_HPM_LOAD); |
| 288 | if (ret < 0) { |
| 289 | dev_err(qphy->phy.dev, "Unable to set HPM of vdda33:%d\n", ret); |
| 290 | goto disable_vdda18; |
| 291 | } |
| 292 | |
| 293 | ret = regulator_set_voltage(qphy->vdda33, QUSB2PHY_3P3_VOL_MIN, |
| 294 | QUSB2PHY_3P3_VOL_MAX); |
| 295 | if (ret) { |
| 296 | dev_err(qphy->phy.dev, |
| 297 | "Unable to set voltage for vdda33:%d\n", ret); |
| 298 | goto put_vdda33_lpm; |
| 299 | } |
| 300 | |
| 301 | ret = regulator_enable(qphy->vdda33); |
| 302 | if (ret) { |
| 303 | dev_err(qphy->phy.dev, "Unable to enable vdda33:%d\n", ret); |
| 304 | goto unset_vdd33; |
| 305 | } |
| 306 | |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 307 | qphy->power_enabled = true; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 308 | |
| 309 | pr_debug("%s(): QUSB PHY's regulators are turned ON.\n", __func__); |
| 310 | return ret; |
| 311 | |
| 312 | disable_vdda33: |
| 313 | ret = regulator_disable(qphy->vdda33); |
| 314 | if (ret) |
| 315 | dev_err(qphy->phy.dev, "Unable to disable vdda33:%d\n", ret); |
| 316 | |
| 317 | unset_vdd33: |
| 318 | ret = regulator_set_voltage(qphy->vdda33, 0, QUSB2PHY_3P3_VOL_MAX); |
| 319 | if (ret) |
| 320 | dev_err(qphy->phy.dev, |
| 321 | "Unable to set (0) voltage for vdda33:%d\n", ret); |
| 322 | |
| 323 | put_vdda33_lpm: |
| 324 | ret = regulator_set_load(qphy->vdda33, 0); |
| 325 | if (ret < 0) |
| 326 | dev_err(qphy->phy.dev, "Unable to set (0) HPM of vdda33\n"); |
| 327 | |
| 328 | disable_vdda18: |
| 329 | ret = regulator_disable(qphy->vdda18); |
| 330 | if (ret) |
| 331 | dev_err(qphy->phy.dev, "Unable to disable vdda18:%d\n", ret); |
| 332 | |
| 333 | unset_vdda18: |
| 334 | ret = regulator_set_voltage(qphy->vdda18, 0, QUSB2PHY_1P8_VOL_MAX); |
| 335 | if (ret) |
| 336 | dev_err(qphy->phy.dev, |
| 337 | "Unable to set (0) voltage for vdda18:%d\n", ret); |
| 338 | |
| 339 | put_vdda18_lpm: |
| 340 | ret = regulator_set_load(qphy->vdda18, 0); |
| 341 | if (ret < 0) |
| 342 | dev_err(qphy->phy.dev, "Unable to set LPM of vdda18\n"); |
| 343 | |
| 344 | disable_vdd: |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 345 | ret = regulator_disable(qphy->vdd); |
| 346 | if (ret) |
| 347 | dev_err(qphy->phy.dev, "Unable to disable vdd:%d\n", |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 348 | ret); |
| 349 | |
| 350 | unconfig_vdd: |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 351 | ret = qusb_phy_config_vdd(qphy, false); |
| 352 | if (ret) |
| 353 | dev_err(qphy->phy.dev, "Unable unconfig VDD:%d\n", |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 354 | ret); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 355 | err_vdd: |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 356 | qphy->power_enabled = false; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 357 | dev_dbg(qphy->phy.dev, "QUSB PHY's regulators are turned OFF.\n"); |
| 358 | return ret; |
| 359 | } |
| 360 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 361 | static void qusb_phy_get_tune2_param(struct qusb_phy *qphy) |
| 362 | { |
| 363 | u8 num_of_bits; |
| 364 | u32 bit_mask = 1; |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 365 | u8 reg_val; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 366 | |
| 367 | pr_debug("%s(): num_of_bits:%d bit_pos:%d\n", __func__, |
| 368 | qphy->tune2_efuse_num_of_bits, |
| 369 | qphy->tune2_efuse_bit_pos); |
| 370 | |
| 371 | /* get bit mask based on number of bits to use with efuse reg */ |
| 372 | if (qphy->tune2_efuse_num_of_bits) { |
| 373 | num_of_bits = qphy->tune2_efuse_num_of_bits; |
| 374 | bit_mask = (bit_mask << num_of_bits) - 1; |
| 375 | } |
| 376 | |
| 377 | /* |
| 378 | * Read EFUSE register having TUNE2 parameter's high nibble. |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 379 | * If efuse register shows value as 0x0, then use previous value |
| 380 | * as it is. Otherwise use efuse register based value for this purpose. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 381 | */ |
| 382 | qphy->tune2_val = readl_relaxed(qphy->tune2_efuse_reg); |
| 383 | pr_debug("%s(): bit_mask:%d efuse based tune2 value:%d\n", |
| 384 | __func__, bit_mask, qphy->tune2_val); |
| 385 | |
| 386 | qphy->tune2_val = TUNE2_HIGH_NIBBLE_VAL(qphy->tune2_val, |
| 387 | qphy->tune2_efuse_bit_pos, bit_mask); |
| 388 | |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 389 | /* Update higher nibble of TUNE2 value for better rise/fall times */ |
| 390 | if (qphy->tune2_efuse_correction && qphy->tune2_val) { |
| 391 | if (qphy->tune2_efuse_correction > 5 || |
| 392 | qphy->tune2_efuse_correction < -10) |
| 393 | pr_warn("Correction value is out of range : %d\n", |
| 394 | qphy->tune2_efuse_correction); |
| 395 | else |
| 396 | qphy->tune2_val = qphy->tune2_val + |
| 397 | qphy->tune2_efuse_correction; |
| 398 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 399 | |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 400 | reg_val = readb_relaxed(qphy->base + QUSB2PHY_PORT_TUNE2); |
| 401 | if (qphy->tune2_val) { |
| 402 | reg_val &= 0x0f; |
| 403 | reg_val |= (qphy->tune2_val << 4); |
| 404 | } |
| 405 | |
| 406 | qphy->tune2_val = reg_val; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | static void qusb_phy_write_seq(void __iomem *base, u32 *seq, int cnt, |
| 410 | unsigned long delay) |
| 411 | { |
| 412 | int i; |
| 413 | |
| 414 | pr_debug("Seq count:%d\n", cnt); |
| 415 | for (i = 0; i < cnt; i = i+2) { |
| 416 | pr_debug("write 0x%02x to 0x%02x\n", seq[i], seq[i+1]); |
| 417 | writel_relaxed(seq[i], base + seq[i+1]); |
| 418 | if (delay) |
| 419 | usleep_range(delay, (delay + 2000)); |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | static int qusb_phy_init(struct usb_phy *phy) |
| 424 | { |
| 425 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 426 | int ret, reset_val = 0; |
| 427 | u8 reg; |
| 428 | bool pll_lock_fail = false; |
| 429 | |
| 430 | dev_dbg(phy->dev, "%s\n", __func__); |
| 431 | |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 432 | ret = qusb_phy_enable_power(qphy, true); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 433 | if (ret) |
| 434 | return ret; |
| 435 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 436 | /* |
| 437 | * ref clock is enabled by default after power on reset. Linux clock |
| 438 | * driver will disable this clock as part of late init if peripheral |
| 439 | * driver(s) does not explicitly votes for it. Linux clock driver also |
| 440 | * does not disable the clock until late init even if peripheral |
| 441 | * driver explicitly requests it and cannot defer the probe until late |
| 442 | * init. Hence, Explicitly disable the clock using register write to |
| 443 | * allow QUSB PHY PLL to lock properly. |
| 444 | */ |
| 445 | if (qphy->ref_clk_base) { |
| 446 | writel_relaxed((readl_relaxed(qphy->ref_clk_base) & |
| 447 | ~QUSB2PHY_REFCLK_ENABLE), |
| 448 | qphy->ref_clk_base); |
| 449 | /* Make sure that above write complete to get ref clk OFF */ |
| 450 | wmb(); |
| 451 | } |
| 452 | |
| 453 | /* Perform phy reset */ |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 454 | ret = reset_control_assert(qphy->phy_reset); |
| 455 | if (ret) |
| 456 | dev_err(phy->dev, "%s: phy_reset assert failed\n", __func__); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 457 | usleep_range(100, 150); |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 458 | ret = reset_control_deassert(qphy->phy_reset); |
| 459 | if (ret) |
| 460 | dev_err(phy->dev, "%s: phy_reset deassert failed\n", __func__); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 461 | |
| 462 | if (qphy->emulation) { |
| 463 | if (qphy->emu_init_seq) |
| 464 | qusb_phy_write_seq(qphy->emu_phy_base, |
| 465 | qphy->emu_init_seq, qphy->emu_init_seq_len, 0); |
| 466 | |
| 467 | if (qphy->qusb_phy_init_seq) |
| 468 | qusb_phy_write_seq(qphy->base, qphy->qusb_phy_init_seq, |
| 469 | qphy->init_seq_len, 0); |
| 470 | |
| 471 | /* Wait for 5ms as per QUSB2 RUMI sequence */ |
| 472 | usleep_range(5000, 7000); |
| 473 | |
| 474 | if (qphy->phy_pll_reset_seq) |
| 475 | qusb_phy_write_seq(qphy->base, qphy->phy_pll_reset_seq, |
| 476 | qphy->phy_pll_reset_seq_len, 10000); |
| 477 | |
| 478 | if (qphy->emu_dcm_reset_seq) |
| 479 | qusb_phy_write_seq(qphy->emu_phy_base, |
| 480 | qphy->emu_dcm_reset_seq, |
| 481 | qphy->emu_dcm_reset_seq_len, 10000); |
| 482 | |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | /* Disable the PHY */ |
| 487 | if (qphy->major_rev < 2) |
| 488 | writel_relaxed(CLAMP_N_EN | FREEZIO_N | POWER_DOWN, |
| 489 | qphy->base + QUSB2PHY_PORT_POWERDOWN); |
| 490 | else |
| 491 | writel_relaxed(readl_relaxed(qphy->base + QUSB2PHY_PWR_CTRL1) | |
| 492 | PWR_CTRL1_POWR_DOWN, |
| 493 | qphy->base + QUSB2PHY_PWR_CTRL1); |
| 494 | |
| 495 | /* configure for ULPI mode if requested */ |
| 496 | if (qphy->ulpi_mode) |
| 497 | writel_relaxed(0x0, qphy->base + QUSB2PHY_PORT_UTMI_CTRL2); |
| 498 | |
| 499 | /* save reset value to override based on clk scheme */ |
| 500 | if (qphy->ref_clk_base) |
| 501 | reset_val = readl_relaxed(qphy->base + QUSB2PHY_PLL_TEST); |
| 502 | |
| 503 | if (qphy->qusb_phy_init_seq) |
| 504 | qusb_phy_write_seq(qphy->base, qphy->qusb_phy_init_seq, |
| 505 | qphy->init_seq_len, 0); |
| 506 | |
| 507 | /* |
| 508 | * Check for EFUSE value only if tune2_efuse_reg is available |
| 509 | * and try to read EFUSE value only once i.e. not every USB |
| 510 | * cable connect case. |
| 511 | */ |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 512 | if (qphy->tune2_efuse_reg && !tune2) { |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 513 | if (!qphy->tune2_val) |
| 514 | qusb_phy_get_tune2_param(qphy); |
| 515 | |
| 516 | pr_debug("%s(): Programming TUNE2 parameter as:%x\n", __func__, |
| 517 | qphy->tune2_val); |
| 518 | writel_relaxed(qphy->tune2_val, |
| 519 | qphy->base + QUSB2PHY_PORT_TUNE2); |
| 520 | } |
| 521 | |
Vijayavardhan Vennapusa | d51acfc | 2017-02-16 16:25:35 +0530 | [diff] [blame] | 522 | /* If tune modparam set, override tune value */ |
| 523 | |
| 524 | pr_debug("%s():userspecified modparams TUNEX val:0x%x %x %x %x %x\n", |
| 525 | __func__, tune1, tune2, tune3, tune4, tune5); |
| 526 | if (tune1) |
| 527 | writel_relaxed(tune1, |
| 528 | qphy->base + QUSB2PHY_PORT_TUNE1); |
| 529 | |
| 530 | if (tune2) |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 531 | writel_relaxed(tune2, |
| 532 | qphy->base + QUSB2PHY_PORT_TUNE2); |
Vijayavardhan Vennapusa | d51acfc | 2017-02-16 16:25:35 +0530 | [diff] [blame] | 533 | |
| 534 | if (tune3) |
| 535 | writel_relaxed(tune3, |
| 536 | qphy->base + QUSB2PHY_PORT_TUNE3); |
| 537 | |
| 538 | if (tune4) |
| 539 | writel_relaxed(tune4, |
| 540 | qphy->base + QUSB2PHY_PORT_TUNE4); |
| 541 | |
| 542 | if (tune5) |
| 543 | writel_relaxed(tune5, |
| 544 | qphy->base + QUSB2PHY_PORT_TUNE5); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 545 | |
| 546 | /* ensure above writes are completed before re-enabling PHY */ |
| 547 | wmb(); |
| 548 | |
| 549 | /* Enable the PHY */ |
| 550 | if (qphy->major_rev < 2) |
| 551 | writel_relaxed(CLAMP_N_EN | FREEZIO_N, |
| 552 | qphy->base + QUSB2PHY_PORT_POWERDOWN); |
| 553 | else |
| 554 | writel_relaxed(readl_relaxed(qphy->base + QUSB2PHY_PWR_CTRL1) & |
| 555 | ~PWR_CTRL1_POWR_DOWN, |
| 556 | qphy->base + QUSB2PHY_PWR_CTRL1); |
| 557 | |
| 558 | /* Ensure above write is completed before turning ON ref clk */ |
| 559 | wmb(); |
| 560 | |
| 561 | /* Require to get phy pll lock successfully */ |
| 562 | usleep_range(150, 160); |
| 563 | |
| 564 | /* Turn on phy ref_clk if DIFF_CLK else select SE_CLK */ |
| 565 | if (qphy->ref_clk_base) { |
| 566 | if (!qphy->is_se_clk) { |
| 567 | reset_val &= ~CLK_REF_SEL; |
| 568 | writel_relaxed((readl_relaxed(qphy->ref_clk_base) | |
| 569 | QUSB2PHY_REFCLK_ENABLE), |
| 570 | qphy->ref_clk_base); |
| 571 | } else { |
| 572 | reset_val |= CLK_REF_SEL; |
| 573 | writel_relaxed(reset_val, |
| 574 | qphy->base + QUSB2PHY_PLL_TEST); |
| 575 | } |
| 576 | |
| 577 | /* Make sure above write is completed to get PLL source clock */ |
| 578 | wmb(); |
| 579 | |
| 580 | /* Required to get PHY PLL lock successfully */ |
| 581 | usleep_range(100, 110); |
| 582 | } |
| 583 | |
| 584 | if (qphy->major_rev < 2) { |
| 585 | reg = readb_relaxed(qphy->base + QUSB2PHY_PLL_STATUS); |
| 586 | dev_dbg(phy->dev, "QUSB2PHY_PLL_STATUS:%x\n", reg); |
| 587 | if (!(reg & QUSB2PHY_PLL_LOCK)) |
| 588 | pll_lock_fail = true; |
| 589 | } else { |
| 590 | reg = readb_relaxed(qphy->base + |
| 591 | QUSB2PHY_PLL_COMMON_STATUS_ONE); |
| 592 | dev_dbg(phy->dev, "QUSB2PHY_PLL_COMMON_STATUS_ONE:%x\n", reg); |
| 593 | if (!(reg & CORE_READY_STATUS)) |
| 594 | pll_lock_fail = true; |
| 595 | } |
| 596 | |
| 597 | if (pll_lock_fail) { |
| 598 | dev_err(phy->dev, "QUSB PHY PLL LOCK fails:%x\n", reg); |
| 599 | WARN_ON(1); |
| 600 | } |
| 601 | |
| 602 | return 0; |
| 603 | } |
| 604 | |
| 605 | static void qusb_phy_shutdown(struct usb_phy *phy) |
| 606 | { |
| 607 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 608 | |
| 609 | dev_dbg(phy->dev, "%s\n", __func__); |
| 610 | |
| 611 | qusb_phy_enable_clocks(qphy, true); |
| 612 | |
| 613 | /* Disable the PHY */ |
| 614 | if (qphy->major_rev < 2) |
| 615 | writel_relaxed(CLAMP_N_EN | FREEZIO_N | POWER_DOWN, |
| 616 | qphy->base + QUSB2PHY_PORT_POWERDOWN); |
| 617 | else |
| 618 | writel_relaxed(readl_relaxed(qphy->base + QUSB2PHY_PWR_CTRL1) | |
| 619 | PWR_CTRL1_POWR_DOWN, |
| 620 | qphy->base + QUSB2PHY_PWR_CTRL1); |
| 621 | |
| 622 | /* Make sure above write complete before turning off clocks */ |
| 623 | wmb(); |
| 624 | |
| 625 | qusb_phy_enable_clocks(qphy, false); |
| 626 | } |
| 627 | /** |
| 628 | * Performs QUSB2 PHY suspend/resume functionality. |
| 629 | * |
| 630 | * @uphy - usb phy pointer. |
| 631 | * @suspend - to enable suspend or not. 1 - suspend, 0 - resume |
| 632 | * |
| 633 | */ |
| 634 | static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend) |
| 635 | { |
| 636 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 637 | u32 linestate = 0, intr_mask = 0; |
| 638 | |
Pratham Pratap | 41b4418 | 2018-12-24 16:17:25 +0530 | [diff] [blame] | 639 | if (qphy->suspended == suspend) { |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 640 | dev_dbg(phy->dev, "%s: USB PHY is already suspended\n", |
| 641 | __func__); |
| 642 | return 0; |
| 643 | } |
| 644 | |
| 645 | if (suspend) { |
| 646 | /* Bus suspend case */ |
| 647 | if (qphy->cable_connected || |
| 648 | (qphy->phy.flags & PHY_HOST_MODE)) { |
| 649 | /* Clear all interrupts */ |
| 650 | writel_relaxed(0x00, |
| 651 | qphy->base + QUSB2PHY_PORT_INTR_CTRL); |
| 652 | |
| 653 | linestate = readl_relaxed(qphy->base + |
| 654 | QUSB2PHY_PORT_UTMI_STATUS); |
| 655 | |
| 656 | /* |
| 657 | * D+/D- interrupts are level-triggered, but we are |
| 658 | * only interested if the line state changes, so enable |
| 659 | * the high/low trigger based on current state. In |
| 660 | * other words, enable the triggers _opposite_ of what |
| 661 | * the current D+/D- levels are. |
| 662 | * e.g. if currently D+ high, D- low (HS 'J'/Suspend), |
| 663 | * configure the mask to trigger on D+ low OR D- high |
| 664 | */ |
| 665 | intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; |
| 666 | if (!(linestate & LINESTATE_DP)) /* D+ low */ |
| 667 | intr_mask |= DPSE_INTR_HIGH_SEL; |
| 668 | if (!(linestate & LINESTATE_DM)) /* D- low */ |
| 669 | intr_mask |= DMSE_INTR_HIGH_SEL; |
| 670 | |
| 671 | writel_relaxed(intr_mask, |
| 672 | qphy->base + QUSB2PHY_PORT_INTR_CTRL); |
| 673 | |
Vijayavardhan Vennapusa | 7126532 | 2017-06-21 12:40:13 +0530 | [diff] [blame] | 674 | if (linestate & (LINESTATE_DP | LINESTATE_DM)) { |
| 675 | /* enable phy auto-resume */ |
| 676 | writel_relaxed(0x0C, |
Vijayavardhan Vennapusa | 5ad836f | 2017-01-03 12:25:36 +0530 | [diff] [blame] | 677 | qphy->base + QUSB2PHY_PORT_TEST_CTRL); |
Vijayavardhan Vennapusa | 7126532 | 2017-06-21 12:40:13 +0530 | [diff] [blame] | 678 | /* flush the previous write before next write */ |
| 679 | wmb(); |
| 680 | writel_relaxed(0x04, |
| 681 | qphy->base + QUSB2PHY_PORT_TEST_CTRL); |
| 682 | } |
Vijayavardhan Vennapusa | 5ad836f | 2017-01-03 12:25:36 +0530 | [diff] [blame] | 683 | |
| 684 | |
| 685 | dev_dbg(phy->dev, "%s: intr_mask = %x\n", |
| 686 | __func__, intr_mask); |
| 687 | |
| 688 | /* Makes sure that above write goes through */ |
| 689 | wmb(); |
| 690 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 691 | qusb_phy_enable_clocks(qphy, false); |
| 692 | } else { /* Disconnect case */ |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 693 | mutex_lock(&qphy->phy_lock); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 694 | /* Disable all interrupts */ |
| 695 | writel_relaxed(0x00, |
| 696 | qphy->base + QUSB2PHY_PORT_INTR_CTRL); |
Vijayavardhan Vennapusa | 62caca3 | 2017-05-04 13:00:54 +0530 | [diff] [blame] | 697 | |
| 698 | /* Disable PHY */ |
Pratham Pratap | 7a274cb | 2018-05-10 14:31:09 +0530 | [diff] [blame] | 699 | writel_relaxed(POWER_DOWN | |
| 700 | readl_relaxed(qphy->base + |
| 701 | QUSB2PHY_PORT_POWERDOWN), |
Vijayavardhan Vennapusa | 62caca3 | 2017-05-04 13:00:54 +0530 | [diff] [blame] | 702 | qphy->base + QUSB2PHY_PORT_POWERDOWN); |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 703 | /* Make sure that above write is completed */ |
| 704 | wmb(); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 705 | |
| 706 | qusb_phy_enable_clocks(qphy, false); |
Chandana Kishori Chiluveru | 94bd075 | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 707 | if (qphy->tcsr_clamp_dig_n) |
| 708 | writel_relaxed(0x0, |
| 709 | qphy->tcsr_clamp_dig_n); |
Manu Gautam | 182d67e | 2016-12-15 11:39:46 +0530 | [diff] [blame] | 710 | /* Do not disable power rails if there is vote for it */ |
| 711 | if (!qphy->dpdm_enable) |
| 712 | qusb_phy_enable_power(qphy, false); |
| 713 | else |
| 714 | dev_dbg(phy->dev, "race with rm_pulldown. Keep ldo ON\n"); |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 715 | mutex_unlock(&qphy->phy_lock); |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 716 | |
| 717 | /* |
| 718 | * Set put_into_high_z_state to true so next USB |
| 719 | * cable connect, DPF_DMF request performs PHY |
| 720 | * reset and put it into high-z state. For bootup |
| 721 | * with or without USB cable, it doesn't require |
| 722 | * to put QUSB PHY into high-z state. |
| 723 | */ |
| 724 | qphy->put_into_high_z_state = true; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 725 | } |
| 726 | qphy->suspended = true; |
| 727 | } else { |
| 728 | /* Bus suspend case */ |
| 729 | if (qphy->cable_connected || |
| 730 | (qphy->phy.flags & PHY_HOST_MODE)) { |
| 731 | qusb_phy_enable_clocks(qphy, true); |
| 732 | /* Clear all interrupts on resume */ |
| 733 | writel_relaxed(0x00, |
| 734 | qphy->base + QUSB2PHY_PORT_INTR_CTRL); |
| 735 | } else { |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 736 | qusb_phy_enable_power(qphy, true); |
Chandana Kishori Chiluveru | 94bd075 | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 737 | if (qphy->tcsr_clamp_dig_n) |
| 738 | writel_relaxed(0x1, |
| 739 | qphy->tcsr_clamp_dig_n); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 740 | qusb_phy_enable_clocks(qphy, true); |
| 741 | } |
| 742 | qphy->suspended = false; |
| 743 | } |
| 744 | |
| 745 | return 0; |
| 746 | } |
| 747 | |
| 748 | static int qusb_phy_notify_connect(struct usb_phy *phy, |
| 749 | enum usb_device_speed speed) |
| 750 | { |
| 751 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 752 | |
| 753 | qphy->cable_connected = true; |
| 754 | |
| 755 | dev_dbg(phy->dev, "QUSB PHY: connect notification cable_connected=%d\n", |
| 756 | qphy->cable_connected); |
| 757 | return 0; |
| 758 | } |
| 759 | |
| 760 | static int qusb_phy_notify_disconnect(struct usb_phy *phy, |
| 761 | enum usb_device_speed speed) |
| 762 | { |
| 763 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 764 | |
| 765 | qphy->cable_connected = false; |
| 766 | |
| 767 | dev_dbg(phy->dev, "QUSB PHY: connect notification cable_connected=%d\n", |
| 768 | qphy->cable_connected); |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | static int qusb_phy_dpdm_regulator_enable(struct regulator_dev *rdev) |
| 773 | { |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 774 | int ret = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 775 | struct qusb_phy *qphy = rdev_get_drvdata(rdev); |
| 776 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 777 | dev_dbg(qphy->phy.dev, "%s dpdm_enable:%d\n", |
| 778 | __func__, qphy->dpdm_enable); |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 779 | |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 780 | mutex_lock(&qphy->phy_lock); |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 781 | if (!qphy->dpdm_enable) { |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 782 | ret = qusb_phy_enable_power(qphy, true); |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 783 | if (ret < 0) { |
| 784 | dev_dbg(qphy->phy.dev, |
| 785 | "dpdm regulator enable failed:%d\n", ret); |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 786 | mutex_unlock(&qphy->phy_lock); |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 787 | return ret; |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 788 | } |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 789 | qphy->dpdm_enable = true; |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 790 | if (qphy->put_into_high_z_state) { |
Chandana Kishori Chiluveru | 94bd075 | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 791 | if (qphy->tcsr_clamp_dig_n) |
| 792 | writel_relaxed(0x1, |
| 793 | qphy->tcsr_clamp_dig_n); |
| 794 | |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 795 | qusb_phy_gdsc(qphy, true); |
| 796 | qusb_phy_enable_clocks(qphy, true); |
| 797 | |
| 798 | dev_dbg(qphy->phy.dev, "RESET QUSB PHY\n"); |
| 799 | ret = reset_control_assert(qphy->phy_reset); |
| 800 | if (ret) |
| 801 | dev_err(qphy->phy.dev, "phyassert failed\n"); |
| 802 | usleep_range(100, 150); |
| 803 | ret = reset_control_deassert(qphy->phy_reset); |
| 804 | if (ret) |
| 805 | dev_err(qphy->phy.dev, "deassert failed\n"); |
| 806 | |
| 807 | /* |
| 808 | * Phy in non-driving mode leaves Dp and Dm |
| 809 | * lines in high-Z state. Controller power |
| 810 | * collapse is not switching phy to non-driving |
| 811 | * mode causing charger detection failure. Bring |
| 812 | * phy to non-driving mode by overriding |
| 813 | * controller output via UTMI interface. |
| 814 | */ |
| 815 | writel_relaxed(TERM_SELECT | XCVR_SELECT_FS | |
| 816 | OP_MODE_NON_DRIVE, |
| 817 | qphy->base + QUSB2PHY_PORT_UTMI_CTRL1); |
| 818 | writel_relaxed(UTMI_ULPI_SEL | |
| 819 | UTMI_TEST_MUX_SEL, |
| 820 | qphy->base + QUSB2PHY_PORT_UTMI_CTRL2); |
| 821 | |
| 822 | |
| 823 | /* Disable PHY */ |
| 824 | writel_relaxed(CLAMP_N_EN | FREEZIO_N | |
| 825 | POWER_DOWN, |
| 826 | qphy->base + QUSB2PHY_PORT_POWERDOWN); |
| 827 | /* Make sure that above write is completed */ |
| 828 | wmb(); |
| 829 | |
| 830 | qusb_phy_enable_clocks(qphy, false); |
| 831 | qusb_phy_gdsc(qphy, false); |
| 832 | } |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 833 | } |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 834 | mutex_unlock(&qphy->phy_lock); |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 835 | |
| 836 | return ret; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 837 | } |
| 838 | |
| 839 | static int qusb_phy_dpdm_regulator_disable(struct regulator_dev *rdev) |
| 840 | { |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 841 | int ret = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 842 | struct qusb_phy *qphy = rdev_get_drvdata(rdev); |
| 843 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 844 | dev_dbg(qphy->phy.dev, "%s dpdm_enable:%d\n", |
| 845 | __func__, qphy->dpdm_enable); |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 846 | |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 847 | mutex_lock(&qphy->phy_lock); |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 848 | if (qphy->dpdm_enable) { |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 849 | if (!qphy->cable_connected) { |
Chandana Kishori Chiluveru | 94bd075 | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 850 | if (qphy->tcsr_clamp_dig_n) |
| 851 | writel_relaxed(0x0, |
| 852 | qphy->tcsr_clamp_dig_n); |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 853 | dev_dbg(qphy->phy.dev, "turn off for HVDCP case\n"); |
| 854 | ret = qusb_phy_enable_power(qphy, false); |
| 855 | if (ret < 0) { |
| 856 | dev_dbg(qphy->phy.dev, |
| 857 | "dpdm regulator disable failed:%d\n", |
| 858 | ret); |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 859 | mutex_unlock(&qphy->phy_lock); |
Vijayavardhan Vennapusa | 42baddf | 2016-02-19 13:13:32 +0530 | [diff] [blame] | 860 | return ret; |
| 861 | } |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 862 | } |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 863 | qphy->dpdm_enable = false; |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 864 | } |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 865 | mutex_unlock(&qphy->phy_lock); |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 866 | |
| 867 | return ret; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 868 | } |
| 869 | |
| 870 | static int qusb_phy_dpdm_regulator_is_enabled(struct regulator_dev *rdev) |
| 871 | { |
| 872 | struct qusb_phy *qphy = rdev_get_drvdata(rdev); |
| 873 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 874 | dev_dbg(qphy->phy.dev, "%s qphy->dpdm_enable = %d\n", __func__, |
| 875 | qphy->dpdm_enable); |
| 876 | return qphy->dpdm_enable; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 877 | } |
| 878 | |
| 879 | static struct regulator_ops qusb_phy_dpdm_regulator_ops = { |
| 880 | .enable = qusb_phy_dpdm_regulator_enable, |
| 881 | .disable = qusb_phy_dpdm_regulator_disable, |
| 882 | .is_enabled = qusb_phy_dpdm_regulator_is_enabled, |
| 883 | }; |
| 884 | |
| 885 | static int qusb_phy_regulator_init(struct qusb_phy *qphy) |
| 886 | { |
| 887 | struct device *dev = qphy->phy.dev; |
| 888 | struct regulator_config cfg = {}; |
| 889 | struct regulator_init_data *init_data; |
| 890 | |
| 891 | init_data = devm_kzalloc(dev, sizeof(*init_data), GFP_KERNEL); |
| 892 | if (!init_data) |
| 893 | return -ENOMEM; |
| 894 | |
| 895 | init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_STATUS; |
| 896 | qphy->dpdm_rdesc.owner = THIS_MODULE; |
| 897 | qphy->dpdm_rdesc.type = REGULATOR_VOLTAGE; |
| 898 | qphy->dpdm_rdesc.ops = &qusb_phy_dpdm_regulator_ops; |
| 899 | qphy->dpdm_rdesc.name = kbasename(dev->of_node->full_name); |
| 900 | |
| 901 | cfg.dev = dev; |
| 902 | cfg.init_data = init_data; |
| 903 | cfg.driver_data = qphy; |
| 904 | cfg.of_node = dev->of_node; |
| 905 | |
| 906 | qphy->dpdm_rdev = devm_regulator_register(dev, &qphy->dpdm_rdesc, &cfg); |
| 907 | if (IS_ERR(qphy->dpdm_rdev)) |
| 908 | return PTR_ERR(qphy->dpdm_rdev); |
| 909 | |
| 910 | return 0; |
| 911 | } |
| 912 | |
| 913 | static int qusb_phy_probe(struct platform_device *pdev) |
| 914 | { |
| 915 | struct qusb_phy *qphy; |
| 916 | struct device *dev = &pdev->dev; |
| 917 | struct resource *res; |
| 918 | int ret = 0, size = 0; |
| 919 | const char *phy_type; |
| 920 | bool hold_phy_reset; |
| 921 | |
| 922 | qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); |
| 923 | if (!qphy) |
| 924 | return -ENOMEM; |
| 925 | |
| 926 | qphy->phy.dev = dev; |
| 927 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 928 | "qusb_phy_base"); |
| 929 | qphy->base = devm_ioremap_resource(dev, res); |
| 930 | if (IS_ERR(qphy->base)) |
| 931 | return PTR_ERR(qphy->base); |
| 932 | |
| 933 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 934 | "emu_phy_base"); |
| 935 | if (res) { |
| 936 | qphy->emu_phy_base = devm_ioremap_resource(dev, res); |
| 937 | if (IS_ERR(qphy->emu_phy_base)) { |
| 938 | dev_dbg(dev, "couldn't ioremap emu_phy_base\n"); |
| 939 | qphy->emu_phy_base = NULL; |
| 940 | } |
| 941 | } |
| 942 | |
| 943 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 944 | "tune2_efuse_addr"); |
| 945 | if (res) { |
| 946 | qphy->tune2_efuse_reg = devm_ioremap_nocache(dev, res->start, |
| 947 | resource_size(res)); |
| 948 | if (!IS_ERR_OR_NULL(qphy->tune2_efuse_reg)) { |
| 949 | ret = of_property_read_u32(dev->of_node, |
| 950 | "qcom,tune2-efuse-bit-pos", |
| 951 | &qphy->tune2_efuse_bit_pos); |
| 952 | if (!ret) { |
| 953 | ret = of_property_read_u32(dev->of_node, |
| 954 | "qcom,tune2-efuse-num-bits", |
| 955 | &qphy->tune2_efuse_num_of_bits); |
| 956 | } |
Vijayavardhan Vennapusa | d5954b9 | 2017-08-18 11:59:02 +0530 | [diff] [blame] | 957 | of_property_read_u32(dev->of_node, |
| 958 | "qcom,tune2-efuse-correction", |
| 959 | &qphy->tune2_efuse_correction); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 960 | |
| 961 | if (ret) { |
| 962 | dev_err(dev, "DT Value for tune2 efuse is invalid.\n"); |
| 963 | return -EINVAL; |
| 964 | } |
| 965 | } |
| 966 | } |
| 967 | |
| 968 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 969 | "ref_clk_addr"); |
| 970 | if (res) { |
| 971 | qphy->ref_clk_base = devm_ioremap_nocache(dev, |
| 972 | res->start, resource_size(res)); |
| 973 | if (IS_ERR(qphy->ref_clk_base)) { |
| 974 | dev_dbg(dev, "ref_clk_address is not available.\n"); |
| 975 | return PTR_ERR(qphy->ref_clk_base); |
| 976 | } |
| 977 | |
| 978 | ret = of_property_read_string(dev->of_node, |
| 979 | "qcom,phy-clk-scheme", &phy_type); |
| 980 | if (ret) { |
| 981 | dev_err(dev, "error need qsub_phy_clk_scheme.\n"); |
| 982 | return ret; |
| 983 | } |
| 984 | |
| 985 | if (!strcasecmp(phy_type, "cml")) { |
| 986 | qphy->is_se_clk = false; |
| 987 | } else if (!strcasecmp(phy_type, "cmos")) { |
| 988 | qphy->is_se_clk = true; |
| 989 | } else { |
| 990 | dev_err(dev, "erro invalid qusb_phy_clk_scheme\n"); |
| 991 | return -EINVAL; |
| 992 | } |
| 993 | } |
| 994 | |
Chandana Kishori Chiluveru | 94bd075 | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 995 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 996 | "tcsr_clamp_dig_n_1p8"); |
| 997 | if (res) { |
| 998 | qphy->tcsr_clamp_dig_n = devm_ioremap_nocache(dev, |
| 999 | res->start, resource_size(res)); |
| 1000 | if (IS_ERR(qphy->tcsr_clamp_dig_n)) { |
| 1001 | dev_err(dev, "err reading tcsr_clamp_dig_n\n"); |
| 1002 | qphy->tcsr_clamp_dig_n = NULL; |
| 1003 | } |
| 1004 | } |
| 1005 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1006 | qphy->ref_clk_src = devm_clk_get(dev, "ref_clk_src"); |
| 1007 | if (IS_ERR(qphy->ref_clk_src)) |
| 1008 | dev_dbg(dev, "clk get failed for ref_clk_src\n"); |
| 1009 | |
| 1010 | qphy->ref_clk = devm_clk_get(dev, "ref_clk"); |
| 1011 | if (IS_ERR(qphy->ref_clk)) |
| 1012 | dev_dbg(dev, "clk get failed for ref_clk\n"); |
| 1013 | else |
| 1014 | clk_set_rate(qphy->ref_clk, 19200000); |
| 1015 | |
| 1016 | qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk"); |
| 1017 | if (IS_ERR(qphy->cfg_ahb_clk)) |
| 1018 | return PTR_ERR(qphy->cfg_ahb_clk); |
| 1019 | |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1020 | qphy->phy_reset = devm_reset_control_get(dev, "phy_reset"); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1021 | if (IS_ERR(qphy->phy_reset)) |
| 1022 | return PTR_ERR(qphy->phy_reset); |
| 1023 | |
Chandana Kishori Chiluveru | 9e999cc | 2017-11-08 17:48:03 +0530 | [diff] [blame] | 1024 | if (of_property_match_string(dev->of_node, |
| 1025 | "clock-names", "iface_clk") >= 0) { |
| 1026 | qphy->iface_clk = devm_clk_get(dev, "iface_clk"); |
| 1027 | if (IS_ERR(qphy->iface_clk)) { |
| 1028 | ret = PTR_ERR(qphy->iface_clk); |
| 1029 | qphy->iface_clk = NULL; |
| 1030 | if (ret == -EPROBE_DEFER) |
| 1031 | return ret; |
| 1032 | dev_err(dev, "couldn't get iface_clk(%d)\n", ret); |
| 1033 | } |
| 1034 | } |
| 1035 | |
| 1036 | if (of_property_match_string(dev->of_node, |
| 1037 | "clock-names", "core_clk") >= 0) { |
| 1038 | qphy->core_clk = devm_clk_get(dev, "core_clk"); |
| 1039 | if (IS_ERR(qphy->core_clk)) { |
| 1040 | ret = PTR_ERR(qphy->core_clk); |
| 1041 | qphy->core_clk = NULL; |
| 1042 | if (ret == -EPROBE_DEFER) |
| 1043 | return ret; |
| 1044 | dev_err(dev, "couldn't get core_clk(%d)\n", ret); |
| 1045 | } |
| 1046 | } |
| 1047 | |
| 1048 | qphy->gdsc = devm_regulator_get(dev, "USB3_GDSC"); |
| 1049 | if (IS_ERR(qphy->gdsc)) |
| 1050 | qphy->gdsc = NULL; |
| 1051 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1052 | qphy->emulation = of_property_read_bool(dev->of_node, |
| 1053 | "qcom,emulation"); |
| 1054 | |
| 1055 | of_get_property(dev->of_node, "qcom,emu-init-seq", &size); |
| 1056 | if (size) { |
| 1057 | qphy->emu_init_seq = devm_kzalloc(dev, |
| 1058 | size, GFP_KERNEL); |
| 1059 | if (qphy->emu_init_seq) { |
| 1060 | qphy->emu_init_seq_len = |
| 1061 | (size / sizeof(*qphy->emu_init_seq)); |
| 1062 | if (qphy->emu_init_seq_len % 2) { |
| 1063 | dev_err(dev, "invalid emu_init_seq_len\n"); |
| 1064 | return -EINVAL; |
| 1065 | } |
| 1066 | |
| 1067 | of_property_read_u32_array(dev->of_node, |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1068 | "qcom,emu-init-seq", |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1069 | qphy->emu_init_seq, |
| 1070 | qphy->emu_init_seq_len); |
| 1071 | } else { |
| 1072 | dev_dbg(dev, "error allocating memory for emu_init_seq\n"); |
| 1073 | } |
| 1074 | } |
| 1075 | |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1076 | size = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1077 | of_get_property(dev->of_node, "qcom,phy-pll-reset-seq", &size); |
| 1078 | if (size) { |
| 1079 | qphy->phy_pll_reset_seq = devm_kzalloc(dev, |
| 1080 | size, GFP_KERNEL); |
| 1081 | if (qphy->phy_pll_reset_seq) { |
| 1082 | qphy->phy_pll_reset_seq_len = |
| 1083 | (size / sizeof(*qphy->phy_pll_reset_seq)); |
| 1084 | if (qphy->phy_pll_reset_seq_len % 2) { |
| 1085 | dev_err(dev, "invalid phy_pll_reset_seq_len\n"); |
| 1086 | return -EINVAL; |
| 1087 | } |
| 1088 | |
| 1089 | of_property_read_u32_array(dev->of_node, |
| 1090 | "qcom,phy-pll-reset-seq", |
| 1091 | qphy->phy_pll_reset_seq, |
| 1092 | qphy->phy_pll_reset_seq_len); |
| 1093 | } else { |
| 1094 | dev_dbg(dev, "error allocating memory for phy_pll_reset_seq\n"); |
| 1095 | } |
| 1096 | } |
| 1097 | |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1098 | size = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1099 | of_get_property(dev->of_node, "qcom,emu-dcm-reset-seq", &size); |
| 1100 | if (size) { |
| 1101 | qphy->emu_dcm_reset_seq = devm_kzalloc(dev, |
| 1102 | size, GFP_KERNEL); |
| 1103 | if (qphy->emu_dcm_reset_seq) { |
| 1104 | qphy->emu_dcm_reset_seq_len = |
| 1105 | (size / sizeof(*qphy->emu_dcm_reset_seq)); |
| 1106 | if (qphy->emu_dcm_reset_seq_len % 2) { |
| 1107 | dev_err(dev, "invalid emu_dcm_reset_seq_len\n"); |
| 1108 | return -EINVAL; |
| 1109 | } |
| 1110 | |
| 1111 | of_property_read_u32_array(dev->of_node, |
| 1112 | "qcom,emu-dcm-reset-seq", |
| 1113 | qphy->emu_dcm_reset_seq, |
| 1114 | qphy->emu_dcm_reset_seq_len); |
| 1115 | } else { |
| 1116 | dev_dbg(dev, "error allocating memory for emu_dcm_reset_seq\n"); |
| 1117 | } |
| 1118 | } |
| 1119 | |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1120 | size = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1121 | of_get_property(dev->of_node, "qcom,qusb-phy-init-seq", &size); |
| 1122 | if (size) { |
| 1123 | qphy->qusb_phy_init_seq = devm_kzalloc(dev, |
| 1124 | size, GFP_KERNEL); |
| 1125 | if (qphy->qusb_phy_init_seq) { |
| 1126 | qphy->init_seq_len = |
| 1127 | (size / sizeof(*qphy->qusb_phy_init_seq)); |
| 1128 | if (qphy->init_seq_len % 2) { |
| 1129 | dev_err(dev, "invalid init_seq_len\n"); |
| 1130 | return -EINVAL; |
| 1131 | } |
| 1132 | |
| 1133 | of_property_read_u32_array(dev->of_node, |
| 1134 | "qcom,qusb-phy-init-seq", |
| 1135 | qphy->qusb_phy_init_seq, |
| 1136 | qphy->init_seq_len); |
| 1137 | } else { |
| 1138 | dev_err(dev, "error allocating memory for phy_init_seq\n"); |
| 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | qphy->ulpi_mode = false; |
| 1143 | ret = of_property_read_string(dev->of_node, "phy_type", &phy_type); |
| 1144 | |
| 1145 | if (!ret) { |
| 1146 | if (!strcasecmp(phy_type, "ulpi")) |
| 1147 | qphy->ulpi_mode = true; |
| 1148 | } else { |
| 1149 | dev_err(dev, "error reading phy_type property\n"); |
| 1150 | return ret; |
| 1151 | } |
| 1152 | |
| 1153 | hold_phy_reset = of_property_read_bool(dev->of_node, "qcom,hold-reset"); |
| 1154 | |
| 1155 | /* use default major revision as 2 */ |
| 1156 | qphy->major_rev = 2; |
| 1157 | ret = of_property_read_u32(dev->of_node, "qcom,major-rev", |
| 1158 | &qphy->major_rev); |
| 1159 | |
| 1160 | ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level", |
| 1161 | (u32 *) qphy->vdd_levels, |
| 1162 | ARRAY_SIZE(qphy->vdd_levels)); |
| 1163 | if (ret) { |
| 1164 | dev_err(dev, "error reading qcom,vdd-voltage-level property\n"); |
| 1165 | return ret; |
| 1166 | } |
| 1167 | |
| 1168 | qphy->vdd = devm_regulator_get(dev, "vdd"); |
| 1169 | if (IS_ERR(qphy->vdd)) { |
| 1170 | dev_err(dev, "unable to get vdd supply\n"); |
| 1171 | return PTR_ERR(qphy->vdd); |
| 1172 | } |
| 1173 | |
| 1174 | qphy->vdda33 = devm_regulator_get(dev, "vdda33"); |
| 1175 | if (IS_ERR(qphy->vdda33)) { |
| 1176 | dev_err(dev, "unable to get vdda33 supply\n"); |
| 1177 | return PTR_ERR(qphy->vdda33); |
| 1178 | } |
| 1179 | |
| 1180 | qphy->vdda18 = devm_regulator_get(dev, "vdda18"); |
| 1181 | if (IS_ERR(qphy->vdda18)) { |
| 1182 | dev_err(dev, "unable to get vdda18 supply\n"); |
| 1183 | return PTR_ERR(qphy->vdda18); |
| 1184 | } |
| 1185 | |
Vijayavardhan Vennapusa | d577964 | 2017-02-03 11:42:36 +0530 | [diff] [blame] | 1186 | mutex_init(&qphy->phy_lock); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1187 | platform_set_drvdata(pdev, qphy); |
| 1188 | |
| 1189 | qphy->phy.label = "msm-qusb-phy"; |
| 1190 | qphy->phy.init = qusb_phy_init; |
| 1191 | qphy->phy.set_suspend = qusb_phy_set_suspend; |
| 1192 | qphy->phy.shutdown = qusb_phy_shutdown; |
| 1193 | qphy->phy.type = USB_PHY_TYPE_USB2; |
| 1194 | qphy->phy.notify_connect = qusb_phy_notify_connect; |
| 1195 | qphy->phy.notify_disconnect = qusb_phy_notify_disconnect; |
| 1196 | |
| 1197 | /* |
| 1198 | * On some platforms multiple QUSB PHYs are available. If QUSB PHY is |
| 1199 | * not used, there is leakage current seen with QUSB PHY related voltage |
| 1200 | * rail. Hence keep QUSB PHY into reset state explicitly here. |
| 1201 | */ |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1202 | if (hold_phy_reset) { |
| 1203 | ret = reset_control_assert(qphy->phy_reset); |
| 1204 | if (ret) |
| 1205 | dev_err(dev, "%s:phy_reset assert failed\n", __func__); |
| 1206 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1207 | |
| 1208 | ret = usb_add_phy_dev(&qphy->phy); |
| 1209 | if (ret) |
| 1210 | return ret; |
| 1211 | |
| 1212 | ret = qusb_phy_regulator_init(qphy); |
| 1213 | if (ret) |
| 1214 | usb_remove_phy(&qphy->phy); |
| 1215 | |
Vijayavardhan Vennapusa | e036a3d | 2016-12-13 12:44:18 +0530 | [diff] [blame] | 1216 | /* de-assert clamp dig n to reduce leakage on 1p8 upon boot up */ |
| 1217 | if (qphy->tcsr_clamp_dig_n) |
| 1218 | writel_relaxed(0x0, qphy->tcsr_clamp_dig_n); |
| 1219 | |
Pratham Pratap | 41b4418 | 2018-12-24 16:17:25 +0530 | [diff] [blame] | 1220 | qphy->suspended = true; |
| 1221 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1222 | return ret; |
| 1223 | } |
| 1224 | |
| 1225 | static int qusb_phy_remove(struct platform_device *pdev) |
| 1226 | { |
| 1227 | struct qusb_phy *qphy = platform_get_drvdata(pdev); |
| 1228 | |
| 1229 | usb_remove_phy(&qphy->phy); |
Pratham Pratap | 41b4418 | 2018-12-24 16:17:25 +0530 | [diff] [blame] | 1230 | qphy->cable_connected = false; |
| 1231 | qusb_phy_set_suspend(&qphy->phy, true); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1232 | |
| 1233 | return 0; |
| 1234 | } |
| 1235 | |
| 1236 | static const struct of_device_id qusb_phy_id_table[] = { |
| 1237 | { .compatible = "qcom,qusb2phy", }, |
| 1238 | { }, |
| 1239 | }; |
| 1240 | MODULE_DEVICE_TABLE(of, qusb_phy_id_table); |
| 1241 | |
| 1242 | static struct platform_driver qusb_phy_driver = { |
| 1243 | .probe = qusb_phy_probe, |
| 1244 | .remove = qusb_phy_remove, |
| 1245 | .driver = { |
| 1246 | .name = "msm-qusb-phy", |
| 1247 | .of_match_table = of_match_ptr(qusb_phy_id_table), |
| 1248 | }, |
| 1249 | }; |
| 1250 | |
| 1251 | module_platform_driver(qusb_phy_driver); |
| 1252 | |
| 1253 | MODULE_DESCRIPTION("MSM QUSB2 PHY driver"); |
| 1254 | MODULE_LICENSE("GPL v2"); |