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Rod Whitby3145d8a2006-01-04 17:17:11 +00001/*
2 * arch/arm/mach-ixp4xx/nas100d-pci.c
3 *
4 * NAS 100d board-level PCI initialization
5 *
6 * based on ixdp425-pci.c:
7 * Copyright (C) 2002 Intel Corporation.
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * Maintainer: http://www.nslu2-linux.org/
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
Rod Whitby3145d8a2006-01-04 17:17:11 +000018#include <linux/pci.h>
19#include <linux/init.h>
Thomas Gleixner698dfe22006-07-01 23:01:49 +010020#include <linux/irq.h>
Rod Whitby3145d8a2006-01-04 17:17:11 +000021#include <asm/mach/pci.h>
22#include <asm/mach-types.h>
23
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010024#define MAX_DEV 3
25#define IRQ_LINES 3
Krzysztof Hałasa23fa6842009-11-16 16:06:47 +010026
27/* PCI controller GPIO to IRQ pin mappings */
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010028#define INTA 11
29#define INTB 10
30#define INTC 9
31#define INTD 8
32#define INTE 7
Krzysztof Hałasa23fa6842009-11-16 16:06:47 +010033
Rod Whitby3145d8a2006-01-04 17:17:11 +000034void __init nas100d_pci_preinit(void)
35{
Thomas Gleixner6845664a2011-03-24 13:25:22 +010036 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
38 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
Rod Whitby3145d8a2006-01-04 17:17:11 +000041 ixp4xx_pci_preinit();
42}
43
Ralf Baechled5341942011-06-10 15:30:21 +010044static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
Rod Whitby3145d8a2006-01-04 17:17:11 +000045{
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010046 static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
47 { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
48 { IXP4XX_GPIO_IRQ(INTB), -1, -1 },
49 { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
50 IXP4XX_GPIO_IRQ(INTE) },
Rod Whitby3145d8a2006-01-04 17:17:11 +000051 };
52
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010053 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
54 return pci_irq_table[slot - 1][pin - 1];
Rod Whitby3145d8a2006-01-04 17:17:11 +000055
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010056 return -1;
Rod Whitby3145d8a2006-01-04 17:17:11 +000057}
58
59struct hw_pci __initdata nas100d_pci = {
60 .nr_controllers = 1,
Russell Kingc23bfc32012-03-10 12:49:16 +000061 .ops = &ixp4xx_ops,
Rod Whitby3145d8a2006-01-04 17:17:11 +000062 .preinit = nas100d_pci_preinit,
Rod Whitby3145d8a2006-01-04 17:17:11 +000063 .setup = ixp4xx_setup,
Rod Whitby3145d8a2006-01-04 17:17:11 +000064 .map_irq = nas100d_map_irq,
65};
66
67int __init nas100d_pci_init(void)
68{
69 if (machine_is_nas100d())
70 pci_common_init(&nas100d_pci);
71
72 return 0;
73}
74
75subsys_initcall(nas100d_pci_init);