blob: 840e47d1c86c2aa9046de7ec0664a22ae2e3c804 [file] [log] [blame]
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +00001/*
2 * Renesas SuperH DMA Engine support
3 *
4 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __DMA_SHDMA_H
14#define __DMA_SHDMA_H
15
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020016#include <linux/shdma-base.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000017#include <linux/dmaengine.h>
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -070018#include <linux/interrupt.h>
19#include <linux/list.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000020
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020021#define SH_DMAE_MAX_CHANNELS 20
22#define SH_DMAE_TCR_MAX 0x00FFFFFF /* 16MB */
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000023
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -070024struct device;
25
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000026struct sh_dmae_chan {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020027 struct shdma_chan shdma_chan;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +000028 int xmit_shift; /* log_2(bytes_per_xfer) */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000029 u32 __iomem *base;
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +010030 char dev_id[16]; /* unique name per DMAC of channel */
Guennadi Liakhovetski467017b2011-04-29 17:09:25 +000031 int pm_error;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000032};
33
34struct sh_dmae_device {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020035 struct shdma_dev shdma_dev;
36 struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000037 struct sh_dmae_pdata *pdata;
Paul Mundt03aa18f2010-12-17 19:16:10 +090038 struct list_head node;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000039 u32 __iomem *chan_reg;
40 u16 __iomem *dmars;
Kuninori Morimoto5899a722011-06-17 08:20:40 +000041 unsigned int chcr_offset;
Kuninori Morimoto67c62692011-06-17 08:20:51 +000042 u32 chcr_ie_bit;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000043};
44
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020045struct sh_dmae_regs {
46 u32 sar; /* SAR / source address */
47 u32 dar; /* DAR / destination address */
48 u32 tcr; /* TCR / transfer count */
49};
50
51struct sh_dmae_desc {
52 struct sh_dmae_regs hw;
53 struct shdma_desc shdma_desc;
54};
55
56#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000057#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
58#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020059#define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
60 struct sh_dmae_device, shdma_dev.dma_dev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000061
62#endif /* __DMA_SHDMA_H */