blob: 3dcc1f288adf93f8909c203963d6e6b36b426511 [file] [log] [blame]
Olof Johanssonf5cd7872007-01-31 21:43:54 -06001/*
2 * Copyright (C) 2006 PA Semi, Inc
3 *
4 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
5 * hardware register layouts.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef PASEMI_MAC_H
22#define PASEMI_MAC_H
23
24#include <linux/ethtool.h>
25#include <linux/netdevice.h>
26#include <linux/spinlock.h>
27
28struct pasemi_mac_txring {
29 spinlock_t lock;
30 struct pas_dma_xct_descr *desc;
31 dma_addr_t dma;
32 unsigned int size;
33 unsigned int next_to_use;
34 unsigned int next_to_clean;
35 struct pasemi_mac_buffer *desc_info;
36 char irq_name[10]; /* "eth%d tx" */
37};
38
39struct pasemi_mac_rxring {
40 spinlock_t lock;
41 struct pas_dma_xct_descr *desc; /* RX channel descriptor ring */
42 dma_addr_t dma;
43 u64 *buffers; /* RX interface buffer ring */
44 dma_addr_t buf_dma;
45 unsigned int size;
46 unsigned int next_to_fill;
47 unsigned int next_to_clean;
48 struct pasemi_mac_buffer *desc_info;
49 char irq_name[10]; /* "eth%d rx" */
50};
51
52struct pasemi_mac {
53 struct net_device *netdev;
54 struct pci_dev *pdev;
55 struct pci_dev *dma_pdev;
56 struct pci_dev *iob_pdev;
57 struct net_device_stats stats;
58
59 /* Pointer to the cacheable per-channel status registers */
60 u64 *rx_status;
61 u64 *tx_status;
62
63 u8 type;
64#define MAC_TYPE_GMAC 1
65#define MAC_TYPE_XAUI 2
66 u32 dma_txch;
67 u32 dma_if;
68 u32 dma_rxch;
69
70 u8 mac_addr[6];
71
72 struct timer_list rxtimer;
73
74 struct pasemi_mac_txring *tx;
75 struct pasemi_mac_rxring *rx;
Olof Johansson771f7402007-05-08 00:47:21 -050076 unsigned long tx_irq;
77 unsigned long rx_irq;
Olof Johanssonf5cd7872007-01-31 21:43:54 -060078};
79
80/* Software status descriptor (desc_info) */
81struct pasemi_mac_buffer {
82 struct sk_buff *skb;
83 dma_addr_t dma;
84};
85
86
87/* status register layout in IOB region, at 0xfb800000 */
88struct pasdma_status {
89 u64 rx_sta[64];
90 u64 tx_sta[20];
91};
92
93/* descriptor structure */
94struct pas_dma_xct_descr {
95 union {
96 u64 mactx;
97 u64 macrx;
98 };
99 union {
100 u64 ptr;
101 u64 rxb;
102 };
103};
104
105/* MAC CFG register offsets */
106
107enum {
108 PAS_MAC_CFG_PCFG = 0x80,
109 PAS_MAC_CFG_TXP = 0x98,
110 PAS_MAC_IPC_CHNL = 0x208,
111};
112
113/* MAC CFG register fields */
114#define PAS_MAC_CFG_PCFG_PE 0x80000000
115#define PAS_MAC_CFG_PCFG_CE 0x40000000
116#define PAS_MAC_CFG_PCFG_BU 0x20000000
117#define PAS_MAC_CFG_PCFG_TT 0x10000000
118#define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
119#define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
120#define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
121#define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
122#define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
123#define PAS_MAC_CFG_PCFG_T24 0x02000000
124#define PAS_MAC_CFG_PCFG_PR 0x01000000
125#define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
126#define PAS_MAC_CFG_PCFG_CRO_S 16
127#define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
128#define PAS_MAC_CFG_PCFG_IPO_S 8
129#define PAS_MAC_CFG_PCFG_S1 0x00000080
130#define PAS_MAC_CFG_PCFG_IO_M 0x00000060
131#define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
132#define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
133#define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
134#define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
135#define PAS_MAC_CFG_PCFG_LP 0x00000010
136#define PAS_MAC_CFG_PCFG_TS 0x00000008
137#define PAS_MAC_CFG_PCFG_HD 0x00000004
138#define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
139#define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
140#define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
141#define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
142#define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
143#define PAS_MAC_CFG_TXP_FCF 0x01000000
144#define PAS_MAC_CFG_TXP_FCE 0x00800000
145#define PAS_MAC_CFG_TXP_FC 0x00400000
146#define PAS_MAC_CFG_TXP_FPC_M 0x00300000
147#define PAS_MAC_CFG_TXP_FPC_S 20
148#define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
149 PAS_MAC_CFG_TXP_FPC_M)
150#define PAS_MAC_CFG_TXP_RT 0x00080000
151#define PAS_MAC_CFG_TXP_BL 0x00040000
152#define PAS_MAC_CFG_TXP_SL_M 0x00030000
153#define PAS_MAC_CFG_TXP_SL_S 16
154#define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
155 PAS_MAC_CFG_TXP_SL_M)
156#define PAS_MAC_CFG_TXP_COB_M 0x0000f000
157#define PAS_MAC_CFG_TXP_COB_S 12
158#define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
159 PAS_MAC_CFG_TXP_COB_M)
160#define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
161#define PAS_MAC_CFG_TXP_TIFT_S 8
162#define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
163 PAS_MAC_CFG_TXP_TIFT_M)
164#define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
165#define PAS_MAC_CFG_TXP_TIFG_S 0
166#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
167 PAS_MAC_CFG_TXP_TIFG_M)
168
169#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
170#define PAS_MAC_IPC_CHNL_DCHNO_S 16
171#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
172 PAS_MAC_IPC_CHNL_DCHNO_M)
173#define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
174#define PAS_MAC_IPC_CHNL_BCH_S 0
175#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
176 PAS_MAC_IPC_CHNL_BCH_M)
177
178/* All these registers live in the PCI configuration space for the DMA PCI
179 * device. Use the normal PCI config access functions for them.
180 */
181enum {
182 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
183 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
184 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
185 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
186};
187#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
188#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
189#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
190#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
191
192
193/* Per-interface and per-channel registers */
194#define _PAS_DMA_RXINT_STRIDE 0x20
195#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
196#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
197#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
Olof Johanssoncfa80072007-05-08 00:47:41 -0500198#define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008
199#define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010
200#define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020
201#define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040
Olof Johanssonf5cd7872007-01-31 21:43:54 -0600202#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
Olof Johanssoncfa80072007-05-08 00:47:41 -0500203#define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000
204#define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000
205#define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000
206#define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000
Olof Johanssonf5cd7872007-01-31 21:43:54 -0600207#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
208#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
209#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
210#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
211#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
212#define PAS_DMA_RXINT_INCR_INCR_S 0
213#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
214#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
215#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
216#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
217#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
218#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
219#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
220#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
221 PAS_DMA_RXINT_BASEU_SIZ_M)
222
223
224#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
225#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
226#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
227#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
228#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
229#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
230#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
231#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
232#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
233#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
234#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
235#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
236#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
237#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
238#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
239#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
240#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
241 PAS_DMA_TXCHAN_CFG_TATTR_M)
242#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
243#define PAS_DMA_TXCHAN_CFG_WT_S 6
244#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
245 PAS_DMA_TXCHAN_CFG_WT_M)
246#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
247#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
248#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
249#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
250#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
251#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
252#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
253#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
254 PAS_DMA_TXCHAN_BASEL_BRBL_M)
255#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
256#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
257#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
258#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
259 PAS_DMA_TXCHAN_BASEU_BRBH_M)
260/* # of cache lines worth of buffer ring */
261#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
262#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
263#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
264 PAS_DMA_TXCHAN_BASEU_SIZ_M)
265
266#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
267#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
268#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
269#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
270#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
271#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
272#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
273#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
274#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
275#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
276#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
277#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
278#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
279#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
280#define PAS_DMA_RXCHAN_CFG_HBU_S 7
281#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
282 PAS_DMA_RXCHAN_CFG_HBU_M)
283#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
284#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
285#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
286#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
287#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
288 PAS_DMA_RXCHAN_BASEL_BRBL_M)
289#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
290#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
291#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
292#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
293 PAS_DMA_RXCHAN_BASEU_BRBH_M)
294/* # of cache lines worth of buffer ring */
295#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
296#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
297#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
298 PAS_DMA_RXCHAN_BASEU_SIZ_M)
299
300#define PAS_STATUS_PCNT_M 0x000000000000ffffull
301#define PAS_STATUS_PCNT_S 0
302#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
303#define PAS_STATUS_DCNT_S 16
304#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
305#define PAS_STATUS_BPCNT_S 32
Olof Johansson6dfa7522007-05-08 00:47:32 -0500306#define PAS_STATUS_CAUSE_M 0xf000000000000000ull
Olof Johanssonf5cd7872007-01-31 21:43:54 -0600307#define PAS_STATUS_TIMER 0x1000000000000000ull
308#define PAS_STATUS_ERROR 0x2000000000000000ull
309#define PAS_STATUS_SOFT 0x4000000000000000ull
310#define PAS_STATUS_INT 0x8000000000000000ull
311
312#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
313#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
314#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
315#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
316 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
317#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
318#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
319#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
320#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
321 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
322#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
323#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
324#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
325#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
326#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
327 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
328#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
329#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
330#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
331#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
332#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
333 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
334#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
335#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
336#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 0
337#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
338 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
339#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
340#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
341#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
342#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
343#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
344#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
345#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
346#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
347#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 0
348#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
349 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
350#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
351#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
352#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
353#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
354#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
355#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
356
357#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
358#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
359#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
360#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
361 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
362
363/* Transmit descriptor fields */
364#define XCT_MACTX_T 0x8000000000000000ull
365#define XCT_MACTX_ST 0x4000000000000000ull
366#define XCT_MACTX_NORES 0x0000000000000000ull
367#define XCT_MACTX_8BRES 0x1000000000000000ull
368#define XCT_MACTX_24BRES 0x2000000000000000ull
369#define XCT_MACTX_40BRES 0x3000000000000000ull
370#define XCT_MACTX_I 0x0800000000000000ull
371#define XCT_MACTX_O 0x0400000000000000ull
372#define XCT_MACTX_E 0x0200000000000000ull
373#define XCT_MACTX_VLAN_M 0x0180000000000000ull
374#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
375#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
376#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
377#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
378#define XCT_MACTX_CRC_M 0x0060000000000000ull
379#define XCT_MACTX_CRC_NOP 0x0000000000000000ull
380#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
381#define XCT_MACTX_CRC_PAD 0x0040000000000000ull
382#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
383#define XCT_MACTX_SS 0x0010000000000000ull
384#define XCT_MACTX_LLEN_M 0x00007fff00000000ull
385#define XCT_MACTX_LLEN_S 32ull
386#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
387 XCT_MACTX_LLEN_M)
388#define XCT_MACTX_IPH_M 0x00000000f8000000ull
389#define XCT_MACTX_IPH_S 27ull
390#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
391 XCT_MACTX_IPH_M)
392#define XCT_MACTX_IPO_M 0x0000000007c00000ull
393#define XCT_MACTX_IPO_S 22ull
394#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
395 XCT_MACTX_IPO_M)
396#define XCT_MACTX_CSUM_M 0x0000000000000060ull
397#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
398#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
399#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
400#define XCT_MACTX_V6 0x0000000000000010ull
401#define XCT_MACTX_C 0x0000000000000004ull
402#define XCT_MACTX_AL2 0x0000000000000002ull
403
404/* Receive descriptor fields */
405#define XCT_MACRX_T 0x8000000000000000ull
406#define XCT_MACRX_ST 0x4000000000000000ull
407#define XCT_MACRX_NORES 0x0000000000000000ull
408#define XCT_MACRX_8BRES 0x1000000000000000ull
409#define XCT_MACRX_24BRES 0x2000000000000000ull
410#define XCT_MACRX_40BRES 0x3000000000000000ull
411#define XCT_MACRX_O 0x0400000000000000ull
412#define XCT_MACRX_E 0x0200000000000000ull
413#define XCT_MACRX_FF 0x0100000000000000ull
414#define XCT_MACRX_PF 0x0080000000000000ull
415#define XCT_MACRX_OB 0x0040000000000000ull
416#define XCT_MACRX_OD 0x0020000000000000ull
417#define XCT_MACRX_FS 0x0010000000000000ull
418#define XCT_MACRX_NB_M 0x000fc00000000000ull
419#define XCT_MACRX_NB_S 46ULL
420#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
421 XCT_MACRX_NB_M)
422#define XCT_MACRX_LLEN_M 0x00003fff00000000ull
423#define XCT_MACRX_LLEN_S 32ULL
424#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
425 XCT_MACRX_LLEN_M)
426#define XCT_MACRX_CRC 0x0000000080000000ull
427#define XCT_MACRX_LEN_M 0x0000000060000000ull
428#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
429#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
430#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
431#define XCT_MACRX_CAST_M 0x0000000018000000ull
432#define XCT_MACRX_CAST_UNI 0x0000000000000000ull
433#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
434#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
435#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
436#define XCT_MACRX_VLC_M 0x0000000006000000ull
437#define XCT_MACRX_FM 0x0000000001000000ull
438#define XCT_MACRX_HTY_M 0x0000000000c00000ull
439#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
440#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
441#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
442#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
443#define XCT_MACRX_IPP_M 0x00000000003f0000ull
444#define XCT_MACRX_IPP_S 16
445#define XCT_MACRX_CSUM_M 0x000000000000ffffull
446#define XCT_MACRX_CSUM_S 0
447
448#define XCT_PTR_T 0x8000000000000000ull
449#define XCT_PTR_LEN_M 0x7ffff00000000000ull
450#define XCT_PTR_LEN_S 44
451#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
452 XCT_PTR_LEN_M)
453#define XCT_PTR_ADDR_M 0x00000fffffffffffull
454#define XCT_PTR_ADDR_S 0
455#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
456 XCT_PTR_ADDR_M)
457
458/* Receive interface buffer fields */
459#define XCT_RXB_LEN_M 0x0ffff00000000000ull
460#define XCT_RXB_LEN_S 44
461#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
462#define XCT_RXB_ADDR_M 0x00000fffffffffffull
463#define XCT_RXB_ADDR_S 0
464#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)
465
466
467#endif /* PASEMI_MAC_H */