Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1 | /* |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * KVM/MIPS: Instruction/Exception emulation |
| 7 | * |
| 8 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
| 9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> |
| 10 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 11 | |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/err.h> |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 14 | #include <linux/ktime.h> |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 15 | #include <linux/kvm_host.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/vmalloc.h> |
| 18 | #include <linux/fs.h> |
| 19 | #include <linux/bootmem.h> |
| 20 | #include <linux/random.h> |
| 21 | #include <asm/page.h> |
| 22 | #include <asm/cacheflush.h> |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 23 | #include <asm/cacheops.h> |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 24 | #include <asm/cpu-info.h> |
| 25 | #include <asm/mmu_context.h> |
| 26 | #include <asm/tlbflush.h> |
| 27 | #include <asm/inst.h> |
| 28 | |
| 29 | #undef CONFIG_MIPS_MT |
| 30 | #include <asm/r4kcache.h> |
| 31 | #define CONFIG_MIPS_MT |
| 32 | |
Deng-Cheng Zhu | d7d5b05 | 2014-06-26 12:11:38 -0700 | [diff] [blame] | 33 | #include "interrupt.h" |
| 34 | #include "commpage.h" |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 35 | |
| 36 | #include "trace.h" |
| 37 | |
| 38 | /* |
| 39 | * Compute the return address and do emulate branch simulation, if required. |
| 40 | * This function should be called only in branch delay slot active. |
| 41 | */ |
| 42 | unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu, |
| 43 | unsigned long instpc) |
| 44 | { |
| 45 | unsigned int dspcontrol; |
| 46 | union mips_instruction insn; |
| 47 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 48 | long epc = instpc; |
| 49 | long nextpc = KVM_INVALID_INST; |
| 50 | |
| 51 | if (epc & 3) |
| 52 | goto unaligned; |
| 53 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 54 | /* Read the instruction */ |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 55 | insn.word = kvm_get_inst((u32 *) epc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 56 | |
| 57 | if (insn.word == KVM_INVALID_INST) |
| 58 | return KVM_INVALID_INST; |
| 59 | |
| 60 | switch (insn.i_format.opcode) { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 61 | /* jr and jalr are in r_format format. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 62 | case spec_op: |
| 63 | switch (insn.r_format.func) { |
| 64 | case jalr_op: |
| 65 | arch->gprs[insn.r_format.rd] = epc + 8; |
| 66 | /* Fall through */ |
| 67 | case jr_op: |
| 68 | nextpc = arch->gprs[insn.r_format.rs]; |
| 69 | break; |
| 70 | } |
| 71 | break; |
| 72 | |
| 73 | /* |
| 74 | * This group contains: |
| 75 | * bltz_op, bgez_op, bltzl_op, bgezl_op, |
| 76 | * bltzal_op, bgezal_op, bltzall_op, bgezall_op. |
| 77 | */ |
| 78 | case bcond_op: |
| 79 | switch (insn.i_format.rt) { |
| 80 | case bltz_op: |
| 81 | case bltzl_op: |
| 82 | if ((long)arch->gprs[insn.i_format.rs] < 0) |
| 83 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 84 | else |
| 85 | epc += 8; |
| 86 | nextpc = epc; |
| 87 | break; |
| 88 | |
| 89 | case bgez_op: |
| 90 | case bgezl_op: |
| 91 | if ((long)arch->gprs[insn.i_format.rs] >= 0) |
| 92 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 93 | else |
| 94 | epc += 8; |
| 95 | nextpc = epc; |
| 96 | break; |
| 97 | |
| 98 | case bltzal_op: |
| 99 | case bltzall_op: |
| 100 | arch->gprs[31] = epc + 8; |
| 101 | if ((long)arch->gprs[insn.i_format.rs] < 0) |
| 102 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 103 | else |
| 104 | epc += 8; |
| 105 | nextpc = epc; |
| 106 | break; |
| 107 | |
| 108 | case bgezal_op: |
| 109 | case bgezall_op: |
| 110 | arch->gprs[31] = epc + 8; |
| 111 | if ((long)arch->gprs[insn.i_format.rs] >= 0) |
| 112 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 113 | else |
| 114 | epc += 8; |
| 115 | nextpc = epc; |
| 116 | break; |
| 117 | case bposge32_op: |
| 118 | if (!cpu_has_dsp) |
| 119 | goto sigill; |
| 120 | |
| 121 | dspcontrol = rddsp(0x01); |
| 122 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 123 | if (dspcontrol >= 32) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 124 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 125 | else |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 126 | epc += 8; |
| 127 | nextpc = epc; |
| 128 | break; |
| 129 | } |
| 130 | break; |
| 131 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 132 | /* These are unconditional and in j_format. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 133 | case jal_op: |
| 134 | arch->gprs[31] = instpc + 8; |
| 135 | case j_op: |
| 136 | epc += 4; |
| 137 | epc >>= 28; |
| 138 | epc <<= 28; |
| 139 | epc |= (insn.j_format.target << 2); |
| 140 | nextpc = epc; |
| 141 | break; |
| 142 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 143 | /* These are conditional and in i_format. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 144 | case beq_op: |
| 145 | case beql_op: |
| 146 | if (arch->gprs[insn.i_format.rs] == |
| 147 | arch->gprs[insn.i_format.rt]) |
| 148 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 149 | else |
| 150 | epc += 8; |
| 151 | nextpc = epc; |
| 152 | break; |
| 153 | |
| 154 | case bne_op: |
| 155 | case bnel_op: |
| 156 | if (arch->gprs[insn.i_format.rs] != |
| 157 | arch->gprs[insn.i_format.rt]) |
| 158 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 159 | else |
| 160 | epc += 8; |
| 161 | nextpc = epc; |
| 162 | break; |
| 163 | |
| 164 | case blez_op: /* not really i_format */ |
| 165 | case blezl_op: |
| 166 | /* rt field assumed to be zero */ |
| 167 | if ((long)arch->gprs[insn.i_format.rs] <= 0) |
| 168 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 169 | else |
| 170 | epc += 8; |
| 171 | nextpc = epc; |
| 172 | break; |
| 173 | |
| 174 | case bgtz_op: |
| 175 | case bgtzl_op: |
| 176 | /* rt field assumed to be zero */ |
| 177 | if ((long)arch->gprs[insn.i_format.rs] > 0) |
| 178 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 179 | else |
| 180 | epc += 8; |
| 181 | nextpc = epc; |
| 182 | break; |
| 183 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 184 | /* And now the FPA/cp1 branch instructions. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 185 | case cop1_op: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 186 | kvm_err("%s: unsupported cop1_op\n", __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 187 | break; |
| 188 | } |
| 189 | |
| 190 | return nextpc; |
| 191 | |
| 192 | unaligned: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 193 | kvm_err("%s: unaligned epc\n", __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 194 | return nextpc; |
| 195 | |
| 196 | sigill: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 197 | kvm_err("%s: DSP branch but not DSP ASE\n", __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 198 | return nextpc; |
| 199 | } |
| 200 | |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 201 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 202 | { |
| 203 | unsigned long branch_pc; |
| 204 | enum emulation_result er = EMULATE_DONE; |
| 205 | |
| 206 | if (cause & CAUSEF_BD) { |
| 207 | branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc); |
| 208 | if (branch_pc == KVM_INVALID_INST) { |
| 209 | er = EMULATE_FAIL; |
| 210 | } else { |
| 211 | vcpu->arch.pc = branch_pc; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 212 | kvm_debug("BD update_pc(): New PC: %#lx\n", |
| 213 | vcpu->arch.pc); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 214 | } |
| 215 | } else |
| 216 | vcpu->arch.pc += 4; |
| 217 | |
| 218 | kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc); |
| 219 | |
| 220 | return er; |
| 221 | } |
| 222 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 223 | /** |
| 224 | * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled. |
| 225 | * @vcpu: Virtual CPU. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 226 | * |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 227 | * Returns: 1 if the CP0_Count timer is disabled by either the guest |
| 228 | * CP0_Cause.DC bit or the count_ctl.DC bit. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 229 | * 0 otherwise (in which case CP0_Count timer is running). |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 230 | */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 231 | static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 232 | { |
| 233 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 234 | |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 235 | return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) || |
| 236 | (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 237 | } |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 238 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 239 | /** |
| 240 | * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count. |
| 241 | * |
| 242 | * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias. |
| 243 | * |
| 244 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). |
| 245 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 246 | static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 247 | { |
| 248 | s64 now_ns, periods; |
| 249 | u64 delta; |
| 250 | |
| 251 | now_ns = ktime_to_ns(now); |
| 252 | delta = now_ns + vcpu->arch.count_dyn_bias; |
| 253 | |
| 254 | if (delta >= vcpu->arch.count_period) { |
| 255 | /* If delta is out of safe range the bias needs adjusting */ |
| 256 | periods = div64_s64(now_ns, vcpu->arch.count_period); |
| 257 | vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period; |
| 258 | /* Recalculate delta with new bias */ |
| 259 | delta = now_ns + vcpu->arch.count_dyn_bias; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 260 | } |
| 261 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 262 | /* |
| 263 | * We've ensured that: |
| 264 | * delta < count_period |
| 265 | * |
| 266 | * Therefore the intermediate delta*count_hz will never overflow since |
| 267 | * at the boundary condition: |
| 268 | * delta = count_period |
| 269 | * delta = NSEC_PER_SEC * 2^32 / count_hz |
| 270 | * delta * count_hz = NSEC_PER_SEC * 2^32 |
| 271 | */ |
| 272 | return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC); |
| 273 | } |
| 274 | |
| 275 | /** |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 276 | * kvm_mips_count_time() - Get effective current time. |
| 277 | * @vcpu: Virtual CPU. |
| 278 | * |
| 279 | * Get effective monotonic ktime. This is usually a straightforward ktime_get(), |
| 280 | * except when the master disable bit is set in count_ctl, in which case it is |
| 281 | * count_resume, i.e. the time that the count was disabled. |
| 282 | * |
| 283 | * Returns: Effective monotonic ktime for CP0_Count. |
| 284 | */ |
| 285 | static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu) |
| 286 | { |
| 287 | if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) |
| 288 | return vcpu->arch.count_resume; |
| 289 | |
| 290 | return ktime_get(); |
| 291 | } |
| 292 | |
| 293 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 294 | * kvm_mips_read_count_running() - Read the current count value as if running. |
| 295 | * @vcpu: Virtual CPU. |
| 296 | * @now: Kernel time to read CP0_Count at. |
| 297 | * |
| 298 | * Returns the current guest CP0_Count register at time @now and handles if the |
| 299 | * timer interrupt is pending and hasn't been handled yet. |
| 300 | * |
| 301 | * Returns: The current value of the guest CP0_Count register. |
| 302 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 303 | static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 304 | { |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 305 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 306 | ktime_t expires, threshold; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 307 | u32 count, compare; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 308 | int running; |
| 309 | |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 310 | /* Calculate the biased and scaled guest CP0_Count */ |
| 311 | count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now); |
| 312 | compare = kvm_read_c0_guest_compare(cop0); |
| 313 | |
| 314 | /* |
| 315 | * Find whether CP0_Count has reached the closest timer interrupt. If |
| 316 | * not, we shouldn't inject it. |
| 317 | */ |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 318 | if ((s32)(count - compare) < 0) |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 319 | return count; |
| 320 | |
| 321 | /* |
| 322 | * The CP0_Count we're going to return has already reached the closest |
| 323 | * timer interrupt. Quickly check if it really is a new interrupt by |
| 324 | * looking at whether the interval until the hrtimer expiry time is |
| 325 | * less than 1/4 of the timer period. |
| 326 | */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 327 | expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer); |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 328 | threshold = ktime_add_ns(now, vcpu->arch.count_period / 4); |
| 329 | if (ktime_before(expires, threshold)) { |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 330 | /* |
| 331 | * Cancel it while we handle it so there's no chance of |
| 332 | * interference with the timeout handler. |
| 333 | */ |
| 334 | running = hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 335 | |
| 336 | /* Nothing should be waiting on the timeout */ |
| 337 | kvm_mips_callbacks->queue_timer_int(vcpu); |
| 338 | |
| 339 | /* |
| 340 | * Restart the timer if it was running based on the expiry time |
| 341 | * we read, so that we don't push it back 2 periods. |
| 342 | */ |
| 343 | if (running) { |
| 344 | expires = ktime_add_ns(expires, |
| 345 | vcpu->arch.count_period); |
| 346 | hrtimer_start(&vcpu->arch.comparecount_timer, expires, |
| 347 | HRTIMER_MODE_ABS); |
| 348 | } |
| 349 | } |
| 350 | |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 351 | return count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | /** |
| 355 | * kvm_mips_read_count() - Read the current count value. |
| 356 | * @vcpu: Virtual CPU. |
| 357 | * |
| 358 | * Read the current guest CP0_Count value, taking into account whether the timer |
| 359 | * is stopped. |
| 360 | * |
| 361 | * Returns: The current guest CP0_Count value. |
| 362 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 363 | u32 kvm_mips_read_count(struct kvm_vcpu *vcpu) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 364 | { |
| 365 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 366 | |
| 367 | /* If count disabled just read static copy of count */ |
| 368 | if (kvm_mips_count_disabled(vcpu)) |
| 369 | return kvm_read_c0_guest_count(cop0); |
| 370 | |
| 371 | return kvm_mips_read_count_running(vcpu, ktime_get()); |
| 372 | } |
| 373 | |
| 374 | /** |
| 375 | * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer. |
| 376 | * @vcpu: Virtual CPU. |
| 377 | * @count: Output pointer for CP0_Count value at point of freeze. |
| 378 | * |
| 379 | * Freeze the hrtimer safely and return both the ktime and the CP0_Count value |
| 380 | * at the point it was frozen. It is guaranteed that any pending interrupts at |
| 381 | * the point it was frozen are handled, and none after that point. |
| 382 | * |
| 383 | * This is useful where the time/CP0_Count is needed in the calculation of the |
| 384 | * new parameters. |
| 385 | * |
| 386 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). |
| 387 | * |
| 388 | * Returns: The ktime at the point of freeze. |
| 389 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 390 | static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 391 | { |
| 392 | ktime_t now; |
| 393 | |
| 394 | /* stop hrtimer before finding time */ |
| 395 | hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 396 | now = ktime_get(); |
| 397 | |
| 398 | /* find count at this point and handle pending hrtimer */ |
| 399 | *count = kvm_mips_read_count_running(vcpu, now); |
| 400 | |
| 401 | return now; |
| 402 | } |
| 403 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 404 | /** |
| 405 | * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry. |
| 406 | * @vcpu: Virtual CPU. |
| 407 | * @now: ktime at point of resume. |
| 408 | * @count: CP0_Count at point of resume. |
| 409 | * |
| 410 | * Resumes the timer and updates the timer expiry based on @now and @count. |
| 411 | * This can be used in conjunction with kvm_mips_freeze_timer() when timer |
| 412 | * parameters need to be changed. |
| 413 | * |
| 414 | * It is guaranteed that a timer interrupt immediately after resume will be |
| 415 | * handled, but not if CP_Compare is exactly at @count. That case is already |
| 416 | * handled by kvm_mips_freeze_timer(). |
| 417 | * |
| 418 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). |
| 419 | */ |
| 420 | static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 421 | ktime_t now, u32 count) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 422 | { |
| 423 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 424 | u32 compare; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 425 | u64 delta; |
| 426 | ktime_t expire; |
| 427 | |
| 428 | /* Calculate timeout (wrap 0 to 2^32) */ |
| 429 | compare = kvm_read_c0_guest_compare(cop0); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 430 | delta = (u64)(u32)(compare - count - 1) + 1; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 431 | delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz); |
| 432 | expire = ktime_add_ns(now, delta); |
| 433 | |
| 434 | /* Update hrtimer to use new timeout */ |
| 435 | hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 436 | hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS); |
| 437 | } |
| 438 | |
| 439 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 440 | * kvm_mips_write_count() - Modify the count and update timer. |
| 441 | * @vcpu: Virtual CPU. |
| 442 | * @count: Guest CP0_Count value to set. |
| 443 | * |
| 444 | * Sets the CP0_Count value and updates the timer accordingly. |
| 445 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 446 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 447 | { |
| 448 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 449 | ktime_t now; |
| 450 | |
| 451 | /* Calculate bias */ |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 452 | now = kvm_mips_count_time(vcpu); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 453 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); |
| 454 | |
| 455 | if (kvm_mips_count_disabled(vcpu)) |
| 456 | /* The timer's disabled, adjust the static count */ |
| 457 | kvm_write_c0_guest_count(cop0, count); |
| 458 | else |
| 459 | /* Update timeout */ |
| 460 | kvm_mips_resume_hrtimer(vcpu, now, count); |
| 461 | } |
| 462 | |
| 463 | /** |
| 464 | * kvm_mips_init_count() - Initialise timer. |
| 465 | * @vcpu: Virtual CPU. |
| 466 | * |
| 467 | * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set |
| 468 | * it going if it's enabled. |
| 469 | */ |
| 470 | void kvm_mips_init_count(struct kvm_vcpu *vcpu) |
| 471 | { |
| 472 | /* 100 MHz */ |
| 473 | vcpu->arch.count_hz = 100*1000*1000; |
| 474 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, |
| 475 | vcpu->arch.count_hz); |
| 476 | vcpu->arch.count_dyn_bias = 0; |
| 477 | |
| 478 | /* Starting at 0 */ |
| 479 | kvm_mips_write_count(vcpu, 0); |
| 480 | } |
| 481 | |
| 482 | /** |
James Hogan | f74a8e2 | 2014-05-29 10:16:38 +0100 | [diff] [blame] | 483 | * kvm_mips_set_count_hz() - Update the frequency of the timer. |
| 484 | * @vcpu: Virtual CPU. |
| 485 | * @count_hz: Frequency of CP0_Count timer in Hz. |
| 486 | * |
| 487 | * Change the frequency of the CP0_Count timer. This is done atomically so that |
| 488 | * CP0_Count is continuous and no timer interrupt is lost. |
| 489 | * |
| 490 | * Returns: -EINVAL if @count_hz is out of range. |
| 491 | * 0 on success. |
| 492 | */ |
| 493 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz) |
| 494 | { |
| 495 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 496 | int dc; |
| 497 | ktime_t now; |
| 498 | u32 count; |
| 499 | |
| 500 | /* ensure the frequency is in a sensible range... */ |
| 501 | if (count_hz <= 0 || count_hz > NSEC_PER_SEC) |
| 502 | return -EINVAL; |
| 503 | /* ... and has actually changed */ |
| 504 | if (vcpu->arch.count_hz == count_hz) |
| 505 | return 0; |
| 506 | |
| 507 | /* Safely freeze timer so we can keep it continuous */ |
| 508 | dc = kvm_mips_count_disabled(vcpu); |
| 509 | if (dc) { |
| 510 | now = kvm_mips_count_time(vcpu); |
| 511 | count = kvm_read_c0_guest_count(cop0); |
| 512 | } else { |
| 513 | now = kvm_mips_freeze_hrtimer(vcpu, &count); |
| 514 | } |
| 515 | |
| 516 | /* Update the frequency */ |
| 517 | vcpu->arch.count_hz = count_hz; |
| 518 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz); |
| 519 | vcpu->arch.count_dyn_bias = 0; |
| 520 | |
| 521 | /* Calculate adjusted bias so dynamic count is unchanged */ |
| 522 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); |
| 523 | |
| 524 | /* Update and resume hrtimer */ |
| 525 | if (!dc) |
| 526 | kvm_mips_resume_hrtimer(vcpu, now, count); |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 531 | * kvm_mips_write_compare() - Modify compare and update timer. |
| 532 | * @vcpu: Virtual CPU. |
| 533 | * @compare: New CP0_Compare value. |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 534 | * @ack: Whether to acknowledge timer interrupt. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 535 | * |
| 536 | * Update CP0_Compare to a new value and update the timeout. |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 537 | * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure |
| 538 | * any pending timer interrupt is preserved. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 539 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 540 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 541 | { |
| 542 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 543 | int dc; |
| 544 | u32 old_compare = kvm_read_c0_guest_compare(cop0); |
| 545 | ktime_t now; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 546 | u32 count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 547 | |
| 548 | /* if unchanged, must just be an ack */ |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 549 | if (old_compare == compare) { |
| 550 | if (!ack) |
| 551 | return; |
| 552 | kvm_mips_callbacks->dequeue_timer_int(vcpu); |
| 553 | kvm_write_c0_guest_compare(cop0, compare); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 554 | return; |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 555 | } |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 556 | |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 557 | /* freeze_hrtimer() takes care of timer interrupts <= count */ |
| 558 | dc = kvm_mips_count_disabled(vcpu); |
| 559 | if (!dc) |
| 560 | now = kvm_mips_freeze_hrtimer(vcpu, &count); |
| 561 | |
| 562 | if (ack) |
| 563 | kvm_mips_callbacks->dequeue_timer_int(vcpu); |
| 564 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 565 | kvm_write_c0_guest_compare(cop0, compare); |
| 566 | |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 567 | /* resume_hrtimer() takes care of timer interrupts > count */ |
| 568 | if (!dc) |
| 569 | kvm_mips_resume_hrtimer(vcpu, now, count); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | /** |
| 573 | * kvm_mips_count_disable() - Disable count. |
| 574 | * @vcpu: Virtual CPU. |
| 575 | * |
| 576 | * Disable the CP0_Count timer. A timer interrupt on or before the final stop |
| 577 | * time will be handled but not after. |
| 578 | * |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 579 | * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or |
| 580 | * count_ctl.DC has been set (count disabled). |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 581 | * |
| 582 | * Returns: The time that the timer was stopped. |
| 583 | */ |
| 584 | static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu) |
| 585 | { |
| 586 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 587 | u32 count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 588 | ktime_t now; |
| 589 | |
| 590 | /* Stop hrtimer */ |
| 591 | hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 592 | |
| 593 | /* Set the static count from the dynamic count, handling pending TI */ |
| 594 | now = ktime_get(); |
| 595 | count = kvm_mips_read_count_running(vcpu, now); |
| 596 | kvm_write_c0_guest_count(cop0, count); |
| 597 | |
| 598 | return now; |
| 599 | } |
| 600 | |
| 601 | /** |
| 602 | * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC. |
| 603 | * @vcpu: Virtual CPU. |
| 604 | * |
| 605 | * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 606 | * before the final stop time will be handled if the timer isn't disabled by |
| 607 | * count_ctl.DC, but not after. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 608 | * |
| 609 | * Assumes CP0_Cause.DC is clear (count enabled). |
| 610 | */ |
| 611 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu) |
| 612 | { |
| 613 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 614 | |
| 615 | kvm_set_c0_guest_cause(cop0, CAUSEF_DC); |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 616 | if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) |
| 617 | kvm_mips_count_disable(vcpu); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | /** |
| 621 | * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC. |
| 622 | * @vcpu: Virtual CPU. |
| 623 | * |
| 624 | * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 625 | * the start time will be handled if the timer isn't disabled by count_ctl.DC, |
| 626 | * potentially before even returning, so the caller should be careful with |
| 627 | * ordering of CP0_Cause modifications so as not to lose it. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 628 | * |
| 629 | * Assumes CP0_Cause.DC is set (count disabled). |
| 630 | */ |
| 631 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu) |
| 632 | { |
| 633 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 634 | u32 count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 635 | |
| 636 | kvm_clear_c0_guest_cause(cop0, CAUSEF_DC); |
| 637 | |
| 638 | /* |
| 639 | * Set the dynamic count to match the static count. |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 640 | * This starts the hrtimer if count_ctl.DC allows it. |
| 641 | * Otherwise it conveniently updates the biases. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 642 | */ |
| 643 | count = kvm_read_c0_guest_count(cop0); |
| 644 | kvm_mips_write_count(vcpu, count); |
| 645 | } |
| 646 | |
| 647 | /** |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 648 | * kvm_mips_set_count_ctl() - Update the count control KVM register. |
| 649 | * @vcpu: Virtual CPU. |
| 650 | * @count_ctl: Count control register new value. |
| 651 | * |
| 652 | * Set the count control KVM register. The timer is updated accordingly. |
| 653 | * |
| 654 | * Returns: -EINVAL if reserved bits are set. |
| 655 | * 0 on success. |
| 656 | */ |
| 657 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl) |
| 658 | { |
| 659 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 660 | s64 changed = count_ctl ^ vcpu->arch.count_ctl; |
| 661 | s64 delta; |
| 662 | ktime_t expire, now; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 663 | u32 count, compare; |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 664 | |
| 665 | /* Only allow defined bits to be changed */ |
| 666 | if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC)) |
| 667 | return -EINVAL; |
| 668 | |
| 669 | /* Apply new value */ |
| 670 | vcpu->arch.count_ctl = count_ctl; |
| 671 | |
| 672 | /* Master CP0_Count disable */ |
| 673 | if (changed & KVM_REG_MIPS_COUNT_CTL_DC) { |
| 674 | /* Is CP0_Cause.DC already disabling CP0_Count? */ |
| 675 | if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) { |
| 676 | if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) |
| 677 | /* Just record the current time */ |
| 678 | vcpu->arch.count_resume = ktime_get(); |
| 679 | } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) { |
| 680 | /* disable timer and record current time */ |
| 681 | vcpu->arch.count_resume = kvm_mips_count_disable(vcpu); |
| 682 | } else { |
| 683 | /* |
| 684 | * Calculate timeout relative to static count at resume |
| 685 | * time (wrap 0 to 2^32). |
| 686 | */ |
| 687 | count = kvm_read_c0_guest_count(cop0); |
| 688 | compare = kvm_read_c0_guest_compare(cop0); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 689 | delta = (u64)(u32)(compare - count - 1) + 1; |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 690 | delta = div_u64(delta * NSEC_PER_SEC, |
| 691 | vcpu->arch.count_hz); |
| 692 | expire = ktime_add_ns(vcpu->arch.count_resume, delta); |
| 693 | |
| 694 | /* Handle pending interrupt */ |
| 695 | now = ktime_get(); |
| 696 | if (ktime_compare(now, expire) >= 0) |
| 697 | /* Nothing should be waiting on the timeout */ |
| 698 | kvm_mips_callbacks->queue_timer_int(vcpu); |
| 699 | |
| 700 | /* Resume hrtimer without changing bias */ |
| 701 | count = kvm_mips_read_count_running(vcpu, now); |
| 702 | kvm_mips_resume_hrtimer(vcpu, now, count); |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | return 0; |
| 707 | } |
| 708 | |
| 709 | /** |
| 710 | * kvm_mips_set_count_resume() - Update the count resume KVM register. |
| 711 | * @vcpu: Virtual CPU. |
| 712 | * @count_resume: Count resume register new value. |
| 713 | * |
| 714 | * Set the count resume KVM register. |
| 715 | * |
| 716 | * Returns: -EINVAL if out of valid range (0..now). |
| 717 | * 0 on success. |
| 718 | */ |
| 719 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume) |
| 720 | { |
| 721 | /* |
| 722 | * It doesn't make sense for the resume time to be in the future, as it |
| 723 | * would be possible for the next interrupt to be more than a full |
| 724 | * period in the future. |
| 725 | */ |
| 726 | if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get())) |
| 727 | return -EINVAL; |
| 728 | |
| 729 | vcpu->arch.count_resume = ns_to_ktime(count_resume); |
| 730 | return 0; |
| 731 | } |
| 732 | |
| 733 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 734 | * kvm_mips_count_timeout() - Push timer forward on timeout. |
| 735 | * @vcpu: Virtual CPU. |
| 736 | * |
| 737 | * Handle an hrtimer event by push the hrtimer forward a period. |
| 738 | * |
| 739 | * Returns: The hrtimer_restart value to return to the hrtimer subsystem. |
| 740 | */ |
| 741 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu) |
| 742 | { |
| 743 | /* Add the Count period to the current expiry time */ |
| 744 | hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer, |
| 745 | vcpu->arch.count_period); |
| 746 | return HRTIMER_RESTART; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 747 | } |
| 748 | |
| 749 | enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu) |
| 750 | { |
| 751 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 752 | enum emulation_result er = EMULATE_DONE; |
| 753 | |
| 754 | if (kvm_read_c0_guest_status(cop0) & ST0_EXL) { |
| 755 | kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc, |
| 756 | kvm_read_c0_guest_epc(cop0)); |
| 757 | kvm_clear_c0_guest_status(cop0, ST0_EXL); |
| 758 | vcpu->arch.pc = kvm_read_c0_guest_epc(cop0); |
| 759 | |
| 760 | } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) { |
| 761 | kvm_clear_c0_guest_status(cop0, ST0_ERL); |
| 762 | vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0); |
| 763 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 764 | kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n", |
| 765 | vcpu->arch.pc); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 766 | er = EMULATE_FAIL; |
| 767 | } |
| 768 | |
| 769 | return er; |
| 770 | } |
| 771 | |
| 772 | enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu) |
| 773 | { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 774 | kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc, |
| 775 | vcpu->arch.pending_exceptions); |
| 776 | |
| 777 | ++vcpu->stat.wait_exits; |
James Hogan | 1e09e86 | 2016-06-14 09:40:12 +0100 | [diff] [blame] | 778 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_WAIT); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 779 | if (!vcpu->arch.pending_exceptions) { |
| 780 | vcpu->arch.wait = 1; |
| 781 | kvm_vcpu_block(vcpu); |
| 782 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 783 | /* |
| 784 | * We we are runnable, then definitely go off to user space to |
| 785 | * check if any I/O interrupts are pending. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 786 | */ |
| 787 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { |
| 788 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
| 789 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
| 790 | } |
| 791 | } |
| 792 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 793 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 794 | } |
| 795 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 796 | /* |
| 797 | * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that |
| 798 | * we can catch this, if things ever change |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 799 | */ |
| 800 | enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu) |
| 801 | { |
| 802 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 803 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 804 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 805 | kvm_err("[%#lx] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0)); |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 806 | return EMULATE_FAIL; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 807 | } |
| 808 | |
| 809 | /* Write Guest TLB Entry @ Index */ |
| 810 | enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu) |
| 811 | { |
| 812 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 813 | int index = kvm_read_c0_guest_index(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 814 | struct kvm_mips_tlb *tlb = NULL; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 815 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 816 | |
| 817 | if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 818 | kvm_debug("%s: illegal index: %d\n", __func__, index); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 819 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 820 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
| 821 | kvm_read_c0_guest_entrylo0(cop0), |
| 822 | kvm_read_c0_guest_entrylo1(cop0), |
| 823 | kvm_read_c0_guest_pagemask(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 824 | index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE; |
| 825 | } |
| 826 | |
| 827 | tlb = &vcpu->arch.guest_tlb[index]; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 828 | /* |
| 829 | * Probe the shadow host TLB for the entry being overwritten, if one |
| 830 | * matches, invalidate it |
| 831 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 832 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 833 | |
| 834 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); |
| 835 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); |
James Hogan | 9fbfb06 | 2016-06-09 14:19:17 +0100 | [diff] [blame] | 836 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
| 837 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 838 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 839 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 840 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
| 841 | kvm_read_c0_guest_entrylo0(cop0), |
| 842 | kvm_read_c0_guest_entrylo1(cop0), |
| 843 | kvm_read_c0_guest_pagemask(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 844 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 845 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 846 | } |
| 847 | |
| 848 | /* Write Guest TLB Entry @ Random Index */ |
| 849 | enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) |
| 850 | { |
| 851 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 852 | struct kvm_mips_tlb *tlb = NULL; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 853 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 854 | int index; |
| 855 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 856 | get_random_bytes(&index, sizeof(index)); |
| 857 | index &= (KVM_MIPS_GUEST_TLB_SIZE - 1); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 858 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 859 | tlb = &vcpu->arch.guest_tlb[index]; |
| 860 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 861 | /* |
| 862 | * Probe the shadow host TLB for the entry being overwritten, if one |
| 863 | * matches, invalidate it |
| 864 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 865 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 866 | |
| 867 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); |
| 868 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); |
James Hogan | 9fbfb06 | 2016-06-09 14:19:17 +0100 | [diff] [blame] | 869 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
| 870 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 871 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 872 | kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n", |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 873 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
| 874 | kvm_read_c0_guest_entrylo0(cop0), |
| 875 | kvm_read_c0_guest_entrylo1(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 876 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 877 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu) |
| 881 | { |
| 882 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 883 | long entryhi = kvm_read_c0_guest_entryhi(cop0); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 884 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 885 | int index = -1; |
| 886 | |
| 887 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); |
| 888 | |
| 889 | kvm_write_c0_guest_index(cop0, index); |
| 890 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 891 | kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi, |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 892 | index); |
| 893 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 894 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 895 | } |
| 896 | |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 897 | /** |
| 898 | * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1 |
| 899 | * @vcpu: Virtual CPU. |
| 900 | * |
| 901 | * Finds the mask of bits which are writable in the guest's Config1 CP0 |
| 902 | * register, by userland (currently read-only to the guest). |
| 903 | */ |
| 904 | unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu) |
| 905 | { |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 906 | unsigned int mask = 0; |
| 907 | |
| 908 | /* Permit FPU to be present if FPU is supported */ |
| 909 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) |
| 910 | mask |= MIPS_CONF1_FP; |
| 911 | |
| 912 | return mask; |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 913 | } |
| 914 | |
| 915 | /** |
| 916 | * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3 |
| 917 | * @vcpu: Virtual CPU. |
| 918 | * |
| 919 | * Finds the mask of bits which are writable in the guest's Config3 CP0 |
| 920 | * register, by userland (currently read-only to the guest). |
| 921 | */ |
| 922 | unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu) |
| 923 | { |
James Hogan | cef061d0 | 2016-06-15 19:29:54 +0100 | [diff] [blame] | 924 | /* Config4 and ULRI are optional */ |
| 925 | unsigned int mask = MIPS_CONF_M | MIPS_CONF3_ULRI; |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 926 | |
| 927 | /* Permit MSA to be present if MSA is supported */ |
| 928 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) |
| 929 | mask |= MIPS_CONF3_MSA; |
| 930 | |
| 931 | return mask; |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | /** |
| 935 | * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4 |
| 936 | * @vcpu: Virtual CPU. |
| 937 | * |
| 938 | * Finds the mask of bits which are writable in the guest's Config4 CP0 |
| 939 | * register, by userland (currently read-only to the guest). |
| 940 | */ |
| 941 | unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu) |
| 942 | { |
| 943 | /* Config5 is optional */ |
| 944 | return MIPS_CONF_M; |
| 945 | } |
| 946 | |
| 947 | /** |
| 948 | * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5 |
| 949 | * @vcpu: Virtual CPU. |
| 950 | * |
| 951 | * Finds the mask of bits which are writable in the guest's Config5 CP0 |
| 952 | * register, by the guest itself. |
| 953 | */ |
| 954 | unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu) |
| 955 | { |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 956 | unsigned int mask = 0; |
| 957 | |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 958 | /* Permit MSAEn changes if MSA supported and enabled */ |
| 959 | if (kvm_mips_guest_has_msa(&vcpu->arch)) |
| 960 | mask |= MIPS_CONF5_MSAEN; |
| 961 | |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 962 | /* |
| 963 | * Permit guest FPU mode changes if FPU is enabled and the relevant |
| 964 | * feature exists according to FIR register. |
| 965 | */ |
| 966 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) { |
| 967 | if (cpu_has_fre) |
| 968 | mask |= MIPS_CONF5_FRE; |
| 969 | /* We don't support UFR or UFE */ |
| 970 | } |
| 971 | |
| 972 | return mask; |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 973 | } |
| 974 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 975 | enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, |
| 976 | u32 *opc, u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 977 | struct kvm_run *run, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 978 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 979 | { |
| 980 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 981 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 982 | u32 rt, rd, sel; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 983 | unsigned long curr_pc; |
| 984 | |
| 985 | /* |
| 986 | * Update PC and hold onto current PC in case there is |
| 987 | * an error and we want to rollback the PC |
| 988 | */ |
| 989 | curr_pc = vcpu->arch.pc; |
| 990 | er = update_pc(vcpu, cause); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 991 | if (er == EMULATE_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 992 | return er; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 993 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 994 | if (inst.co_format.co) { |
| 995 | switch (inst.co_format.func) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 996 | case tlbr_op: /* Read indexed TLB entry */ |
| 997 | er = kvm_mips_emul_tlbr(vcpu); |
| 998 | break; |
| 999 | case tlbwi_op: /* Write indexed */ |
| 1000 | er = kvm_mips_emul_tlbwi(vcpu); |
| 1001 | break; |
| 1002 | case tlbwr_op: /* Write random */ |
| 1003 | er = kvm_mips_emul_tlbwr(vcpu); |
| 1004 | break; |
| 1005 | case tlbp_op: /* TLB Probe */ |
| 1006 | er = kvm_mips_emul_tlbp(vcpu); |
| 1007 | break; |
| 1008 | case rfe_op: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1009 | kvm_err("!!!COP0_RFE!!!\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1010 | break; |
| 1011 | case eret_op: |
| 1012 | er = kvm_mips_emul_eret(vcpu); |
| 1013 | goto dont_update_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1014 | case wait_op: |
| 1015 | er = kvm_mips_emul_wait(vcpu); |
| 1016 | break; |
| 1017 | } |
| 1018 | } else { |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1019 | rt = inst.c0r_format.rt; |
| 1020 | rd = inst.c0r_format.rd; |
| 1021 | sel = inst.c0r_format.sel; |
| 1022 | |
| 1023 | switch (inst.c0r_format.rs) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1024 | case mfc_op: |
| 1025 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS |
| 1026 | cop0->stat[rd][sel]++; |
| 1027 | #endif |
| 1028 | /* Get reg */ |
| 1029 | if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1030 | vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1031 | } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) { |
| 1032 | vcpu->arch.gprs[rt] = 0x0; |
| 1033 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1034 | kvm_mips_trans_mfc0(inst, opc, vcpu); |
| 1035 | #endif |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1036 | } else { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1037 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; |
| 1038 | |
| 1039 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1040 | kvm_mips_trans_mfc0(inst, opc, vcpu); |
| 1041 | #endif |
| 1042 | } |
| 1043 | |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1044 | trace_kvm_hwr(vcpu, KVM_TRACE_MFC0, |
| 1045 | KVM_TRACE_COP0(rd, sel), |
| 1046 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1047 | break; |
| 1048 | |
| 1049 | case dmfc_op: |
| 1050 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1051 | |
| 1052 | trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0, |
| 1053 | KVM_TRACE_COP0(rd, sel), |
| 1054 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1055 | break; |
| 1056 | |
| 1057 | case mtc_op: |
| 1058 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS |
| 1059 | cop0->stat[rd][sel]++; |
| 1060 | #endif |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1061 | trace_kvm_hwr(vcpu, KVM_TRACE_MTC0, |
| 1062 | KVM_TRACE_COP0(rd, sel), |
| 1063 | vcpu->arch.gprs[rt]); |
| 1064 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1065 | if ((rd == MIPS_CP0_TLB_INDEX) |
| 1066 | && (vcpu->arch.gprs[rt] >= |
| 1067 | KVM_MIPS_GUEST_TLB_SIZE)) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1068 | kvm_err("Invalid TLB Index: %ld", |
| 1069 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1070 | er = EMULATE_FAIL; |
| 1071 | break; |
| 1072 | } |
| 1073 | #define C0_EBASE_CORE_MASK 0xff |
| 1074 | if ((rd == MIPS_CP0_PRID) && (sel == 1)) { |
| 1075 | /* Preserve CORE number */ |
| 1076 | kvm_change_c0_guest_ebase(cop0, |
| 1077 | ~(C0_EBASE_CORE_MASK), |
| 1078 | vcpu->arch.gprs[rt]); |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1079 | kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n", |
| 1080 | kvm_read_c0_guest_ebase(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1081 | } else if (rd == MIPS_CP0_TLB_HI && sel == 0) { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1082 | u32 nasid = |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1083 | vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1084 | if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) && |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 1085 | ((kvm_read_c0_guest_entryhi(cop0) & |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1086 | KVM_ENTRYHI_ASID) != nasid)) { |
James Hogan | 9887d1c | 2016-06-14 09:40:13 +0100 | [diff] [blame] | 1087 | trace_kvm_asid_change(vcpu, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1088 | kvm_read_c0_guest_entryhi(cop0) |
James Hogan | 9887d1c | 2016-06-14 09:40:13 +0100 | [diff] [blame] | 1089 | & KVM_ENTRYHI_ASID, |
| 1090 | nasid); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1091 | |
| 1092 | /* Blow away the shadow host TLBs */ |
| 1093 | kvm_mips_flush_host_tlb(1); |
| 1094 | } |
| 1095 | kvm_write_c0_guest_entryhi(cop0, |
| 1096 | vcpu->arch.gprs[rt]); |
| 1097 | } |
| 1098 | /* Are we writing to COUNT */ |
| 1099 | else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1100 | kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1101 | goto done; |
| 1102 | } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1103 | /* If we are writing to COMPARE */ |
| 1104 | /* Clear pending timer interrupt, if any */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1105 | kvm_mips_write_compare(vcpu, |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 1106 | vcpu->arch.gprs[rt], |
| 1107 | true); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1108 | } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) { |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1109 | unsigned int old_val, val, change; |
| 1110 | |
| 1111 | old_val = kvm_read_c0_guest_status(cop0); |
| 1112 | val = vcpu->arch.gprs[rt]; |
| 1113 | change = val ^ old_val; |
| 1114 | |
| 1115 | /* Make sure that the NMI bit is never set */ |
| 1116 | val &= ~ST0_NMI; |
| 1117 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1118 | /* |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1119 | * Don't allow CU1 or FR to be set unless FPU |
| 1120 | * capability enabled and exists in guest |
| 1121 | * configuration. |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1122 | */ |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1123 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) |
| 1124 | val &= ~(ST0_CU1 | ST0_FR); |
| 1125 | |
| 1126 | /* |
| 1127 | * Also don't allow FR to be set if host doesn't |
| 1128 | * support it. |
| 1129 | */ |
| 1130 | if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64)) |
| 1131 | val &= ~ST0_FR; |
| 1132 | |
| 1133 | |
| 1134 | /* Handle changes in FPU mode */ |
| 1135 | preempt_disable(); |
| 1136 | |
| 1137 | /* |
| 1138 | * FPU and Vector register state is made |
| 1139 | * UNPREDICTABLE by a change of FR, so don't |
| 1140 | * even bother saving it. |
| 1141 | */ |
| 1142 | if (change & ST0_FR) |
| 1143 | kvm_drop_fpu(vcpu); |
| 1144 | |
| 1145 | /* |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1146 | * If MSA state is already live, it is undefined |
| 1147 | * how it interacts with FR=0 FPU state, and we |
| 1148 | * don't want to hit reserved instruction |
| 1149 | * exceptions trying to save the MSA state later |
| 1150 | * when CU=1 && FR=1, so play it safe and save |
| 1151 | * it first. |
| 1152 | */ |
| 1153 | if (change & ST0_CU1 && !(val & ST0_FR) && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1154 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1155 | kvm_lose_fpu(vcpu); |
| 1156 | |
| 1157 | /* |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1158 | * Propagate CU1 (FPU enable) changes |
| 1159 | * immediately if the FPU context is already |
| 1160 | * loaded. When disabling we leave the context |
| 1161 | * loaded so it can be quickly enabled again in |
| 1162 | * the near future. |
| 1163 | */ |
| 1164 | if (change & ST0_CU1 && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1165 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1166 | change_c0_status(ST0_CU1, val); |
| 1167 | |
| 1168 | preempt_enable(); |
| 1169 | |
| 1170 | kvm_write_c0_guest_status(cop0, val); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1171 | |
| 1172 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1173 | /* |
| 1174 | * If FPU present, we need CU1/FR bits to take |
| 1175 | * effect fairly soon. |
| 1176 | */ |
| 1177 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) |
| 1178 | kvm_mips_trans_mtc0(inst, opc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1179 | #endif |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1180 | } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) { |
| 1181 | unsigned int old_val, val, change, wrmask; |
| 1182 | |
| 1183 | old_val = kvm_read_c0_guest_config5(cop0); |
| 1184 | val = vcpu->arch.gprs[rt]; |
| 1185 | |
| 1186 | /* Only a few bits are writable in Config5 */ |
| 1187 | wrmask = kvm_mips_config5_wrmask(vcpu); |
| 1188 | change = (val ^ old_val) & wrmask; |
| 1189 | val = old_val ^ change; |
| 1190 | |
| 1191 | |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1192 | /* Handle changes in FPU/MSA modes */ |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1193 | preempt_disable(); |
| 1194 | |
| 1195 | /* |
| 1196 | * Propagate FRE changes immediately if the FPU |
| 1197 | * context is already loaded. |
| 1198 | */ |
| 1199 | if (change & MIPS_CONF5_FRE && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1200 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1201 | change_c0_config5(MIPS_CONF5_FRE, val); |
| 1202 | |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1203 | /* |
| 1204 | * Propagate MSAEn changes immediately if the |
| 1205 | * MSA context is already loaded. When disabling |
| 1206 | * we leave the context loaded so it can be |
| 1207 | * quickly enabled again in the near future. |
| 1208 | */ |
| 1209 | if (change & MIPS_CONF5_MSAEN && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1210 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1211 | change_c0_config5(MIPS_CONF5_MSAEN, |
| 1212 | val); |
| 1213 | |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1214 | preempt_enable(); |
| 1215 | |
| 1216 | kvm_write_c0_guest_config5(cop0, val); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1217 | } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1218 | u32 old_cause, new_cause; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1219 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1220 | old_cause = kvm_read_c0_guest_cause(cop0); |
| 1221 | new_cause = vcpu->arch.gprs[rt]; |
| 1222 | /* Update R/W bits */ |
| 1223 | kvm_change_c0_guest_cause(cop0, 0x08800300, |
| 1224 | new_cause); |
| 1225 | /* DC bit enabling/disabling timer? */ |
| 1226 | if ((old_cause ^ new_cause) & CAUSEF_DC) { |
| 1227 | if (new_cause & CAUSEF_DC) |
| 1228 | kvm_mips_count_disable_cause(vcpu); |
| 1229 | else |
| 1230 | kvm_mips_count_enable_cause(vcpu); |
| 1231 | } |
James Hogan | cef061d0 | 2016-06-15 19:29:54 +0100 | [diff] [blame] | 1232 | } else if ((rd == MIPS_CP0_HWRENA) && (sel == 0)) { |
| 1233 | u32 mask = MIPS_HWRENA_CPUNUM | |
| 1234 | MIPS_HWRENA_SYNCISTEP | |
| 1235 | MIPS_HWRENA_CC | |
| 1236 | MIPS_HWRENA_CCRES; |
| 1237 | |
| 1238 | if (kvm_read_c0_guest_config3(cop0) & |
| 1239 | MIPS_CONF3_ULRI) |
| 1240 | mask |= MIPS_HWRENA_ULR; |
| 1241 | cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1242 | } else { |
| 1243 | cop0->reg[rd][sel] = vcpu->arch.gprs[rt]; |
| 1244 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1245 | kvm_mips_trans_mtc0(inst, opc, vcpu); |
| 1246 | #endif |
| 1247 | } |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1248 | break; |
| 1249 | |
| 1250 | case dmtc_op: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1251 | kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n", |
| 1252 | vcpu->arch.pc, rt, rd, sel); |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1253 | trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0, |
| 1254 | KVM_TRACE_COP0(rd, sel), |
| 1255 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1256 | er = EMULATE_FAIL; |
| 1257 | break; |
| 1258 | |
James Hogan | b2c5963 | 2015-12-16 23:49:38 +0000 | [diff] [blame] | 1259 | case mfmc0_op: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1260 | #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS |
| 1261 | cop0->stat[MIPS_CP0_STATUS][0]++; |
| 1262 | #endif |
James Hogan | caa1faa | 2015-12-16 23:49:26 +0000 | [diff] [blame] | 1263 | if (rt != 0) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1264 | vcpu->arch.gprs[rt] = |
| 1265 | kvm_read_c0_guest_status(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1266 | /* EI */ |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1267 | if (inst.mfmc0_format.sc) { |
James Hogan | b2c5963 | 2015-12-16 23:49:38 +0000 | [diff] [blame] | 1268 | kvm_debug("[%#lx] mfmc0_op: EI\n", |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1269 | vcpu->arch.pc); |
| 1270 | kvm_set_c0_guest_status(cop0, ST0_IE); |
| 1271 | } else { |
James Hogan | b2c5963 | 2015-12-16 23:49:38 +0000 | [diff] [blame] | 1272 | kvm_debug("[%#lx] mfmc0_op: DI\n", |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1273 | vcpu->arch.pc); |
| 1274 | kvm_clear_c0_guest_status(cop0, ST0_IE); |
| 1275 | } |
| 1276 | |
| 1277 | break; |
| 1278 | |
| 1279 | case wrpgpr_op: |
| 1280 | { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1281 | u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf; |
| 1282 | u32 pss = |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1283 | (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1284 | /* |
| 1285 | * We don't support any shadow register sets, so |
| 1286 | * SRSCtl[PSS] == SRSCtl[CSS] = 0 |
| 1287 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1288 | if (css || pss) { |
| 1289 | er = EMULATE_FAIL; |
| 1290 | break; |
| 1291 | } |
| 1292 | kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd, |
| 1293 | vcpu->arch.gprs[rt]); |
| 1294 | vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt]; |
| 1295 | } |
| 1296 | break; |
| 1297 | default: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1298 | kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n", |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1299 | vcpu->arch.pc, inst.c0r_format.rs); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1300 | er = EMULATE_FAIL; |
| 1301 | break; |
| 1302 | } |
| 1303 | } |
| 1304 | |
| 1305 | done: |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1306 | /* Rollback PC only if emulation was unsuccessful */ |
| 1307 | if (er == EMULATE_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1308 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1309 | |
| 1310 | dont_update_pc: |
| 1311 | /* |
| 1312 | * This is for special instructions whose emulation |
| 1313 | * updates the PC, so do not overwrite the PC under |
| 1314 | * any circumstances |
| 1315 | */ |
| 1316 | |
| 1317 | return er; |
| 1318 | } |
| 1319 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1320 | enum emulation_result kvm_mips_emulate_store(union mips_instruction inst, |
| 1321 | u32 cause, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1322 | struct kvm_run *run, |
| 1323 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1324 | { |
| 1325 | enum emulation_result er = EMULATE_DO_MMIO; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1326 | u32 rt; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1327 | u32 bytes; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1328 | void *data = run->mmio.data; |
| 1329 | unsigned long curr_pc; |
| 1330 | |
| 1331 | /* |
| 1332 | * Update PC and hold onto current PC in case there is |
| 1333 | * an error and we want to rollback the PC |
| 1334 | */ |
| 1335 | curr_pc = vcpu->arch.pc; |
| 1336 | er = update_pc(vcpu, cause); |
| 1337 | if (er == EMULATE_FAIL) |
| 1338 | return er; |
| 1339 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1340 | rt = inst.i_format.rt; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1341 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1342 | switch (inst.i_format.opcode) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1343 | case sb_op: |
| 1344 | bytes = 1; |
| 1345 | if (bytes > sizeof(run->mmio.data)) { |
| 1346 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1347 | run->mmio.len); |
| 1348 | } |
| 1349 | run->mmio.phys_addr = |
| 1350 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1351 | host_cp0_badvaddr); |
| 1352 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1353 | er = EMULATE_FAIL; |
| 1354 | break; |
| 1355 | } |
| 1356 | run->mmio.len = bytes; |
| 1357 | run->mmio.is_write = 1; |
| 1358 | vcpu->mmio_needed = 1; |
| 1359 | vcpu->mmio_is_write = 1; |
| 1360 | *(u8 *) data = vcpu->arch.gprs[rt]; |
| 1361 | kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n", |
| 1362 | vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt], |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1363 | *(u8 *) data); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1364 | |
| 1365 | break; |
| 1366 | |
| 1367 | case sw_op: |
| 1368 | bytes = 4; |
| 1369 | if (bytes > sizeof(run->mmio.data)) { |
| 1370 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1371 | run->mmio.len); |
| 1372 | } |
| 1373 | run->mmio.phys_addr = |
| 1374 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1375 | host_cp0_badvaddr); |
| 1376 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1377 | er = EMULATE_FAIL; |
| 1378 | break; |
| 1379 | } |
| 1380 | |
| 1381 | run->mmio.len = bytes; |
| 1382 | run->mmio.is_write = 1; |
| 1383 | vcpu->mmio_needed = 1; |
| 1384 | vcpu->mmio_is_write = 1; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1385 | *(u32 *) data = vcpu->arch.gprs[rt]; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1386 | |
| 1387 | kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n", |
| 1388 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1389 | vcpu->arch.gprs[rt], *(u32 *) data); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1390 | break; |
| 1391 | |
| 1392 | case sh_op: |
| 1393 | bytes = 2; |
| 1394 | if (bytes > sizeof(run->mmio.data)) { |
| 1395 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1396 | run->mmio.len); |
| 1397 | } |
| 1398 | run->mmio.phys_addr = |
| 1399 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1400 | host_cp0_badvaddr); |
| 1401 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1402 | er = EMULATE_FAIL; |
| 1403 | break; |
| 1404 | } |
| 1405 | |
| 1406 | run->mmio.len = bytes; |
| 1407 | run->mmio.is_write = 1; |
| 1408 | vcpu->mmio_needed = 1; |
| 1409 | vcpu->mmio_is_write = 1; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1410 | *(u16 *) data = vcpu->arch.gprs[rt]; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1411 | |
| 1412 | kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n", |
| 1413 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1414 | vcpu->arch.gprs[rt], *(u32 *) data); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1415 | break; |
| 1416 | |
| 1417 | default: |
James Hogan | d86c1eb | 2016-06-14 09:40:17 +0100 | [diff] [blame] | 1418 | kvm_err("Store not yet supported (inst=0x%08x)\n", |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1419 | inst.word); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1420 | er = EMULATE_FAIL; |
| 1421 | break; |
| 1422 | } |
| 1423 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1424 | /* Rollback PC if emulation was unsuccessful */ |
| 1425 | if (er == EMULATE_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1426 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1427 | |
| 1428 | return er; |
| 1429 | } |
| 1430 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1431 | enum emulation_result kvm_mips_emulate_load(union mips_instruction inst, |
| 1432 | u32 cause, struct kvm_run *run, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1433 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1434 | { |
| 1435 | enum emulation_result er = EMULATE_DO_MMIO; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1436 | u32 op, rt; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1437 | u32 bytes; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1438 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1439 | rt = inst.i_format.rt; |
| 1440 | op = inst.i_format.opcode; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1441 | |
| 1442 | vcpu->arch.pending_load_cause = cause; |
| 1443 | vcpu->arch.io_gpr = rt; |
| 1444 | |
| 1445 | switch (op) { |
| 1446 | case lw_op: |
| 1447 | bytes = 4; |
| 1448 | if (bytes > sizeof(run->mmio.data)) { |
| 1449 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1450 | run->mmio.len); |
| 1451 | er = EMULATE_FAIL; |
| 1452 | break; |
| 1453 | } |
| 1454 | run->mmio.phys_addr = |
| 1455 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1456 | host_cp0_badvaddr); |
| 1457 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1458 | er = EMULATE_FAIL; |
| 1459 | break; |
| 1460 | } |
| 1461 | |
| 1462 | run->mmio.len = bytes; |
| 1463 | run->mmio.is_write = 0; |
| 1464 | vcpu->mmio_needed = 1; |
| 1465 | vcpu->mmio_is_write = 0; |
| 1466 | break; |
| 1467 | |
| 1468 | case lh_op: |
| 1469 | case lhu_op: |
| 1470 | bytes = 2; |
| 1471 | if (bytes > sizeof(run->mmio.data)) { |
| 1472 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1473 | run->mmio.len); |
| 1474 | er = EMULATE_FAIL; |
| 1475 | break; |
| 1476 | } |
| 1477 | run->mmio.phys_addr = |
| 1478 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1479 | host_cp0_badvaddr); |
| 1480 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1481 | er = EMULATE_FAIL; |
| 1482 | break; |
| 1483 | } |
| 1484 | |
| 1485 | run->mmio.len = bytes; |
| 1486 | run->mmio.is_write = 0; |
| 1487 | vcpu->mmio_needed = 1; |
| 1488 | vcpu->mmio_is_write = 0; |
| 1489 | |
| 1490 | if (op == lh_op) |
| 1491 | vcpu->mmio_needed = 2; |
| 1492 | else |
| 1493 | vcpu->mmio_needed = 1; |
| 1494 | |
| 1495 | break; |
| 1496 | |
| 1497 | case lbu_op: |
| 1498 | case lb_op: |
| 1499 | bytes = 1; |
| 1500 | if (bytes > sizeof(run->mmio.data)) { |
| 1501 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1502 | run->mmio.len); |
| 1503 | er = EMULATE_FAIL; |
| 1504 | break; |
| 1505 | } |
| 1506 | run->mmio.phys_addr = |
| 1507 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1508 | host_cp0_badvaddr); |
| 1509 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1510 | er = EMULATE_FAIL; |
| 1511 | break; |
| 1512 | } |
| 1513 | |
| 1514 | run->mmio.len = bytes; |
| 1515 | run->mmio.is_write = 0; |
| 1516 | vcpu->mmio_is_write = 0; |
| 1517 | |
| 1518 | if (op == lb_op) |
| 1519 | vcpu->mmio_needed = 2; |
| 1520 | else |
| 1521 | vcpu->mmio_needed = 1; |
| 1522 | |
| 1523 | break; |
| 1524 | |
| 1525 | default: |
James Hogan | d86c1eb | 2016-06-14 09:40:17 +0100 | [diff] [blame] | 1526 | kvm_err("Load not yet supported (inst=0x%08x)\n", |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1527 | inst.word); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1528 | er = EMULATE_FAIL; |
| 1529 | break; |
| 1530 | } |
| 1531 | |
| 1532 | return er; |
| 1533 | } |
| 1534 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1535 | enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst, |
| 1536 | u32 *opc, u32 cause, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1537 | struct kvm_run *run, |
| 1538 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1539 | { |
| 1540 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1541 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1542 | u32 cache, op_inst, op, base; |
| 1543 | s16 offset; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1544 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 1545 | unsigned long va; |
| 1546 | unsigned long curr_pc; |
| 1547 | |
| 1548 | /* |
| 1549 | * Update PC and hold onto current PC in case there is |
| 1550 | * an error and we want to rollback the PC |
| 1551 | */ |
| 1552 | curr_pc = vcpu->arch.pc; |
| 1553 | er = update_pc(vcpu, cause); |
| 1554 | if (er == EMULATE_FAIL) |
| 1555 | return er; |
| 1556 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1557 | base = inst.i_format.rs; |
| 1558 | op_inst = inst.i_format.rt; |
| 1559 | offset = inst.i_format.simmediate; |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1560 | cache = op_inst & CacheOp_Cache; |
| 1561 | op = op_inst & CacheOp_Op; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1562 | |
| 1563 | va = arch->gprs[base] + offset; |
| 1564 | |
| 1565 | kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1566 | cache, op, base, arch->gprs[base], offset); |
| 1567 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1568 | /* |
| 1569 | * Treat INDEX_INV as a nop, basically issued by Linux on startup to |
| 1570 | * invalidate the caches entirely by stepping through all the |
| 1571 | * ways/indexes |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1572 | */ |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1573 | if (op == Index_Writeback_Inv) { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1574 | kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1575 | vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base, |
| 1576 | arch->gprs[base], offset); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1577 | |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1578 | if (cache == Cache_D) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1579 | r4k_blast_dcache(); |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1580 | else if (cache == Cache_I) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1581 | r4k_blast_icache(); |
| 1582 | else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1583 | kvm_err("%s: unsupported CACHE INDEX operation\n", |
| 1584 | __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1585 | return EMULATE_FAIL; |
| 1586 | } |
| 1587 | |
| 1588 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1589 | kvm_mips_trans_cache_index(inst, opc, vcpu); |
| 1590 | #endif |
| 1591 | goto done; |
| 1592 | } |
| 1593 | |
| 1594 | preempt_disable(); |
| 1595 | if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1596 | if (kvm_mips_host_tlb_lookup(vcpu, va) < 0) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1597 | kvm_mips_handle_kseg0_tlb_fault(va, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1598 | } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) || |
| 1599 | KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) { |
| 1600 | int index; |
| 1601 | |
| 1602 | /* If an entry already exists then skip */ |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1603 | if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1604 | goto skip_fault; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1605 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1606 | /* |
| 1607 | * If address not in the guest TLB, then give the guest a fault, |
| 1608 | * the resulting handler will do the right thing |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1609 | */ |
| 1610 | index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) | |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 1611 | (kvm_read_c0_guest_entryhi |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1612 | (cop0) & KVM_ENTRYHI_ASID)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1613 | |
| 1614 | if (index < 0) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1615 | vcpu->arch.host_cp0_badvaddr = va; |
James Hogan | 6df82a7 | 2016-06-09 10:50:46 +0100 | [diff] [blame] | 1616 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1617 | er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run, |
| 1618 | vcpu); |
| 1619 | preempt_enable(); |
| 1620 | goto dont_update_pc; |
| 1621 | } else { |
| 1622 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1623 | /* |
| 1624 | * Check if the entry is valid, if not then setup a TLB |
| 1625 | * invalid exception to the guest |
| 1626 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1627 | if (!TLB_IS_VALID(*tlb, va)) { |
James Hogan | 6df82a7 | 2016-06-09 10:50:46 +0100 | [diff] [blame] | 1628 | vcpu->arch.host_cp0_badvaddr = va; |
| 1629 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1630 | er = kvm_mips_emulate_tlbinv_ld(cause, NULL, |
| 1631 | run, vcpu); |
| 1632 | preempt_enable(); |
| 1633 | goto dont_update_pc; |
| 1634 | } else { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1635 | /* |
| 1636 | * We fault an entry from the guest tlb to the |
| 1637 | * shadow host TLB |
| 1638 | */ |
James Hogan | 26ee17f | 2016-06-09 14:19:13 +0100 | [diff] [blame] | 1639 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1640 | } |
| 1641 | } |
| 1642 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1643 | kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1644 | cache, op, base, arch->gprs[base], offset); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1645 | er = EMULATE_FAIL; |
| 1646 | preempt_enable(); |
James Hogan | cc81e94 | 2016-06-09 10:50:45 +0100 | [diff] [blame] | 1647 | goto done; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1648 | |
| 1649 | } |
| 1650 | |
| 1651 | skip_fault: |
| 1652 | /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */ |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1653 | if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1654 | flush_dcache_line(va); |
| 1655 | |
| 1656 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1657 | /* |
| 1658 | * Replace the CACHE instruction, with a SYNCI, not the same, |
| 1659 | * but avoids a trap |
| 1660 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1661 | kvm_mips_trans_cache_va(inst, opc, vcpu); |
| 1662 | #endif |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1663 | } else if (op_inst == Hit_Invalidate_I) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1664 | flush_dcache_line(va); |
| 1665 | flush_icache_line(va); |
| 1666 | |
| 1667 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1668 | /* Replace the CACHE instruction, with a SYNCI */ |
| 1669 | kvm_mips_trans_cache_va(inst, opc, vcpu); |
| 1670 | #endif |
| 1671 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1672 | kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1673 | cache, op, base, arch->gprs[base], offset); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1674 | er = EMULATE_FAIL; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1675 | } |
| 1676 | |
| 1677 | preempt_enable(); |
James Hogan | cc81e94 | 2016-06-09 10:50:45 +0100 | [diff] [blame] | 1678 | done: |
| 1679 | /* Rollback PC only if emulation was unsuccessful */ |
| 1680 | if (er == EMULATE_FAIL) |
| 1681 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1682 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1683 | dont_update_pc: |
James Hogan | cc81e94 | 2016-06-09 10:50:45 +0100 | [diff] [blame] | 1684 | /* |
| 1685 | * This is for exceptions whose emulation updates the PC, so do not |
| 1686 | * overwrite the PC under any circumstances |
| 1687 | */ |
| 1688 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1689 | return er; |
| 1690 | } |
| 1691 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1692 | enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1693 | struct kvm_run *run, |
| 1694 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1695 | { |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1696 | union mips_instruction inst; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1697 | enum emulation_result er = EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1698 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1699 | /* Fetch the instruction. */ |
| 1700 | if (cause & CAUSEF_BD) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1701 | opc += 1; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1702 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1703 | inst.word = kvm_get_inst(opc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1704 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1705 | switch (inst.r_format.opcode) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1706 | case cop0_op: |
| 1707 | er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu); |
| 1708 | break; |
| 1709 | case sb_op: |
| 1710 | case sh_op: |
| 1711 | case sw_op: |
| 1712 | er = kvm_mips_emulate_store(inst, cause, run, vcpu); |
| 1713 | break; |
| 1714 | case lb_op: |
| 1715 | case lbu_op: |
| 1716 | case lhu_op: |
| 1717 | case lh_op: |
| 1718 | case lw_op: |
| 1719 | er = kvm_mips_emulate_load(inst, cause, run, vcpu); |
| 1720 | break; |
| 1721 | |
| 1722 | case cache_op: |
| 1723 | ++vcpu->stat.cache_exits; |
James Hogan | 1e09e86 | 2016-06-14 09:40:12 +0100 | [diff] [blame] | 1724 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1725 | er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu); |
| 1726 | break; |
| 1727 | |
| 1728 | default: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1729 | kvm_err("Instruction emulation not supported (%p/%#x)\n", opc, |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1730 | inst.word); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1731 | kvm_arch_vcpu_dump_regs(vcpu); |
| 1732 | er = EMULATE_FAIL; |
| 1733 | break; |
| 1734 | } |
| 1735 | |
| 1736 | return er; |
| 1737 | } |
| 1738 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1739 | enum emulation_result kvm_mips_emulate_syscall(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1740 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1741 | struct kvm_run *run, |
| 1742 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1743 | { |
| 1744 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1745 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 1746 | enum emulation_result er = EMULATE_DONE; |
| 1747 | |
| 1748 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1749 | /* save old pc */ |
| 1750 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1751 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1752 | |
| 1753 | if (cause & CAUSEF_BD) |
| 1754 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1755 | else |
| 1756 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1757 | |
| 1758 | kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc); |
| 1759 | |
| 1760 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1761 | (EXCCODE_SYS << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1762 | |
| 1763 | /* Set PC to the exception entry point */ |
| 1764 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1765 | |
| 1766 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1767 | kvm_err("Trying to deliver SYSCALL when EXL is already set\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1768 | er = EMULATE_FAIL; |
| 1769 | } |
| 1770 | |
| 1771 | return er; |
| 1772 | } |
| 1773 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1774 | enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1775 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1776 | struct kvm_run *run, |
| 1777 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1778 | { |
| 1779 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1780 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1781 | unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1782 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1783 | |
| 1784 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1785 | /* save old pc */ |
| 1786 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1787 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1788 | |
| 1789 | if (cause & CAUSEF_BD) |
| 1790 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1791 | else |
| 1792 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1793 | |
| 1794 | kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n", |
| 1795 | arch->pc); |
| 1796 | |
| 1797 | /* set pc to the exception entry point */ |
| 1798 | arch->pc = KVM_GUEST_KSEG0 + 0x0; |
| 1799 | |
| 1800 | } else { |
| 1801 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", |
| 1802 | arch->pc); |
| 1803 | |
| 1804 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1805 | } |
| 1806 | |
| 1807 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1808 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1809 | |
| 1810 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1811 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1812 | /* XXXKYMA: is the context register used by linux??? */ |
| 1813 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1814 | /* Blow away the shadow host TLBs */ |
| 1815 | kvm_mips_flush_host_tlb(1); |
| 1816 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1817 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1818 | } |
| 1819 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1820 | enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1821 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1822 | struct kvm_run *run, |
| 1823 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1824 | { |
| 1825 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1826 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1827 | unsigned long entryhi = |
| 1828 | (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1829 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1830 | |
| 1831 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1832 | /* save old pc */ |
| 1833 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1834 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1835 | |
| 1836 | if (cause & CAUSEF_BD) |
| 1837 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1838 | else |
| 1839 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1840 | |
| 1841 | kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n", |
| 1842 | arch->pc); |
| 1843 | |
| 1844 | /* set pc to the exception entry point */ |
| 1845 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1846 | |
| 1847 | } else { |
| 1848 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", |
| 1849 | arch->pc); |
| 1850 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1851 | } |
| 1852 | |
| 1853 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1854 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1855 | |
| 1856 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1857 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1858 | /* XXXKYMA: is the context register used by linux??? */ |
| 1859 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1860 | /* Blow away the shadow host TLBs */ |
| 1861 | kvm_mips_flush_host_tlb(1); |
| 1862 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1863 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1864 | } |
| 1865 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1866 | enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1867 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1868 | struct kvm_run *run, |
| 1869 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1870 | { |
| 1871 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1872 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1873 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1874 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1875 | |
| 1876 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1877 | /* save old pc */ |
| 1878 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1879 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1880 | |
| 1881 | if (cause & CAUSEF_BD) |
| 1882 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1883 | else |
| 1884 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1885 | |
| 1886 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", |
| 1887 | arch->pc); |
| 1888 | |
| 1889 | /* Set PC to the exception entry point */ |
| 1890 | arch->pc = KVM_GUEST_KSEG0 + 0x0; |
| 1891 | } else { |
| 1892 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", |
| 1893 | arch->pc); |
| 1894 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1895 | } |
| 1896 | |
| 1897 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1898 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1899 | |
| 1900 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1901 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1902 | /* XXXKYMA: is the context register used by linux??? */ |
| 1903 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1904 | /* Blow away the shadow host TLBs */ |
| 1905 | kvm_mips_flush_host_tlb(1); |
| 1906 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1907 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1908 | } |
| 1909 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1910 | enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1911 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1912 | struct kvm_run *run, |
| 1913 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1914 | { |
| 1915 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1916 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1917 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1918 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1919 | |
| 1920 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1921 | /* save old pc */ |
| 1922 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1923 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1924 | |
| 1925 | if (cause & CAUSEF_BD) |
| 1926 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1927 | else |
| 1928 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1929 | |
| 1930 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", |
| 1931 | arch->pc); |
| 1932 | |
| 1933 | /* Set PC to the exception entry point */ |
| 1934 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1935 | } else { |
| 1936 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", |
| 1937 | arch->pc); |
| 1938 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1939 | } |
| 1940 | |
| 1941 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1942 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1943 | |
| 1944 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1945 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1946 | /* XXXKYMA: is the context register used by linux??? */ |
| 1947 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1948 | /* Blow away the shadow host TLBs */ |
| 1949 | kvm_mips_flush_host_tlb(1); |
| 1950 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1951 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1952 | } |
| 1953 | |
| 1954 | /* TLBMOD: store into address matching TLB with Dirty bit off */ |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1955 | enum emulation_result kvm_mips_handle_tlbmod(u32 cause, u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1956 | struct kvm_run *run, |
| 1957 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1958 | { |
| 1959 | enum emulation_result er = EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1960 | #ifdef DEBUG |
James Hogan | 3d65483 | 2014-05-29 10:16:41 +0100 | [diff] [blame] | 1961 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1962 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1963 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
James Hogan | 3d65483 | 2014-05-29 10:16:41 +0100 | [diff] [blame] | 1964 | int index; |
| 1965 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1966 | /* If address not in the guest TLB, then we are in trouble */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1967 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); |
| 1968 | if (index < 0) { |
| 1969 | /* XXXKYMA Invalidate and retry */ |
| 1970 | kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr); |
| 1971 | kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n", |
| 1972 | __func__, entryhi); |
| 1973 | kvm_mips_dump_guest_tlbs(vcpu); |
| 1974 | kvm_mips_dump_host_tlbs(); |
| 1975 | return EMULATE_FAIL; |
| 1976 | } |
| 1977 | #endif |
| 1978 | |
| 1979 | er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu); |
| 1980 | return er; |
| 1981 | } |
| 1982 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1983 | enum emulation_result kvm_mips_emulate_tlbmod(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1984 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1985 | struct kvm_run *run, |
| 1986 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1987 | { |
| 1988 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1989 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1990 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1991 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1992 | |
| 1993 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1994 | /* save old pc */ |
| 1995 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1996 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1997 | |
| 1998 | if (cause & CAUSEF_BD) |
| 1999 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2000 | else |
| 2001 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2002 | |
| 2003 | kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n", |
| 2004 | arch->pc); |
| 2005 | |
| 2006 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2007 | } else { |
| 2008 | kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n", |
| 2009 | arch->pc); |
| 2010 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2011 | } |
| 2012 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2013 | kvm_change_c0_guest_cause(cop0, (0xff), |
| 2014 | (EXCCODE_MOD << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2015 | |
| 2016 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 2017 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 2018 | /* XXXKYMA: is the context register used by linux??? */ |
| 2019 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 2020 | /* Blow away the shadow host TLBs */ |
| 2021 | kvm_mips_flush_host_tlb(1); |
| 2022 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 2023 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2024 | } |
| 2025 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2026 | enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2027 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2028 | struct kvm_run *run, |
| 2029 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2030 | { |
| 2031 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2032 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2033 | |
| 2034 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2035 | /* save old pc */ |
| 2036 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2037 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2038 | |
| 2039 | if (cause & CAUSEF_BD) |
| 2040 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2041 | else |
| 2042 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2043 | |
| 2044 | } |
| 2045 | |
| 2046 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2047 | |
| 2048 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2049 | (EXCCODE_CPU << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2050 | kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE)); |
| 2051 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 2052 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2053 | } |
| 2054 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2055 | enum emulation_result kvm_mips_emulate_ri_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2056 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2057 | struct kvm_run *run, |
| 2058 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2059 | { |
| 2060 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2061 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2062 | enum emulation_result er = EMULATE_DONE; |
| 2063 | |
| 2064 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2065 | /* save old pc */ |
| 2066 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2067 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2068 | |
| 2069 | if (cause & CAUSEF_BD) |
| 2070 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2071 | else |
| 2072 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2073 | |
| 2074 | kvm_debug("Delivering RI @ pc %#lx\n", arch->pc); |
| 2075 | |
| 2076 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2077 | (EXCCODE_RI << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2078 | |
| 2079 | /* Set PC to the exception entry point */ |
| 2080 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2081 | |
| 2082 | } else { |
| 2083 | kvm_err("Trying to deliver RI when EXL is already set\n"); |
| 2084 | er = EMULATE_FAIL; |
| 2085 | } |
| 2086 | |
| 2087 | return er; |
| 2088 | } |
| 2089 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2090 | enum emulation_result kvm_mips_emulate_bp_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2091 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2092 | struct kvm_run *run, |
| 2093 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2094 | { |
| 2095 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2096 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2097 | enum emulation_result er = EMULATE_DONE; |
| 2098 | |
| 2099 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2100 | /* save old pc */ |
| 2101 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2102 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2103 | |
| 2104 | if (cause & CAUSEF_BD) |
| 2105 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2106 | else |
| 2107 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2108 | |
| 2109 | kvm_debug("Delivering BP @ pc %#lx\n", arch->pc); |
| 2110 | |
| 2111 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2112 | (EXCCODE_BP << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2113 | |
| 2114 | /* Set PC to the exception entry point */ |
| 2115 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2116 | |
| 2117 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2118 | kvm_err("Trying to deliver BP when EXL is already set\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2119 | er = EMULATE_FAIL; |
| 2120 | } |
| 2121 | |
| 2122 | return er; |
| 2123 | } |
| 2124 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2125 | enum emulation_result kvm_mips_emulate_trap_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2126 | u32 *opc, |
James Hogan | 0a56042 | 2015-02-06 16:03:57 +0000 | [diff] [blame] | 2127 | struct kvm_run *run, |
| 2128 | struct kvm_vcpu *vcpu) |
| 2129 | { |
| 2130 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2131 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2132 | enum emulation_result er = EMULATE_DONE; |
| 2133 | |
| 2134 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2135 | /* save old pc */ |
| 2136 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2137 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2138 | |
| 2139 | if (cause & CAUSEF_BD) |
| 2140 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2141 | else |
| 2142 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2143 | |
| 2144 | kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc); |
| 2145 | |
| 2146 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2147 | (EXCCODE_TR << CAUSEB_EXCCODE)); |
James Hogan | 0a56042 | 2015-02-06 16:03:57 +0000 | [diff] [blame] | 2148 | |
| 2149 | /* Set PC to the exception entry point */ |
| 2150 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2151 | |
| 2152 | } else { |
| 2153 | kvm_err("Trying to deliver TRAP when EXL is already set\n"); |
| 2154 | er = EMULATE_FAIL; |
| 2155 | } |
| 2156 | |
| 2157 | return er; |
| 2158 | } |
| 2159 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2160 | enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2161 | u32 *opc, |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2162 | struct kvm_run *run, |
| 2163 | struct kvm_vcpu *vcpu) |
| 2164 | { |
| 2165 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2166 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2167 | enum emulation_result er = EMULATE_DONE; |
| 2168 | |
| 2169 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2170 | /* save old pc */ |
| 2171 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2172 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2173 | |
| 2174 | if (cause & CAUSEF_BD) |
| 2175 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2176 | else |
| 2177 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2178 | |
| 2179 | kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc); |
| 2180 | |
| 2181 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2182 | (EXCCODE_MSAFPE << CAUSEB_EXCCODE)); |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2183 | |
| 2184 | /* Set PC to the exception entry point */ |
| 2185 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2186 | |
| 2187 | } else { |
| 2188 | kvm_err("Trying to deliver MSAFPE when EXL is already set\n"); |
| 2189 | er = EMULATE_FAIL; |
| 2190 | } |
| 2191 | |
| 2192 | return er; |
| 2193 | } |
| 2194 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2195 | enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2196 | u32 *opc, |
James Hogan | 1c0cd66 | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2197 | struct kvm_run *run, |
| 2198 | struct kvm_vcpu *vcpu) |
| 2199 | { |
| 2200 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2201 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2202 | enum emulation_result er = EMULATE_DONE; |
| 2203 | |
| 2204 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2205 | /* save old pc */ |
| 2206 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2207 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2208 | |
| 2209 | if (cause & CAUSEF_BD) |
| 2210 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2211 | else |
| 2212 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2213 | |
| 2214 | kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc); |
| 2215 | |
| 2216 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2217 | (EXCCODE_FPE << CAUSEB_EXCCODE)); |
James Hogan | 1c0cd66 | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2218 | |
| 2219 | /* Set PC to the exception entry point */ |
| 2220 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2221 | |
| 2222 | } else { |
| 2223 | kvm_err("Trying to deliver FPE when EXL is already set\n"); |
| 2224 | er = EMULATE_FAIL; |
| 2225 | } |
| 2226 | |
| 2227 | return er; |
| 2228 | } |
| 2229 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2230 | enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2231 | u32 *opc, |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2232 | struct kvm_run *run, |
| 2233 | struct kvm_vcpu *vcpu) |
| 2234 | { |
| 2235 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2236 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2237 | enum emulation_result er = EMULATE_DONE; |
| 2238 | |
| 2239 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2240 | /* save old pc */ |
| 2241 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2242 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2243 | |
| 2244 | if (cause & CAUSEF_BD) |
| 2245 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2246 | else |
| 2247 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2248 | |
| 2249 | kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc); |
| 2250 | |
| 2251 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2252 | (EXCCODE_MSADIS << CAUSEB_EXCCODE)); |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2253 | |
| 2254 | /* Set PC to the exception entry point */ |
| 2255 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2256 | |
| 2257 | } else { |
| 2258 | kvm_err("Trying to deliver MSADIS when EXL is already set\n"); |
| 2259 | er = EMULATE_FAIL; |
| 2260 | } |
| 2261 | |
| 2262 | return er; |
| 2263 | } |
| 2264 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2265 | enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2266 | struct kvm_run *run, |
| 2267 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2268 | { |
| 2269 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2270 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2271 | enum emulation_result er = EMULATE_DONE; |
| 2272 | unsigned long curr_pc; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2273 | union mips_instruction inst; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2274 | |
| 2275 | /* |
| 2276 | * Update PC and hold onto current PC in case there is |
| 2277 | * an error and we want to rollback the PC |
| 2278 | */ |
| 2279 | curr_pc = vcpu->arch.pc; |
| 2280 | er = update_pc(vcpu, cause); |
| 2281 | if (er == EMULATE_FAIL) |
| 2282 | return er; |
| 2283 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2284 | /* Fetch the instruction. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2285 | if (cause & CAUSEF_BD) |
| 2286 | opc += 1; |
| 2287 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2288 | inst.word = kvm_get_inst(opc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2289 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2290 | if (inst.word == KVM_INVALID_INST) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2291 | kvm_err("%s: Cannot get inst @ %p\n", __func__, opc); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2292 | return EMULATE_FAIL; |
| 2293 | } |
| 2294 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2295 | if (inst.r_format.opcode == spec3_op && |
| 2296 | inst.r_format.func == rdhwr_op) { |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2297 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2298 | int rd = inst.r_format.rd; |
| 2299 | int rt = inst.r_format.rt; |
| 2300 | int sel = inst.r_format.re & 0x7; |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 2301 | |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2302 | /* If usermode, check RDHWR rd is allowed by guest HWREna */ |
| 2303 | if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) { |
| 2304 | kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n", |
| 2305 | rd, opc); |
| 2306 | goto emulate_ri; |
| 2307 | } |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2308 | switch (rd) { |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2309 | case MIPS_HWR_CPUNUM: /* CPU number */ |
James Hogan | cf1fb0f | 2016-06-15 19:29:55 +0100 | [diff] [blame^] | 2310 | arch->gprs[rt] = vcpu->vcpu_id; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2311 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2312 | case MIPS_HWR_SYNCISTEP: /* SYNCI length */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2313 | arch->gprs[rt] = min(current_cpu_data.dcache.linesz, |
| 2314 | current_cpu_data.icache.linesz); |
| 2315 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2316 | case MIPS_HWR_CC: /* Read count register */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 2317 | arch->gprs[rt] = kvm_mips_read_count(vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2318 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2319 | case MIPS_HWR_CCRES: /* Count register resolution */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2320 | switch (current_cpu_data.cputype) { |
| 2321 | case CPU_20KC: |
| 2322 | case CPU_25KF: |
| 2323 | arch->gprs[rt] = 1; |
| 2324 | break; |
| 2325 | default: |
| 2326 | arch->gprs[rt] = 2; |
| 2327 | } |
| 2328 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2329 | case MIPS_HWR_ULR: /* Read UserLocal register */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2330 | arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2331 | break; |
| 2332 | |
| 2333 | default: |
James Hogan | 1550567 | 2014-03-14 13:06:07 +0000 | [diff] [blame] | 2334 | kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc); |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2335 | goto emulate_ri; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2336 | } |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 2337 | |
| 2338 | trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel), |
| 2339 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2340 | } else { |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2341 | kvm_debug("Emulate RI not supported @ %p: %#x\n", |
| 2342 | opc, inst.word); |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2343 | goto emulate_ri; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2344 | } |
| 2345 | |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2346 | return EMULATE_DONE; |
| 2347 | |
| 2348 | emulate_ri: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2349 | /* |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2350 | * Rollback PC (if in branch delay slot then the PC already points to |
| 2351 | * branch target), and pass the RI exception to the guest OS. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2352 | */ |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2353 | vcpu->arch.pc = curr_pc; |
| 2354 | return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2355 | } |
| 2356 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2357 | enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
| 2358 | struct kvm_run *run) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2359 | { |
| 2360 | unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr]; |
| 2361 | enum emulation_result er = EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2362 | |
| 2363 | if (run->mmio.len > sizeof(*gpr)) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2364 | kvm_err("Bad MMIO length: %d", run->mmio.len); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2365 | er = EMULATE_FAIL; |
| 2366 | goto done; |
| 2367 | } |
| 2368 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2369 | er = update_pc(vcpu, vcpu->arch.pending_load_cause); |
| 2370 | if (er == EMULATE_FAIL) |
| 2371 | return er; |
| 2372 | |
| 2373 | switch (run->mmio.len) { |
| 2374 | case 4: |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2375 | *gpr = *(s32 *) run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2376 | break; |
| 2377 | |
| 2378 | case 2: |
| 2379 | if (vcpu->mmio_needed == 2) |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2380 | *gpr = *(s16 *) run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2381 | else |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2382 | *gpr = *(u16 *)run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2383 | |
| 2384 | break; |
| 2385 | case 1: |
| 2386 | if (vcpu->mmio_needed == 2) |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2387 | *gpr = *(s8 *) run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2388 | else |
| 2389 | *gpr = *(u8 *) run->mmio.data; |
| 2390 | break; |
| 2391 | } |
| 2392 | |
| 2393 | if (vcpu->arch.pending_load_cause & CAUSEF_BD) |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2394 | kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n", |
| 2395 | vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr, |
| 2396 | vcpu->mmio_needed); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2397 | |
| 2398 | done: |
| 2399 | return er; |
| 2400 | } |
| 2401 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2402 | static enum emulation_result kvm_mips_emulate_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2403 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2404 | struct kvm_run *run, |
| 2405 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2406 | { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2407 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2408 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2409 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2410 | enum emulation_result er = EMULATE_DONE; |
| 2411 | |
| 2412 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2413 | /* save old pc */ |
| 2414 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2415 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2416 | |
| 2417 | if (cause & CAUSEF_BD) |
| 2418 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2419 | else |
| 2420 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2421 | |
| 2422 | kvm_change_c0_guest_cause(cop0, (0xff), |
| 2423 | (exccode << CAUSEB_EXCCODE)); |
| 2424 | |
| 2425 | /* Set PC to the exception entry point */ |
| 2426 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2427 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 2428 | |
| 2429 | kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n", |
| 2430 | exccode, kvm_read_c0_guest_epc(cop0), |
| 2431 | kvm_read_c0_guest_badvaddr(cop0)); |
| 2432 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2433 | kvm_err("Trying to deliver EXC when EXL is already set\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2434 | er = EMULATE_FAIL; |
| 2435 | } |
| 2436 | |
| 2437 | return er; |
| 2438 | } |
| 2439 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2440 | enum emulation_result kvm_mips_check_privilege(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2441 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2442 | struct kvm_run *run, |
| 2443 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2444 | { |
| 2445 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2446 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2447 | unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; |
| 2448 | |
| 2449 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); |
| 2450 | |
| 2451 | if (usermode) { |
| 2452 | switch (exccode) { |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2453 | case EXCCODE_INT: |
| 2454 | case EXCCODE_SYS: |
| 2455 | case EXCCODE_BP: |
| 2456 | case EXCCODE_RI: |
| 2457 | case EXCCODE_TR: |
| 2458 | case EXCCODE_MSAFPE: |
| 2459 | case EXCCODE_FPE: |
| 2460 | case EXCCODE_MSADIS: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2461 | break; |
| 2462 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2463 | case EXCCODE_CPU: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2464 | if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0) |
| 2465 | er = EMULATE_PRIV_FAIL; |
| 2466 | break; |
| 2467 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2468 | case EXCCODE_MOD: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2469 | break; |
| 2470 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2471 | case EXCCODE_TLBL: |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2472 | /* |
| 2473 | * We we are accessing Guest kernel space, then send an |
| 2474 | * address error exception to the guest |
| 2475 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2476 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2477 | kvm_debug("%s: LD MISS @ %#lx\n", __func__, |
| 2478 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2479 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2480 | cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2481 | er = EMULATE_PRIV_FAIL; |
| 2482 | } |
| 2483 | break; |
| 2484 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2485 | case EXCCODE_TLBS: |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2486 | /* |
| 2487 | * We we are accessing Guest kernel space, then send an |
| 2488 | * address error exception to the guest |
| 2489 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2490 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2491 | kvm_debug("%s: ST MISS @ %#lx\n", __func__, |
| 2492 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2493 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2494 | cause |= (EXCCODE_ADES << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2495 | er = EMULATE_PRIV_FAIL; |
| 2496 | } |
| 2497 | break; |
| 2498 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2499 | case EXCCODE_ADES: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2500 | kvm_debug("%s: address error ST @ %#lx\n", __func__, |
| 2501 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2502 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
| 2503 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2504 | cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2505 | } |
| 2506 | er = EMULATE_PRIV_FAIL; |
| 2507 | break; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2508 | case EXCCODE_ADEL: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2509 | kvm_debug("%s: address error LD @ %#lx\n", __func__, |
| 2510 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2511 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
| 2512 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2513 | cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2514 | } |
| 2515 | er = EMULATE_PRIV_FAIL; |
| 2516 | break; |
| 2517 | default: |
| 2518 | er = EMULATE_PRIV_FAIL; |
| 2519 | break; |
| 2520 | } |
| 2521 | } |
| 2522 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2523 | if (er == EMULATE_PRIV_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2524 | kvm_mips_emulate_exc(cause, opc, run, vcpu); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2525 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2526 | return er; |
| 2527 | } |
| 2528 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2529 | /* |
| 2530 | * User Address (UA) fault, this could happen if |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2531 | * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this |
| 2532 | * case we pass on the fault to the guest kernel and let it handle it. |
| 2533 | * (2) TLB entry is present in the Guest TLB but not in the shadow, in this |
| 2534 | * case we inject the TLB from the Guest TLB into the shadow host TLB |
| 2535 | */ |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2536 | enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2537 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2538 | struct kvm_run *run, |
| 2539 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2540 | { |
| 2541 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2542 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2543 | unsigned long va = vcpu->arch.host_cp0_badvaddr; |
| 2544 | int index; |
| 2545 | |
James Hogan | e4e94c0 | 2016-06-09 14:19:05 +0100 | [diff] [blame] | 2546 | kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n", |
| 2547 | vcpu->arch.host_cp0_badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2548 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2549 | /* |
| 2550 | * KVM would not have got the exception if this entry was valid in the |
| 2551 | * shadow host TLB. Check the Guest TLB, if the entry is not there then |
| 2552 | * send the guest an exception. The guest exc handler should then inject |
| 2553 | * an entry into the guest TLB. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2554 | */ |
| 2555 | index = kvm_mips_guest_tlb_lookup(vcpu, |
James Hogan | caa1faa | 2015-12-16 23:49:26 +0000 | [diff] [blame] | 2556 | (va & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 2557 | (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) & |
| 2558 | KVM_ENTRYHI_ASID)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2559 | if (index < 0) { |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2560 | if (exccode == EXCCODE_TLBL) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2561 | er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu); |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2562 | } else if (exccode == EXCCODE_TLBS) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2563 | er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu); |
| 2564 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2565 | kvm_err("%s: invalid exc code: %d\n", __func__, |
| 2566 | exccode); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2567 | er = EMULATE_FAIL; |
| 2568 | } |
| 2569 | } else { |
| 2570 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; |
| 2571 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2572 | /* |
| 2573 | * Check if the entry is valid, if not then setup a TLB invalid |
| 2574 | * exception to the guest |
| 2575 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2576 | if (!TLB_IS_VALID(*tlb, va)) { |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2577 | if (exccode == EXCCODE_TLBL) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2578 | er = kvm_mips_emulate_tlbinv_ld(cause, opc, run, |
| 2579 | vcpu); |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2580 | } else if (exccode == EXCCODE_TLBS) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2581 | er = kvm_mips_emulate_tlbinv_st(cause, opc, run, |
| 2582 | vcpu); |
| 2583 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2584 | kvm_err("%s: invalid exc code: %d\n", __func__, |
| 2585 | exccode); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2586 | er = EMULATE_FAIL; |
| 2587 | } |
| 2588 | } else { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2589 | kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n", |
James Hogan | 9fbfb06 | 2016-06-09 14:19:17 +0100 | [diff] [blame] | 2590 | tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2591 | /* |
| 2592 | * OK we have a Guest TLB entry, now inject it into the |
| 2593 | * shadow host TLB |
| 2594 | */ |
James Hogan | 26ee17f | 2016-06-09 14:19:13 +0100 | [diff] [blame] | 2595 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2596 | } |
| 2597 | } |
| 2598 | |
| 2599 | return er; |
| 2600 | } |