Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 13 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 14 | #include <linux/sort.h> |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 15 | #include <linux/debugfs.h> |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 16 | #include <linux/ktime.h> |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 17 | #include <uapi/drm/sde_drm.h> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 18 | #include <drm/drm_mode.h> |
| 19 | #include <drm/drm_crtc.h> |
| 20 | #include <drm/drm_crtc_helper.h> |
| 21 | #include <drm/drm_flip_work.h> |
| 22 | |
| 23 | #include "sde_kms.h" |
| 24 | #include "sde_hw_lm.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 25 | #include "sde_hw_ctl.h" |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 26 | #include "sde_crtc.h" |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 27 | #include "sde_color_processing.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 28 | |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 29 | #define CTL(i) (CTL_0 + (i)) |
| 30 | #define LM(i) (LM_0 + (i)) |
| 31 | #define INTF(i) (INTF_0 + (i)) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 32 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 33 | /* uncomment to enable higher level IRQ msg's */ |
| 34 | /*#define DBG_IRQ DBG*/ |
| 35 | #define DBG_IRQ(fmt, ...) |
| 36 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 37 | /* default input fence timeout, in ms */ |
| 38 | #define SDE_CRTC_INPUT_FENCE_TIMEOUT 2000 |
| 39 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 40 | /* |
| 41 | * The default input fence timeout is 2 seconds while max allowed |
| 42 | * range is 10 seconds. Any value above 10 seconds adds glitches beyond |
| 43 | * tolerance limit. |
| 44 | */ |
| 45 | #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000 |
| 46 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 47 | /* layer mixer index on sde_crtc */ |
| 48 | #define LEFT_MIXER 0 |
| 49 | #define RIGHT_MIXER 1 |
| 50 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 51 | static struct sde_kms *get_kms(struct drm_crtc *crtc) |
| 52 | { |
| 53 | struct msm_drm_private *priv = crtc->dev->dev_private; |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 54 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 55 | return to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 56 | } |
| 57 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 58 | static void sde_crtc_destroy(struct drm_crtc *crtc) |
| 59 | { |
| 60 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 61 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 62 | DBG(""); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 63 | |
| 64 | if (!crtc) |
| 65 | return; |
| 66 | |
| 67 | msm_property_destroy(&sde_crtc->property_info); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 68 | sde_cp_crtc_destroy_properties(crtc); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 69 | debugfs_remove_recursive(sde_crtc->debugfs_root); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 70 | sde_fence_deinit(&sde_crtc->output_fence); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 71 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 72 | drm_crtc_cleanup(crtc); |
| 73 | kfree(sde_crtc); |
| 74 | } |
| 75 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 76 | static bool sde_crtc_mode_fixup(struct drm_crtc *crtc, |
| 77 | const struct drm_display_mode *mode, |
| 78 | struct drm_display_mode *adjusted_mode) |
| 79 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 80 | DBG(""); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 81 | |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 82 | if (msm_is_mode_seamless(adjusted_mode)) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 83 | SDE_DEBUG("seamless mode set requested\n"); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 84 | if (!crtc->enabled || crtc->state->active_changed) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 85 | SDE_ERROR("crtc state prevents seamless transition\n"); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 86 | return false; |
| 87 | } |
| 88 | } |
| 89 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 90 | return true; |
| 91 | } |
| 92 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 93 | static void sde_crtc_mode_set_nofb(struct drm_crtc *crtc) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 94 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 95 | DBG(""); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 96 | } |
| 97 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 98 | static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer, |
| 99 | struct sde_plane_state *pstate, struct sde_format *format) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 100 | { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 101 | uint32_t blend_op, fg_alpha, bg_alpha; |
| 102 | uint32_t blend_type; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 103 | struct sde_hw_mixer *lm = mixer->hw_lm; |
| 104 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 105 | /* default to opaque blending */ |
| 106 | fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA); |
| 107 | bg_alpha = 0xFF - fg_alpha; |
| 108 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 109 | blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 110 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 111 | SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha); |
| 112 | |
| 113 | switch (blend_type) { |
| 114 | |
| 115 | case SDE_DRM_BLEND_OP_OPAQUE: |
| 116 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 117 | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 118 | break; |
| 119 | |
| 120 | case SDE_DRM_BLEND_OP_PREMULTIPLIED: |
| 121 | if (format->alpha_enable) { |
| 122 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 123 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 124 | if (fg_alpha != 0xff) { |
| 125 | bg_alpha = fg_alpha; |
| 126 | blend_op |= SDE_BLEND_BG_MOD_ALPHA | |
| 127 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 128 | } else { |
| 129 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 130 | } |
| 131 | } |
| 132 | break; |
| 133 | |
| 134 | case SDE_DRM_BLEND_OP_COVERAGE: |
| 135 | if (format->alpha_enable) { |
| 136 | blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL | |
| 137 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 138 | if (fg_alpha != 0xff) { |
| 139 | bg_alpha = fg_alpha; |
| 140 | blend_op |= SDE_BLEND_FG_MOD_ALPHA | |
| 141 | SDE_BLEND_FG_INV_MOD_ALPHA | |
| 142 | SDE_BLEND_BG_MOD_ALPHA | |
| 143 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 144 | } else { |
| 145 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 146 | } |
| 147 | } |
| 148 | break; |
| 149 | default: |
| 150 | /* do nothing */ |
| 151 | break; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 152 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 153 | |
| 154 | lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha, |
| 155 | bg_alpha, blend_op); |
| 156 | SDE_DEBUG("format 0x%x, alpha_enable %u fg alpha:0x%x bg alpha:0x%x \"\ |
| 157 | blend_op:0x%x\n", format->base.pixel_format, |
| 158 | format->alpha_enable, fg_alpha, bg_alpha, blend_op); |
| 159 | } |
| 160 | |
| 161 | static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc, |
| 162 | struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer) |
| 163 | { |
| 164 | struct drm_plane *plane; |
| 165 | |
| 166 | struct sde_plane_state *pstate = NULL; |
| 167 | struct sde_format *format; |
| 168 | struct sde_hw_ctl *ctl = mixer->hw_ctl; |
| 169 | struct sde_hw_stage_cfg *stage_cfg = &sde_crtc->stage_cfg; |
| 170 | |
| 171 | u32 flush_mask = 0, crtc_split_width; |
| 172 | uint32_t lm_idx = LEFT_MIXER, idx; |
| 173 | bool bg_alpha_enable[CRTC_DUAL_MIXERS] = {false}; |
| 174 | bool lm_right = false; |
| 175 | int left_crtc_zpos_cnt[SDE_STAGE_MAX + 1] = {0}; |
| 176 | int right_crtc_zpos_cnt[SDE_STAGE_MAX + 1] = {0}; |
| 177 | |
| 178 | crtc_split_width = get_crtc_split_width(crtc); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 179 | |
| 180 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 181 | |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 182 | pstate = to_sde_plane_state(plane->state); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 183 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 184 | flush_mask = ctl->ops.get_bitmask_sspp(ctl, |
| 185 | sde_plane_pipe(plane)); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 186 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 187 | /* always stage plane on either left or right lm */ |
| 188 | if (plane->state->crtc_x >= crtc_split_width) { |
| 189 | lm_idx = RIGHT_MIXER; |
| 190 | idx = right_crtc_zpos_cnt[pstate->stage]++; |
| 191 | } else { |
| 192 | lm_idx = LEFT_MIXER; |
| 193 | idx = left_crtc_zpos_cnt[pstate->stage]++; |
| 194 | } |
| 195 | |
| 196 | /* stage plane on right LM if it crosses the boundary */ |
| 197 | lm_right = (lm_idx == LEFT_MIXER) && |
| 198 | (plane->state->crtc_x + plane->state->crtc_w > |
| 199 | crtc_split_width); |
| 200 | |
| 201 | stage_cfg->stage[lm_idx][pstate->stage][idx] = |
| 202 | sde_plane_pipe(plane); |
| 203 | mixer[lm_idx].flush_mask |= flush_mask; |
| 204 | |
| 205 | SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 206 | crtc->base.id, |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 207 | pstate->stage, |
| 208 | plane->base.id, |
| 209 | sde_plane_pipe(plane) - SSPP_VIG0, |
| 210 | plane->state->fb ? |
| 211 | plane->state->fb->base.id : -1); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 212 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 213 | format = to_sde_format(msm_framebuffer_format(pstate->base.fb)); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 214 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 215 | /* blend config update */ |
| 216 | if (pstate->stage != SDE_STAGE_BASE) { |
| 217 | _sde_crtc_setup_blend_cfg(mixer + lm_idx, pstate, |
| 218 | format); |
| 219 | |
| 220 | if (bg_alpha_enable[lm_idx] && !format->alpha_enable) |
| 221 | mixer[lm_idx].mixer_op_mode = 0; |
| 222 | else |
| 223 | mixer[lm_idx].mixer_op_mode |= |
| 224 | 1 << pstate->stage; |
| 225 | } else if (format->alpha_enable) { |
| 226 | bg_alpha_enable[lm_idx] = true; |
| 227 | } |
| 228 | |
| 229 | if (lm_right) { |
| 230 | idx = right_crtc_zpos_cnt[pstate->stage]++; |
| 231 | stage_cfg->stage[RIGHT_MIXER][pstate->stage][idx] = |
| 232 | sde_plane_pipe(plane); |
| 233 | mixer[RIGHT_MIXER].flush_mask |= flush_mask; |
| 234 | |
| 235 | /* blend config update */ |
| 236 | if (pstate->stage != SDE_STAGE_BASE) { |
| 237 | _sde_crtc_setup_blend_cfg(mixer + RIGHT_MIXER, |
| 238 | pstate, format); |
| 239 | |
| 240 | if (bg_alpha_enable[RIGHT_MIXER] && |
| 241 | !format->alpha_enable) |
| 242 | mixer[RIGHT_MIXER].mixer_op_mode = 0; |
| 243 | else |
| 244 | mixer[RIGHT_MIXER].mixer_op_mode |= |
| 245 | 1 << pstate->stage; |
| 246 | } else if (format->alpha_enable) { |
| 247 | bg_alpha_enable[RIGHT_MIXER] = true; |
| 248 | } |
| 249 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 250 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 251 | } |
| 252 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 253 | /** |
| 254 | * _sde_crtc_blend_setup - configure crtc mixers |
| 255 | * @crtc: Pointer to drm crtc structure |
| 256 | */ |
| 257 | static void _sde_crtc_blend_setup(struct drm_crtc *crtc) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 258 | { |
| 259 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 260 | struct sde_crtc_mixer *mixer = sde_crtc->mixers; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 261 | struct sde_hw_ctl *ctl; |
| 262 | struct sde_hw_mixer *lm; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 263 | |
| 264 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 265 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 266 | SDE_DEBUG("%s\n", sde_crtc->name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 267 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 268 | if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) { |
| 269 | SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers); |
| 270 | return; |
| 271 | } |
| 272 | |
| 273 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 274 | if (!mixer[i].hw_lm || !mixer[i].hw_ctl) { |
| 275 | SDE_ERROR("invalid lm or ctl assigned to mixer\n"); |
| 276 | return; |
| 277 | } |
| 278 | mixer[i].mixer_op_mode = 0; |
| 279 | mixer[i].flush_mask = 0; |
| 280 | } |
| 281 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 282 | /* initialize stage cfg */ |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 283 | memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 284 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 285 | _sde_crtc_blend_setup_mixer(crtc, sde_crtc, mixer); |
| 286 | |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 287 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 288 | ctl = mixer[i].hw_ctl; |
| 289 | lm = mixer[i].hw_lm; |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 290 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 291 | lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 292 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 293 | mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 294 | mixer[i].hw_lm->idx); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 295 | |
| 296 | /* stage config flush mask */ |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 297 | ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); |
| 298 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 299 | SDE_DEBUG("lm %d ctl %d add mask 0x%x to pending flush\n", |
Alan Kwong | 8576728 | 2016-10-03 18:03:37 -0400 | [diff] [blame] | 300 | mixer[i].hw_lm->idx, ctl->idx, mixer[i].flush_mask); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 301 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 302 | ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 303 | &sde_crtc->stage_cfg, i); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 304 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 305 | } |
| 306 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 307 | void sde_crtc_prepare_fence(struct drm_crtc *crtc) |
| 308 | { |
| 309 | struct sde_crtc *sde_crtc; |
| 310 | |
| 311 | if (!crtc) { |
| 312 | SDE_ERROR("invalid crtc\n"); |
| 313 | return; |
| 314 | } |
| 315 | |
| 316 | sde_crtc = to_sde_crtc(crtc); |
| 317 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 318 | MSM_EVT(crtc->dev, crtc->base.id, 0); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 319 | |
| 320 | sde_fence_prepare(&sde_crtc->output_fence); |
| 321 | } |
| 322 | |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 323 | /* if file!=NULL, this is preclose potential cancel-flip path */ |
| 324 | static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) |
| 325 | { |
| 326 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 327 | struct drm_device *dev = crtc->dev; |
| 328 | struct drm_pending_vblank_event *event; |
| 329 | unsigned long flags; |
| 330 | |
| 331 | spin_lock_irqsave(&dev->event_lock, flags); |
| 332 | event = sde_crtc->event; |
| 333 | if (event) { |
| 334 | /* if regular vblank case (!file) or if cancel-flip from |
| 335 | * preclose on file that requested flip, then send the |
| 336 | * event: |
| 337 | */ |
| 338 | if (!file || (event->base.file_priv == file)) { |
| 339 | sde_crtc->event = NULL; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 340 | SDE_DEBUG("%s: send event: %pK\n", |
| 341 | sde_crtc->name, event); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 342 | drm_send_vblank_event(dev, sde_crtc->drm_crtc_id, |
| 343 | event); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 344 | } |
| 345 | } |
| 346 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 347 | } |
| 348 | |
| 349 | static void sde_crtc_vblank_cb(void *data) |
| 350 | { |
| 351 | struct drm_crtc *crtc = (struct drm_crtc *)data; |
| 352 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 353 | struct sde_kms *sde_kms = get_kms(crtc); |
| 354 | struct drm_device *dev = sde_kms->dev; |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 355 | |
Alan Kwong | cf42ee0 | 2016-10-04 09:19:17 -0400 | [diff] [blame^] | 356 | drm_handle_vblank(dev, sde_crtc->drm_crtc_id); |
| 357 | DBG_IRQ(""); |
| 358 | MSM_EVT(crtc->dev, crtc->base.id, 0); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 359 | } |
| 360 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 361 | void sde_crtc_complete_commit(struct drm_crtc *crtc) |
| 362 | { |
| 363 | if (!crtc) { |
| 364 | SDE_ERROR("invalid crtc\n"); |
| 365 | return; |
| 366 | } |
| 367 | |
| 368 | /* signal out fence at end of commit */ |
| 369 | sde_fence_signal(&to_sde_crtc(crtc)->output_fence, 0); |
| 370 | } |
| 371 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 372 | /** |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 373 | * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout |
| 374 | * @cstate: Pointer to sde crtc state |
| 375 | */ |
| 376 | static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate) |
| 377 | { |
| 378 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 379 | SDE_ERROR("invalid cstate\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 380 | return; |
| 381 | } |
| 382 | cstate->input_fence_timeout_ns = |
| 383 | sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 384 | cstate->input_fence_timeout_ns *= NSEC_PER_MSEC; |
| 385 | } |
| 386 | |
| 387 | /** |
| 388 | * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences |
| 389 | * @crtc: Pointer to CRTC object |
| 390 | */ |
| 391 | static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc) |
| 392 | { |
| 393 | struct drm_plane *plane = NULL; |
| 394 | uint32_t wait_ms = 1; |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 395 | ktime_t kt_end, kt_wait; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 396 | |
| 397 | DBG(""); |
| 398 | |
| 399 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 400 | SDE_ERROR("invalid crtc/state %pK\n", crtc); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 401 | return; |
| 402 | } |
| 403 | |
| 404 | /* use monotonic timer to limit total fence wait time */ |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 405 | kt_end = ktime_add_ns(ktime_get(), |
| 406 | to_sde_crtc_state(crtc->state)->input_fence_timeout_ns); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 407 | |
| 408 | /* |
| 409 | * Wait for fences sequentially, as all of them need to be signalled |
| 410 | * before we can proceed. |
| 411 | * |
| 412 | * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call |
| 413 | * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so |
| 414 | * that each plane can check its fence status and react appropriately |
| 415 | * if its fence has timed out. |
| 416 | */ |
| 417 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
| 418 | if (wait_ms) { |
| 419 | /* determine updated wait time */ |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 420 | kt_wait = ktime_sub(kt_end, ktime_get()); |
| 421 | if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0) |
| 422 | wait_ms = ktime_to_ms(kt_wait); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 423 | else |
| 424 | wait_ms = 0; |
| 425 | } |
| 426 | sde_plane_wait_input_fence(plane, wait_ms); |
| 427 | } |
| 428 | } |
| 429 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 430 | static void _sde_crtc_setup_mixer_for_encoder( |
| 431 | struct drm_crtc *crtc, |
| 432 | struct drm_encoder *enc) |
| 433 | { |
| 434 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 435 | struct sde_kms *sde_kms = get_kms(crtc); |
| 436 | struct sde_rm *rm = &sde_kms->rm; |
| 437 | struct sde_crtc_mixer *mixer; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 438 | struct sde_hw_ctl *last_valid_ctl = NULL; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 439 | int i; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 440 | struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 441 | |
| 442 | sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM); |
| 443 | sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 444 | sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 445 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 446 | /* Set up all the mixers and ctls reserved by this encoder */ |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 447 | for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) { |
| 448 | mixer = &sde_crtc->mixers[i]; |
| 449 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 450 | if (!sde_rm_get_hw(rm, &lm_iter)) |
| 451 | break; |
| 452 | mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw; |
| 453 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 454 | /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ |
| 455 | if (!sde_rm_get_hw(rm, &ctl_iter)) { |
| 456 | SDE_DEBUG("no ctl assigned to lm %d, using previous\n", |
| 457 | mixer->hw_lm->idx); |
| 458 | mixer->hw_ctl = last_valid_ctl; |
| 459 | } else { |
| 460 | mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw; |
| 461 | last_valid_ctl = mixer->hw_ctl; |
| 462 | } |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 463 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 464 | /* Shouldn't happen, mixers are always >= ctls */ |
| 465 | if (!mixer->hw_ctl) { |
| 466 | SDE_ERROR("no valid ctls found for lm %d\n", |
| 467 | mixer->hw_lm->idx); |
| 468 | return; |
| 469 | } |
| 470 | |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 471 | /* Dspp may be null */ |
| 472 | (void) sde_rm_get_hw(rm, &dspp_iter); |
| 473 | mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw; |
| 474 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 475 | mixer->encoder = enc; |
| 476 | |
| 477 | sde_crtc->num_mixers++; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 478 | SDE_DEBUG("setup mixer %d: lm %d\n", |
| 479 | i, mixer->hw_lm->idx - LM_0); |
| 480 | SDE_DEBUG("setup mixer %d: ctl %d\n", |
| 481 | i, mixer->hw_ctl->idx - CTL_0); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 482 | } |
| 483 | } |
| 484 | |
| 485 | static void _sde_crtc_setup_mixers(struct drm_crtc *crtc) |
| 486 | { |
| 487 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 488 | struct drm_encoder *enc; |
| 489 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 490 | sde_crtc->num_mixers = 0; |
| 491 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 492 | |
| 493 | /* Check for mixers on all encoders attached to this crtc */ |
| 494 | list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { |
| 495 | if (enc->crtc != crtc) |
| 496 | continue; |
| 497 | |
| 498 | _sde_crtc_setup_mixer_for_encoder(crtc, enc); |
| 499 | } |
| 500 | } |
| 501 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 502 | static void sde_crtc_atomic_begin(struct drm_crtc *crtc, |
| 503 | struct drm_crtc_state *old_crtc_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 504 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 505 | struct sde_crtc *sde_crtc; |
| 506 | struct drm_device *dev; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 507 | unsigned long flags; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 508 | u32 i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 509 | |
| 510 | DBG(""); |
| 511 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 512 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 513 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 514 | return; |
| 515 | } |
| 516 | |
| 517 | sde_crtc = to_sde_crtc(crtc); |
| 518 | dev = crtc->dev; |
| 519 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 520 | if (!sde_crtc->num_mixers) |
| 521 | _sde_crtc_setup_mixers(crtc); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 522 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 523 | if (sde_crtc->event) { |
| 524 | WARN_ON(sde_crtc->event); |
| 525 | } else { |
| 526 | spin_lock_irqsave(&dev->event_lock, flags); |
| 527 | sde_crtc->event = crtc->state->event; |
| 528 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 529 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 530 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 531 | /* Reset flush mask from previous commit */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 532 | for (i = 0; i < ARRAY_SIZE(sde_crtc->mixers); i++) { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 533 | struct sde_hw_ctl *ctl = sde_crtc->mixers[i].hw_ctl; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 534 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 535 | if (ctl) |
| 536 | ctl->ops.clear_pending_flush(ctl); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 537 | } |
| 538 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 539 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 540 | * If no mixers have been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 541 | * it means we are trying to flush a CRTC whose state is disabled: |
| 542 | * nothing else needs to be done. |
| 543 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 544 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 545 | return; |
| 546 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 547 | _sde_crtc_blend_setup(crtc); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 548 | sde_cp_crtc_apply_properties(crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 549 | |
| 550 | /* |
| 551 | * PP_DONE irq is only used by command mode for now. |
| 552 | * It is better to request pending before FLUSH and START trigger |
| 553 | * to make sure no pp_done irq missed. |
| 554 | * This is safe because no pp_done will happen before SW trigger |
| 555 | * in command mode. |
| 556 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 557 | } |
| 558 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 559 | static void sde_crtc_atomic_flush(struct drm_crtc *crtc, |
| 560 | struct drm_crtc_state *old_crtc_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 561 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 562 | struct sde_crtc *sde_crtc; |
| 563 | struct drm_device *dev; |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 564 | struct drm_plane *plane; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 565 | unsigned long flags; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 566 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 567 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 568 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 569 | return; |
| 570 | } |
| 571 | |
| 572 | DBG(""); |
| 573 | |
| 574 | sde_crtc = to_sde_crtc(crtc); |
| 575 | |
| 576 | dev = crtc->dev; |
| 577 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 578 | if (sde_crtc->event) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 579 | SDE_DEBUG("already received sde_crtc->event\n"); |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 580 | } else { |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 581 | spin_lock_irqsave(&dev->event_lock, flags); |
| 582 | sde_crtc->event = crtc->state->event; |
| 583 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 584 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 585 | |
| 586 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 587 | * If no mixers has been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 588 | * it means we are trying to flush a CRTC whose state is disabled: |
| 589 | * nothing else needs to be done. |
| 590 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 591 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 592 | return; |
| 593 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 594 | /* wait for acquire fences before anything else is done */ |
| 595 | _sde_crtc_wait_for_fences(crtc); |
| 596 | |
| 597 | /* |
| 598 | * Final plane updates: Give each plane a chance to complete all |
| 599 | * required writes/flushing before crtc's "flush |
| 600 | * everything" call below. |
| 601 | */ |
| 602 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 603 | sde_plane_flush(plane); |
| 604 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 605 | /* Kickoff will be scheduled by outer layer */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 606 | } |
| 607 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 608 | /** |
| 609 | * sde_crtc_destroy_state - state destroy hook |
| 610 | * @crtc: drm CRTC |
| 611 | * @state: CRTC state object to release |
| 612 | */ |
| 613 | static void sde_crtc_destroy_state(struct drm_crtc *crtc, |
| 614 | struct drm_crtc_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 615 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 616 | struct sde_crtc *sde_crtc; |
| 617 | struct sde_crtc_state *cstate; |
| 618 | |
| 619 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 620 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 621 | return; |
| 622 | } |
| 623 | |
| 624 | sde_crtc = to_sde_crtc(crtc); |
| 625 | cstate = to_sde_crtc_state(state); |
| 626 | |
| 627 | DBG(""); |
| 628 | |
| 629 | __drm_atomic_helper_crtc_destroy_state(crtc, state); |
| 630 | |
| 631 | /* destroy value helper */ |
| 632 | msm_property_destroy_state(&sde_crtc->property_info, cstate, |
| 633 | cstate->property_values, cstate->property_blobs); |
| 634 | } |
| 635 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 636 | void sde_crtc_commit_kickoff(struct drm_crtc *crtc) |
| 637 | { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 638 | struct drm_encoder *encoder; |
| 639 | struct drm_device *dev; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 640 | |
| 641 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 642 | SDE_ERROR("invalid argument\n"); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 643 | return; |
| 644 | } |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 645 | dev = crtc->dev; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 646 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 647 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 648 | if (encoder->crtc != crtc) |
| 649 | continue; |
| 650 | |
| 651 | /* |
| 652 | * Encoder will flush/start now, unless it has a tx pending. |
| 653 | * If so, it may delay and flush at an irq event (e.g. ppdone) |
| 654 | */ |
Clarence Ip | 110d15c | 2016-08-16 14:44:41 -0400 | [diff] [blame] | 655 | sde_encoder_schedule_kickoff(encoder); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 656 | } |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 657 | } |
| 658 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 659 | /** |
| 660 | * sde_crtc_duplicate_state - state duplicate hook |
| 661 | * @crtc: Pointer to drm crtc structure |
| 662 | * @Returns: Pointer to new drm_crtc_state structure |
| 663 | */ |
| 664 | static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc) |
| 665 | { |
| 666 | struct sde_crtc *sde_crtc; |
| 667 | struct sde_crtc_state *cstate, *old_cstate; |
| 668 | |
| 669 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 670 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 671 | return NULL; |
| 672 | } |
| 673 | |
| 674 | sde_crtc = to_sde_crtc(crtc); |
| 675 | old_cstate = to_sde_crtc_state(crtc->state); |
| 676 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 677 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 678 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 679 | return NULL; |
| 680 | } |
| 681 | |
| 682 | /* duplicate value helper */ |
| 683 | msm_property_duplicate_state(&sde_crtc->property_info, |
| 684 | old_cstate, cstate, |
| 685 | cstate->property_values, cstate->property_blobs); |
| 686 | |
| 687 | /* duplicate base helper */ |
| 688 | __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); |
| 689 | |
| 690 | return &cstate->base; |
| 691 | } |
| 692 | |
| 693 | /** |
| 694 | * sde_crtc_reset - reset hook for CRTCs |
| 695 | * Resets the atomic state for @crtc by freeing the state pointer (which might |
| 696 | * be NULL, e.g. at driver load time) and allocating a new empty state object. |
| 697 | * @crtc: Pointer to drm crtc structure |
| 698 | */ |
| 699 | static void sde_crtc_reset(struct drm_crtc *crtc) |
| 700 | { |
| 701 | struct sde_crtc *sde_crtc; |
| 702 | struct sde_crtc_state *cstate; |
| 703 | |
| 704 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 705 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 706 | return; |
| 707 | } |
| 708 | |
| 709 | /* remove previous state, if present */ |
| 710 | if (crtc->state) { |
| 711 | sde_crtc_destroy_state(crtc, crtc->state); |
| 712 | crtc->state = 0; |
| 713 | } |
| 714 | |
| 715 | sde_crtc = to_sde_crtc(crtc); |
| 716 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 717 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 718 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 719 | return; |
| 720 | } |
| 721 | |
| 722 | /* reset value helper */ |
| 723 | msm_property_reset_state(&sde_crtc->property_info, cstate, |
| 724 | cstate->property_values, cstate->property_blobs); |
| 725 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 726 | _sde_crtc_set_input_fence_timeout(cstate); |
| 727 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 728 | cstate->base.crtc = crtc; |
| 729 | crtc->state = &cstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 730 | } |
| 731 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 732 | static void sde_crtc_disable(struct drm_crtc *crtc) |
| 733 | { |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 734 | struct sde_crtc *sde_crtc; |
| 735 | |
| 736 | if (!crtc) { |
| 737 | DRM_ERROR("invalid crtc\n"); |
| 738 | return; |
| 739 | } |
| 740 | sde_crtc = to_sde_crtc(crtc); |
| 741 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 742 | DBG(""); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 743 | |
| 744 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 745 | sde_crtc->num_mixers = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 746 | } |
| 747 | |
| 748 | static void sde_crtc_enable(struct drm_crtc *crtc) |
| 749 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 750 | struct sde_crtc *sde_crtc; |
| 751 | struct sde_crtc_mixer *mixer; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 752 | struct sde_hw_mixer *lm; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 753 | struct drm_display_mode *mode; |
| 754 | struct sde_hw_mixer_cfg cfg; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 755 | int i; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 756 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 757 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 758 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 759 | return; |
| 760 | } |
| 761 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 762 | DBG(""); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 763 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 764 | sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 765 | mixer = sde_crtc->mixers; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 766 | |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 767 | if (WARN_ON(!crtc->state)) |
| 768 | return; |
| 769 | |
| 770 | mode = &crtc->state->adjusted_mode; |
| 771 | |
| 772 | drm_mode_debug_printmodeline(mode); |
| 773 | |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 774 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 775 | lm = mixer[i].hw_lm; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 776 | cfg.out_width = sde_crtc_mixer_width(sde_crtc, mode); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 777 | cfg.out_height = mode->vdisplay; |
| 778 | cfg.right_mixer = (i == 0) ? false : true; |
| 779 | cfg.flags = 0; |
| 780 | lm->ops.setup_mixer_out(lm, &cfg); |
| 781 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 782 | } |
| 783 | |
| 784 | struct plane_state { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 785 | struct sde_plane_state *sde_pstate; |
| 786 | struct drm_plane_state *drm_pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 787 | }; |
| 788 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 789 | static int sde_crtc_atomic_check(struct drm_crtc *crtc, |
| 790 | struct drm_crtc_state *state) |
| 791 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 792 | struct sde_crtc *sde_crtc; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 793 | struct plane_state pstates[SDE_STAGE_MAX * 2]; |
| 794 | |
| 795 | struct drm_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 796 | struct drm_plane *plane; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 797 | struct drm_display_mode *mode; |
| 798 | |
| 799 | int cnt = 0, rc = 0, mixer_width, i, z_pos; |
| 800 | int left_crtc_zpos_cnt[SDE_STAGE_MAX] = {0}; |
| 801 | int right_crtc_zpos_cnt[SDE_STAGE_MAX] = {0}; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 802 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 803 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 804 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 805 | return -EINVAL; |
| 806 | } |
| 807 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 808 | if (!state->enable || !state->active) { |
| 809 | SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", |
| 810 | crtc->base.id, state->enable, state->active); |
| 811 | return 0; |
| 812 | } |
| 813 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 814 | sde_crtc = to_sde_crtc(crtc); |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 815 | mode = &state->adjusted_mode; |
| 816 | SDE_DEBUG("%s: check", sde_crtc->name); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 817 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 818 | mixer_width = sde_crtc_mixer_width(sde_crtc, mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 819 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 820 | /* get plane state for all drm planes associated with crtc state */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 821 | drm_atomic_crtc_state_for_each_plane(plane, state) { |
Alan Kwong | 8576728 | 2016-10-03 18:03:37 -0400 | [diff] [blame] | 822 | pstate = drm_atomic_get_plane_state(state->state, plane); |
| 823 | if (IS_ERR(pstate)) { |
| 824 | SDE_ERROR("%s: failed to get plane:%d state\n", |
| 825 | sde_crtc->name, |
| 826 | plane->base.id); |
| 827 | rc = -EINVAL; |
| 828 | goto end; |
| 829 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 830 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 831 | pstates[cnt].sde_pstate = to_sde_plane_state(pstate); |
| 832 | pstates[cnt].drm_pstate = pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 833 | cnt++; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 834 | |
| 835 | if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h, |
| 836 | mode->vdisplay) || |
| 837 | CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w, |
| 838 | mode->hdisplay)) { |
| 839 | SDE_ERROR("invalid vertical/horizontal destination\n"); |
| 840 | SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n", |
| 841 | pstate->crtc_y, pstate->crtc_h, mode->vdisplay, |
| 842 | pstate->crtc_x, pstate->crtc_w, mode->hdisplay); |
| 843 | rc = -E2BIG; |
| 844 | goto end; |
| 845 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 846 | } |
| 847 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 848 | for (i = 0; i < cnt; i++) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 849 | z_pos = sde_plane_get_property(pstates[i].sde_pstate, |
| 850 | PLANE_PROP_ZPOS); |
| 851 | |
| 852 | if (pstates[i].drm_pstate->crtc_x < mixer_width) { |
| 853 | if (left_crtc_zpos_cnt[z_pos] == 2) { |
| 854 | SDE_ERROR("> 2 plane @ stage%d on left\n", |
| 855 | z_pos); |
| 856 | rc = -EINVAL; |
| 857 | goto end; |
| 858 | } |
| 859 | left_crtc_zpos_cnt[z_pos]++; |
| 860 | } else { |
| 861 | if (right_crtc_zpos_cnt[z_pos] == 2) { |
| 862 | SDE_ERROR("> 2 plane @ stage%d on right\n", |
| 863 | z_pos); |
| 864 | rc = -EINVAL; |
| 865 | goto end; |
| 866 | } |
| 867 | right_crtc_zpos_cnt[z_pos]++; |
| 868 | } |
| 869 | pstates[i].sde_pstate->stage = z_pos; |
| 870 | SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 871 | } |
| 872 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 873 | end: |
| 874 | return rc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 875 | } |
| 876 | |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 877 | int sde_crtc_vblank(struct drm_crtc *crtc, bool en) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 878 | { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 879 | struct drm_encoder *encoder; |
| 880 | struct drm_device *dev = crtc->dev; |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 881 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 882 | SDE_DEBUG("%d", en); |
Lloyd Atkinson | e5c2c0b | 2016-07-05 12:23:29 -0400 | [diff] [blame] | 883 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 884 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 885 | if (encoder->crtc != crtc) |
| 886 | continue; |
Alan Kwong | cf42ee0 | 2016-10-04 09:19:17 -0400 | [diff] [blame^] | 887 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 888 | MSM_EVT(crtc->dev, crtc->base.id, en); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 889 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 890 | if (en) |
| 891 | sde_encoder_register_vblank_callback(encoder, |
| 892 | sde_crtc_vblank_cb, (void *)crtc); |
| 893 | else |
| 894 | sde_encoder_register_vblank_callback(encoder, NULL, |
| 895 | NULL); |
| 896 | } |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 897 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 898 | return 0; |
| 899 | } |
| 900 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 901 | void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file) |
| 902 | { |
| 903 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 904 | |
| 905 | SDE_DEBUG("%s: cancel: %p", sde_crtc->name, file); |
| 906 | complete_flip(crtc, file); |
| 907 | } |
| 908 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 909 | /** |
| 910 | * sde_crtc_install_properties - install all drm properties for crtc |
| 911 | * @crtc: Pointer to drm crtc structure |
| 912 | */ |
| 913 | static void sde_crtc_install_properties(struct drm_crtc *crtc) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 914 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 915 | struct sde_crtc *sde_crtc; |
| 916 | struct drm_device *dev; |
| 917 | |
| 918 | DBG(""); |
| 919 | |
| 920 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 921 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 922 | return; |
| 923 | } |
| 924 | |
| 925 | sde_crtc = to_sde_crtc(crtc); |
| 926 | dev = crtc->dev; |
| 927 | |
| 928 | /* range properties */ |
| 929 | msm_property_install_range(&sde_crtc->property_info, |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 930 | "input_fence_timeout", 0x0, 0, SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, |
| 931 | SDE_CRTC_INPUT_FENCE_TIMEOUT, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 932 | |
| 933 | msm_property_install_range(&sde_crtc->property_info, "output_fence", |
| 934 | 0x0, 0, INR_OPEN_MAX, 0x0, CRTC_PROP_OUTPUT_FENCE); |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 935 | |
| 936 | msm_property_install_range(&sde_crtc->property_info, |
| 937 | "output_fence_offset", 0x0, 0, 1, 0, |
| 938 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 939 | } |
| 940 | |
| 941 | /** |
| 942 | * sde_crtc_atomic_set_property - atomically set a crtc drm property |
| 943 | * @crtc: Pointer to drm crtc structure |
| 944 | * @state: Pointer to drm crtc state structure |
| 945 | * @property: Pointer to targeted drm property |
| 946 | * @val: Updated property value |
| 947 | * @Returns: Zero on success |
| 948 | */ |
| 949 | static int sde_crtc_atomic_set_property(struct drm_crtc *crtc, |
| 950 | struct drm_crtc_state *state, |
| 951 | struct drm_property *property, |
| 952 | uint64_t val) |
| 953 | { |
| 954 | struct sde_crtc *sde_crtc; |
| 955 | struct sde_crtc_state *cstate; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 956 | int idx, ret = -EINVAL; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 957 | |
| 958 | if (!crtc || !state || !property) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 959 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 960 | } else { |
| 961 | sde_crtc = to_sde_crtc(crtc); |
| 962 | cstate = to_sde_crtc_state(state); |
| 963 | ret = msm_property_atomic_set(&sde_crtc->property_info, |
| 964 | cstate->property_values, cstate->property_blobs, |
| 965 | property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 966 | if (!ret) { |
| 967 | idx = msm_property_index(&sde_crtc->property_info, |
| 968 | property); |
| 969 | if (idx == CRTC_PROP_INPUT_FENCE_TIMEOUT) |
| 970 | _sde_crtc_set_input_fence_timeout(cstate); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 971 | } else { |
| 972 | ret = sde_cp_crtc_set_property(crtc, |
| 973 | property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 974 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 975 | if (ret) |
| 976 | DRM_ERROR("failed to set the property\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 977 | } |
| 978 | |
| 979 | return ret; |
| 980 | } |
| 981 | |
| 982 | /** |
| 983 | * sde_crtc_set_property - set a crtc drm property |
| 984 | * @crtc: Pointer to drm crtc structure |
| 985 | * @property: Pointer to targeted drm property |
| 986 | * @val: Updated property value |
| 987 | * @Returns: Zero on success |
| 988 | */ |
| 989 | static int sde_crtc_set_property(struct drm_crtc *crtc, |
| 990 | struct drm_property *property, uint64_t val) |
| 991 | { |
| 992 | DBG(""); |
| 993 | |
| 994 | return sde_crtc_atomic_set_property(crtc, crtc->state, property, val); |
| 995 | } |
| 996 | |
| 997 | /** |
| 998 | * sde_crtc_atomic_get_property - retrieve a crtc drm property |
| 999 | * @crtc: Pointer to drm crtc structure |
| 1000 | * @state: Pointer to drm crtc state structure |
| 1001 | * @property: Pointer to targeted drm property |
| 1002 | * @val: Pointer to variable for receiving property value |
| 1003 | * @Returns: Zero on success |
| 1004 | */ |
| 1005 | static int sde_crtc_atomic_get_property(struct drm_crtc *crtc, |
| 1006 | const struct drm_crtc_state *state, |
| 1007 | struct drm_property *property, |
| 1008 | uint64_t *val) |
| 1009 | { |
| 1010 | struct sde_crtc *sde_crtc; |
| 1011 | struct sde_crtc_state *cstate; |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1012 | int i, ret = -EINVAL; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1013 | |
| 1014 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1015 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1016 | } else { |
| 1017 | sde_crtc = to_sde_crtc(crtc); |
| 1018 | cstate = to_sde_crtc_state(state); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1019 | i = msm_property_index(&sde_crtc->property_info, property); |
| 1020 | if (i == CRTC_PROP_OUTPUT_FENCE) { |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 1021 | int offset = sde_crtc_get_property(cstate, |
| 1022 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
| 1023 | |
| 1024 | ret = sde_fence_create( |
| 1025 | &sde_crtc->output_fence, val, offset); |
| 1026 | if (ret) |
| 1027 | SDE_ERROR("fence create failed\n"); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1028 | } else { |
| 1029 | ret = msm_property_atomic_get(&sde_crtc->property_info, |
| 1030 | cstate->property_values, |
| 1031 | cstate->property_blobs, property, val); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1032 | if (ret) |
| 1033 | ret = sde_cp_crtc_get_property(crtc, |
| 1034 | property, val); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1035 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1036 | if (ret) |
| 1037 | DRM_ERROR("get property failed\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1038 | } |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1039 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1040 | } |
| 1041 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1042 | static int _sde_debugfs_mixer_read(struct seq_file *s, void *data) |
| 1043 | { |
| 1044 | struct sde_crtc *sde_crtc; |
| 1045 | struct sde_crtc_mixer *m; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1046 | int i, j, k; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1047 | |
| 1048 | if (!s || !s->private) |
| 1049 | return -EINVAL; |
| 1050 | |
| 1051 | sde_crtc = s->private; |
| 1052 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 1053 | m = &sde_crtc->mixers[i]; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1054 | if (!m->hw_lm) { |
| 1055 | seq_printf(s, "Mixer[%d] has no LM\n", i); |
| 1056 | } else if (!m->hw_ctl) { |
| 1057 | seq_printf(s, "Mixer[%d] has no CTL\n", i); |
| 1058 | } else { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 1059 | seq_printf(s, "LM_%d/CTL_%d\n", |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1060 | m->hw_lm->idx - LM_0, |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 1061 | m->hw_ctl->idx - CTL_0); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1062 | } |
| 1063 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1064 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1065 | for (k = 0; k < sde_crtc->num_mixers; ++k) { |
| 1066 | seq_printf(s, "Mixer[%d] stages\n", k); |
| 1067 | for (i = 0; i < SDE_STAGE_MAX; ++i) { |
| 1068 | if (i == SDE_STAGE_BASE) |
| 1069 | seq_puts(s, "Base Stage:"); |
| 1070 | else |
| 1071 | seq_printf(s, "Stage %d:", i - SDE_STAGE_0); |
| 1072 | |
| 1073 | for (j = 0; j < PIPES_PER_STAGE; ++j) |
| 1074 | seq_printf(s, " % 2d", |
| 1075 | sde_crtc->stage_cfg.stage[k][i][j]); |
| 1076 | seq_puts(s, "\n"); |
| 1077 | } |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1078 | } |
| 1079 | return 0; |
| 1080 | } |
| 1081 | |
| 1082 | static int _sde_debugfs_mixer_open(struct inode *inode, struct file *file) |
| 1083 | { |
| 1084 | return single_open(file, _sde_debugfs_mixer_read, inode->i_private); |
| 1085 | } |
| 1086 | |
Gopikrishnaiah Anandan | 7f6ef94 | 2016-06-20 15:50:00 -0700 | [diff] [blame] | 1087 | static void sde_crtc_suspend(struct drm_crtc *crtc) |
| 1088 | { |
| 1089 | sde_cp_crtc_suspend(crtc); |
| 1090 | } |
| 1091 | |
| 1092 | static void sde_crtc_resume(struct drm_crtc *crtc) |
| 1093 | { |
| 1094 | sde_cp_crtc_resume(crtc); |
| 1095 | } |
| 1096 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1097 | static const struct drm_crtc_funcs sde_crtc_funcs = { |
| 1098 | .set_config = drm_atomic_helper_set_config, |
| 1099 | .destroy = sde_crtc_destroy, |
| 1100 | .page_flip = drm_atomic_helper_page_flip, |
| 1101 | .set_property = sde_crtc_set_property, |
| 1102 | .atomic_set_property = sde_crtc_atomic_set_property, |
| 1103 | .atomic_get_property = sde_crtc_atomic_get_property, |
| 1104 | .reset = sde_crtc_reset, |
| 1105 | .atomic_duplicate_state = sde_crtc_duplicate_state, |
| 1106 | .atomic_destroy_state = sde_crtc_destroy_state, |
Gopikrishnaiah Anandan | 7f6ef94 | 2016-06-20 15:50:00 -0700 | [diff] [blame] | 1107 | .save = sde_crtc_suspend, |
| 1108 | .restore = sde_crtc_resume, |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1109 | }; |
| 1110 | |
| 1111 | static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = { |
| 1112 | .mode_fixup = sde_crtc_mode_fixup, |
| 1113 | .mode_set_nofb = sde_crtc_mode_set_nofb, |
| 1114 | .disable = sde_crtc_disable, |
| 1115 | .enable = sde_crtc_enable, |
| 1116 | .atomic_check = sde_crtc_atomic_check, |
| 1117 | .atomic_begin = sde_crtc_atomic_begin, |
| 1118 | .atomic_flush = sde_crtc_atomic_flush, |
| 1119 | }; |
| 1120 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1121 | static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc, |
| 1122 | struct sde_kms *sde_kms) |
| 1123 | { |
| 1124 | static const struct file_operations debugfs_mixer_fops = { |
| 1125 | .open = _sde_debugfs_mixer_open, |
| 1126 | .read = seq_read, |
| 1127 | .llseek = seq_lseek, |
| 1128 | .release = single_release, |
| 1129 | }; |
| 1130 | if (sde_crtc && sde_kms) { |
| 1131 | sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name, |
| 1132 | sde_debugfs_get_root(sde_kms)); |
| 1133 | if (sde_crtc->debugfs_root) { |
| 1134 | /* don't error check these */ |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1135 | debugfs_create_file("mixers", 0444, |
| 1136 | sde_crtc->debugfs_root, |
| 1137 | sde_crtc, &debugfs_mixer_fops); |
| 1138 | } |
| 1139 | } |
| 1140 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1141 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1142 | /* initialize crtc */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1143 | struct drm_crtc *sde_crtc_init(struct drm_device *dev, |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 1144 | struct drm_plane *plane, |
| 1145 | int drm_crtc_id) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1146 | { |
| 1147 | struct drm_crtc *crtc = NULL; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1148 | struct sde_crtc *sde_crtc = NULL; |
| 1149 | struct msm_drm_private *priv = NULL; |
| 1150 | struct sde_kms *kms = NULL; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1151 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1152 | priv = dev->dev_private; |
| 1153 | kms = to_sde_kms(priv->kms); |
| 1154 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1155 | sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL); |
| 1156 | if (!sde_crtc) |
| 1157 | return ERR_PTR(-ENOMEM); |
| 1158 | |
| 1159 | crtc = &sde_crtc->base; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1160 | crtc->dev = dev; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1161 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 1162 | sde_crtc->drm_crtc_id = drm_crtc_id; |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 1163 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1164 | drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1165 | |
| 1166 | drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1167 | plane->crtc = crtc; |
| 1168 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1169 | /* save user friendly CRTC name for later */ |
| 1170 | snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); |
| 1171 | |
Clarence Ip | 9a74a44 | 2016-08-25 18:29:03 -0400 | [diff] [blame] | 1172 | /* initialize output fence support */ |
| 1173 | sde_fence_init(dev, &sde_crtc->output_fence, sde_crtc->name); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1174 | |
| 1175 | /* initialize debugfs support */ |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1176 | _sde_crtc_init_debugfs(sde_crtc, kms); |
| 1177 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1178 | /* create CRTC properties */ |
| 1179 | msm_property_init(&sde_crtc->property_info, &crtc->base, dev, |
| 1180 | priv->crtc_property, sde_crtc->property_data, |
| 1181 | CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT, |
| 1182 | sizeof(struct sde_crtc_state)); |
| 1183 | |
| 1184 | sde_crtc_install_properties(crtc); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1185 | sde_cp_crtc_init(crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 1186 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1187 | SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1188 | return crtc; |
| 1189 | } |