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Mattias Wallin489bcce2011-05-27 10:30:12 +02001/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
7 * sched_clock implementation is based on:
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
9 *
10 * DBx500-PRCMU Timer
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
13 * source on DB8500 and Timer 3 on DB5500.
14 */
15#include <linux/clockchips.h>
16#include <linux/clksrc-dbx500-prcmu.h>
17
18#include <asm/sched_clock.h>
19
20#include <mach/setup.h>
21#include <mach/hardware.h>
22
23#define RATE_32K 32768
24
25#define TIMER_MODE_CONTINOUS 0x1
26#define TIMER_DOWNCOUNT_VAL 0xffffffff
27
28#define PRCMU_TIMER_REF 0
29#define PRCMU_TIMER_DOWNCOUNT 0x4
30#define PRCMU_TIMER_MODE 0x8
31
32#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
33
Linus Walleijb1e3be062011-10-03 09:30:20 +020034static void __iomem *clksrc_dbx500_timer_base;
Mattias Wallin489bcce2011-05-27 10:30:12 +020035
36static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
37{
38 u32 count, count2;
39
40 do {
41 count = readl(clksrc_dbx500_timer_base +
42 PRCMU_TIMER_DOWNCOUNT);
43 count2 = readl(clksrc_dbx500_timer_base +
44 PRCMU_TIMER_DOWNCOUNT);
45 } while (count2 != count);
46
47 /* Negate because the timer is a decrementing counter */
48 return ~count;
49}
50
51static struct clocksource clocksource_dbx500_prcmu = {
52 .name = "dbx500-prcmu-timer",
53 .rating = 300,
54 .read = clksrc_dbx500_prcmu_read,
55 .shift = 10,
56 .mask = CLOCKSOURCE_MASK(32),
57 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
58};
59
60#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
Mattias Wallin489bcce2011-05-27 10:30:12 +020061
Linus Walleijcfef0322012-01-02 14:50:15 +010062static u32 notrace dbx500_prcmu_sched_clock_read(void)
Mattias Wallin489bcce2011-05-27 10:30:12 +020063{
Mattias Wallin489bcce2011-05-27 10:30:12 +020064 if (unlikely(!clksrc_dbx500_timer_base))
65 return 0;
66
Linus Walleijcfef0322012-01-02 14:50:15 +010067 return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
Mattias Wallin489bcce2011-05-27 10:30:12 +020068}
69
Mattias Wallin489bcce2011-05-27 10:30:12 +020070#endif
71
Linus Walleijb1e3be062011-10-03 09:30:20 +020072void __init clksrc_dbx500_prcmu_init(void __iomem *base)
Mattias Wallin489bcce2011-05-27 10:30:12 +020073{
Linus Walleijb1e3be062011-10-03 09:30:20 +020074 clksrc_dbx500_timer_base = base;
75
Mattias Wallin489bcce2011-05-27 10:30:12 +020076 /*
77 * The A9 sub system expects the timer to be configured as
78 * a continous looping timer.
79 * The PRCMU should configure it but if it for some reason
80 * don't we do it here.
81 */
82 if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
83 TIMER_MODE_CONTINOUS) {
84 writel(TIMER_MODE_CONTINOUS,
85 clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
86 writel(TIMER_DOWNCOUNT_VAL,
87 clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
88 }
89#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
Linus Walleijcfef0322012-01-02 14:50:15 +010090 setup_sched_clock(dbx500_prcmu_sched_clock_read,
Mattias Wallin489bcce2011-05-27 10:30:12 +020091 32, RATE_32K);
92#endif
93 clocksource_calc_mult_shift(&clocksource_dbx500_prcmu,
94 RATE_32K, SCHED_CLOCK_MIN_WRAP);
95 clocksource_register(&clocksource_dbx500_prcmu);
96}