| Ben Skeggs | d01c309 | 2014-08-10 04:10:21 +1000 | [diff] [blame^] | 1 | #ifndef __NVIF_CLASS_H__ |
| 2 | #define __NVIF_CLASS_H__ |
| 3 | |
| 4 | /******************************************************************************* |
| 5 | * class identifiers |
| 6 | ******************************************************************************/ |
| 7 | |
| 8 | /* the below match nvidia-assigned (either in hw, or sw) class numbers */ |
| 9 | #define NV_DEVICE 0x00000080 |
| 10 | |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * device |
| 14 | ******************************************************************************/ |
| 15 | |
| 16 | #define NV_DEVICE_V0_INFO 0x00 |
| 17 | |
| 18 | struct nv_device_info_v0 { |
| 19 | __u8 version; |
| 20 | #define NV_DEVICE_INFO_V0_IGP 0x00 |
| 21 | #define NV_DEVICE_INFO_V0_PCI 0x01 |
| 22 | #define NV_DEVICE_INFO_V0_AGP 0x02 |
| 23 | #define NV_DEVICE_INFO_V0_PCIE 0x03 |
| 24 | #define NV_DEVICE_INFO_V0_SOC 0x04 |
| 25 | __u8 platform; |
| 26 | __u16 chipset; /* from NV_PMC_BOOT_0 */ |
| 27 | __u8 revision; /* from NV_PMC_BOOT_0 */ |
| 28 | #define NV_DEVICE_INFO_V0_TNT 0x01 |
| 29 | #define NV_DEVICE_INFO_V0_CELSIUS 0x02 |
| 30 | #define NV_DEVICE_INFO_V0_KELVIN 0x03 |
| 31 | #define NV_DEVICE_INFO_V0_RANKINE 0x04 |
| 32 | #define NV_DEVICE_INFO_V0_CURIE 0x05 |
| 33 | #define NV_DEVICE_INFO_V0_TESLA 0x06 |
| 34 | #define NV_DEVICE_INFO_V0_FERMI 0x07 |
| 35 | #define NV_DEVICE_INFO_V0_KEPLER 0x08 |
| 36 | #define NV_DEVICE_INFO_V0_MAXWELL 0x09 |
| 37 | __u8 family; |
| 38 | __u8 pad06[2]; |
| 39 | __u64 ram_size; |
| 40 | __u64 ram_user; |
| 41 | }; |
| 42 | |
| 43 | #endif |