Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xHCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008 Intel Corp. |
| 5 | * |
| 6 | * Author: Sarah Sharp |
| 7 | * Some code borrowed from the Linux EHCI driver. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
| 22 | |
| 23 | #include <linux/irq.h> |
| 24 | #include <linux/module.h> |
| 25 | |
| 26 | #include "xhci.h" |
| 27 | |
| 28 | #define DRIVER_AUTHOR "Sarah Sharp" |
| 29 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" |
| 30 | |
| 31 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
| 32 | /* |
| 33 | * handshake - spin reading hc until handshake completes or fails |
| 34 | * @ptr: address of hc register to be read |
| 35 | * @mask: bits to look at in result of read |
| 36 | * @done: value of those bits when handshake succeeds |
| 37 | * @usec: timeout in microseconds |
| 38 | * |
| 39 | * Returns negative errno, or zero on success |
| 40 | * |
| 41 | * Success happens when the "mask" bits have the specified value (hardware |
| 42 | * handshake done). There are two failure modes: "usec" have passed (major |
| 43 | * hardware flakeout), or the register reads as all-ones (hardware removed). |
| 44 | */ |
| 45 | static int handshake(struct xhci_hcd *xhci, void __iomem *ptr, |
| 46 | u32 mask, u32 done, int usec) |
| 47 | { |
| 48 | u32 result; |
| 49 | |
| 50 | do { |
| 51 | result = xhci_readl(xhci, ptr); |
| 52 | if (result == ~(u32)0) /* card removed */ |
| 53 | return -ENODEV; |
| 54 | result &= mask; |
| 55 | if (result == done) |
| 56 | return 0; |
| 57 | udelay(1); |
| 58 | usec--; |
| 59 | } while (usec > 0); |
| 60 | return -ETIMEDOUT; |
| 61 | } |
| 62 | |
| 63 | /* |
| 64 | * Force HC into halt state. |
| 65 | * |
| 66 | * Disable any IRQs and clear the run/stop bit. |
| 67 | * HC will complete any current and actively pipelined transactions, and |
| 68 | * should halt within 16 microframes of the run/stop bit being cleared. |
| 69 | * Read HC Halted bit in the status register to see when the HC is finished. |
| 70 | * XXX: shouldn't we set HC_STATE_HALT here somewhere? |
| 71 | */ |
| 72 | int xhci_halt(struct xhci_hcd *xhci) |
| 73 | { |
| 74 | u32 halted; |
| 75 | u32 cmd; |
| 76 | u32 mask; |
| 77 | |
| 78 | xhci_dbg(xhci, "// Halt the HC\n"); |
| 79 | /* Disable all interrupts from the host controller */ |
| 80 | mask = ~(XHCI_IRQS); |
| 81 | halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT; |
| 82 | if (!halted) |
| 83 | mask &= ~CMD_RUN; |
| 84 | |
| 85 | cmd = xhci_readl(xhci, &xhci->op_regs->command); |
| 86 | cmd &= mask; |
| 87 | xhci_writel(xhci, cmd, &xhci->op_regs->command); |
| 88 | |
| 89 | return handshake(xhci, &xhci->op_regs->status, |
| 90 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
| 91 | } |
| 92 | |
| 93 | /* |
| 94 | * Reset a halted HC, and set the internal HC state to HC_STATE_HALT. |
| 95 | * |
| 96 | * This resets pipelines, timers, counters, state machines, etc. |
| 97 | * Transactions will be terminated immediately, and operational registers |
| 98 | * will be set to their defaults. |
| 99 | */ |
| 100 | int xhci_reset(struct xhci_hcd *xhci) |
| 101 | { |
| 102 | u32 command; |
| 103 | u32 state; |
| 104 | |
| 105 | state = xhci_readl(xhci, &xhci->op_regs->status); |
| 106 | BUG_ON((state & STS_HALT) == 0); |
| 107 | |
| 108 | xhci_dbg(xhci, "// Reset the HC\n"); |
| 109 | command = xhci_readl(xhci, &xhci->op_regs->command); |
| 110 | command |= CMD_RESET; |
| 111 | xhci_writel(xhci, command, &xhci->op_regs->command); |
| 112 | /* XXX: Why does EHCI set this here? Shouldn't other code do this? */ |
| 113 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; |
| 114 | |
| 115 | return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000); |
| 116 | } |
| 117 | |
| 118 | /* |
| 119 | * Stop the HC from processing the endpoint queues. |
| 120 | */ |
| 121 | static void xhci_quiesce(struct xhci_hcd *xhci) |
| 122 | { |
| 123 | /* |
| 124 | * Queues are per endpoint, so we need to disable an endpoint or slot. |
| 125 | * |
| 126 | * To disable a slot, we need to insert a disable slot command on the |
| 127 | * command ring and ring the doorbell. This will also free any internal |
| 128 | * resources associated with the slot (which might not be what we want). |
| 129 | * |
| 130 | * A Release Endpoint command sounds better - doesn't free internal HC |
| 131 | * memory, but removes the endpoints from the schedule and releases the |
| 132 | * bandwidth, disables the doorbells, and clears the endpoint enable |
| 133 | * flag. Usually used prior to a set interface command. |
| 134 | * |
| 135 | * TODO: Implement after command ring code is done. |
| 136 | */ |
| 137 | BUG_ON(!HC_IS_RUNNING(xhci_to_hcd(xhci)->state)); |
| 138 | xhci_dbg(xhci, "Finished quiescing -- code not written yet\n"); |
| 139 | } |
| 140 | |
| 141 | #if 0 |
| 142 | /* Set up MSI-X table for entry 0 (may claim other entries later) */ |
| 143 | static int xhci_setup_msix(struct xhci_hcd *xhci) |
| 144 | { |
| 145 | int ret; |
| 146 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
| 147 | |
| 148 | xhci->msix_count = 0; |
| 149 | /* XXX: did I do this right? ixgbe does kcalloc for more than one */ |
| 150 | xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL); |
| 151 | if (!xhci->msix_entries) { |
| 152 | xhci_err(xhci, "Failed to allocate MSI-X entries\n"); |
| 153 | return -ENOMEM; |
| 154 | } |
| 155 | xhci->msix_entries[0].entry = 0; |
| 156 | |
| 157 | ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count); |
| 158 | if (ret) { |
| 159 | xhci_err(xhci, "Failed to enable MSI-X\n"); |
| 160 | goto free_entries; |
| 161 | } |
| 162 | |
| 163 | /* |
| 164 | * Pass the xhci pointer value as the request_irq "cookie". |
| 165 | * If more irqs are added, this will need to be unique for each one. |
| 166 | */ |
| 167 | ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0, |
| 168 | "xHCI", xhci_to_hcd(xhci)); |
| 169 | if (ret) { |
| 170 | xhci_err(xhci, "Failed to allocate MSI-X interrupt\n"); |
| 171 | goto disable_msix; |
| 172 | } |
| 173 | xhci_dbg(xhci, "Finished setting up MSI-X\n"); |
| 174 | return 0; |
| 175 | |
| 176 | disable_msix: |
| 177 | pci_disable_msix(pdev); |
| 178 | free_entries: |
| 179 | kfree(xhci->msix_entries); |
| 180 | xhci->msix_entries = NULL; |
| 181 | return ret; |
| 182 | } |
| 183 | |
| 184 | /* XXX: code duplication; can xhci_setup_msix call this? */ |
| 185 | /* Free any IRQs and disable MSI-X */ |
| 186 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) |
| 187 | { |
| 188 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
| 189 | if (!xhci->msix_entries) |
| 190 | return; |
| 191 | |
| 192 | free_irq(xhci->msix_entries[0].vector, xhci); |
| 193 | pci_disable_msix(pdev); |
| 194 | kfree(xhci->msix_entries); |
| 195 | xhci->msix_entries = NULL; |
| 196 | xhci_dbg(xhci, "Finished cleaning up MSI-X\n"); |
| 197 | } |
| 198 | #endif |
| 199 | |
| 200 | /* |
| 201 | * Initialize memory for HCD and xHC (one-time init). |
| 202 | * |
| 203 | * Program the PAGESIZE register, initialize the device context array, create |
| 204 | * device contexts (?), set up a command ring segment (or two?), create event |
| 205 | * ring (one for now). |
| 206 | */ |
| 207 | int xhci_init(struct usb_hcd *hcd) |
| 208 | { |
| 209 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 210 | int retval = 0; |
| 211 | |
| 212 | xhci_dbg(xhci, "xhci_init\n"); |
| 213 | spin_lock_init(&xhci->lock); |
| 214 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
| 215 | xhci_dbg(xhci, "Finished xhci_init\n"); |
| 216 | |
| 217 | return retval; |
| 218 | } |
| 219 | |
| 220 | /* |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 221 | * Called in interrupt context when there might be work |
| 222 | * queued on the event ring |
| 223 | * |
| 224 | * xhci->lock must be held by caller. |
| 225 | */ |
| 226 | static void xhci_work(struct xhci_hcd *xhci) |
| 227 | { |
| 228 | u32 temp; |
| 229 | |
| 230 | /* |
| 231 | * Clear the op reg interrupt status first, |
| 232 | * so we can receive interrupts from other MSI-X interrupters. |
| 233 | * Write 1 to clear the interrupt status. |
| 234 | */ |
| 235 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
| 236 | temp |= STS_EINT; |
| 237 | xhci_writel(xhci, temp, &xhci->op_regs->status); |
| 238 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
| 239 | /* Clear the MSI-X event interrupt status */ |
| 240 | |
| 241 | /* Acknowledge the interrupt */ |
| 242 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 243 | temp |= 0x3; |
| 244 | xhci_writel(xhci, temp, &xhci->ir_set->irq_pending); |
| 245 | /* Flush posted writes */ |
| 246 | xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 247 | |
| 248 | /* FIXME this should be a delayed service routine that clears the EHB */ |
| 249 | handle_event(xhci); |
| 250 | |
| 251 | /* Clear the event handler busy flag; the event ring should be empty. */ |
| 252 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]); |
| 253 | xhci_writel(xhci, temp & ~ERST_EHB, &xhci->ir_set->erst_dequeue[0]); |
| 254 | /* Flush posted writes -- FIXME is this necessary? */ |
| 255 | xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 256 | } |
| 257 | |
| 258 | /*-------------------------------------------------------------------------*/ |
| 259 | |
| 260 | /* |
| 261 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, |
| 262 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of |
| 263 | * indicators of an event TRB error, but we check the status *first* to be safe. |
| 264 | */ |
| 265 | irqreturn_t xhci_irq(struct usb_hcd *hcd) |
| 266 | { |
| 267 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 268 | u32 temp, temp2; |
| 269 | |
| 270 | spin_lock(&xhci->lock); |
| 271 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
| 272 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
| 273 | temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 274 | if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) { |
| 275 | spin_unlock(&xhci->lock); |
| 276 | return IRQ_NONE; |
| 277 | } |
| 278 | |
| 279 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
| 280 | if (temp & STS_FATAL) { |
| 281 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
| 282 | xhci_halt(xhci); |
| 283 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; |
| 284 | return -ESHUTDOWN; |
| 285 | } |
| 286 | |
| 287 | xhci_work(xhci); |
| 288 | spin_unlock(&xhci->lock); |
| 289 | |
| 290 | return IRQ_HANDLED; |
| 291 | } |
| 292 | |
| 293 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
| 294 | void event_ring_work(unsigned long arg) |
| 295 | { |
| 296 | unsigned long flags; |
| 297 | int temp; |
| 298 | struct xhci_hcd *xhci = (struct xhci_hcd *) arg; |
| 299 | int i, j; |
| 300 | |
| 301 | xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies); |
| 302 | |
| 303 | spin_lock_irqsave(&xhci->lock, flags); |
| 304 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
| 305 | xhci_dbg(xhci, "op reg status = 0x%x\n", temp); |
| 306 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 307 | xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp); |
| 308 | xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled); |
| 309 | xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask); |
| 310 | xhci->error_bitmask = 0; |
| 311 | xhci_dbg(xhci, "Event ring:\n"); |
| 312 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); |
| 313 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); |
| 314 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]); |
| 315 | temp &= ERST_PTR_MASK; |
| 316 | xhci_dbg(xhci, "ERST deq = 0x%x\n", temp); |
| 317 | xhci_dbg(xhci, "Command ring:\n"); |
| 318 | xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg); |
| 319 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); |
| 320 | xhci_dbg_cmd_ptrs(xhci); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 321 | for (i = 0; i < MAX_HC_SLOTS; ++i) { |
| 322 | if (xhci->devs[i]) { |
| 323 | for (j = 0; j < 31; ++j) { |
| 324 | if (xhci->devs[i]->ep_rings[j]) { |
| 325 | xhci_dbg(xhci, "Dev %d endpoint ring %d:\n", i, j); |
| 326 | xhci_debug_segment(xhci, xhci->devs[i]->ep_rings[j]->deq_seg); |
| 327 | } |
| 328 | } |
| 329 | } |
| 330 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 331 | |
| 332 | if (xhci->noops_submitted != NUM_TEST_NOOPS) |
| 333 | if (setup_one_noop(xhci)) |
| 334 | ring_cmd_db(xhci); |
| 335 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 336 | |
| 337 | if (!xhci->zombie) |
| 338 | mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ); |
| 339 | else |
| 340 | xhci_dbg(xhci, "Quit polling the event ring.\n"); |
| 341 | } |
| 342 | #endif |
| 343 | |
| 344 | /* |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 345 | * Start the HC after it was halted. |
| 346 | * |
| 347 | * This function is called by the USB core when the HC driver is added. |
| 348 | * Its opposite is xhci_stop(). |
| 349 | * |
| 350 | * xhci_init() must be called once before this function can be called. |
| 351 | * Reset the HC, enable device slot contexts, program DCBAAP, and |
| 352 | * set command ring pointer and event ring pointer. |
| 353 | * |
| 354 | * Setup MSI-X vectors and enable interrupts. |
| 355 | */ |
| 356 | int xhci_run(struct usb_hcd *hcd) |
| 357 | { |
| 358 | u32 temp; |
| 359 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 360 | void (*doorbell)(struct xhci_hcd *) = NULL; |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 361 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 362 | hcd->uses_new_polling = 1; |
| 363 | hcd->poll_rh = 0; |
| 364 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 365 | xhci_dbg(xhci, "xhci_run\n"); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 366 | #if 0 /* FIXME: MSI not setup yet */ |
| 367 | /* Do this at the very last minute */ |
| 368 | ret = xhci_setup_msix(xhci); |
| 369 | if (!ret) |
| 370 | return ret; |
| 371 | |
| 372 | return -ENOSYS; |
| 373 | #endif |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 374 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
| 375 | init_timer(&xhci->event_ring_timer); |
| 376 | xhci->event_ring_timer.data = (unsigned long) xhci; |
| 377 | xhci->event_ring_timer.function = event_ring_work; |
| 378 | /* Poll the event ring */ |
| 379 | xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ; |
| 380 | xhci->zombie = 0; |
| 381 | xhci_dbg(xhci, "Setting event ring polling timer\n"); |
| 382 | add_timer(&xhci->event_ring_timer); |
| 383 | #endif |
| 384 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 385 | xhci_dbg(xhci, "// Set the interrupt modulation register\n"); |
| 386 | temp = xhci_readl(xhci, &xhci->ir_set->irq_control); |
| 387 | temp &= 0xffff; |
| 388 | temp |= (u32) 160; |
| 389 | xhci_writel(xhci, temp, &xhci->ir_set->irq_control); |
| 390 | |
| 391 | /* Set the HCD state before we enable the irqs */ |
| 392 | hcd->state = HC_STATE_RUNNING; |
| 393 | temp = xhci_readl(xhci, &xhci->op_regs->command); |
| 394 | temp |= (CMD_EIE); |
| 395 | xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n", |
| 396 | temp); |
| 397 | xhci_writel(xhci, temp, &xhci->op_regs->command); |
| 398 | |
| 399 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 400 | xhci_dbg(xhci, "// Enabling event ring interrupter 0x%x" |
| 401 | " by writing 0x%x to irq_pending\n", |
| 402 | (unsigned int) xhci->ir_set, |
| 403 | (unsigned int) ER_IRQ_ENABLE(temp)); |
| 404 | xhci_writel(xhci, ER_IRQ_ENABLE(temp), |
| 405 | &xhci->ir_set->irq_pending); |
| 406 | xhci_print_ir_set(xhci, xhci->ir_set, 0); |
| 407 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 408 | if (NUM_TEST_NOOPS > 0) |
| 409 | doorbell = setup_one_noop(xhci); |
| 410 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 411 | xhci_dbg(xhci, "Command ring memory map follows:\n"); |
| 412 | xhci_debug_ring(xhci, xhci->cmd_ring); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 413 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); |
| 414 | xhci_dbg_cmd_ptrs(xhci); |
| 415 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 416 | xhci_dbg(xhci, "ERST memory map follows:\n"); |
| 417 | xhci_dbg_erst(xhci, &xhci->erst); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 418 | xhci_dbg(xhci, "Event ring:\n"); |
| 419 | xhci_debug_ring(xhci, xhci->event_ring); |
| 420 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); |
| 421 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[1]); |
| 422 | xhci_dbg(xhci, "ERST deq upper = 0x%x\n", temp); |
| 423 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]); |
| 424 | temp &= ERST_PTR_MASK; |
| 425 | xhci_dbg(xhci, "ERST deq = 0x%x\n", temp); |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 426 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 427 | temp = xhci_readl(xhci, &xhci->op_regs->command); |
| 428 | temp |= (CMD_RUN); |
| 429 | xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n", |
| 430 | temp); |
| 431 | xhci_writel(xhci, temp, &xhci->op_regs->command); |
| 432 | /* Flush PCI posted writes */ |
| 433 | temp = xhci_readl(xhci, &xhci->op_regs->command); |
| 434 | xhci_dbg(xhci, "// @%x = 0x%x\n", |
| 435 | (unsigned int) &xhci->op_regs->command, temp); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 436 | if (doorbell) |
| 437 | (*doorbell)(xhci); |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 438 | |
| 439 | xhci_dbg(xhci, "Finished xhci_run\n"); |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | /* |
| 444 | * Stop xHCI driver. |
| 445 | * |
| 446 | * This function is called by the USB core when the HC driver is removed. |
| 447 | * Its opposite is xhci_run(). |
| 448 | * |
| 449 | * Disable device contexts, disable IRQs, and quiesce the HC. |
| 450 | * Reset the HC, finish any completed transactions, and cleanup memory. |
| 451 | */ |
| 452 | void xhci_stop(struct usb_hcd *hcd) |
| 453 | { |
| 454 | u32 temp; |
| 455 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 456 | |
| 457 | spin_lock_irq(&xhci->lock); |
| 458 | if (HC_IS_RUNNING(hcd->state)) |
| 459 | xhci_quiesce(xhci); |
| 460 | xhci_halt(xhci); |
| 461 | xhci_reset(xhci); |
| 462 | spin_unlock_irq(&xhci->lock); |
| 463 | |
| 464 | #if 0 /* No MSI yet */ |
| 465 | xhci_cleanup_msix(xhci); |
| 466 | #endif |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 467 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
| 468 | /* Tell the event ring poll function not to reschedule */ |
| 469 | xhci->zombie = 1; |
| 470 | del_timer_sync(&xhci->event_ring_timer); |
| 471 | #endif |
| 472 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 473 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
| 474 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
| 475 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); |
| 476 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 477 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), |
| 478 | &xhci->ir_set->irq_pending); |
| 479 | xhci_print_ir_set(xhci, xhci->ir_set, 0); |
| 480 | |
| 481 | xhci_dbg(xhci, "cleaning up memory\n"); |
| 482 | xhci_mem_cleanup(xhci); |
| 483 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", |
| 484 | xhci_readl(xhci, &xhci->op_regs->status)); |
| 485 | } |
| 486 | |
| 487 | /* |
| 488 | * Shutdown HC (not bus-specific) |
| 489 | * |
| 490 | * This is called when the machine is rebooting or halting. We assume that the |
| 491 | * machine will be powered off, and the HC's internal state will be reset. |
| 492 | * Don't bother to free memory. |
| 493 | */ |
| 494 | void xhci_shutdown(struct usb_hcd *hcd) |
| 495 | { |
| 496 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 497 | |
| 498 | spin_lock_irq(&xhci->lock); |
| 499 | xhci_halt(xhci); |
| 500 | spin_unlock_irq(&xhci->lock); |
| 501 | |
| 502 | #if 0 |
| 503 | xhci_cleanup_msix(xhci); |
| 504 | #endif |
| 505 | |
| 506 | xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n", |
| 507 | xhci_readl(xhci, &xhci->op_regs->status)); |
| 508 | } |
| 509 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 510 | /*-------------------------------------------------------------------------*/ |
| 511 | |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 512 | /* |
| 513 | * At this point, the struct usb_device is about to go away, the device has |
| 514 | * disconnected, and all traffic has been stopped and the endpoints have been |
| 515 | * disabled. Free any HC data structures associated with that device. |
| 516 | */ |
| 517 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) |
| 518 | { |
| 519 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 520 | unsigned long flags; |
| 521 | |
| 522 | if (udev->slot_id == 0) |
| 523 | return; |
| 524 | |
| 525 | spin_lock_irqsave(&xhci->lock, flags); |
| 526 | if (queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) { |
| 527 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 528 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); |
| 529 | return; |
| 530 | } |
| 531 | ring_cmd_db(xhci); |
| 532 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 533 | /* |
| 534 | * Event command completion handler will free any data structures |
| 535 | * associated with the slot |
| 536 | */ |
| 537 | } |
| 538 | |
| 539 | /* |
| 540 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command |
| 541 | * timed out, or allocating memory failed. Returns 1 on success. |
| 542 | */ |
| 543 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) |
| 544 | { |
| 545 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 546 | unsigned long flags; |
| 547 | int timeleft; |
| 548 | int ret; |
| 549 | |
| 550 | spin_lock_irqsave(&xhci->lock, flags); |
| 551 | ret = queue_slot_control(xhci, TRB_ENABLE_SLOT, 0); |
| 552 | if (ret) { |
| 553 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 554 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); |
| 555 | return 0; |
| 556 | } |
| 557 | ring_cmd_db(xhci); |
| 558 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 559 | |
| 560 | /* XXX: how much time for xHC slot assignment? */ |
| 561 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, |
| 562 | USB_CTRL_SET_TIMEOUT); |
| 563 | if (timeleft <= 0) { |
| 564 | xhci_warn(xhci, "%s while waiting for a slot\n", |
| 565 | timeleft == 0 ? "Timeout" : "Signal"); |
| 566 | /* FIXME cancel the enable slot request */ |
| 567 | return 0; |
| 568 | } |
| 569 | |
| 570 | spin_lock_irqsave(&xhci->lock, flags); |
| 571 | if (!xhci->slot_id) { |
| 572 | xhci_err(xhci, "Error while assigning device slot ID\n"); |
| 573 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 574 | return 0; |
| 575 | } |
| 576 | if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) { |
| 577 | /* Disable slot, if we can do it without mem alloc */ |
| 578 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
| 579 | if (!queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) |
| 580 | ring_cmd_db(xhci); |
| 581 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 582 | return 0; |
| 583 | } |
| 584 | udev->slot_id = xhci->slot_id; |
| 585 | /* Is this a LS or FS device under a HS hub? */ |
| 586 | /* Hub or peripherial? */ |
| 587 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 588 | return 1; |
| 589 | } |
| 590 | |
| 591 | /* |
| 592 | * Issue an Address Device command (which will issue a SetAddress request to |
| 593 | * the device). |
| 594 | * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so |
| 595 | * we should only issue and wait on one address command at the same time. |
| 596 | * |
| 597 | * We add one to the device address issued by the hardware because the USB core |
| 598 | * uses address 1 for the root hubs (even though they're not really devices). |
| 599 | */ |
| 600 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) |
| 601 | { |
| 602 | unsigned long flags; |
| 603 | int timeleft; |
| 604 | struct xhci_virt_device *virt_dev; |
| 605 | int ret = 0; |
| 606 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 607 | u32 temp; |
| 608 | |
| 609 | if (!udev->slot_id) { |
| 610 | xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id); |
| 611 | return -EINVAL; |
| 612 | } |
| 613 | |
| 614 | spin_lock_irqsave(&xhci->lock, flags); |
| 615 | virt_dev = xhci->devs[udev->slot_id]; |
| 616 | |
| 617 | /* If this is a Set Address to an unconfigured device, setup ep 0 */ |
| 618 | if (!udev->config) |
| 619 | xhci_setup_addressable_virt_dev(xhci, udev); |
| 620 | /* Otherwise, assume the core has the device configured how it wants */ |
| 621 | |
| 622 | ret = queue_address_device(xhci, virt_dev->in_ctx_dma, udev->slot_id); |
| 623 | if (ret) { |
| 624 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 625 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); |
| 626 | return ret; |
| 627 | } |
| 628 | ring_cmd_db(xhci); |
| 629 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 630 | |
| 631 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ |
| 632 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, |
| 633 | USB_CTRL_SET_TIMEOUT); |
| 634 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
| 635 | * the SetAddress() "recovery interval" required by USB and aborting the |
| 636 | * command on a timeout. |
| 637 | */ |
| 638 | if (timeleft <= 0) { |
| 639 | xhci_warn(xhci, "%s while waiting for a slot\n", |
| 640 | timeleft == 0 ? "Timeout" : "Signal"); |
| 641 | /* FIXME cancel the address device command */ |
| 642 | return -ETIME; |
| 643 | } |
| 644 | |
| 645 | spin_lock_irqsave(&xhci->lock, flags); |
| 646 | switch (virt_dev->cmd_status) { |
| 647 | case COMP_CTX_STATE: |
| 648 | case COMP_EBADSLT: |
| 649 | xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n", |
| 650 | udev->slot_id); |
| 651 | ret = -EINVAL; |
| 652 | break; |
| 653 | case COMP_TX_ERR: |
| 654 | dev_warn(&udev->dev, "Device not responding to set address.\n"); |
| 655 | ret = -EPROTO; |
| 656 | break; |
| 657 | case COMP_SUCCESS: |
| 658 | xhci_dbg(xhci, "Successful Address Device command\n"); |
| 659 | break; |
| 660 | default: |
| 661 | xhci_err(xhci, "ERROR: unexpected command completion " |
| 662 | "code 0x%x.\n", virt_dev->cmd_status); |
| 663 | ret = -EINVAL; |
| 664 | break; |
| 665 | } |
| 666 | if (ret) { |
| 667 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 668 | return ret; |
| 669 | } |
| 670 | temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[0]); |
| 671 | xhci_dbg(xhci, "Op regs DCBAA ptr[0] = %#08x\n", temp); |
| 672 | temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[1]); |
| 673 | xhci_dbg(xhci, "Op regs DCBAA ptr[1] = %#08x\n", temp); |
| 674 | xhci_dbg(xhci, "Slot ID %d dcbaa entry[0] @%08x = %#08x\n", |
| 675 | udev->slot_id, |
| 676 | (unsigned int) &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id], |
| 677 | xhci->dcbaa->dev_context_ptrs[2*udev->slot_id]); |
| 678 | xhci_dbg(xhci, "Slot ID %d dcbaa entry[1] @%08x = %#08x\n", |
| 679 | udev->slot_id, |
| 680 | (unsigned int) &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1], |
| 681 | xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1]); |
| 682 | xhci_dbg(xhci, "Output Context DMA address = %#08x\n", |
| 683 | virt_dev->out_ctx_dma); |
| 684 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
| 685 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, virt_dev->in_ctx_dma, 2); |
| 686 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
| 687 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, virt_dev->out_ctx_dma, 2); |
| 688 | /* |
| 689 | * USB core uses address 1 for the roothubs, so we add one to the |
| 690 | * address given back to us by the HC. |
| 691 | */ |
| 692 | udev->devnum = (virt_dev->out_ctx->slot.dev_state & DEV_ADDR_MASK) + 1; |
| 693 | /* FIXME: Zero the input context control for later use? */ |
| 694 | spin_unlock_irqrestore(&xhci->lock, flags); |
| 695 | |
| 696 | xhci_dbg(xhci, "Device address = %d\n", udev->devnum); |
| 697 | /* XXX Meh, not sure if anyone else but choose_address uses this. */ |
| 698 | set_bit(udev->devnum, udev->bus->devmap.devicemap); |
| 699 | |
| 700 | return 0; |
| 701 | } |
| 702 | |
Sarah Sharp | 66d4ead | 2009-04-27 19:52:28 -0700 | [diff] [blame] | 703 | int xhci_get_frame(struct usb_hcd *hcd) |
| 704 | { |
| 705 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
| 706 | /* EHCI mods by the periodic size. Why? */ |
| 707 | return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3; |
| 708 | } |
| 709 | |
| 710 | MODULE_DESCRIPTION(DRIVER_DESC); |
| 711 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 712 | MODULE_LICENSE("GPL"); |
| 713 | |
| 714 | static int __init xhci_hcd_init(void) |
| 715 | { |
| 716 | #ifdef CONFIG_PCI |
| 717 | int retval = 0; |
| 718 | |
| 719 | retval = xhci_register_pci(); |
| 720 | |
| 721 | if (retval < 0) { |
| 722 | printk(KERN_DEBUG "Problem registering PCI driver."); |
| 723 | return retval; |
| 724 | } |
| 725 | #endif |
| 726 | return 0; |
| 727 | } |
| 728 | module_init(xhci_hcd_init); |
| 729 | |
| 730 | static void __exit xhci_hcd_cleanup(void) |
| 731 | { |
| 732 | #ifdef CONFIG_PCI |
| 733 | xhci_unregister_pci(); |
| 734 | #endif |
| 735 | } |
| 736 | module_exit(xhci_hcd_cleanup); |