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Andrew Lunnb2f427a2011-05-15 13:32:52 +02001/*
2 * arch/arm/plat-orion/mpp.c
3 *
4 * MPP functions for Marvell orion SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16#include <mach/hardware.h>
Rob Herringce915742012-08-29 10:16:55 -050017#include <plat/orion-gpio.h>
Andrew Lunnb2f427a2011-05-15 13:32:52 +020018#include <plat/mpp.h>
19
20/* Address of the ith MPP control register */
Thomas Petazzoni5a2f5502012-09-11 14:27:24 +020021static __init void __iomem *mpp_ctrl_addr(unsigned int i,
22 void __iomem *dev_bus)
Andrew Lunnb2f427a2011-05-15 13:32:52 +020023{
24 return dev_bus + (i) * 4;
25}
26
27
28void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
Thomas Petazzoni5a2f5502012-09-11 14:27:24 +020029 unsigned int mpp_max, void __iomem *dev_bus)
Andrew Lunnb2f427a2011-05-15 13:32:52 +020030{
31 unsigned int mpp_nr_regs = (1 + mpp_max/8);
32 u32 mpp_ctrl[mpp_nr_regs];
33 int i;
34
Andrew Lunnb2f427a2011-05-15 13:32:52 +020035 printk(KERN_DEBUG "initial MPP regs:");
36 for (i = 0; i < mpp_nr_regs; i++) {
37 mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
38 printk(" %08x", mpp_ctrl[i]);
39 }
40 printk("\n");
41
42 for ( ; *mpp_list; mpp_list++) {
43 unsigned int num = MPP_NUM(*mpp_list);
44 unsigned int sel = MPP_SEL(*mpp_list);
45 int shift, gpio_mode;
46
47 if (num > mpp_max) {
48 printk(KERN_ERR "orion_mpp_conf: invalid MPP "
49 "number (%u)\n", num);
50 continue;
51 }
Gerlando Falauto830f8b92013-01-23 14:50:59 +010052 if (variant_mask && !(*mpp_list & variant_mask)) {
Andrew Lunnb2f427a2011-05-15 13:32:52 +020053 printk(KERN_WARNING
54 "orion_mpp_conf: requested MPP%u config "
55 "unavailable on this hardware\n", num);
56 continue;
57 }
58
59 shift = (num & 7) << 2;
60 mpp_ctrl[num / 8] &= ~(0xf << shift);
61 mpp_ctrl[num / 8] |= sel << shift;
62
63 gpio_mode = 0;
64 if (*mpp_list & MPP_INPUT_MASK)
65 gpio_mode |= GPIO_INPUT_OK;
66 if (*mpp_list & MPP_OUTPUT_MASK)
67 gpio_mode |= GPIO_OUTPUT_OK;
Andrew Lunnb0654032012-02-08 15:52:07 +010068
Andrew Lunnb2f427a2011-05-15 13:32:52 +020069 orion_gpio_set_valid(num, gpio_mode);
70 }
71
72 printk(KERN_DEBUG " final MPP regs:");
73 for (i = 0; i < mpp_nr_regs; i++) {
74 writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
75 printk(" %08x", mpp_ctrl[i]);
76 }
77 printk("\n");
78}