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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
Keith Packardf01eca22011-09-28 16:48:10 -07002 * Copyright © 2006 Intel Corporation
Jesse Barnes79e53942008-11-07 14:24:08 -08003 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#ifndef _I830_BIOS_H_
29#define _I830_BIOS_H_
30
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080032
33struct vbt_header {
34 u8 signature[20]; /**< Always starts with 'VBT$' */
35 u16 version; /**< decimal */
36 u16 header_size; /**< in bytes */
37 u16 vbt_size; /**< in bytes */
38 u8 vbt_checksum;
39 u8 reserved0;
40 u32 bdb_offset; /**< from beginning of VBT */
41 u32 aim_offset[4]; /**< from beginning of VBT */
42} __attribute__((packed));
43
44struct bdb_header {
45 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
46 u16 version; /**< decimal */
47 u16 header_size; /**< in bytes */
48 u16 bdb_size; /**< in bytes */
49};
50
51/* strictly speaking, this is a "skip" block, but it has interesting info */
52struct vbios_data {
53 u8 type; /* 0 == desktop, 1 == mobile */
54 u8 relstage;
55 u8 chipset;
56 u8 lvds_present:1;
57 u8 tv_present:1;
58 u8 rsvd2:6; /* finish byte */
59 u8 rsvd3[4];
60 u8 signon[155];
61 u8 copyright[61];
62 u16 code_segment;
63 u8 dos_boot_mode;
64 u8 bandwidth_percent;
65 u8 rsvd4; /* popup memory size */
66 u8 resize_pci_bios;
67 u8 rsvd5; /* is crt already on ddc2 */
68} __attribute__((packed));
69
70/*
71 * There are several types of BIOS data blocks (BDBs), each block has
72 * an ID and size in the first 3 bytes (ID in first, size in next 2).
73 * Known types are listed below.
74 */
75#define BDB_GENERAL_FEATURES 1
76#define BDB_GENERAL_DEFINITIONS 2
77#define BDB_OLD_TOGGLE_LIST 3
78#define BDB_MODE_SUPPORT_LIST 4
79#define BDB_GENERIC_MODE_TABLE 5
80#define BDB_EXT_MMIO_REGS 6
81#define BDB_SWF_IO 7
82#define BDB_SWF_MMIO 8
83#define BDB_DOT_CLOCK_TABLE 9
84#define BDB_MODE_REMOVAL_TABLE 10
85#define BDB_CHILD_DEVICE_TABLE 11
86#define BDB_DRIVER_FEATURES 12
87#define BDB_DRIVER_PERSISTENCE 13
88#define BDB_EXT_TABLE_PTRS 14
89#define BDB_DOT_CLOCK_OVERRIDE 15
90#define BDB_DISPLAY_SELECT 16
91/* 17 rsvd */
92#define BDB_DRIVER_ROTATION 18
93#define BDB_DISPLAY_REMOVE 19
94#define BDB_OEM_CUSTOM 20
95#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
96#define BDB_SDVO_LVDS_OPTIONS 22
97#define BDB_SDVO_PANEL_DTDS 23
98#define BDB_SDVO_LVDS_PNP_IDS 24
99#define BDB_SDVO_LVDS_POWER_SEQ 25
100#define BDB_TV_OPTIONS 26
Zhenyu Wang500a8cc2010-01-13 11:19:52 +0800101#define BDB_EDP 27
Jesse Barnes79e53942008-11-07 14:24:08 -0800102#define BDB_LVDS_OPTIONS 40
103#define BDB_LVDS_LFP_DATA_PTRS 41
104#define BDB_LVDS_LFP_DATA 42
105#define BDB_LVDS_BACKLIGHT 43
106#define BDB_LVDS_POWER 44
Shobhit Kumard17c5442013-08-27 15:12:25 +0300107#define BDB_MIPI 50
Jesse Barnes79e53942008-11-07 14:24:08 -0800108#define BDB_SKIP 254 /* VBIOS private block, ignore */
109
110struct bdb_general_features {
111 /* bits 1 */
112 u8 panel_fitting:2;
113 u8 flexaim:1;
114 u8 msg_enable:1;
115 u8 clear_screen:3;
116 u8 color_flip:1;
117
118 /* bits 2 */
119 u8 download_ext_vbt:1;
120 u8 enable_ssc:1;
121 u8 ssc_freq:1;
122 u8 enable_lfp_on_override:1;
123 u8 disable_ssc_ddt:1;
Keith Packardabd06862011-09-26 14:24:14 -0700124 u8 rsvd7:1;
125 u8 display_clock_mode:1;
126 u8 rsvd8:1; /* finish byte */
Jesse Barnes79e53942008-11-07 14:24:08 -0800127
128 /* bits 3 */
129 u8 disable_smooth_vision:1;
130 u8 single_dvi:1;
Paulo Zanoni3f704fa2013-04-08 15:48:07 -0300131 u8 rsvd9:1;
132 u8 fdi_rx_polarity_inverted:1;
133 u8 rsvd10:4; /* finish byte */
Jesse Barnes79e53942008-11-07 14:24:08 -0800134
135 /* bits 4 */
136 u8 legacy_monitor_detect;
137
138 /* bits 5 */
139 u8 int_crt_support:1;
140 u8 int_tv_support:1;
Keith Packardd2830bd2011-09-26 14:25:57 -0700141 u8 int_efp_support:1;
142 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
143 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
144 u8 rsvd11:3; /* finish byte */
Jesse Barnes79e53942008-11-07 14:24:08 -0800145} __attribute__((packed));
146
yakui_zhao59a036c2009-05-31 17:16:22 +0800147/* pre-915 */
148#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
149#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
150#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
151#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
152
153/* Pre 915 */
154#define DEVICE_TYPE_NONE 0x00
155#define DEVICE_TYPE_CRT 0x01
156#define DEVICE_TYPE_TV 0x09
157#define DEVICE_TYPE_EFP 0x12
158#define DEVICE_TYPE_LFP 0x22
159/* On 915+ */
160#define DEVICE_TYPE_CRT_DPMS 0x6001
161#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
162#define DEVICE_TYPE_TV_COMPOSITE 0x0209
163#define DEVICE_TYPE_TV_MACROVISION 0x0289
164#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
165#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
166#define DEVICE_TYPE_TV_SCART 0x0209
167#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
168#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
169#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
170#define DEVICE_TYPE_EFP_DVI_I 0x6053
171#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
172#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
173#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
174#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
175#define DEVICE_TYPE_LFP_PANELLINK 0x5012
176#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
177#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
178#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
179#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
180
181#define DEVICE_CFG_NONE 0x00
182#define DEVICE_CFG_12BIT_DVOB 0x01
183#define DEVICE_CFG_12BIT_DVOC 0x02
184#define DEVICE_CFG_24BIT_DVOBC 0x09
185#define DEVICE_CFG_24BIT_DVOCB 0x0a
186#define DEVICE_CFG_DUAL_DVOB 0x11
187#define DEVICE_CFG_DUAL_DVOC 0x12
188#define DEVICE_CFG_DUAL_DVOBC 0x13
189#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
190#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
191
192#define DEVICE_WIRE_NONE 0x00
193#define DEVICE_WIRE_DVOB 0x01
194#define DEVICE_WIRE_DVOC 0x02
195#define DEVICE_WIRE_DVOBC 0x03
196#define DEVICE_WIRE_DVOBB 0x05
197#define DEVICE_WIRE_DVOCC 0x06
198#define DEVICE_WIRE_DVOB_MASTER 0x0d
199#define DEVICE_WIRE_DVOC_MASTER 0x0e
200
201#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
202#define DEVICE_PORT_DVOB 0x01
203#define DEVICE_PORT_DVOC 0x02
204
205struct child_device_config {
206 u16 handle;
207 u16 device_type;
Adam Jackson46eb3032011-06-16 16:36:23 -0400208 u8 device_id[10]; /* ascii string */
yakui_zhao59a036c2009-05-31 17:16:22 +0800209 u16 addin_offset;
210 u8 dvo_port; /* See Device_PORT_* above */
211 u8 i2c_pin;
212 u8 slave_addr;
213 u8 ddc_pin;
214 u16 edid_ptr;
215 u8 dvo_cfg; /* See DEVICE_CFG_* above */
216 u8 dvo2_port;
217 u8 i2c2_pin;
218 u8 slave2_addr;
219 u8 ddc2_pin;
220 u8 capabilities;
221 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
222 u8 dvo2_wiring;
223 u16 extended_type;
224 u8 dvo_function;
225} __attribute__((packed));
226
Jesse Barnes79e53942008-11-07 14:24:08 -0800227struct bdb_general_definitions {
228 /* DDC GPIO */
229 u8 crt_ddc_gmbus_pin;
230
231 /* DPMS bits */
232 u8 dpms_acpi:1;
233 u8 skip_boot_crt_detect:1;
234 u8 dpms_aim:1;
235 u8 rsvd1:5; /* finish byte */
236
237 /* boot device bits */
238 u8 boot_display[2];
239 u8 child_dev_size;
240
yakui_zhao59a036c2009-05-31 17:16:22 +0800241 /*
242 * Device info:
243 * If TV is present, it'll be at devices[0].
244 * LVDS will be next, either devices[0] or [1], if present.
245 * On some platforms the number of device is 6. But could be as few as
246 * 4 if both TV and LVDS are missing.
247 * And the device num is related with the size of general definition
248 * block. It is obtained by using the following formula:
249 * number = (block_size - sizeof(bdb_general_definitions))/
Akshay Joshi0206e352011-08-16 15:34:10 -0400250 * sizeof(child_device_config);
yakui_zhao59a036c2009-05-31 17:16:22 +0800251 */
252 struct child_device_config devices[0];
253} __attribute__((packed));
Jesse Barnes79e53942008-11-07 14:24:08 -0800254
255struct bdb_lvds_options {
256 u8 panel_type;
257 u8 rsvd1;
258 /* LVDS capabilities, stored in a dword */
Jesse Barnes79e53942008-11-07 14:24:08 -0800259 u8 pfit_mode:2;
Li Peng2b5cde22009-03-13 10:25:07 +0800260 u8 pfit_text_mode_enhanced:1;
261 u8 pfit_gfx_mode_enhanced:1;
262 u8 pfit_ratio_auto:1;
263 u8 pixel_dither:1;
264 u8 lvds_edid:1;
265 u8 rsvd2:1;
Jesse Barnes79e53942008-11-07 14:24:08 -0800266 u8 rsvd4;
267} __attribute__((packed));
268
269/* LFP pointer table contains entries to the struct below */
270struct bdb_lvds_lfp_data_ptr {
271 u16 fp_timing_offset; /* offsets are from start of bdb */
272 u8 fp_table_size;
273 u16 dvo_timing_offset;
274 u8 dvo_table_size;
275 u16 panel_pnp_id_offset;
276 u8 pnp_table_size;
277} __attribute__((packed));
278
279struct bdb_lvds_lfp_data_ptrs {
280 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
281 struct bdb_lvds_lfp_data_ptr ptr[16];
282} __attribute__((packed));
283
284/* LFP data has 3 blocks per entry */
285struct lvds_fp_timing {
286 u16 x_res;
287 u16 y_res;
288 u32 lvds_reg;
289 u32 lvds_reg_val;
290 u32 pp_on_reg;
291 u32 pp_on_reg_val;
292 u32 pp_off_reg;
293 u32 pp_off_reg_val;
294 u32 pp_cycle_reg;
295 u32 pp_cycle_reg_val;
296 u32 pfit_reg;
297 u32 pfit_reg_val;
298 u16 terminator;
299} __attribute__((packed));
300
301struct lvds_dvo_timing {
302 u16 clock; /**< In 10khz */
303 u8 hactive_lo;
304 u8 hblank_lo;
305 u8 hblank_hi:4;
306 u8 hactive_hi:4;
307 u8 vactive_lo;
308 u8 vblank_lo;
309 u8 vblank_hi:4;
310 u8 vactive_hi:4;
311 u8 hsync_off_lo;
312 u8 hsync_pulse_width;
313 u8 vsync_pulse_width:4;
314 u8 vsync_off:4;
315 u8 rsvd0:6;
316 u8 hsync_off_hi:2;
317 u8 h_image;
318 u8 v_image;
319 u8 max_hv;
320 u8 h_border;
321 u8 v_border;
322 u8 rsvd1:3;
323 u8 digital:2;
324 u8 vsync_positive:1;
325 u8 hsync_positive:1;
326 u8 rsvd2:1;
327} __attribute__((packed));
328
329struct lvds_pnp_id {
330 u16 mfg_name;
331 u16 product_code;
332 u32 serial;
333 u8 mfg_week;
334 u8 mfg_year;
335} __attribute__((packed));
336
337struct bdb_lvds_lfp_data_entry {
338 struct lvds_fp_timing fp_timing;
339 struct lvds_dvo_timing dvo_timing;
340 struct lvds_pnp_id pnp_id;
341} __attribute__((packed));
342
343struct bdb_lvds_lfp_data {
344 struct bdb_lvds_lfp_data_entry data[16];
345} __attribute__((packed));
346
347struct aimdb_header {
348 char signature[16];
349 char oem_device[20];
350 u16 aimdb_version;
351 u16 aimdb_header_size;
352 u16 aimdb_size;
353} __attribute__((packed));
354
355struct aimdb_block {
356 u8 aimdb_id;
357 u16 aimdb_size;
358} __attribute__((packed));
359
360struct vch_panel_data {
361 u16 fp_timing_offset;
362 u8 fp_timing_size;
363 u16 dvo_timing_offset;
364 u8 dvo_timing_size;
365 u16 text_fitting_offset;
366 u8 text_fitting_size;
367 u16 graphics_fitting_offset;
368 u8 graphics_fitting_size;
369} __attribute__((packed));
370
371struct vch_bdb_22 {
372 struct aimdb_block aimdb_block;
373 struct vch_panel_data panels[16];
374} __attribute__((packed));
375
Ma Ling88631702009-05-13 11:19:55 +0800376struct bdb_sdvo_lvds_options {
377 u8 panel_backlight;
378 u8 h40_set_panel_type;
379 u8 panel_type;
380 u8 ssc_clk_freq;
381 u16 als_low_trip;
382 u16 als_high_trip;
383 u8 sclalarcoeff_tab_row_num;
384 u8 sclalarcoeff_tab_row_size;
385 u8 coefficient[8];
386 u8 panel_misc_bits_1;
387 u8 panel_misc_bits_2;
388 u8 panel_misc_bits_3;
389 u8 panel_misc_bits_4;
390} __attribute__((packed));
391
392
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800393#define BDB_DRIVER_FEATURE_NO_LVDS 0
394#define BDB_DRIVER_FEATURE_INT_LVDS 1
395#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
396#define BDB_DRIVER_FEATURE_EDP 3
397
398struct bdb_driver_features {
399 u8 boot_dev_algorithm:1;
400 u8 block_display_switch:1;
401 u8 allow_display_switch:1;
402 u8 hotplug_dvo:1;
403 u8 dual_view_zoom:1;
404 u8 int15h_hook:1;
405 u8 sprite_in_clone:1;
406 u8 primary_lfp_id:1;
407
408 u16 boot_mode_x;
409 u16 boot_mode_y;
410 u8 boot_mode_bpp;
411 u8 boot_mode_refresh;
412
413 u16 enable_lfp_primary:1;
414 u16 selective_mode_pruning:1;
415 u16 dual_frequency:1;
416 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
417 u16 nt_clone_support:1;
418 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
419 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
420 u16 cui_aspect_scaling:1;
421 u16 preserve_aspect_ratio:1;
422 u16 sdvo_device_power_down:1;
423 u16 crt_hotplug:1;
424 u16 lvds_config:2;
425 u16 tv_hotplug:1;
426 u16 hdmi_config:2;
427
428 u8 static_display:1;
429 u8 reserved2:7;
430 u16 legacy_crt_max_x;
431 u16 legacy_crt_max_y;
432 u8 legacy_crt_max_refresh;
433
434 u8 hdmi_termination;
435 u8 custom_vbt_version;
436} __attribute__((packed));
437
Zhenyu Wang500a8cc2010-01-13 11:19:52 +0800438#define EDP_18BPP 0
439#define EDP_24BPP 1
440#define EDP_30BPP 2
441#define EDP_RATE_1_62 0
442#define EDP_RATE_2_7 1
443#define EDP_LANE_1 0
444#define EDP_LANE_2 1
445#define EDP_LANE_4 3
446#define EDP_PREEMPHASIS_NONE 0
447#define EDP_PREEMPHASIS_3_5dB 1
448#define EDP_PREEMPHASIS_6dB 2
449#define EDP_PREEMPHASIS_9_5dB 3
450#define EDP_VSWING_0_4V 0
451#define EDP_VSWING_0_6V 1
452#define EDP_VSWING_0_8V 2
453#define EDP_VSWING_1_2V 3
454
455struct edp_power_seq {
Keith Packardf01eca22011-09-28 16:48:10 -0700456 u16 t1_t3;
457 u16 t8;
Zhenyu Wang500a8cc2010-01-13 11:19:52 +0800458 u16 t9;
459 u16 t10;
Keith Packardf01eca22011-09-28 16:48:10 -0700460 u16 t11_t12;
Zhenyu Wang500a8cc2010-01-13 11:19:52 +0800461} __attribute__ ((packed));
462
463struct edp_link_params {
464 u8 rate:4;
465 u8 lanes:4;
466 u8 preemphasis:4;
467 u8 vswing:4;
468} __attribute__ ((packed));
469
470struct bdb_edp {
471 struct edp_power_seq power_seqs[16];
472 u32 color_depth;
Zhenyu Wang500a8cc2010-01-13 11:19:52 +0800473 struct edp_link_params link_params[16];
Rohit Jain96c0a2f2012-01-12 12:19:44 +0530474 u32 sdrrs_msa_timing_delay;
475
476 /* ith bit indicates enabled/disabled for (i+1)th panel */
477 u16 edp_s3d_feature;
478 u16 edp_t3_optimization;
Zhenyu Wang500a8cc2010-01-13 11:19:52 +0800479} __attribute__ ((packed));
480
Bryan Freed6d139a82010-10-14 09:14:51 +0100481void intel_setup_bios(struct drm_device *dev);
Dan Carpenter0317c6c2012-06-27 12:10:30 +0300482int intel_parse_bios(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800483
484/*
485 * Driver<->VBIOS interaction occurs through scratch bits in
486 * GR18 & SWF*.
487 */
488
489/* GR18 bits are set on display switch and hotkey events */
490#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
491#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
492#define GR18_HK_NONE (0x0<<3)
493#define GR18_HK_LFP_STRETCH (0x1<<3)
494#define GR18_HK_TOGGLE_DISP (0x2<<3)
495#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
496#define GR18_HK_POPUP_DISABLED (0x6<<3)
497#define GR18_HK_POPUP_ENABLED (0x7<<3)
498#define GR18_HK_PFIT (0x8<<3)
499#define GR18_HK_APM_CHANGE (0xa<<3)
500#define GR18_HK_MULTIPLE (0xc<<3)
501#define GR18_USER_INT_EN (1<<2)
502#define GR18_A0000_FLUSH_EN (1<<1)
503#define GR18_SMM_EN (1<<0)
504
505/* Set by driver, cleared by VBIOS */
506#define SWF00_YRES_SHIFT 16
507#define SWF00_XRES_SHIFT 0
508#define SWF00_RES_MASK 0xffff
509
510/* Set by VBIOS at boot time and driver at runtime */
511#define SWF01_TV2_FORMAT_SHIFT 8
512#define SWF01_TV1_FORMAT_SHIFT 0
513#define SWF01_TV_FORMAT_MASK 0xffff
514
515#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
516#define SWF10_GTT_OVERRIDE_EN (1<<28)
517#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
518#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
519#define SWF10_OLD_TOGGLE 0x0
520#define SWF10_TOGGLE_LIST_1 0x1
521#define SWF10_TOGGLE_LIST_2 0x2
522#define SWF10_TOGGLE_LIST_3 0x3
523#define SWF10_TOGGLE_LIST_4 0x4
524#define SWF10_PANNING_EN (1<<23)
525#define SWF10_DRIVER_LOADED (1<<22)
526#define SWF10_EXTENDED_DESKTOP (1<<21)
527#define SWF10_EXCLUSIVE_MODE (1<<20)
528#define SWF10_OVERLAY_EN (1<<19)
529#define SWF10_PLANEB_HOLDOFF (1<<18)
530#define SWF10_PLANEA_HOLDOFF (1<<17)
531#define SWF10_VGA_HOLDOFF (1<<16)
532#define SWF10_ACTIVE_DISP_MASK 0xffff
533#define SWF10_PIPEB_LFP2 (1<<15)
534#define SWF10_PIPEB_EFP2 (1<<14)
535#define SWF10_PIPEB_TV2 (1<<13)
536#define SWF10_PIPEB_CRT2 (1<<12)
537#define SWF10_PIPEB_LFP (1<<11)
538#define SWF10_PIPEB_EFP (1<<10)
539#define SWF10_PIPEB_TV (1<<9)
540#define SWF10_PIPEB_CRT (1<<8)
541#define SWF10_PIPEA_LFP2 (1<<7)
542#define SWF10_PIPEA_EFP2 (1<<6)
543#define SWF10_PIPEA_TV2 (1<<5)
544#define SWF10_PIPEA_CRT2 (1<<4)
545#define SWF10_PIPEA_LFP (1<<3)
546#define SWF10_PIPEA_EFP (1<<2)
547#define SWF10_PIPEA_TV (1<<1)
548#define SWF10_PIPEA_CRT (1<<0)
549
550#define SWF11_MEMORY_SIZE_SHIFT 16
551#define SWF11_SV_TEST_EN (1<<15)
552#define SWF11_IS_AGP (1<<14)
553#define SWF11_DISPLAY_HOLDOFF (1<<13)
554#define SWF11_DPMS_REDUCED (1<<12)
555#define SWF11_IS_VBE_MODE (1<<11)
556#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
557#define SWF11_DPMS_MASK 0x07
558#define SWF11_DPMS_OFF (1<<2)
559#define SWF11_DPMS_SUSPEND (1<<1)
560#define SWF11_DPMS_STANDBY (1<<0)
561#define SWF11_DPMS_ON 0
562
563#define SWF14_GFX_PFIT_EN (1<<31)
564#define SWF14_TEXT_PFIT_EN (1<<30)
565#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
566#define SWF14_POPUP_EN (1<<28)
567#define SWF14_DISPLAY_HOLDOFF (1<<27)
568#define SWF14_DISP_DETECT_EN (1<<26)
569#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
570#define SWF14_DRIVER_STATUS (1<<24)
571#define SWF14_OS_TYPE_WIN9X (1<<23)
572#define SWF14_OS_TYPE_WINNT (1<<22)
573/* 21:19 rsvd */
574#define SWF14_PM_TYPE_MASK 0x00070000
575#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
576#define SWF14_PM_ACPI (0x3 << 16)
577#define SWF14_PM_APM_12 (0x2 << 16)
578#define SWF14_PM_APM_11 (0x1 << 16)
579#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
580 /* if GR18 indicates a display switch */
581#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
582#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
583#define SWF14_DS_PIPEB_TV2_EN (1<<13)
584#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
585#define SWF14_DS_PIPEB_LFP_EN (1<<11)
586#define SWF14_DS_PIPEB_EFP_EN (1<<10)
587#define SWF14_DS_PIPEB_TV_EN (1<<9)
588#define SWF14_DS_PIPEB_CRT_EN (1<<8)
589#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
590#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
591#define SWF14_DS_PIPEA_TV2_EN (1<<5)
592#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
593#define SWF14_DS_PIPEA_LFP_EN (1<<3)
594#define SWF14_DS_PIPEA_EFP_EN (1<<2)
595#define SWF14_DS_PIPEA_TV_EN (1<<1)
596#define SWF14_DS_PIPEA_CRT_EN (1<<0)
597 /* if GR18 indicates a panel fitting request */
598#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
599 /* if GR18 indicates an APM change request */
600#define SWF14_APM_HIBERNATE 0x4
601#define SWF14_APM_SUSPEND 0x3
602#define SWF14_APM_STANDBY 0x1
603#define SWF14_APM_RESTORE 0x0
604
Zhao Yakui6363ee62009-11-24 09:48:44 +0800605/* Add the device class for LFP, TV, HDMI */
606#define DEVICE_TYPE_INT_LFP 0x1022
607#define DEVICE_TYPE_INT_TV 0x1009
608#define DEVICE_TYPE_HDMI 0x60D2
609#define DEVICE_TYPE_DP 0x68C6
610#define DEVICE_TYPE_eDP 0x78C6
611
612/* define the DVO port for HDMI output type */
613#define DVO_B 1
614#define DVO_C 2
615#define DVO_D 3
616
617/* define the PORT for DP output type */
618#define PORT_IDPB 7
619#define PORT_IDPC 8
620#define PORT_IDPD 9
621
Shobhit Kumard17c5442013-08-27 15:12:25 +0300622/* MIPI DSI panel info */
623struct bdb_mipi {
624 u16 panel_id;
625 u16 bridge_revision;
626
627 /* General params */
628 u32 dithering:1;
629 u32 bpp_pixel_format:1;
630 u32 rsvd1:1;
631 u32 dphy_valid:1;
632 u32 resvd2:28;
633
634 u16 port_info;
635 u16 rsvd3:2;
636 u16 num_lanes:2;
637 u16 rsvd4:12;
638
639 /* DSI config */
640 u16 virt_ch_num:2;
641 u16 vtm:2;
642 u16 rsvd5:12;
643
644 u32 dsi_clock;
645 u32 bridge_ref_clk;
646 u16 rsvd_pwr;
647
648 /* Dphy Params */
649 u32 prepare_cnt:5;
650 u32 rsvd6:3;
651 u32 clk_zero_cnt:8;
652 u32 trail_cnt:5;
653 u32 rsvd7:3;
654 u32 exit_zero_cnt:6;
655 u32 rsvd8:2;
656
657 u32 hl_switch_cnt;
658 u32 lp_byte_clk;
659 u32 clk_lane_switch_cnt;
660} __attribute__((packed));
661
Jesse Barnes79e53942008-11-07 14:24:08 -0800662#endif /* _I830_BIOS_H_ */