Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OHCI HCD (Host Controller Driver) for USB. |
| 3 | * |
| 4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
| 5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> |
| 6 | * |
| 7 | * [ Initialisation is based on Linus' ] |
| 8 | * [ uhci code and gregs ohci fragments ] |
| 9 | * [ (C) Copyright 1999 Linus Torvalds ] |
| 10 | * [ (C) Copyright 1999 Gregory P. Smith] |
| 11 | * |
| 12 | * |
| 13 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
| 14 | * interfaces (though some non-x86 Intel chips use it). It supports |
| 15 | * smarter hardware than UHCI. A download link for the spec available |
| 16 | * through the http://www.usb.org website. |
| 17 | * |
| 18 | * History: |
| 19 | * |
| 20 | * 2004/03/24 LH7A404 support (Durgesh Pattamatta & Marc Singer) |
| 21 | * 2004/02/04 use generic dma_* functions instead of pci_* (dsaxena@plexity.net) |
| 22 | * 2003/02/24 show registers in sysfs (Kevin Brosius) |
| 23 | * |
| 24 | * 2002/09/03 get rid of ed hashtables, rework periodic scheduling and |
| 25 | * bandwidth accounting; if debugging, show schedules in driverfs |
| 26 | * 2002/07/19 fixes to management of ED and schedule state. |
| 27 | * 2002/06/09 SA-1111 support (Christopher Hoover) |
| 28 | * 2002/06/01 remember frame when HC won't see EDs any more; use that info |
| 29 | * to fix urb unlink races caused by interrupt latency assumptions; |
| 30 | * minor ED field and function naming updates |
| 31 | * 2002/01/18 package as a patch for 2.5.3; this should match the |
| 32 | * 2.4.17 kernel modulo some bugs being fixed. |
| 33 | * |
| 34 | * 2001/10/18 merge pmac cleanup (Benjamin Herrenschmidt) and bugfixes |
| 35 | * from post-2.4.5 patches. |
| 36 | * 2001/09/20 URB_ZERO_PACKET support; hcca_dma portability, OPTi warning |
| 37 | * 2001/09/07 match PCI PM changes, errnos from Linus' tree |
| 38 | * 2001/05/05 fork 2.4.5 version into "hcd" framework, cleanup, simplify; |
| 39 | * pbook pci quirks gone (please fix pbook pci sw!) (db) |
| 40 | * |
| 41 | * 2001/04/08 Identify version on module load (gb) |
| 42 | * 2001/03/24 td/ed hashing to remove bus_to_virt (Steve Longerbeam); |
| 43 | pci_map_single (db) |
| 44 | * 2001/03/21 td and dev/ed allocation uses new pci_pool API (db) |
| 45 | * 2001/03/07 hcca allocation uses pci_alloc_consistent (Steve Longerbeam) |
| 46 | * |
| 47 | * 2000/09/26 fixed races in removing the private portion of the urb |
| 48 | * 2000/09/07 disable bulk and control lists when unlinking the last |
| 49 | * endpoint descriptor in order to avoid unrecoverable errors on |
| 50 | * the Lucent chips. (rwc@sgi) |
| 51 | * 2000/08/29 use bandwidth claiming hooks (thanks Randy!), fix some |
| 52 | * urb unlink probs, indentation fixes |
| 53 | * 2000/08/11 various oops fixes mostly affecting iso and cleanup from |
| 54 | * device unplugs. |
| 55 | * 2000/06/28 use PCI hotplug framework, for better power management |
| 56 | * and for Cardbus support (David Brownell) |
| 57 | * 2000/earlier: fixes for NEC/Lucent chips; suspend/resume handling |
| 58 | * when the controller loses power; handle UE; cleanup; ... |
| 59 | * |
| 60 | * v5.2 1999/12/07 URB 3rd preview, |
| 61 | * v5.1 1999/11/30 URB 2nd preview, cpia, (usb-scsi) |
| 62 | * v5.0 1999/11/22 URB Technical preview, Paul Mackerras powerbook susp/resume |
| 63 | * i386: HUB, Keyboard, Mouse, Printer |
| 64 | * |
| 65 | * v4.3 1999/10/27 multiple HCs, bulk_request |
| 66 | * v4.2 1999/09/05 ISO API alpha, new dev alloc, neg Error-codes |
| 67 | * v4.1 1999/08/27 Randy Dunlap's - ISO API first impl. |
| 68 | * v4.0 1999/08/18 |
| 69 | * v3.0 1999/06/25 |
| 70 | * v2.1 1999/05/09 code clean up |
| 71 | * v2.0 1999/05/04 |
| 72 | * v1.0 1999/04/27 initial release |
| 73 | * |
| 74 | * This file is licenced under the GPL. |
| 75 | */ |
| 76 | |
| 77 | #include <linux/config.h> |
| 78 | |
| 79 | #ifdef CONFIG_USB_DEBUG |
| 80 | # define DEBUG |
| 81 | #else |
| 82 | # undef DEBUG |
| 83 | #endif |
| 84 | |
| 85 | #include <linux/module.h> |
| 86 | #include <linux/moduleparam.h> |
| 87 | #include <linux/pci.h> |
| 88 | #include <linux/kernel.h> |
| 89 | #include <linux/delay.h> |
| 90 | #include <linux/ioport.h> |
| 91 | #include <linux/sched.h> |
| 92 | #include <linux/slab.h> |
| 93 | #include <linux/smp_lock.h> |
| 94 | #include <linux/errno.h> |
| 95 | #include <linux/init.h> |
| 96 | #include <linux/timer.h> |
| 97 | #include <linux/list.h> |
| 98 | #include <linux/interrupt.h> /* for in_interrupt () */ |
| 99 | #include <linux/usb.h> |
| 100 | #include <linux/usb_otg.h> |
| 101 | #include "../core/hcd.h" |
| 102 | #include <linux/dma-mapping.h> |
| 103 | #include <linux/dmapool.h> /* needed by ohci-mem.c when no PCI */ |
| 104 | |
| 105 | #include <asm/io.h> |
| 106 | #include <asm/irq.h> |
| 107 | #include <asm/system.h> |
| 108 | #include <asm/unaligned.h> |
| 109 | #include <asm/byteorder.h> |
| 110 | |
| 111 | |
| 112 | #define DRIVER_VERSION "2004 Nov 08" |
| 113 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
| 114 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" |
| 115 | |
| 116 | /*-------------------------------------------------------------------------*/ |
| 117 | |
| 118 | // #define OHCI_VERBOSE_DEBUG /* not always helpful */ |
| 119 | |
| 120 | /* For initializing controller (mask in an HCFS mode too) */ |
| 121 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
| 122 | #define OHCI_INTR_INIT \ |
| 123 | (OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_RD | OHCI_INTR_WDH) |
| 124 | |
| 125 | #ifdef __hppa__ |
| 126 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ |
| 127 | #define IR_DISABLE |
| 128 | #endif |
| 129 | |
| 130 | #ifdef CONFIG_ARCH_OMAP |
| 131 | /* OMAP doesn't support IR (no SMM; not needed) */ |
| 132 | #define IR_DISABLE |
| 133 | #endif |
| 134 | |
| 135 | /*-------------------------------------------------------------------------*/ |
| 136 | |
| 137 | static const char hcd_name [] = "ohci_hcd"; |
| 138 | |
| 139 | #include "ohci.h" |
| 140 | |
| 141 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); |
| 142 | static int ohci_init (struct ohci_hcd *ohci); |
| 143 | static void ohci_stop (struct usb_hcd *hcd); |
| 144 | |
| 145 | #include "ohci-hub.c" |
| 146 | #include "ohci-dbg.c" |
| 147 | #include "ohci-mem.c" |
| 148 | #include "ohci-q.c" |
| 149 | |
| 150 | |
| 151 | /* |
| 152 | * On architectures with edge-triggered interrupts we must never return |
| 153 | * IRQ_NONE. |
| 154 | */ |
| 155 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ |
| 156 | #define IRQ_NOTMINE IRQ_HANDLED |
| 157 | #else |
| 158 | #define IRQ_NOTMINE IRQ_NONE |
| 159 | #endif |
| 160 | |
| 161 | |
| 162 | /* Some boards misreport power switching/overcurrent */ |
| 163 | static int distrust_firmware = 1; |
| 164 | module_param (distrust_firmware, bool, 0); |
| 165 | MODULE_PARM_DESC (distrust_firmware, |
| 166 | "true to distrust firmware power/overcurrent setup"); |
| 167 | |
| 168 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ |
| 169 | static int no_handshake = 0; |
| 170 | module_param (no_handshake, bool, 0); |
| 171 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); |
| 172 | |
| 173 | /*-------------------------------------------------------------------------*/ |
| 174 | |
| 175 | /* |
| 176 | * queue up an urb for anything except the root hub |
| 177 | */ |
| 178 | static int ohci_urb_enqueue ( |
| 179 | struct usb_hcd *hcd, |
| 180 | struct usb_host_endpoint *ep, |
| 181 | struct urb *urb, |
| 182 | int mem_flags |
| 183 | ) { |
| 184 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
| 185 | struct ed *ed; |
| 186 | urb_priv_t *urb_priv; |
| 187 | unsigned int pipe = urb->pipe; |
| 188 | int i, size = 0; |
| 189 | unsigned long flags; |
| 190 | int retval = 0; |
| 191 | |
| 192 | #ifdef OHCI_VERBOSE_DEBUG |
| 193 | urb_print (urb, "SUB", usb_pipein (pipe)); |
| 194 | #endif |
| 195 | |
| 196 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
| 197 | if (! (ed = ed_get (ohci, ep, urb->dev, pipe, urb->interval))) |
| 198 | return -ENOMEM; |
| 199 | |
| 200 | /* for the private part of the URB we need the number of TDs (size) */ |
| 201 | switch (ed->type) { |
| 202 | case PIPE_CONTROL: |
| 203 | /* td_submit_urb() doesn't yet handle these */ |
| 204 | if (urb->transfer_buffer_length > 4096) |
| 205 | return -EMSGSIZE; |
| 206 | |
| 207 | /* 1 TD for setup, 1 for ACK, plus ... */ |
| 208 | size = 2; |
| 209 | /* FALLTHROUGH */ |
| 210 | // case PIPE_INTERRUPT: |
| 211 | // case PIPE_BULK: |
| 212 | default: |
| 213 | /* one TD for every 4096 Bytes (can be upto 8K) */ |
| 214 | size += urb->transfer_buffer_length / 4096; |
| 215 | /* ... and for any remaining bytes ... */ |
| 216 | if ((urb->transfer_buffer_length % 4096) != 0) |
| 217 | size++; |
| 218 | /* ... and maybe a zero length packet to wrap it up */ |
| 219 | if (size == 0) |
| 220 | size++; |
| 221 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 |
| 222 | && (urb->transfer_buffer_length |
| 223 | % usb_maxpacket (urb->dev, pipe, |
| 224 | usb_pipeout (pipe))) == 0) |
| 225 | size++; |
| 226 | break; |
| 227 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ |
| 228 | size = urb->number_of_packets; |
| 229 | break; |
| 230 | } |
| 231 | |
| 232 | /* allocate the private part of the URB */ |
| 233 | urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), |
| 234 | mem_flags); |
| 235 | if (!urb_priv) |
| 236 | return -ENOMEM; |
| 237 | memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (struct td *)); |
| 238 | INIT_LIST_HEAD (&urb_priv->pending); |
| 239 | urb_priv->length = size; |
| 240 | urb_priv->ed = ed; |
| 241 | |
| 242 | /* allocate the TDs (deferring hash chain updates) */ |
| 243 | for (i = 0; i < size; i++) { |
| 244 | urb_priv->td [i] = td_alloc (ohci, mem_flags); |
| 245 | if (!urb_priv->td [i]) { |
| 246 | urb_priv->length = i; |
| 247 | urb_free_priv (ohci, urb_priv); |
| 248 | return -ENOMEM; |
| 249 | } |
| 250 | } |
| 251 | |
| 252 | spin_lock_irqsave (&ohci->lock, flags); |
| 253 | |
| 254 | /* don't submit to a dead HC */ |
| 255 | if (!HC_IS_RUNNING(hcd->state)) { |
| 256 | retval = -ENODEV; |
| 257 | goto fail; |
| 258 | } |
| 259 | |
| 260 | /* in case of unlink-during-submit */ |
| 261 | spin_lock (&urb->lock); |
| 262 | if (urb->status != -EINPROGRESS) { |
| 263 | spin_unlock (&urb->lock); |
| 264 | urb->hcpriv = urb_priv; |
| 265 | finish_urb (ohci, urb, NULL); |
| 266 | retval = 0; |
| 267 | goto fail; |
| 268 | } |
| 269 | |
| 270 | /* schedule the ed if needed */ |
| 271 | if (ed->state == ED_IDLE) { |
| 272 | retval = ed_schedule (ohci, ed); |
| 273 | if (retval < 0) |
| 274 | goto fail0; |
| 275 | if (ed->type == PIPE_ISOCHRONOUS) { |
| 276 | u16 frame = ohci_frame_no(ohci); |
| 277 | |
| 278 | /* delay a few frames before the first TD */ |
| 279 | frame += max_t (u16, 8, ed->interval); |
| 280 | frame &= ~(ed->interval - 1); |
| 281 | frame |= ed->branch; |
| 282 | urb->start_frame = frame; |
| 283 | |
| 284 | /* yes, only URB_ISO_ASAP is supported, and |
| 285 | * urb->start_frame is never used as input. |
| 286 | */ |
| 287 | } |
| 288 | } else if (ed->type == PIPE_ISOCHRONOUS) |
| 289 | urb->start_frame = ed->last_iso + ed->interval; |
| 290 | |
| 291 | /* fill the TDs and link them to the ed; and |
| 292 | * enable that part of the schedule, if needed |
| 293 | * and update count of queued periodic urbs |
| 294 | */ |
| 295 | urb->hcpriv = urb_priv; |
| 296 | td_submit_urb (ohci, urb); |
| 297 | |
| 298 | fail0: |
| 299 | spin_unlock (&urb->lock); |
| 300 | fail: |
| 301 | if (retval) |
| 302 | urb_free_priv (ohci, urb_priv); |
| 303 | spin_unlock_irqrestore (&ohci->lock, flags); |
| 304 | return retval; |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * decouple the URB from the HC queues (TDs, urb_priv); it's |
| 309 | * already marked using urb->status. reporting is always done |
| 310 | * asynchronously, and we might be dealing with an urb that's |
| 311 | * partially transferred, or an ED with other urbs being unlinked. |
| 312 | */ |
| 313 | static int ohci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) |
| 314 | { |
| 315 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
| 316 | unsigned long flags; |
| 317 | |
| 318 | #ifdef OHCI_VERBOSE_DEBUG |
| 319 | urb_print (urb, "UNLINK", 1); |
| 320 | #endif |
| 321 | |
| 322 | spin_lock_irqsave (&ohci->lock, flags); |
| 323 | if (HC_IS_RUNNING(hcd->state)) { |
| 324 | urb_priv_t *urb_priv; |
| 325 | |
| 326 | /* Unless an IRQ completed the unlink while it was being |
| 327 | * handed to us, flag it for unlink and giveback, and force |
| 328 | * some upcoming INTR_SF to call finish_unlinks() |
| 329 | */ |
| 330 | urb_priv = urb->hcpriv; |
| 331 | if (urb_priv) { |
| 332 | if (urb_priv->ed->state == ED_OPER) |
| 333 | start_ed_unlink (ohci, urb_priv->ed); |
| 334 | } |
| 335 | } else { |
| 336 | /* |
| 337 | * with HC dead, we won't respect hc queue pointers |
| 338 | * any more ... just clean up every urb's memory. |
| 339 | */ |
| 340 | if (urb->hcpriv) |
| 341 | finish_urb (ohci, urb, NULL); |
| 342 | } |
| 343 | spin_unlock_irqrestore (&ohci->lock, flags); |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | /*-------------------------------------------------------------------------*/ |
| 348 | |
| 349 | /* frees config/altsetting state for endpoints, |
| 350 | * including ED memory, dummy TD, and bulk/intr data toggle |
| 351 | */ |
| 352 | |
| 353 | static void |
| 354 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) |
| 355 | { |
| 356 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
| 357 | unsigned long flags; |
| 358 | struct ed *ed = ep->hcpriv; |
| 359 | unsigned limit = 1000; |
| 360 | |
| 361 | /* ASSERT: any requests/urbs are being unlinked */ |
| 362 | /* ASSERT: nobody can be submitting urbs for this any more */ |
| 363 | |
| 364 | if (!ed) |
| 365 | return; |
| 366 | |
| 367 | rescan: |
| 368 | spin_lock_irqsave (&ohci->lock, flags); |
| 369 | |
| 370 | if (!HC_IS_RUNNING (hcd->state)) { |
| 371 | sanitize: |
| 372 | ed->state = ED_IDLE; |
| 373 | finish_unlinks (ohci, 0, NULL); |
| 374 | } |
| 375 | |
| 376 | switch (ed->state) { |
| 377 | case ED_UNLINK: /* wait for hw to finish? */ |
| 378 | /* major IRQ delivery trouble loses INTR_SF too... */ |
| 379 | if (limit-- == 0) { |
| 380 | ohci_warn (ohci, "IRQ INTR_SF lossage\n"); |
| 381 | goto sanitize; |
| 382 | } |
| 383 | spin_unlock_irqrestore (&ohci->lock, flags); |
| 384 | set_current_state (TASK_UNINTERRUPTIBLE); |
| 385 | schedule_timeout (1); |
| 386 | goto rescan; |
| 387 | case ED_IDLE: /* fully unlinked */ |
| 388 | if (list_empty (&ed->td_list)) { |
| 389 | td_free (ohci, ed->dummy); |
| 390 | ed_free (ohci, ed); |
| 391 | break; |
| 392 | } |
| 393 | /* else FALL THROUGH */ |
| 394 | default: |
| 395 | /* caller was supposed to have unlinked any requests; |
| 396 | * that's not our job. can't recover; must leak ed. |
| 397 | */ |
| 398 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", |
| 399 | ed, ep->desc.bEndpointAddress, ed->state, |
| 400 | list_empty (&ed->td_list) ? "" : " (has tds)"); |
| 401 | td_free (ohci, ed->dummy); |
| 402 | break; |
| 403 | } |
| 404 | ep->hcpriv = NULL; |
| 405 | spin_unlock_irqrestore (&ohci->lock, flags); |
| 406 | return; |
| 407 | } |
| 408 | |
| 409 | static int ohci_get_frame (struct usb_hcd *hcd) |
| 410 | { |
| 411 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
| 412 | |
| 413 | return ohci_frame_no(ohci); |
| 414 | } |
| 415 | |
| 416 | static void ohci_usb_reset (struct ohci_hcd *ohci) |
| 417 | { |
| 418 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); |
| 419 | ohci->hc_control &= OHCI_CTRL_RWC; |
| 420 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); |
| 421 | } |
| 422 | |
| 423 | /*-------------------------------------------------------------------------* |
| 424 | * HC functions |
| 425 | *-------------------------------------------------------------------------*/ |
| 426 | |
| 427 | /* init memory, and kick BIOS/SMM off */ |
| 428 | |
| 429 | static int ohci_init (struct ohci_hcd *ohci) |
| 430 | { |
| 431 | int ret; |
| 432 | |
| 433 | disable (ohci); |
| 434 | ohci->regs = ohci_to_hcd(ohci)->regs; |
| 435 | ohci->next_statechange = jiffies; |
| 436 | |
| 437 | #ifndef IR_DISABLE |
| 438 | /* SMM owns the HC? not for long! */ |
| 439 | if (!no_handshake && ohci_readl (ohci, |
| 440 | &ohci->regs->control) & OHCI_CTRL_IR) { |
| 441 | u32 temp; |
| 442 | |
| 443 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); |
| 444 | |
| 445 | /* this timeout is arbitrary. we make it long, so systems |
| 446 | * depending on usb keyboards may be usable even if the |
| 447 | * BIOS/SMM code seems pretty broken. |
| 448 | */ |
| 449 | temp = 500; /* arbitrary: five seconds */ |
| 450 | |
| 451 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); |
| 452 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); |
| 453 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { |
| 454 | msleep (10); |
| 455 | if (--temp == 0) { |
| 456 | ohci_err (ohci, "USB HC takeover failed!" |
| 457 | " (BIOS/SMM bug)\n"); |
| 458 | return -EBUSY; |
| 459 | } |
| 460 | } |
| 461 | ohci_usb_reset (ohci); |
| 462 | } |
| 463 | #endif |
| 464 | |
| 465 | /* Disable HC interrupts */ |
| 466 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
| 467 | // flush the writes |
| 468 | (void) ohci_readl (ohci, &ohci->regs->control); |
| 469 | |
| 470 | if (ohci->hcca) |
| 471 | return 0; |
| 472 | |
| 473 | ohci->hcca = dma_alloc_coherent (ohci_to_hcd(ohci)->self.controller, |
| 474 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
| 475 | if (!ohci->hcca) |
| 476 | return -ENOMEM; |
| 477 | |
| 478 | if ((ret = ohci_mem_init (ohci)) < 0) |
| 479 | ohci_stop (ohci_to_hcd(ohci)); |
| 480 | |
| 481 | return ret; |
| 482 | |
| 483 | } |
| 484 | |
| 485 | /*-------------------------------------------------------------------------*/ |
| 486 | |
| 487 | /* Start an OHCI controller, set the BUS operational |
| 488 | * resets USB and controller |
| 489 | * enable interrupts |
| 490 | * connect the virtual root hub |
| 491 | */ |
| 492 | static int ohci_run (struct ohci_hcd *ohci) |
| 493 | { |
| 494 | u32 mask, temp; |
| 495 | struct usb_device *udev; |
| 496 | struct usb_bus *bus; |
| 497 | int first = ohci->fminterval == 0; |
| 498 | |
| 499 | disable (ohci); |
| 500 | |
| 501 | /* boot firmware should have set this up (5.1.1.3.1) */ |
| 502 | if (first) { |
| 503 | |
| 504 | temp = ohci_readl (ohci, &ohci->regs->fminterval); |
| 505 | ohci->fminterval = temp & 0x3fff; |
| 506 | if (ohci->fminterval != FI) |
| 507 | ohci_dbg (ohci, "fminterval delta %d\n", |
| 508 | ohci->fminterval - FI); |
| 509 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; |
| 510 | /* also: power/overcurrent flags in roothub.a */ |
| 511 | } |
| 512 | |
| 513 | /* Reset USB nearly "by the book". RemoteWakeupConnected |
| 514 | * saved if boot firmware (BIOS/SMM/...) told us it's connected |
| 515 | * (for OHCI integrated on mainboard, it normally is) |
| 516 | */ |
| 517 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); |
| 518 | ohci_dbg (ohci, "resetting from state '%s', control = 0x%x\n", |
| 519 | hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS), |
| 520 | ohci->hc_control); |
| 521 | |
| 522 | if (ohci->hc_control & OHCI_CTRL_RWC |
| 523 | && !(ohci->flags & OHCI_QUIRK_AMD756)) |
| 524 | ohci_to_hcd(ohci)->can_wakeup = 1; |
| 525 | |
| 526 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { |
| 527 | case OHCI_USB_OPER: |
| 528 | temp = 0; |
| 529 | break; |
| 530 | case OHCI_USB_SUSPEND: |
| 531 | case OHCI_USB_RESUME: |
| 532 | ohci->hc_control &= OHCI_CTRL_RWC; |
| 533 | ohci->hc_control |= OHCI_USB_RESUME; |
| 534 | temp = 10 /* msec wait */; |
| 535 | break; |
| 536 | // case OHCI_USB_RESET: |
| 537 | default: |
| 538 | ohci->hc_control &= OHCI_CTRL_RWC; |
| 539 | ohci->hc_control |= OHCI_USB_RESET; |
| 540 | temp = 50 /* msec wait */; |
| 541 | break; |
| 542 | } |
| 543 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); |
| 544 | // flush the writes |
| 545 | (void) ohci_readl (ohci, &ohci->regs->control); |
| 546 | msleep(temp); |
| 547 | temp = roothub_a (ohci); |
| 548 | if (!(temp & RH_A_NPS)) { |
| 549 | unsigned ports = temp & RH_A_NDP; |
| 550 | |
| 551 | /* power down each port */ |
| 552 | for (temp = 0; temp < ports; temp++) |
| 553 | ohci_writel (ohci, RH_PS_LSDA, |
| 554 | &ohci->regs->roothub.portstatus [temp]); |
| 555 | } |
| 556 | // flush those writes |
| 557 | (void) ohci_readl (ohci, &ohci->regs->control); |
| 558 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); |
| 559 | |
| 560 | /* 2msec timelimit here means no irqs/preempt */ |
| 561 | spin_lock_irq (&ohci->lock); |
| 562 | |
| 563 | retry: |
| 564 | /* HC Reset requires max 10 us delay */ |
| 565 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); |
| 566 | temp = 30; /* ... allow extra time */ |
| 567 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { |
| 568 | if (--temp == 0) { |
| 569 | spin_unlock_irq (&ohci->lock); |
| 570 | ohci_err (ohci, "USB HC reset timed out!\n"); |
| 571 | return -1; |
| 572 | } |
| 573 | udelay (1); |
| 574 | } |
| 575 | |
| 576 | /* now we're in the SUSPEND state ... must go OPERATIONAL |
| 577 | * within 2msec else HC enters RESUME |
| 578 | * |
| 579 | * ... but some hardware won't init fmInterval "by the book" |
| 580 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need |
| 581 | * this if we write fmInterval after we're OPERATIONAL. |
| 582 | * Unclear about ALi, ServerWorks, and others ... this could |
| 583 | * easily be a longstanding bug in chip init on Linux. |
| 584 | */ |
| 585 | if (ohci->flags & OHCI_QUIRK_INITRESET) { |
| 586 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); |
| 587 | // flush those writes |
| 588 | (void) ohci_readl (ohci, &ohci->regs->control); |
| 589 | } |
| 590 | |
| 591 | /* Tell the controller where the control and bulk lists are |
| 592 | * The lists are empty now. */ |
| 593 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); |
| 594 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); |
| 595 | |
| 596 | /* a reset clears this */ |
| 597 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); |
| 598 | |
| 599 | periodic_reinit (ohci); |
| 600 | |
| 601 | /* some OHCI implementations are finicky about how they init. |
| 602 | * bogus values here mean not even enumeration could work. |
| 603 | */ |
| 604 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 |
| 605 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { |
| 606 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { |
| 607 | ohci->flags |= OHCI_QUIRK_INITRESET; |
| 608 | ohci_dbg (ohci, "enabling initreset quirk\n"); |
| 609 | goto retry; |
| 610 | } |
| 611 | spin_unlock_irq (&ohci->lock); |
| 612 | ohci_err (ohci, "init err (%08x %04x)\n", |
| 613 | ohci_readl (ohci, &ohci->regs->fminterval), |
| 614 | ohci_readl (ohci, &ohci->regs->periodicstart)); |
| 615 | return -EOVERFLOW; |
| 616 | } |
| 617 | |
| 618 | /* start controller operations */ |
| 619 | ohci->hc_control &= OHCI_CTRL_RWC; |
| 620 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
| 621 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); |
| 622 | ohci_to_hcd(ohci)->state = HC_STATE_RUNNING; |
| 623 | |
| 624 | /* wake on ConnectStatusChange, matching external hubs */ |
| 625 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); |
| 626 | |
| 627 | /* Choose the interrupts we care about now, others later on demand */ |
| 628 | mask = OHCI_INTR_INIT; |
| 629 | ohci_writel (ohci, mask, &ohci->regs->intrstatus); |
| 630 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
| 631 | |
| 632 | /* handle root hub init quirks ... */ |
| 633 | temp = roothub_a (ohci); |
| 634 | temp &= ~(RH_A_PSM | RH_A_OCPM); |
| 635 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { |
| 636 | /* NSC 87560 and maybe others */ |
| 637 | temp |= RH_A_NOCP; |
| 638 | temp &= ~(RH_A_POTPGT | RH_A_NPS); |
| 639 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); |
| 640 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || distrust_firmware) { |
| 641 | /* hub power always on; required for AMD-756 and some |
| 642 | * Mac platforms. ganged overcurrent reporting, if any. |
| 643 | */ |
| 644 | temp |= RH_A_NPS; |
| 645 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); |
| 646 | } |
| 647 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); |
| 648 | ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM, |
| 649 | &ohci->regs->roothub.b); |
| 650 | // flush those writes |
| 651 | (void) ohci_readl (ohci, &ohci->regs->control); |
| 652 | |
| 653 | spin_unlock_irq (&ohci->lock); |
| 654 | |
| 655 | // POTPGT delay is bits 24-31, in 2 ms units. |
| 656 | mdelay ((temp >> 23) & 0x1fe); |
| 657 | bus = &ohci_to_hcd(ohci)->self; |
| 658 | ohci_to_hcd(ohci)->state = HC_STATE_RUNNING; |
| 659 | |
| 660 | ohci_dump (ohci, 1); |
| 661 | |
| 662 | udev = bus->root_hub; |
| 663 | if (udev) { |
| 664 | return 0; |
| 665 | } |
| 666 | |
| 667 | /* connect the virtual root hub */ |
| 668 | udev = usb_alloc_dev (NULL, bus, 0); |
| 669 | if (!udev) { |
| 670 | disable (ohci); |
| 671 | ohci->hc_control &= ~OHCI_CTRL_HCFS; |
| 672 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); |
| 673 | return -ENOMEM; |
| 674 | } |
| 675 | |
| 676 | udev->speed = USB_SPEED_FULL; |
| 677 | if (usb_hcd_register_root_hub (udev, ohci_to_hcd(ohci)) != 0) { |
| 678 | usb_put_dev (udev); |
| 679 | disable (ohci); |
| 680 | ohci->hc_control &= ~OHCI_CTRL_HCFS; |
| 681 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); |
| 682 | return -ENODEV; |
| 683 | } |
| 684 | if (ohci->power_budget) |
| 685 | hub_set_power_budget(udev, ohci->power_budget); |
| 686 | |
| 687 | create_debug_files (ohci); |
| 688 | return 0; |
| 689 | } |
| 690 | |
| 691 | /*-------------------------------------------------------------------------*/ |
| 692 | |
| 693 | /* an interrupt happens */ |
| 694 | |
| 695 | static irqreturn_t ohci_irq (struct usb_hcd *hcd, struct pt_regs *ptregs) |
| 696 | { |
| 697 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
| 698 | struct ohci_regs __iomem *regs = ohci->regs; |
| 699 | int ints; |
| 700 | |
| 701 | /* we can eliminate a (slow) ohci_readl() |
| 702 | if _only_ WDH caused this irq */ |
| 703 | if ((ohci->hcca->done_head != 0) |
| 704 | && ! (hc32_to_cpup (ohci, &ohci->hcca->done_head) |
| 705 | & 0x01)) { |
| 706 | ints = OHCI_INTR_WDH; |
| 707 | |
| 708 | /* cardbus/... hardware gone before remove() */ |
| 709 | } else if ((ints = ohci_readl (ohci, ®s->intrstatus)) == ~(u32)0) { |
| 710 | disable (ohci); |
| 711 | ohci_dbg (ohci, "device removed!\n"); |
| 712 | return IRQ_HANDLED; |
| 713 | |
| 714 | /* interrupt for some other device? */ |
| 715 | } else if ((ints &= ohci_readl (ohci, ®s->intrenable)) == 0) { |
| 716 | return IRQ_NOTMINE; |
| 717 | } |
| 718 | |
| 719 | if (ints & OHCI_INTR_UE) { |
| 720 | disable (ohci); |
| 721 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); |
| 722 | // e.g. due to PCI Master/Target Abort |
| 723 | |
| 724 | ohci_dump (ohci, 1); |
| 725 | ohci_usb_reset (ohci); |
| 726 | } |
| 727 | |
| 728 | if (ints & OHCI_INTR_RD) { |
| 729 | ohci_vdbg (ohci, "resume detect\n"); |
| 730 | if (hcd->state != HC_STATE_QUIESCING) |
| 731 | schedule_work(&ohci->rh_resume); |
| 732 | } |
| 733 | |
| 734 | if (ints & OHCI_INTR_WDH) { |
| 735 | if (HC_IS_RUNNING(hcd->state)) |
| 736 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrdisable); |
| 737 | spin_lock (&ohci->lock); |
| 738 | dl_done_list (ohci, ptregs); |
| 739 | spin_unlock (&ohci->lock); |
| 740 | if (HC_IS_RUNNING(hcd->state)) |
| 741 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrenable); |
| 742 | } |
| 743 | |
| 744 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
| 745 | |
| 746 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled |
| 747 | * when there's still unlinking to be done (next frame). |
| 748 | */ |
| 749 | spin_lock (&ohci->lock); |
| 750 | if (ohci->ed_rm_list) |
| 751 | finish_unlinks (ohci, ohci_frame_no(ohci), ptregs); |
| 752 | if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list |
| 753 | && HC_IS_RUNNING(hcd->state)) |
| 754 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
| 755 | spin_unlock (&ohci->lock); |
| 756 | |
| 757 | if (HC_IS_RUNNING(hcd->state)) { |
| 758 | ohci_writel (ohci, ints, ®s->intrstatus); |
| 759 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
| 760 | // flush those writes |
| 761 | (void) ohci_readl (ohci, &ohci->regs->control); |
| 762 | } |
| 763 | |
| 764 | return IRQ_HANDLED; |
| 765 | } |
| 766 | |
| 767 | /*-------------------------------------------------------------------------*/ |
| 768 | |
| 769 | static void ohci_stop (struct usb_hcd *hcd) |
| 770 | { |
| 771 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
| 772 | |
| 773 | ohci_dbg (ohci, "stop %s controller (state 0x%02x)\n", |
| 774 | hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS), |
| 775 | hcd->state); |
| 776 | ohci_dump (ohci, 1); |
| 777 | |
| 778 | flush_scheduled_work(); |
| 779 | |
| 780 | ohci_usb_reset (ohci); |
| 781 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
| 782 | |
| 783 | remove_debug_files (ohci); |
| 784 | ohci_mem_cleanup (ohci); |
| 785 | if (ohci->hcca) { |
| 786 | dma_free_coherent (hcd->self.controller, |
| 787 | sizeof *ohci->hcca, |
| 788 | ohci->hcca, ohci->hcca_dma); |
| 789 | ohci->hcca = NULL; |
| 790 | ohci->hcca_dma = 0; |
| 791 | } |
| 792 | } |
| 793 | |
| 794 | /*-------------------------------------------------------------------------*/ |
| 795 | |
| 796 | /* must not be called from interrupt context */ |
| 797 | |
| 798 | #if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_PM) |
| 799 | |
| 800 | static int ohci_restart (struct ohci_hcd *ohci) |
| 801 | { |
| 802 | int temp; |
| 803 | int i; |
| 804 | struct urb_priv *priv; |
| 805 | struct usb_device *root = ohci_to_hcd(ohci)->self.root_hub; |
| 806 | |
| 807 | /* mark any devices gone, so they do nothing till khubd disconnects. |
| 808 | * recycle any "live" eds/tds (and urbs) right away. |
| 809 | * later, khubd disconnect processing will recycle the other state, |
| 810 | * (either as disconnect/reconnect, or maybe someday as a reset). |
| 811 | */ |
| 812 | spin_lock_irq(&ohci->lock); |
| 813 | disable (ohci); |
| 814 | for (i = 0; i < root->maxchild; i++) { |
| 815 | if (root->children [i]) |
| 816 | usb_set_device_state (root->children[i], |
| 817 | USB_STATE_NOTATTACHED); |
| 818 | } |
| 819 | if (!list_empty (&ohci->pending)) |
| 820 | ohci_dbg(ohci, "abort schedule...\n"); |
| 821 | list_for_each_entry (priv, &ohci->pending, pending) { |
| 822 | struct urb *urb = priv->td[0]->urb; |
| 823 | struct ed *ed = priv->ed; |
| 824 | |
| 825 | switch (ed->state) { |
| 826 | case ED_OPER: |
| 827 | ed->state = ED_UNLINK; |
| 828 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); |
| 829 | ed_deschedule (ohci, ed); |
| 830 | |
| 831 | ed->ed_next = ohci->ed_rm_list; |
| 832 | ed->ed_prev = NULL; |
| 833 | ohci->ed_rm_list = ed; |
| 834 | /* FALLTHROUGH */ |
| 835 | case ED_UNLINK: |
| 836 | break; |
| 837 | default: |
| 838 | ohci_dbg(ohci, "bogus ed %p state %d\n", |
| 839 | ed, ed->state); |
| 840 | } |
| 841 | |
| 842 | spin_lock (&urb->lock); |
| 843 | urb->status = -ESHUTDOWN; |
| 844 | spin_unlock (&urb->lock); |
| 845 | } |
| 846 | finish_unlinks (ohci, 0, NULL); |
| 847 | spin_unlock_irq(&ohci->lock); |
| 848 | |
| 849 | /* paranoia, in case that didn't work: */ |
| 850 | |
| 851 | /* empty the interrupt branches */ |
| 852 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; |
| 853 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; |
| 854 | |
| 855 | /* no EDs to remove */ |
| 856 | ohci->ed_rm_list = NULL; |
| 857 | |
| 858 | /* empty control and bulk lists */ |
| 859 | ohci->ed_controltail = NULL; |
| 860 | ohci->ed_bulktail = NULL; |
| 861 | |
| 862 | if ((temp = ohci_run (ohci)) < 0) { |
| 863 | ohci_err (ohci, "can't restart, %d\n", temp); |
| 864 | return temp; |
| 865 | } else { |
| 866 | /* here we "know" root ports should always stay powered, |
| 867 | * and that if we try to turn them back on the root hub |
| 868 | * will respond to CSC processing. |
| 869 | */ |
| 870 | i = roothub_a (ohci) & RH_A_NDP; |
| 871 | while (i--) |
| 872 | ohci_writel (ohci, RH_PS_PSS, |
| 873 | &ohci->regs->roothub.portstatus [temp]); |
| 874 | ohci_dbg (ohci, "restart complete\n"); |
| 875 | } |
| 876 | return 0; |
| 877 | } |
| 878 | #endif |
| 879 | |
| 880 | /*-------------------------------------------------------------------------*/ |
| 881 | |
| 882 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC |
| 883 | |
| 884 | MODULE_AUTHOR (DRIVER_AUTHOR); |
| 885 | MODULE_DESCRIPTION (DRIVER_INFO); |
| 886 | MODULE_LICENSE ("GPL"); |
| 887 | |
| 888 | #ifdef CONFIG_PCI |
| 889 | #include "ohci-pci.c" |
| 890 | #endif |
| 891 | |
| 892 | #ifdef CONFIG_SA1111 |
| 893 | #include "ohci-sa1111.c" |
| 894 | #endif |
| 895 | |
| 896 | #ifdef CONFIG_ARCH_OMAP |
| 897 | #include "ohci-omap.c" |
| 898 | #endif |
| 899 | |
| 900 | #ifdef CONFIG_ARCH_LH7A404 |
| 901 | #include "ohci-lh7a404.c" |
| 902 | #endif |
| 903 | |
| 904 | #ifdef CONFIG_PXA27x |
| 905 | #include "ohci-pxa27x.c" |
| 906 | #endif |
| 907 | |
| 908 | #ifdef CONFIG_SOC_AU1X00 |
| 909 | #include "ohci-au1xxx.c" |
| 910 | #endif |
| 911 | |
| 912 | #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC |
| 913 | #include "ohci-ppc-soc.c" |
| 914 | #endif |
| 915 | |
| 916 | #if !(defined(CONFIG_PCI) \ |
| 917 | || defined(CONFIG_SA1111) \ |
| 918 | || defined(CONFIG_ARCH_OMAP) \ |
| 919 | || defined (CONFIG_ARCH_LH7A404) \ |
| 920 | || defined (CONFIG_PXA27x) \ |
| 921 | || defined (CONFIG_SOC_AU1X00) \ |
| 922 | || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \ |
| 923 | ) |
| 924 | #error "missing bus glue for ohci-hcd" |
| 925 | #endif |