Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 1 | /* |
Jack Pham | 975df89 | 2017-02-01 14:13:09 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 14 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
Mayank Rana | f4f71a3 | 2017-04-12 19:41:51 -0700 | [diff] [blame] | 15 | #include <dt-bindings/msm/msm-bus-ids.h> |
| 16 | |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 17 | &soc { |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 18 | /* Primary USB port related DWC3 controller */ |
| 19 | usb0: ssusb@a600000 { |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 20 | compatible = "qcom,dwc-usb3-msm"; |
| 21 | reg = <0x0a600000 0xf8c00>, |
Mayank Rana | e9de1fd | 2017-02-16 09:38:15 -0800 | [diff] [blame] | 22 | <0x088ee000 0x400>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 23 | reg-names = "core_base", "ahb2phy_base"; |
| 24 | #address-cells = <1>; |
| 25 | #size-cells = <1>; |
| 26 | ranges; |
| 27 | |
Mayank Rana | fd930e6 | 2017-05-31 10:37:07 -0700 | [diff] [blame] | 28 | interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; |
| 29 | interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", |
| 30 | "ss_phy_irq", "dm_hs_phy_irq"; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 31 | |
| 32 | USB3_GDSC-supply = <&usb30_prim_gdsc>; |
| 33 | qcom,usb-dbm = <&dbm_1p5>; |
| 34 | qcom,dwc-usb3-msm-tx-fifo-size = <21288>; |
Mayank Rana | ab02117 | 2016-12-16 09:50:33 -0800 | [diff] [blame] | 35 | qcom,num-gsi-evt-buffs = <0x3>; |
Mayank Rana | fd930e6 | 2017-05-31 10:37:07 -0700 | [diff] [blame] | 36 | qcom,use-pdc-interrupts; |
Jack Pham | af5edc8 | 2017-03-30 17:26:02 -0700 | [diff] [blame] | 37 | extcon = <&pmi8998_pdphy>, <&pmi8998_pdphy>, <&eud>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 38 | |
| 39 | clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, |
| 40 | <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
| 41 | <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
| 42 | <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| 43 | <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, |
| 44 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| 45 | <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>; |
| 46 | |
| 47 | clock-names = "core_clk", "iface_clk", "bus_aggr_clk", |
| 48 | "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; |
| 49 | |
Vamsi Krishna Samavedam | ca6a814 | 2017-02-03 17:52:15 -0800 | [diff] [blame] | 50 | qcom,core-clk-rate = <133333333>; |
| 51 | qcom,core-clk-rate-hs = <66666667>; |
| 52 | |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 53 | resets = <&clock_gcc GCC_USB30_PRIM_BCR>; |
| 54 | reset-names = "core_reset"; |
| 55 | |
Mayank Rana | f4f71a3 | 2017-04-12 19:41:51 -0700 | [diff] [blame] | 56 | qcom,msm-bus,name = "usb0"; |
| 57 | qcom,msm-bus,num-cases = <2>; |
| 58 | qcom,msm-bus,num-paths = <3>; |
| 59 | qcom,msm-bus,vectors-KBps = |
| 60 | <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 61 | <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>, |
| 62 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>, |
| 63 | <MSM_BUS_MASTER_USB3 |
| 64 | MSM_BUS_SLAVE_EBI_CH0 240000 800000>, |
| 65 | <MSM_BUS_MASTER_USB3 |
| 66 | MSM_BUS_SLAVE_IPA_CFG 0 2400>, |
| 67 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 80000>; |
| 68 | |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 69 | dwc3@a600000 { |
| 70 | compatible = "snps,dwc3"; |
| 71 | reg = <0x0a600000 0xcd00>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 72 | interrupts = <0 133 0>; |
Mayank Rana | dbcfd28 | 2017-04-11 21:09:18 -0700 | [diff] [blame] | 73 | usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 74 | tx-fifo-resize; |
Jack Pham | 490792d | 2017-03-23 18:48:05 -0700 | [diff] [blame] | 75 | linux,sysdev_is_parent; |
Jack Pham | 975df89 | 2017-02-01 14:13:09 -0800 | [diff] [blame] | 76 | snps,disable-clk-gating; |
Mayank Rana | dfd399c | 2017-03-08 18:19:03 -0800 | [diff] [blame] | 77 | snps,has-lpm-erratum; |
| 78 | snps,hird-threshold = /bits/ 8 <0x10>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 79 | }; |
Mayank Rana | 98a247c | 2017-04-06 15:06:22 -0700 | [diff] [blame] | 80 | |
| 81 | qcom,usbbam@a704000 { |
| 82 | compatible = "qcom,usb-bam-msm"; |
| 83 | reg = <0xa704000 0x17000>; |
Mayank Rana | 98a247c | 2017-04-06 15:06:22 -0700 | [diff] [blame] | 84 | interrupts = <0 132 0>; |
| 85 | |
| 86 | qcom,bam-type = <0>; |
| 87 | qcom,usb-bam-fifo-baseaddr = <0x146bb000>; |
| 88 | qcom,usb-bam-num-pipes = <8>; |
| 89 | qcom,ignore-core-reset-ack; |
| 90 | qcom,disable-clk-gating; |
| 91 | qcom,usb-bam-override-threshold = <0x4001>; |
| 92 | qcom,usb-bam-max-mbps-highspeed = <400>; |
| 93 | qcom,usb-bam-max-mbps-superspeed = <3600>; |
| 94 | qcom,reset-bam-on-connect; |
| 95 | |
| 96 | qcom,pipe0 { |
| 97 | label = "ssusb-qdss-in-0"; |
| 98 | qcom,usb-bam-mem-type = <2>; |
| 99 | qcom,dir = <1>; |
| 100 | qcom,pipe-num = <0>; |
| 101 | qcom,peer-bam = <0>; |
| 102 | qcom,peer-bam-physical-address = <0x6064000>; |
| 103 | qcom,src-bam-pipe-index = <0>; |
| 104 | qcom,dst-bam-pipe-index = <0>; |
| 105 | qcom,data-fifo-offset = <0x0>; |
| 106 | qcom,data-fifo-size = <0x1800>; |
| 107 | qcom,descriptor-fifo-offset = <0x1800>; |
| 108 | qcom,descriptor-fifo-size = <0x800>; |
| 109 | }; |
| 110 | }; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 111 | }; |
| 112 | |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 113 | /* Primary USB port related QUSB2 PHY */ |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 114 | qusb_phy0: qusb@88e2000 { |
| 115 | compatible = "qcom,qusb2phy-v2"; |
| 116 | reg = <0x088e2000 0x400>; |
| 117 | reg-names = "qusb_phy_base"; |
| 118 | |
David Collins | 3a45794 | 2016-12-09 16:59:51 -0800 | [diff] [blame] | 119 | vdd-supply = <&pm8998_l1>; |
| 120 | vdda18-supply = <&pm8998_l12>; |
| 121 | vdda33-supply = <&pm8998_l24>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 122 | qcom,vdd-voltage-level = <0 880000 880000>; |
| 123 | qcom,qusb-phy-init-seq = |
Mayank Rana | c8d69e2 | 2017-04-03 18:13:34 -0700 | [diff] [blame] | 124 | /* <value reg_offset> */ |
| 125 | <0x23 0x210 /* PWR_CTRL1 */ |
| 126 | 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ |
| 127 | 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ |
| 128 | 0x80 0x2c /* PLL_CMODE */ |
| 129 | 0x0a 0x184 /* PLL_LOCK_DELAY */ |
| 130 | 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ |
| 131 | 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ |
| 132 | 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ |
| 133 | 0x21 0x214 /* PWR_CTRL2 */ |
| 134 | 0x00 0x220 /* IMP_CTRL1 */ |
| 135 | 0x58 0x224 /* IMP_CTRL2 */ |
Mayank Rana | d2581e6 | 2017-06-20 09:47:58 -0700 | [diff] [blame^] | 136 | 0x30 0x240 /* TUNE1 */ |
Mayank Rana | c8d69e2 | 2017-04-03 18:13:34 -0700 | [diff] [blame] | 137 | 0x29 0x244 /* TUNE2 */ |
| 138 | 0xca 0x248 /* TUNE3 */ |
| 139 | 0x04 0x24c /* TUNE4 */ |
Mayank Rana | 471513c | 2017-04-20 11:02:07 -0700 | [diff] [blame] | 140 | 0x03 0x250 /* TUNE5 */ |
Mayank Rana | c8d69e2 | 2017-04-03 18:13:34 -0700 | [diff] [blame] | 141 | 0x00 0x23c /* CHG_CTRL2 */ |
| 142 | 0x22 0x210>; /* PWR_CTRL1 */ |
| 143 | |
Hemant Kumar | 6f55535 | 2017-06-20 16:13:16 -0700 | [diff] [blame] | 144 | qcom,phy-auto-resume-offset = <0x254>; |
| 145 | |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 146 | phy_type= "utmi"; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 147 | clocks = <&clock_rpmh RPMH_CXO_CLK>, |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 148 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 149 | clock-names = "ref_clk_src", "cfg_ahb_clk"; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 150 | |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 151 | resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 152 | reset-names = "phy_reset"; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 153 | }; |
| 154 | |
Mayank Rana | 8d12e40 | 2017-04-04 12:34:24 -0700 | [diff] [blame] | 155 | /* Primary USB port related QMP USB DP Combo PHY */ |
| 156 | usb_qmp_dp_phy: ssphy@88e8000 { |
| 157 | compatible = "qcom,usb-ssphy-qmp-dp-combo"; |
| 158 | reg = <0x88e8000 0x3000>; |
| 159 | reg-names = "qmp_phy_base"; |
| 160 | |
| 161 | vdd-supply = <&pm8998_l1>; |
| 162 | core-supply = <&pm8998_l26>; |
| 163 | qcom,vdd-voltage-level = <0 880000 880000>; |
| 164 | qcom,vbus-valid-override; |
| 165 | qcom,qmp-phy-init-seq = |
| 166 | /* <reg_offset, value, delay> */ |
| 167 | <0x1048 0x07 0x00 /* COM_PLL_IVCO */ |
| 168 | 0x1080 0x14 0x00 /* COM_SYSCLK_EN_SEL */ |
| 169 | 0x1034 0x08 0x00 /* COM_BIAS_EN_CLKBUFLR_EN */ |
Mayank Rana | dbcfd28 | 2017-04-11 21:09:18 -0700 | [diff] [blame] | 170 | 0x1138 0x30 0x00 /* COM_CLK_SELECT */ |
Mayank Rana | 8d12e40 | 2017-04-04 12:34:24 -0700 | [diff] [blame] | 171 | 0x103c 0x02 0x00 /* COM_SYS_CLK_CTRL */ |
| 172 | 0x108c 0x08 0x00 /* COM_RESETSM_CNTRL2 */ |
| 173 | 0x115c 0x16 0x00 /* COM_CMN_CONFIG */ |
| 174 | 0x1164 0x01 0x00 /* COM_SVS_MODE_CLK_SEL */ |
| 175 | 0x113c 0x80 0x00 /* COM_HSCLK_SEL */ |
| 176 | 0x10b0 0x82 0x00 /* COM_DEC_START_MODE0 */ |
| 177 | 0x10b8 0xab 0x00 /* COM_DIV_FRAC_START1_MODE0 */ |
| 178 | 0x10bc 0xea 0x00 /* COM_DIV_FRAC_START2_MODE0 */ |
| 179 | 0x10c0 0x02 0x00 /* COM_DIV_FRAC_START3_MODE0 */ |
| 180 | 0x1060 0x06 0x00 /* COM_CP_CTRL_MODE0 */ |
| 181 | 0x1068 0x16 0x00 /* COM_PLL_RCTRL_MODE0 */ |
| 182 | 0x1070 0x36 0x00 /* COM_PLL_CCTRL_MODE0 */ |
| 183 | 0x10dc 0x00 0x00 /* COM_INTEGLOOP_GAIN1_MODE0 */ |
| 184 | 0x10d8 0x3f 0x00 /* COM_INTEGLOOP_GAIN0_MODE0 */ |
| 185 | 0x10f8 0x01 0x00 /* COM_VCO_TUNE2_MODE0 */ |
| 186 | 0x10f4 0xc9 0x00 /* COM_VCO_TUNE1_MODE0 */ |
| 187 | 0x1148 0x0a 0x00 /* COM_CORECLK_DIV_MODE0 */ |
| 188 | 0x10a0 0x00 0x00 /* COM_LOCK_CMP3_MODE0 */ |
| 189 | 0x109c 0x34 0x00 /* COM_LOCK_CMP2_MODE0 */ |
Mayank Rana | dbcfd28 | 2017-04-11 21:09:18 -0700 | [diff] [blame] | 190 | 0x1098 0x15 0x00 /* COM_LOCK_CMP1_MODE0 */ |
Mayank Rana | 8d12e40 | 2017-04-04 12:34:24 -0700 | [diff] [blame] | 191 | 0x1090 0x04 0x00 /* COM_LOCK_CMP_EN */ |
| 192 | 0x1154 0x00 0x00 /* COM_CORE_CLK_EN */ |
| 193 | 0x1094 0x00 0x00 /* COM_LOCK_CMP_CFG */ |
| 194 | 0x10f0 0x00 0x00 /* COM_VCO_TUNE_MAP */ |
| 195 | 0x1040 0x0a 0x00 /* COM_SYSCLK_BUF_ENABLE */ |
| 196 | 0x1010 0x01 0x00 /* COM_SSC_EN_CENTER */ |
| 197 | 0x101c 0x31 0x00 /* COM_SSC_PER1 */ |
| 198 | 0x1020 0x01 0x00 /* COM_SSC_PER2 */ |
| 199 | 0x1014 0x00 0x00 /* COM_SSC_ADJ_PER1 */ |
| 200 | 0x1018 0x00 0x00 /* COM_SSC_ADJ_PER2 */ |
| 201 | 0x1024 0x85 0x00 /* COM_SSC_STEP_SIZE1 */ |
| 202 | 0x1028 0x07 0x00 /* COM_SSC_STEP_SIZE2 */ |
| 203 | 0x1430 0x0b 0x00 /* RXA_UCDR_FASTLOCK_FO_GAIN */ |
| 204 | 0x14d4 0x0f 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL2 */ |
| 205 | 0x14d8 0x4e 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL3 */ |
| 206 | 0x14dc 0x18 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL4 */ |
| 207 | 0x14f8 0x77 0x00 /* RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */ |
| 208 | 0x14fc 0x80 0x00 /* RXA_RX_OFFSET_ADAPTOR_CNTRL2 */ |
| 209 | 0x1504 0x03 0x00 /* RXA_SIGDET_CNTRL */ |
| 210 | 0x150c 0x16 0x00 /* RXA_SIGDET_DEGLITCH_CNTRL */ |
| 211 | 0x1830 0x0b 0x00 /* RXB_UCDR_FASTLOCK_FO_GAIN */ |
| 212 | 0x18d4 0x0f 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL2 */ |
| 213 | 0x18d8 0x4e 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL3 */ |
| 214 | 0x18dc 0x18 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL4 */ |
| 215 | 0x18f8 0x77 0x00 /* RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */ |
| 216 | 0x18fc 0x80 0x00 /* RXB_RX_OFFSET_ADAPTOR_CNTRL2 */ |
| 217 | 0x1904 0x03 0x00 /* RXB_SIGDET_CNTRL */ |
| 218 | 0x190c 0x16 0x00 /* RXB_SIGDET_DEGLITCH_CNTRL */ |
| 219 | 0x1260 0x10 0x00 /* TXA_HIGHZ_DRVR_EN */ |
| 220 | 0x12a4 0x12 0x00 /* TXA_RCV_DETECT_LVL_2 */ |
| 221 | 0x128c 0x16 0x00 /* TXA_LANE_MODE_1 */ |
Mayank Rana | dbcfd28 | 2017-04-11 21:09:18 -0700 | [diff] [blame] | 222 | 0x1248 0x09 0x00 /* TXA_RES_CODE_LANE_OFFSET_RX */ |
| 223 | 0x1244 0x0d 0x00 /* TXA_RES_CODE_LANE_OFFSET_TX */ |
Mayank Rana | 8d12e40 | 2017-04-04 12:34:24 -0700 | [diff] [blame] | 224 | 0x1660 0x10 0x00 /* TXB_HIGHZ_DRVR_EN */ |
| 225 | 0x16a4 0x12 0x00 /* TXB_RCV_DETECT_LVL_2 */ |
| 226 | 0x168c 0x16 0x00 /* TXB_LANE_MODE_1 */ |
| 227 | 0x1648 0x09 0x00 /* TXB_RES_CODE_LANE_OFFSET_RX */ |
| 228 | 0x1644 0x0d 0x00 /* TXB_RES_CODE_LANE_OFFSET_TX */ |
| 229 | 0x1cc8 0x83 0x00 /* PCS_FLL_CNTRL2 */ |
| 230 | 0x1ccc 0x09 0x00 /* PCS_FLL_CNT_VAL_L */ |
| 231 | 0x1cd0 0xa2 0x00 /* PCS_FLL_CNT_VAL_H_TOL */ |
| 232 | 0x1cd4 0x40 0x00 /* PCS_FLL_MAN_CODE */ |
| 233 | 0x1cc4 0x02 0x00 /* PCS_FLL_CNTRL1 */ |
| 234 | 0x1c80 0xd1 0x00 /* PCS_LOCK_DETECT_CONFIG1 */ |
| 235 | 0x1c84 0x1f 0x00 /* PCS_LOCK_DETECT_CONFIG2 */ |
| 236 | 0x1c88 0x47 0x00 /* PCS_LOCK_DETECT_CONFIG3 */ |
| 237 | 0x1c64 0x1b 0x00 /* PCS_POWER_STATE_CONFIG2 */ |
| 238 | 0x1434 0x75 0x00 /* RXA_UCDR_SO_SATURATION */ |
| 239 | 0x1834 0x75 0x00 /* RXB_UCDR_SO_SATURATION */ |
| 240 | 0x1dd8 0xba 0x00 /* PCS_RX_SIGDET_LVL */ |
| 241 | 0x1c0c 0x9f 0x00 /* PCS_TXMGN_V0 */ |
| 242 | 0x1c10 0x9f 0x00 /* PCS_TXMGN_V1 */ |
| 243 | 0x1c14 0xb7 0x00 /* PCS_TXMGN_V2 */ |
| 244 | 0x1c18 0x4e 0x00 /* PCS_TXMGN_V3 */ |
| 245 | 0x1c1c 0x65 0x00 /* PCS_TXMGN_V4 */ |
| 246 | 0x1c20 0x6b 0x00 /* PCS_TXMGN_LS */ |
| 247 | 0x1c24 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V0 */ |
| 248 | 0x1c28 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V0 */ |
| 249 | 0x1c2c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V1 */ |
| 250 | 0x1c30 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V1 */ |
| 251 | 0x1c34 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V2 */ |
| 252 | 0x1c38 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V2 */ |
| 253 | 0x1c3c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V3 */ |
| 254 | 0x1c40 0x1d 0x00 /* PCS_TXDEEMPH_M3P5DB_V3 */ |
| 255 | 0x1c44 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V4 */ |
| 256 | 0x1c48 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V4 */ |
| 257 | 0x1c4c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_LS */ |
| 258 | 0x1c50 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_LS */ |
| 259 | 0x1c5c 0x02 0x00 /* PCS_RATE_SLEW_CNTRL */ |
| 260 | 0x1ca0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */ |
| 261 | 0x1c8c 0x44 0x00 /* PCS_TSYNC_RSYNC_TIME */ |
| 262 | 0x1c70 0xe7 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_L */ |
| 263 | 0x1c74 0x03 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_H */ |
| 264 | 0x1c78 0x40 0x00 /* PCS_RCVR_DTCT_DLY_U3_L */ |
| 265 | 0x1c7c 0x00 0x00 /* PCS_RCVR_DTCT_DLY_U3_H */ |
| 266 | 0x1cb8 0x75 0x00 /* PCS_RXEQTRAINING_WAIT_TIME */ |
| 267 | 0x1cb0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */ |
| 268 | 0x1cbc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */ |
| 269 | 0xffffffff 0xffffffff 0x00>; |
| 270 | |
| 271 | qcom,qmp-phy-reg-offset = |
| 272 | <0x1d74 /* USB3_DP_PCS_PCS_STATUS */ |
| 273 | 0x1cd8 /* USB3_DP_PCS_AUTONOMOUS_MODE_CTRL */ |
| 274 | 0x1cdc /* USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR */ |
| 275 | 0x1c04 /* USB3_DP_PCS_POWER_DOWN_CONTROL */ |
| 276 | 0x1c00 /* USB3_DP_PCS_SW_RESET */ |
| 277 | 0x1c08 /* USB3_DP_PCS_START_CONTROL */ |
| 278 | 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */ |
| 279 | 0x0008 /* USB3_DP_COM_POWER_DOWN_CTRL */ |
| 280 | 0x0004 /* USB3_DP_COM_SW_RESET */ |
| 281 | 0x001c /* USB3_DP_COM_RESET_OVRD_CTRL */ |
| 282 | 0x0000 /* USB3_DP_COM_PHY_MODE_CTRL */ |
| 283 | 0x0010 /* USB3_DP_COM_TYPEC_CTRL */ |
| 284 | 0x000c /* USB3_DP_COM_SWI_CTRL */ |
| 285 | 0x1a0c>; /* USB3_DP_PCS_MISC_CLAMP_ENABLE */ |
| 286 | |
| 287 | clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
| 288 | <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, |
| 289 | <&clock_rpmh RPMH_CXO_CLK>, |
| 290 | <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, |
Mayank Rana | 43378fa | 2017-04-19 20:23:33 -0700 | [diff] [blame] | 291 | <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, |
| 292 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; |
Mayank Rana | 8d12e40 | 2017-04-04 12:34:24 -0700 | [diff] [blame] | 293 | |
| 294 | clock-names = "aux_clk", "pipe_clk", "ref_clk_src", |
Mayank Rana | 43378fa | 2017-04-19 20:23:33 -0700 | [diff] [blame] | 295 | "ref_clk", "com_aux_clk", "cfg_ahb_clk"; |
Mayank Rana | 8d12e40 | 2017-04-04 12:34:24 -0700 | [diff] [blame] | 296 | |
Mayank Rana | dbcfd28 | 2017-04-11 21:09:18 -0700 | [diff] [blame] | 297 | resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
| 298 | <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; |
| 299 | reset-names = "global_phy_reset", "phy_reset"; |
Mayank Rana | 8d12e40 | 2017-04-04 12:34:24 -0700 | [diff] [blame] | 300 | }; |
| 301 | |
Mayank Rana | c8e9b3a | 2017-04-10 15:01:11 -0700 | [diff] [blame] | 302 | dbm_1p5: dbm@a6f8000 { |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 303 | compatible = "qcom,usb-dbm-1p5"; |
Mayank Rana | c8e9b3a | 2017-04-10 15:01:11 -0700 | [diff] [blame] | 304 | reg = <0xa6f8000 0x400>; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 305 | qcom,reset-ep-after-lpm-resume; |
| 306 | }; |
| 307 | |
Mayank Rana | ba7359c | 2017-04-26 13:29:38 -0700 | [diff] [blame] | 308 | usb_audio_qmi_dev { |
| 309 | compatible = "qcom,usb-audio-qmi-dev"; |
Patrick Daly | d70904d | 2017-05-08 14:57:43 -0700 | [diff] [blame] | 310 | iommus = <&apps_smmu 0x182c 0x0>; |
Mayank Rana | ba7359c | 2017-04-26 13:29:38 -0700 | [diff] [blame] | 311 | qcom,usb-audio-stream-id = <0xc>; |
| 312 | qcom,usb-audio-intr-num = <2>; |
| 313 | }; |
| 314 | |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 315 | usb_nop_phy: usb_nop_phy { |
| 316 | compatible = "usb-nop-xceiv"; |
| 317 | }; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 318 | |
| 319 | /* Secondary USB port related DWC3 controller */ |
| 320 | usb1: ssusb@a800000 { |
| 321 | compatible = "qcom,dwc-usb3-msm"; |
| 322 | reg = <0x0a800000 0xf8c00>, |
| 323 | <0x088ee000 0x400>; |
| 324 | reg-names = "core_base", "ahb2phy_base"; |
| 325 | #address-cells = <1>; |
| 326 | #size-cells = <1>; |
| 327 | ranges; |
| 328 | |
Mayank Rana | fd930e6 | 2017-05-31 10:37:07 -0700 | [diff] [blame] | 329 | interrupts = <0 491 0>, <0 135 0>, <0 487 0>, <0 490 0>; |
| 330 | interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", |
| 331 | "ss_phy_irq", "dm_hs_phy_irq"; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 332 | |
| 333 | USB3_GDSC-supply = <&usb30_sec_gdsc>; |
| 334 | qcom,dwc-usb3-msm-tx-fifo-size = <21288>; |
Mayank Rana | fd930e6 | 2017-05-31 10:37:07 -0700 | [diff] [blame] | 335 | qcom,use-pdc-interrupts; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 336 | |
| 337 | clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, |
| 338 | <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
| 339 | <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
| 340 | <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
| 341 | <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, |
| 342 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| 343 | <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>; |
| 344 | |
| 345 | clock-names = "core_clk", "iface_clk", "bus_aggr_clk", |
| 346 | "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; |
| 347 | |
| 348 | qcom,core-clk-rate = <133333333>; |
| 349 | qcom,core-clk-rate-hs = <66666667>; |
| 350 | |
| 351 | resets = <&clock_gcc GCC_USB30_SEC_BCR>; |
| 352 | reset-names = "core_reset"; |
| 353 | status = "disabled"; |
| 354 | |
Mayank Rana | f4f71a3 | 2017-04-12 19:41:51 -0700 | [diff] [blame] | 355 | qcom,msm-bus,name = "usb1"; |
| 356 | qcom,msm-bus,num-cases = <2>; |
| 357 | qcom,msm-bus,num-paths = <2>; |
| 358 | qcom,msm-bus,vectors-KBps = |
| 359 | <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 360 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 0>, |
| 361 | <MSM_BUS_MASTER_USB3_1 |
| 362 | MSM_BUS_SLAVE_EBI_CH0 240000 800000>, |
| 363 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 80000>; |
| 364 | |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 365 | dwc3@a600000 { |
| 366 | compatible = "snps,dwc3"; |
| 367 | reg = <0x0a800000 0xcd00>; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 368 | interrupts = <0 138 0>; |
| 369 | usb-phy = <&qusb_phy1>, <&usb_qmp_phy>; |
| 370 | tx-fifo-resize; |
Jack Pham | 490792d | 2017-03-23 18:48:05 -0700 | [diff] [blame] | 371 | linux,sysdev_is_parent; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 372 | snps,disable-clk-gating; |
| 373 | snps,has-lpm-erratum; |
| 374 | snps,hird-threshold = /bits/ 8 <0x10>; |
| 375 | }; |
| 376 | }; |
| 377 | |
| 378 | /* Secondary USB port related QUSB2 PHY */ |
| 379 | qusb_phy1: qusb@88e3000 { |
| 380 | compatible = "qcom,qusb2phy-v2"; |
| 381 | reg = <0x088e3000 0x400>; |
| 382 | reg-names = "qusb_phy_base"; |
| 383 | |
| 384 | vdd-supply = <&pm8998_l1>; |
| 385 | vdda18-supply = <&pm8998_l12>; |
| 386 | vdda33-supply = <&pm8998_l24>; |
| 387 | qcom,vdd-voltage-level = <0 880000 880000>; |
| 388 | qcom,qusb-phy-init-seq = |
Mayank Rana | c8d69e2 | 2017-04-03 18:13:34 -0700 | [diff] [blame] | 389 | /* <value reg_offset> */ |
| 390 | <0x23 0x210 /* PWR_CTRL1 */ |
| 391 | 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ |
| 392 | 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ |
| 393 | 0x80 0x2c /* PLL_CMODE */ |
| 394 | 0x0a 0x184 /* PLL_LOCK_DELAY */ |
| 395 | 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ |
| 396 | 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ |
| 397 | 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ |
| 398 | 0x21 0x214 /* PWR_CTRL2 */ |
| 399 | 0x00 0x220 /* IMP_CTRL1 */ |
| 400 | 0x58 0x224 /* IMP_CTRL2 */ |
Mayank Rana | d2581e6 | 2017-06-20 09:47:58 -0700 | [diff] [blame^] | 401 | 0x20 0x240 /* TUNE1 */ |
Mayank Rana | c8d69e2 | 2017-04-03 18:13:34 -0700 | [diff] [blame] | 402 | 0x29 0x244 /* TUNE2 */ |
| 403 | 0xca 0x248 /* TUNE3 */ |
| 404 | 0x04 0x24c /* TUNE4 */ |
Mayank Rana | 471513c | 2017-04-20 11:02:07 -0700 | [diff] [blame] | 405 | 0x03 0x250 /* TUNE5 */ |
Mayank Rana | c8d69e2 | 2017-04-03 18:13:34 -0700 | [diff] [blame] | 406 | 0x00 0x23c /* CHG_CTRL2 */ |
| 407 | 0x22 0x210>; /* PWR_CTRL1 */ |
| 408 | |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 409 | phy_type= "utmi"; |
| 410 | clocks = <&clock_rpmh RPMH_CXO_CLK>, |
| 411 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; |
| 412 | clock-names = "ref_clk_src", "cfg_ahb_clk"; |
| 413 | |
| 414 | resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>; |
| 415 | reset-names = "phy_reset"; |
| 416 | status = "disabled"; |
| 417 | }; |
| 418 | |
| 419 | /* Secondary USB port related QMP PHY */ |
| 420 | usb_qmp_phy: ssphy@88eb000 { |
| 421 | compatible = "qcom,usb-ssphy-qmp-v2"; |
| 422 | reg = <0x88eb000 0x1000>, |
| 423 | <0x01fcbff0 0x4>; |
| 424 | reg-names = "qmp_phy_base", |
| 425 | "vls_clamp_reg"; |
| 426 | |
| 427 | vdd-supply = <&pm8998_l1>; |
| 428 | core-supply = <&pm8998_l26>; |
| 429 | qcom,vdd-voltage-level = <0 880000 880000>; |
| 430 | qcom,vbus-valid-override; |
| 431 | qcom,qmp-phy-init-seq = |
| 432 | /* <reg_offset, value, delay> */ |
| 433 | <0x048 0x07 0x00 /* QSERDES_COM_PLL_IVCO */ |
| 434 | 0x080 0x14 0x00 /* QSERDES_COM_SYSCLK_EN_SEL */ |
| 435 | 0x034 0x04 0x00 /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */ |
| 436 | 0x138 0x30 0x00 /* QSERDES_COM_CLK_SELECT */ |
| 437 | 0x03c 0x02 0x00 /* QSERDES_COM_SYS_CLK_CTRL */ |
| 438 | 0x08c 0x08 0x00 /* QSERDES_COM_RESETSM_CNTRL2 */ |
| 439 | 0x15c 0x06 0x00 /* QSERDES_COM_CMN_CONFIG */ |
| 440 | 0x164 0x01 0x00 /* QSERDES_COM_SVS_MODE_CLK_SEL */ |
| 441 | 0x13c 0x80 0x00 /* QSERDES_COM_HSCLK_SEL */ |
| 442 | 0x0b0 0x82 0x00 /* QSERDES_COM_DEC_START_MODE0 */ |
| 443 | 0x0b8 0xab 0x00 /* QSERDES_COM_DIV_FRAC_START1_MODE0 */ |
| 444 | 0x0bc 0xea 0x00 /* QSERDES_COM_DIV_FRAC_START2_MODE0 */ |
| 445 | 0x0c0 0x02 0x00 /* QSERDES_COM_DIV_FRAC_START3_MODE0 */ |
| 446 | 0x060 0x06 0x00 /* QSERDES_COM_CP_CTRL_MODE0 */ |
| 447 | 0x068 0x16 0x00 /* QSERDES_COM_PLL_RCTRL_MODE0 */ |
| 448 | 0x070 0x36 0x00 /* QSERDES_COM_PLL_CCTRL_MODE0 */ |
| 449 | 0x0dc 0x00 0x00 /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */ |
| 450 | 0x0d8 0x3f 0x00 /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */ |
| 451 | 0x0f8 0x01 0x00 /* QSERDES_COM_VCO_TUNE2_MODE0 */ |
| 452 | 0x0f4 0xc9 0x00 /* QSERDES_COM_VCO_TUNE1_MODE0 */ |
| 453 | 0x148 0x0a 0x00 /* QSERDES_COM_CORECLK_DIV_MODE0 */ |
| 454 | 0x0a0 0x00 0x00 /* QSERDES_COM_LOCK_CMP3_MODE0 */ |
| 455 | 0x09c 0x34 0x00 /* QSERDES_COM_LOCK_CMP2_MODE0 */ |
| 456 | 0x098 0x15 0x00 /* QSERDES_COM_LOCK_CMP1_MODE0 */ |
| 457 | 0x090 0x04 0x00 /* QSERDES_COM_LOCK_CMP_EN */ |
| 458 | 0x154 0x00 0x00 /* QSERDES_COM_CORE_CLK_EN */ |
| 459 | 0x094 0x00 0x00 /* QSERDES_COM_LOCK_CMP_CFG */ |
| 460 | 0x0f0 0x00 0x00 /* QSERDES_COM_VCO_TUNE_MAP */ |
| 461 | 0x040 0x0a 0x00 /* QSERDES_COM_SYSCLK_BUF_ENABLE */ |
| 462 | 0x0d0 0x80 0x00 /* QSERDES_COM_INTEGLOOP_INITVAL */ |
| 463 | 0x010 0x01 0x00 /* QSERDES_COM_SSC_EN_CENTER */ |
| 464 | 0x01c 0x31 0x00 /* QSERDES_COM_SSC_PER1 */ |
| 465 | 0x020 0x01 0x00 /* QSERDES_COM_SSC_PER2 */ |
| 466 | 0x014 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER1 */ |
| 467 | 0x018 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER2 */ |
| 468 | 0x024 0x85 0x00 /* QSERDES_COM_SSC_STEP_SIZE1 */ |
| 469 | 0x028 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE2 */ |
| 470 | 0x4c0 0x0c 0x00 /* QSERDES_RX_VGA_CAL_CNTRL2 */ |
| 471 | 0x564 0x50 0x00 /* QSERDES_RX_RX_MODE_00 */ |
| 472 | 0x430 0x0b 0x00 /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */ |
| 473 | 0x4d4 0x0e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */ |
| 474 | 0x4d8 0x4e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */ |
| 475 | 0x4dc 0x18 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */ |
| 476 | 0x4f8 0x77 0x00 /* RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */ |
| 477 | 0x4fc 0x80 0x00 /* RX_RX_OFFSET_ADAPTOR_CNTRL2 */ |
| 478 | 0x504 0x03 0x00 /* QSERDES_RX_SIGDET_CNTRL */ |
| 479 | 0x50c 0x1c 0x00 /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */ |
| 480 | 0x434 0x75 0x00 /* RX_UCDR_SO_SATURATION_AND_ENABLE */ |
| 481 | 0x444 0x80 0x00 /* QSERDES_RX_UCDR_PI_CONTROLS */ |
| 482 | 0x408 0x0a 0x00 /* QSERDES_RX_UCDR_FO_GAIN */ |
| 483 | 0x40c 0x06 0x00 /* QSERDES_RX_UCDR_SO_GAIN */ |
| 484 | 0x500 0x00 0x00 /* QSERDES_RX_SIGDET_ENABLES */ |
| 485 | 0x260 0x10 0x00 /* QSERDES_TX_HIGHZ_DRVR_EN */ |
| 486 | 0x2a4 0x12 0x00 /* QSERDES_TX_RCV_DETECT_LVL_2 */ |
| 487 | 0x28c 0xc6 0x00 /* QSERDES_TX_LANE_MODE_1 */ |
| 488 | 0x248 0x09 0x00 /* TX_RES_CODE_LANE_OFFSET_RX */ |
| 489 | 0x244 0x0d 0x00 /* TX_RES_CODE_LANE_OFFSET_TX */ |
| 490 | 0x8c8 0x83 0x00 /* USB3_UNI_PCS_FLL_CNTRL2 */ |
| 491 | 0x8cc 0x09 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_L */ |
| 492 | 0x8d0 0xa2 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */ |
| 493 | 0x8d4 0x40 0x00 /* USB3_UNI_PCS_FLL_MAN_CODE */ |
| 494 | 0x8c4 0x02 0x00 /* USB3_UNI_PCS_FLL_CNTRL1 */ |
| 495 | 0x864 0x1b 0x00 /* USB3_UNI_PCS_POWER_STATE_CONFIG2 */ |
| 496 | 0x80c 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V0 */ |
| 497 | 0x810 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V1 */ |
| 498 | 0x814 0xb5 0x00 /* USB3_UNI_PCS_TXMGN_V2 */ |
| 499 | 0x818 0x4c 0x00 /* USB3_UNI_PCS_TXMGN_V3 */ |
| 500 | 0x81c 0x64 0x00 /* USB3_UNI_PCS_TXMGN_V4 */ |
| 501 | 0x820 0x6a 0x00 /* USB3_UNI_PCS_TXMGN_LS */ |
| 502 | 0x824 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V0 */ |
| 503 | 0x828 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V0 */ |
| 504 | 0x82c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V1 */ |
| 505 | 0x830 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V1 */ |
| 506 | 0x834 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V2 */ |
| 507 | 0x838 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V2 */ |
| 508 | 0x83c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V3 */ |
| 509 | 0x840 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V3 */ |
| 510 | 0x844 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V4 */ |
| 511 | 0x848 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V4 */ |
| 512 | 0x84c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_LS */ |
| 513 | 0x850 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_LS */ |
| 514 | 0x85c 0x02 0x00 /* USB3_UNI_PCS_RATE_SLEW_CNTRL */ |
| 515 | 0x8a0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */ |
| 516 | 0x88c 0x44 0x00 /* USB3_UNI_PCS_TSYNC_RSYNC_TIME */ |
| 517 | 0x880 0xd1 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */ |
| 518 | 0x884 0x1f 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */ |
| 519 | 0x888 0x47 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */ |
| 520 | 0x870 0xe7 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L */ |
| 521 | 0x874 0x03 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H */ |
| 522 | 0x878 0x40 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_L */ |
| 523 | 0x87c 0x00 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_H */ |
| 524 | 0x9d8 0xba 0x00 /* USB3_UNI_PCS_RX_SIGDET_LVL */ |
| 525 | 0x8b8 0x75 0x00 /* RXEQTRAINING_WAIT_TIME */ |
| 526 | 0x8b0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */ |
| 527 | 0x8bc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */ |
| 528 | 0xa0c 0x21 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG1 */ |
| 529 | 0xa10 0x60 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG2 */ |
| 530 | 0xffffffff 0xffffffff 0x00>; |
| 531 | |
| 532 | qcom,qmp-phy-reg-offset = |
| 533 | <0x974 /* USB3_UNI_PCS_PCS_STATUS */ |
| 534 | 0x8d8 /* USB3_UNI_PCS_AUTONOMOUS_MODE_CTRL */ |
| 535 | 0x8dc /* USB3_UNI_PCS_LFPS_RXTERM_IRQ_CLEAR */ |
| 536 | 0x804 /* USB3_UNI_PCS_POWER_DOWN_CONTROL */ |
| 537 | 0x800 /* USB3_UNI_PCS_SW_RESET */ |
| 538 | 0x808>; /* USB3_UNI_PCS_START_CONTROL */ |
| 539 | |
| 540 | clocks = <&clock_gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
| 541 | <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>, |
| 542 | <&clock_rpmh RPMH_CXO_CLK>, |
Mayank Rana | 43378fa | 2017-04-19 20:23:33 -0700 | [diff] [blame] | 543 | <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>, |
| 544 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 545 | |
| 546 | clock-names = "aux_clk", "pipe_clk", "ref_clk_src", |
Mayank Rana | 43378fa | 2017-04-19 20:23:33 -0700 | [diff] [blame] | 547 | "ref_clk", "cfg_ahb_clk"; |
Mayank Rana | 2f59669 | 2017-03-13 17:35:09 -0700 | [diff] [blame] | 548 | |
| 549 | resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>, |
| 550 | <&clock_gcc GCC_USB3PHY_PHY_SEC_BCR>; |
| 551 | reset-names = "phy_reset", "phy_phy_reset"; |
| 552 | status = "disabled"; |
| 553 | }; |
Mayank Rana | 0caa5e7 | 2016-08-09 14:37:43 -0700 | [diff] [blame] | 554 | }; |