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gerrit-public.fairphone.software / kernel / msm-4.9 / d2e08473f2488d53a71c2f53455f934ec6c44c53 / . / arch / arm / mach-omap2 / cm1_44xx.h
blob: 1bc00dc4876c0678e1bbd78e43f0806d822ddeeb [file] [log] [blame]
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]1/*
2 * OMAP44xx CM1 instance offset macros
3 *
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22 * or "OMAP4430".
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
27
28/* CM1 base address */
29#define OMAP4430_CM1_BASE 0x4a004000
30
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]31#define OMAP44XX_CM1_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]33
34/* CM1 instances */
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]35#define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
36#define OMAP4430_CM1_CKGEN_INST 0x0100
37#define OMAP4430_CM1_MPU_INST 0x0300
38#define OMAP4430_CM1_TESLA_INST 0x0400
39#define OMAP4430_CM1_ABE_INST 0x0500
40#define OMAP4430_CM1_RESTORE_INST 0x0e00
41#define OMAP4430_CM1_INSTR_INST 0x0f00
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]42
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]43/* CM1 clockdomain register offsets (from instance start) */
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]44#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
45#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
46#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]47
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]48/* CM1 */
49
50/* CM1.OCP_SOCKET_CM1 register offsets */
51#define OMAP4_REVISION_CM1_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]52#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]53#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]54#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]55
56/* CM1.CKGEN_CM1 register offsets */
57#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]58#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]59#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]60#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]61#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]62#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]63#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]64#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]65#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]66#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]67#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]68#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]69#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]70#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]71#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]72#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]73#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]74#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]75#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]76#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]77#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]78#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]79#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]80#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]81#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]82#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]83#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]84#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]85#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
86#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]87#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]88#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]89#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]90#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]91#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]92#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]93#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]94#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]95#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]96#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]97#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]98#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]99#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]101#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
102#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]106#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]107#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]108#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]109#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]110#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]111#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]112#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]113#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]114#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]115#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]119#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
120#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]124#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]125#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]126#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]127#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]128#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]129#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]130#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]131#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]132#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]133#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]142#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]143#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]144#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]145#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]146#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]147#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]148#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]149#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]150#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]151#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]152#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]153#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]157#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
158#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]162#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]163#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]164#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]165#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]166#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]167
168/* CM1.MPU_CM1 register offsets */
169#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]170#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]171#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]172#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]173#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]174#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]175#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]176#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]177
178/* CM1.TESLA_CM1 register offsets */
179#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]180#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]181#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]182#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]183#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]184#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]185#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]186#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]187
188/* CM1.ABE_CM1 register offsets */
189#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]190#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]191#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]192#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]193#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]194#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]195#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]196#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]197#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]198#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]199#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]200#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]201#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]202#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]203#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]204#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]205#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]206#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]207#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]208#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]209#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]210#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]211#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]212#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]213#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]214#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]215#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]216#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]219
Paul Walmsley2ace8312010-12-21 21:05:14 -0700[diff] [blame]220/* Function prototypes */
221extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
222extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
223extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
224
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]225#endif