blob: abfcb3a2588fb7de4e98190fd95723d2de526e55 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef _ASM_IA64_PAL_H
2#define _ASM_IA64_PAL_H
3
4/*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
19 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
20 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
21 * 00/05/25 eranian Support for stack calls, and static physical calls
22 * 00/06/18 eranian Support for stacked physical calls
Russ Anderson5b4d5682006-11-06 16:45:18 -060023 * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's
24 * Manual Rev 2.2 (Jan 2006)
Linus Torvalds1da177e2005-04-16 15:20:36 -070025 */
26
27/*
28 * Note that some of these calls use a static-register only calling
29 * convention which has nothing to do with the regular calling
30 * convention.
31 */
32#define PAL_CACHE_FLUSH 1 /* flush i/d cache */
33#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
34#define PAL_CACHE_INIT 3 /* initialize i/d cache */
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +010035#define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
37#define PAL_PTCE_INFO 6 /* purge TLB info */
38#define PAL_VM_INFO 7 /* return supported virtual memory features */
39#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
40#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
41#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
42#define PAL_DEBUG_INFO 11 /* get number of debug registers */
43#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
44#define PAL_FREQ_BASE 13 /* base frequency of the platform */
45#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
46#define PAL_PERF_MON_INFO 15 /* return performance monitor info */
47#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
48#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
49#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
50#define PAL_RSE_INFO 19 /* return rse information */
51#define PAL_VERSION 20 /* return version of PAL code */
52#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
53#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
54#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
55#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
56#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
57#define PAL_MC_RESUME 26 /* Return to interrupted process */
58#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
59#define PAL_HALT 28 /* enter the low power HALT state */
60#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
61#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
62#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
63#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
64#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
65#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
66
67#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
68#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
69#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
70#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
71#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
Suresh Siddhae927ecb2005-04-25 13:25:06 -070072#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
Zhang, Yanminf1918002006-02-27 11:37:45 +080073#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
Russ Anderson5b4d5682006-11-06 16:45:18 -060074#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
75#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
Linus Torvalds1da177e2005-04-16 15:20:36 -070076
77#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
78#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
79#define PAL_TEST_PROC 258 /* perform late processor self-test */
80#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
81#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
82#define PAL_VM_TR_READ 261 /* read contents of translation register */
Venkatesh Pallipadi4db86992005-07-29 16:15:00 -070083#define PAL_GET_PSTATE 262 /* get the current P-state */
84#define PAL_SET_PSTATE 263 /* set the P-state */
Tony Luck76d08bb2006-06-05 13:54:14 -070085#define PAL_BRAND_INFO 274 /* Processor branding information */
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
Venkatesh Pallipadi17e77b12006-12-01 15:28:14 -080087#define PAL_GET_PSTATE_TYPE_LASTSET 0
88#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
89#define PAL_GET_PSTATE_TYPE_AVGNORESET 2
90#define PAL_GET_PSTATE_TYPE_INSTANT 3
91
Fenghua Yu1138b7e2006-12-08 16:17:31 -080092#define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */
93
Linus Torvalds1da177e2005-04-16 15:20:36 -070094#ifndef __ASSEMBLY__
95
96#include <linux/types.h>
97#include <asm/fpu.h>
98
99/*
100 * Data types needed to pass information into PAL procedures and
101 * interpret information returned by them.
102 */
103
104/* Return status from the PAL procedure */
105typedef s64 pal_status_t;
106
107#define PAL_STATUS_SUCCESS 0 /* No error */
108#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
109#define PAL_STATUS_EINVAL (-2) /* Invalid argument */
110#define PAL_STATUS_ERROR (-3) /* Error */
111#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
112 * specified level and type of
113 * cache without sideeffects
114 * and "restrict" was 1
115 */
Russ Anderson5b4d5682006-11-06 16:45:18 -0600116#define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100118/* Processor cache level in the hierarchy */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119typedef u64 pal_cache_level_t;
120#define PAL_CACHE_LEVEL_L0 0 /* L0 */
121#define PAL_CACHE_LEVEL_L1 1 /* L1 */
122#define PAL_CACHE_LEVEL_L2 2 /* L2 */
123
124
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100125/* Processor cache type at a particular level in the hierarchy */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126
127typedef u64 pal_cache_type_t;
128#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
129#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
130#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
131
132
133#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
134#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
135
136/* Processor cache line size in bytes */
137typedef int pal_cache_line_size_t;
138
139/* Processor cache line state */
140typedef u64 pal_cache_line_state_t;
141#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
142#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
143#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
144#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
145
146typedef struct pal_freq_ratio {
Tony Luck2ab93912006-03-31 10:28:29 -0800147 u32 den, num; /* numerator & denominator */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148} itc_ratio, proc_ratio;
149
150typedef union pal_cache_config_info_1_s {
151 struct {
152 u64 u : 1, /* 0 Unified cache ? */
153 at : 2, /* 2-1 Cache mem attr*/
154 reserved : 5, /* 7-3 Reserved */
155 associativity : 8, /* 16-8 Associativity*/
156 line_size : 8, /* 23-17 Line size */
157 stride : 8, /* 31-24 Stride */
158 store_latency : 8, /*39-32 Store latency*/
159 load_latency : 8, /* 47-40 Load latency*/
160 store_hints : 8, /* 55-48 Store hints*/
161 load_hints : 8; /* 63-56 Load hints */
162 } pcci1_bits;
163 u64 pcci1_data;
164} pal_cache_config_info_1_t;
165
166typedef union pal_cache_config_info_2_s {
167 struct {
Tony Luck2ab93912006-03-31 10:28:29 -0800168 u32 cache_size; /*cache size in bytes*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169
170
Tony Luck2ab93912006-03-31 10:28:29 -0800171 u32 alias_boundary : 8, /* 39-32 aliased addr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 * separation for max
173 * performance.
174 */
175 tag_ls_bit : 8, /* 47-40 LSb of addr*/
176 tag_ms_bit : 8, /* 55-48 MSb of addr*/
177 reserved : 8; /* 63-56 Reserved */
178 } pcci2_bits;
179 u64 pcci2_data;
180} pal_cache_config_info_2_t;
181
182
183typedef struct pal_cache_config_info_s {
184 pal_status_t pcci_status;
185 pal_cache_config_info_1_t pcci_info_1;
186 pal_cache_config_info_2_t pcci_info_2;
187 u64 pcci_reserved;
188} pal_cache_config_info_t;
189
190#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
191#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
192#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
193#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
194#define pcci_stride pcci_info_1.pcci1_bits.stride
195#define pcci_line_size pcci_info_1.pcci1_bits.line_size
196#define pcci_assoc pcci_info_1.pcci1_bits.associativity
197#define pcci_cache_attr pcci_info_1.pcci1_bits.at
198#define pcci_unified pcci_info_1.pcci1_bits.u
199#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
200#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
201#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
202#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
203
204
205
206/* Possible values for cache attributes */
207
208#define PAL_CACHE_ATTR_WT 0 /* Write through cache */
209#define PAL_CACHE_ATTR_WB 1 /* Write back cache */
210#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
211 * back depending on TLB
212 * memory attributes
213 */
214
215
216/* Possible values for cache hints */
217
218#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
219#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
220#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
221
222/* Processor cache protection information */
223typedef union pal_cache_protection_element_u {
224 u32 pcpi_data;
225 struct {
226 u32 data_bits : 8, /* # data bits covered by
227 * each unit of protection
228 */
229
230 tagprot_lsb : 6, /* Least -do- */
231 tagprot_msb : 6, /* Most Sig. tag address
232 * bit that this
233 * protection covers.
234 */
235 prot_bits : 6, /* # of protection bits */
236 method : 4, /* Protection method */
237 t_d : 2; /* Indicates which part
238 * of the cache this
239 * protection encoding
240 * applies.
241 */
242 } pcp_info;
243} pal_cache_protection_element_t;
244
245#define pcpi_cache_prot_part pcp_info.t_d
246#define pcpi_prot_method pcp_info.method
247#define pcpi_prot_bits pcp_info.prot_bits
248#define pcpi_tagprot_msb pcp_info.tagprot_msb
249#define pcpi_tagprot_lsb pcp_info.tagprot_lsb
250#define pcpi_data_bits pcp_info.data_bits
251
252/* Processor cache part encodings */
253#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
254#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
255#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
256 * more significant )
257 */
258#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
259 * more significant )
260 */
261#define PAL_CACHE_PROT_PART_MAX 6
262
263
264typedef struct pal_cache_protection_info_s {
265 pal_status_t pcpi_status;
266 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
267} pal_cache_protection_info_t;
268
269
270/* Processor cache protection method encodings */
271#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
272#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
273#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
274#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
275
276
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100277/* Processor cache line identification in the hierarchy */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278typedef union pal_cache_line_id_u {
279 u64 pclid_data;
280 struct {
281 u64 cache_type : 8, /* 7-0 cache type */
282 level : 8, /* 15-8 level of the
283 * cache in the
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100284 * hierarchy.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 */
286 way : 8, /* 23-16 way in the set
287 */
288 part : 8, /* 31-24 part of the
289 * cache
290 */
291 reserved : 32; /* 63-32 is reserved*/
292 } pclid_info_read;
293 struct {
294 u64 cache_type : 8, /* 7-0 cache type */
295 level : 8, /* 15-8 level of the
296 * cache in the
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100297 * hierarchy.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 */
299 way : 8, /* 23-16 way in the set
300 */
301 part : 8, /* 31-24 part of the
302 * cache
303 */
304 mesi : 8, /* 39-32 cache line
305 * state
306 */
307 start : 8, /* 47-40 lsb of data to
308 * invert
309 */
310 length : 8, /* 55-48 #bits to
311 * invert
312 */
313 trigger : 8; /* 63-56 Trigger error
314 * by doing a load
315 * after the write
316 */
317
318 } pclid_info_write;
319} pal_cache_line_id_u_t;
320
321#define pclid_read_part pclid_info_read.part
322#define pclid_read_way pclid_info_read.way
323#define pclid_read_level pclid_info_read.level
324#define pclid_read_cache_type pclid_info_read.cache_type
325
326#define pclid_write_trigger pclid_info_write.trigger
327#define pclid_write_length pclid_info_write.length
328#define pclid_write_start pclid_info_write.start
329#define pclid_write_mesi pclid_info_write.mesi
330#define pclid_write_part pclid_info_write.part
331#define pclid_write_way pclid_info_write.way
332#define pclid_write_level pclid_info_write.level
333#define pclid_write_cache_type pclid_info_write.cache_type
334
335/* Processor cache line part encodings */
336#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
337#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
338#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
339#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
340#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
341 * protection
342 */
343typedef struct pal_cache_line_info_s {
344 pal_status_t pcli_status; /* Return status of the read cache line
345 * info call.
346 */
347 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
348 u64 pcli_data_len; /* data length in bits */
349 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
350
351} pal_cache_line_info_t;
352
353
354/* Machine Check related crap */
355
356/* Pending event status bits */
357typedef u64 pal_mc_pending_events_t;
358
359#define PAL_MC_PENDING_MCA (1 << 0)
360#define PAL_MC_PENDING_INIT (1 << 1)
361
362/* Error information type */
363typedef u64 pal_mc_info_index_t;
364
365#define PAL_MC_INFO_PROCESSOR 0 /* Processor */
366#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
367#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
368#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
369#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
370#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
371#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
372#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
373 * dependent
374 */
375
Russ Anderson618b2062006-12-14 16:01:41 -0600376#define PAL_TLB_CHECK_OP_PURGE 8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377
378typedef struct pal_process_state_info_s {
379 u64 reserved1 : 2,
380 rz : 1, /* PAL_CHECK processor
381 * rendezvous
382 * successful.
383 */
384
385 ra : 1, /* PAL_CHECK attempted
386 * a rendezvous.
387 */
388 me : 1, /* Distinct multiple
389 * errors occurred
390 */
391
392 mn : 1, /* Min. state save
393 * area has been
394 * registered with PAL
395 */
396
397 sy : 1, /* Storage integrity
398 * synched
399 */
400
401
402 co : 1, /* Continuable */
403 ci : 1, /* MC isolated */
404 us : 1, /* Uncontained storage
405 * damage.
406 */
407
408
409 hd : 1, /* Non-essential hw
410 * lost (no loss of
411 * functionality)
412 * causing the
413 * processor to run in
414 * degraded mode.
415 */
416
417 tl : 1, /* 1 => MC occurred
418 * after an instr was
419 * executed but before
420 * the trap that
421 * resulted from instr
422 * execution was
423 * generated.
424 * (Trap Lost )
425 */
426 mi : 1, /* More information available
427 * call PAL_MC_ERROR_INFO
428 */
429 pi : 1, /* Precise instruction pointer */
430 pm : 1, /* Precise min-state save area */
431
432 dy : 1, /* Processor dynamic
433 * state valid
434 */
435
436
437 in : 1, /* 0 = MC, 1 = INIT */
438 rs : 1, /* RSE valid */
439 cm : 1, /* MC corrected */
440 ex : 1, /* MC is expected */
441 cr : 1, /* Control regs valid*/
442 pc : 1, /* Perf cntrs valid */
443 dr : 1, /* Debug regs valid */
444 tr : 1, /* Translation regs
445 * valid
446 */
447 rr : 1, /* Region regs valid */
448 ar : 1, /* App regs valid */
449 br : 1, /* Branch regs valid */
450 pr : 1, /* Predicate registers
451 * valid
452 */
453
454 fp : 1, /* fp registers valid*/
455 b1 : 1, /* Preserved bank one
456 * general registers
457 * are valid
458 */
459 b0 : 1, /* Preserved bank zero
460 * general registers
461 * are valid
462 */
463 gr : 1, /* General registers
464 * are valid
465 * (excl. banked regs)
466 */
467 dsize : 16, /* size of dynamic
468 * state returned
469 * by the processor
470 */
471
Russ Anderson6533bde2006-10-26 11:53:17 -0500472 se : 1, /* Shared error. MCA in a
473 shared structure */
474 reserved2 : 10,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 cc : 1, /* Cache check */
476 tc : 1, /* TLB check */
477 bc : 1, /* Bus check */
478 rc : 1, /* Register file check */
479 uc : 1; /* Uarch check */
480
481} pal_processor_state_info_t;
482
483typedef struct pal_cache_check_info_s {
484 u64 op : 4, /* Type of cache
485 * operation that
486 * caused the machine
487 * check.
488 */
489 level : 2, /* Cache level */
490 reserved1 : 2,
491 dl : 1, /* Failure in data part
492 * of cache line
493 */
494 tl : 1, /* Failure in tag part
495 * of cache line
496 */
497 dc : 1, /* Failure in dcache */
498 ic : 1, /* Failure in icache */
499 mesi : 3, /* Cache line state */
500 mv : 1, /* mesi valid */
501 way : 5, /* Way in which the
502 * error occurred
503 */
504 wiv : 1, /* Way field valid */
Russ Anderson323cbb02006-10-25 14:18:27 -0500505 reserved2 : 1,
506 dp : 1, /* Data poisoned on MBE */
507 reserved3 : 8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508
509 index : 20, /* Cache line index */
Russ Anderson323cbb02006-10-25 14:18:27 -0500510 reserved4 : 2,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511
512 is : 1, /* instruction set (1 == ia32) */
513 iv : 1, /* instruction set field valid */
514 pl : 2, /* privilege level */
515 pv : 1, /* privilege level field valid */
516 mcc : 1, /* Machine check corrected */
517 tv : 1, /* Target address
518 * structure is valid
519 */
520 rq : 1, /* Requester identifier
521 * structure is valid
522 */
523 rp : 1, /* Responder identifier
524 * structure is valid
525 */
526 pi : 1; /* Precise instruction pointer
527 * structure is valid
528 */
529} pal_cache_check_info_t;
530
531typedef struct pal_tlb_check_info_s {
532
533 u64 tr_slot : 8, /* Slot# of TR where
534 * error occurred
535 */
536 trv : 1, /* tr_slot field is valid */
537 reserved1 : 1,
538 level : 2, /* TLB level where failure occurred */
539 reserved2 : 4,
540 dtr : 1, /* Fail in data TR */
541 itr : 1, /* Fail in inst TR */
542 dtc : 1, /* Fail in data TC */
543 itc : 1, /* Fail in inst. TC */
544 op : 4, /* Cache operation */
545 reserved3 : 30,
546
547 is : 1, /* instruction set (1 == ia32) */
548 iv : 1, /* instruction set field valid */
549 pl : 2, /* privilege level */
550 pv : 1, /* privilege level field valid */
551 mcc : 1, /* Machine check corrected */
552 tv : 1, /* Target address
553 * structure is valid
554 */
555 rq : 1, /* Requester identifier
556 * structure is valid
557 */
558 rp : 1, /* Responder identifier
559 * structure is valid
560 */
561 pi : 1; /* Precise instruction pointer
562 * structure is valid
563 */
564} pal_tlb_check_info_t;
565
566typedef struct pal_bus_check_info_s {
567 u64 size : 5, /* Xaction size */
568 ib : 1, /* Internal bus error */
569 eb : 1, /* External bus error */
570 cc : 1, /* Error occurred
571 * during cache-cache
572 * transfer.
573 */
574 type : 8, /* Bus xaction type*/
575 sev : 5, /* Bus error severity*/
576 hier : 2, /* Bus hierarchy level */
Russ Anderson323cbb02006-10-25 14:18:27 -0500577 dp : 1, /* Data poisoned on MBE */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 bsi : 8, /* Bus error status
579 * info
580 */
581 reserved2 : 22,
582
583 is : 1, /* instruction set (1 == ia32) */
584 iv : 1, /* instruction set field valid */
585 pl : 2, /* privilege level */
586 pv : 1, /* privilege level field valid */
587 mcc : 1, /* Machine check corrected */
588 tv : 1, /* Target address
589 * structure is valid
590 */
591 rq : 1, /* Requester identifier
592 * structure is valid
593 */
594 rp : 1, /* Responder identifier
595 * structure is valid
596 */
597 pi : 1; /* Precise instruction pointer
598 * structure is valid
599 */
600} pal_bus_check_info_t;
601
602typedef struct pal_reg_file_check_info_s {
603 u64 id : 4, /* Register file identifier */
604 op : 4, /* Type of register
605 * operation that
606 * caused the machine
607 * check.
608 */
609 reg_num : 7, /* Register number */
610 rnv : 1, /* reg_num valid */
611 reserved2 : 38,
612
613 is : 1, /* instruction set (1 == ia32) */
614 iv : 1, /* instruction set field valid */
615 pl : 2, /* privilege level */
616 pv : 1, /* privilege level field valid */
617 mcc : 1, /* Machine check corrected */
618 reserved3 : 3,
619 pi : 1; /* Precise instruction pointer
620 * structure is valid
621 */
622} pal_reg_file_check_info_t;
623
624typedef struct pal_uarch_check_info_s {
625 u64 sid : 5, /* Structure identification */
626 level : 3, /* Level of failure */
627 array_id : 4, /* Array identification */
628 op : 4, /* Type of
629 * operation that
630 * caused the machine
631 * check.
632 */
633 way : 6, /* Way of structure */
634 wv : 1, /* way valid */
635 xv : 1, /* index valid */
636 reserved1 : 8,
637 index : 8, /* Index or set of the uarch
638 * structure that failed.
639 */
640 reserved2 : 24,
641
642 is : 1, /* instruction set (1 == ia32) */
643 iv : 1, /* instruction set field valid */
644 pl : 2, /* privilege level */
645 pv : 1, /* privilege level field valid */
646 mcc : 1, /* Machine check corrected */
647 tv : 1, /* Target address
648 * structure is valid
649 */
650 rq : 1, /* Requester identifier
651 * structure is valid
652 */
653 rp : 1, /* Responder identifier
654 * structure is valid
655 */
656 pi : 1; /* Precise instruction pointer
657 * structure is valid
658 */
659} pal_uarch_check_info_t;
660
661typedef union pal_mc_error_info_u {
662 u64 pmei_data;
663 pal_processor_state_info_t pme_processor;
664 pal_cache_check_info_t pme_cache;
665 pal_tlb_check_info_t pme_tlb;
666 pal_bus_check_info_t pme_bus;
667 pal_reg_file_check_info_t pme_reg_file;
668 pal_uarch_check_info_t pme_uarch;
669} pal_mc_error_info_t;
670
671#define pmci_proc_unknown_check pme_processor.uc
672#define pmci_proc_bus_check pme_processor.bc
673#define pmci_proc_tlb_check pme_processor.tc
674#define pmci_proc_cache_check pme_processor.cc
675#define pmci_proc_dynamic_state_size pme_processor.dsize
676#define pmci_proc_gpr_valid pme_processor.gr
677#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
678#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
679#define pmci_proc_fp_valid pme_processor.fp
680#define pmci_proc_predicate_regs_valid pme_processor.pr
681#define pmci_proc_branch_regs_valid pme_processor.br
682#define pmci_proc_app_regs_valid pme_processor.ar
683#define pmci_proc_region_regs_valid pme_processor.rr
684#define pmci_proc_translation_regs_valid pme_processor.tr
685#define pmci_proc_debug_regs_valid pme_processor.dr
686#define pmci_proc_perf_counters_valid pme_processor.pc
687#define pmci_proc_control_regs_valid pme_processor.cr
688#define pmci_proc_machine_check_expected pme_processor.ex
689#define pmci_proc_machine_check_corrected pme_processor.cm
690#define pmci_proc_rse_valid pme_processor.rs
691#define pmci_proc_machine_check_or_init pme_processor.in
692#define pmci_proc_dynamic_state_valid pme_processor.dy
693#define pmci_proc_operation pme_processor.op
694#define pmci_proc_trap_lost pme_processor.tl
695#define pmci_proc_hardware_damage pme_processor.hd
696#define pmci_proc_uncontained_storage_damage pme_processor.us
697#define pmci_proc_machine_check_isolated pme_processor.ci
698#define pmci_proc_continuable pme_processor.co
699#define pmci_proc_storage_intergrity_synced pme_processor.sy
700#define pmci_proc_min_state_save_area_regd pme_processor.mn
701#define pmci_proc_distinct_multiple_errors pme_processor.me
702#define pmci_proc_pal_attempted_rendezvous pme_processor.ra
703#define pmci_proc_pal_rendezvous_complete pme_processor.rz
704
705
706#define pmci_cache_level pme_cache.level
707#define pmci_cache_line_state pme_cache.mesi
708#define pmci_cache_line_state_valid pme_cache.mv
709#define pmci_cache_line_index pme_cache.index
710#define pmci_cache_instr_cache_fail pme_cache.ic
711#define pmci_cache_data_cache_fail pme_cache.dc
712#define pmci_cache_line_tag_fail pme_cache.tl
713#define pmci_cache_line_data_fail pme_cache.dl
714#define pmci_cache_operation pme_cache.op
715#define pmci_cache_way_valid pme_cache.wv
716#define pmci_cache_target_address_valid pme_cache.tv
717#define pmci_cache_way pme_cache.way
718#define pmci_cache_mc pme_cache.mc
719
720#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
721#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
722#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
723#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
724#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
725#define pmci_tlb_mc pme_tlb.mc
726
727#define pmci_bus_status_info pme_bus.bsi
728#define pmci_bus_req_address_valid pme_bus.rq
729#define pmci_bus_resp_address_valid pme_bus.rp
730#define pmci_bus_target_address_valid pme_bus.tv
731#define pmci_bus_error_severity pme_bus.sev
732#define pmci_bus_transaction_type pme_bus.type
733#define pmci_bus_cache_cache_transfer pme_bus.cc
734#define pmci_bus_transaction_size pme_bus.size
735#define pmci_bus_internal_error pme_bus.ib
736#define pmci_bus_external_error pme_bus.eb
737#define pmci_bus_mc pme_bus.mc
738
739/*
740 * NOTE: this min_state_save area struct only includes the 1KB
741 * architectural state save area. The other 3 KB is scratch space
742 * for PAL.
743 */
744
745typedef struct pal_min_state_area_s {
746 u64 pmsa_nat_bits; /* nat bits for saved GRs */
747 u64 pmsa_gr[15]; /* GR1 - GR15 */
748 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
749 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
750 u64 pmsa_pr; /* predicate registers */
751 u64 pmsa_br0; /* branch register 0 */
752 u64 pmsa_rsc; /* ar.rsc */
753 u64 pmsa_iip; /* cr.iip */
754 u64 pmsa_ipsr; /* cr.ipsr */
755 u64 pmsa_ifs; /* cr.ifs */
756 u64 pmsa_xip; /* previous iip */
757 u64 pmsa_xpsr; /* previous psr */
758 u64 pmsa_xfs; /* previous ifs */
759 u64 pmsa_br1; /* branch register 1 */
760 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
761} pal_min_state_area_t;
762
763
764struct ia64_pal_retval {
765 /*
766 * A zero status value indicates call completed without error.
767 * A negative status value indicates reason of call failure.
768 * A positive status value indicates success but an
769 * informational value should be printed (e.g., "reboot for
770 * change to take effect").
771 */
772 s64 status;
773 u64 v0;
774 u64 v1;
775 u64 v2;
776};
777
778/*
779 * Note: Currently unused PAL arguments are generally labeled
780 * "reserved" so the value specified in the PAL documentation
781 * (generally 0) MUST be passed. Reserved parameters are not optional
782 * parameters.
783 */
Bjorn Helgaasc12fb182006-10-12 16:20:59 -0600784extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
786extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
787extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
788extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
789extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
790
791#define PAL_CALL(iprv,a0,a1,a2,a3) do { \
792 struct ia64_fpreg fr[6]; \
793 ia64_save_scratch_fpregs(fr); \
Bjorn Helgaasc12fb182006-10-12 16:20:59 -0600794 iprv = ia64_pal_call_static(a0, a1, a2, a3); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 ia64_load_scratch_fpregs(fr); \
796} while (0)
797
798#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
799 struct ia64_fpreg fr[6]; \
800 ia64_save_scratch_fpregs(fr); \
801 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
802 ia64_load_scratch_fpregs(fr); \
803} while (0)
804
805#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
806 struct ia64_fpreg fr[6]; \
807 ia64_save_scratch_fpregs(fr); \
808 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
809 ia64_load_scratch_fpregs(fr); \
810} while (0)
811
812#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
813 struct ia64_fpreg fr[6]; \
814 ia64_save_scratch_fpregs(fr); \
815 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
816 ia64_load_scratch_fpregs(fr); \
817} while (0)
818
819typedef int (*ia64_pal_handler) (u64, ...);
820extern ia64_pal_handler ia64_pal;
821extern void ia64_pal_handler_init (void *);
822
823extern ia64_pal_handler ia64_pal;
824
825extern pal_cache_config_info_t l0d_cache_config_info;
826extern pal_cache_config_info_t l0i_cache_config_info;
827extern pal_cache_config_info_t l1_cache_config_info;
828extern pal_cache_config_info_t l2_cache_config_info;
829
830extern pal_cache_protection_info_t l0d_cache_protection_info;
831extern pal_cache_protection_info_t l0i_cache_protection_info;
832extern pal_cache_protection_info_t l1_cache_protection_info;
833extern pal_cache_protection_info_t l2_cache_protection_info;
834
835extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
836 pal_cache_type_t);
837
838extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
839 pal_cache_type_t);
840
841
842extern void pal_error(int);
843
844
845/* Useful wrappers for the current list of pal procedures */
846
847typedef union pal_bus_features_u {
848 u64 pal_bus_features_val;
849 struct {
850 u64 pbf_reserved1 : 29;
851 u64 pbf_req_bus_parking : 1;
852 u64 pbf_bus_lock_mask : 1;
853 u64 pbf_enable_half_xfer_rate : 1;
Russ Anderson5b4d5682006-11-06 16:45:18 -0600854 u64 pbf_reserved2 : 20;
855 u64 pbf_enable_shared_line_replace : 1;
856 u64 pbf_enable_exclusive_line_replace : 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 u64 pbf_disable_xaction_queueing : 1;
858 u64 pbf_disable_resp_err_check : 1;
859 u64 pbf_disable_berr_check : 1;
860 u64 pbf_disable_bus_req_internal_err_signal : 1;
861 u64 pbf_disable_bus_req_berr_signal : 1;
862 u64 pbf_disable_bus_init_event_check : 1;
863 u64 pbf_disable_bus_init_event_signal : 1;
864 u64 pbf_disable_bus_addr_err_check : 1;
865 u64 pbf_disable_bus_addr_err_signal : 1;
866 u64 pbf_disable_bus_data_err_check : 1;
867 } pal_bus_features_s;
868} pal_bus_features_u_t;
869
870extern void pal_bus_features_print (u64);
871
872/* Provide information about configurable processor bus features */
873static inline s64
874ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
875 pal_bus_features_u_t *features_status,
876 pal_bus_features_u_t *features_control)
877{
878 struct ia64_pal_retval iprv;
879 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
880 if (features_avail)
881 features_avail->pal_bus_features_val = iprv.v0;
882 if (features_status)
883 features_status->pal_bus_features_val = iprv.v1;
884 if (features_control)
885 features_control->pal_bus_features_val = iprv.v2;
886 return iprv.status;
887}
888
889/* Enables/disables specific processor bus features */
890static inline s64
891ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
892{
893 struct ia64_pal_retval iprv;
894 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
895 return iprv.status;
896}
897
898/* Get detailed cache information */
899static inline s64
900ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
901{
902 struct ia64_pal_retval iprv;
903
904 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
905
906 if (iprv.status == 0) {
907 conf->pcci_status = iprv.status;
908 conf->pcci_info_1.pcci1_data = iprv.v0;
909 conf->pcci_info_2.pcci2_data = iprv.v1;
910 conf->pcci_reserved = iprv.v2;
911 }
912 return iprv.status;
913
914}
915
916/* Get detailed cche protection information */
917static inline s64
918ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
919{
920 struct ia64_pal_retval iprv;
921
922 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
923
924 if (iprv.status == 0) {
925 prot->pcpi_status = iprv.status;
926 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
927 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
928 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
929 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
930 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
931 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
932 }
933 return iprv.status;
934}
935
936/*
937 * Flush the processor instruction or data caches. *PROGRESS must be
938 * initialized to zero before calling this for the first time..
939 */
940static inline s64
941ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
942{
943 struct ia64_pal_retval iprv;
Xu, Anthonyf15ac582006-01-09 10:36:35 +0800944 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945 if (vector)
946 *vector = iprv.v0;
947 *progress = iprv.v1;
948 return iprv.status;
949}
950
951
952/* Initialize the processor controlled caches */
953static inline s64
954ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
955{
956 struct ia64_pal_retval iprv;
957 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
958 return iprv.status;
959}
960
961/* Initialize the tags and data of a data or unified cache line of
962 * processor controlled cache to known values without the availability
963 * of backing memory.
964 */
965static inline s64
966ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
967{
968 struct ia64_pal_retval iprv;
969 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
970 return iprv.status;
971}
972
973
974/* Read the data and tag of a processor controlled cache line for diags */
975static inline s64
976ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
977{
978 struct ia64_pal_retval iprv;
Russ Andersonb29e7132006-09-26 14:47:48 -0500979 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
980 physical_addr, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 return iprv.status;
982}
983
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100984/* Return summary information about the hierarchy of caches controlled by the processor */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985static inline s64
986ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
987{
988 struct ia64_pal_retval iprv;
989 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
990 if (cache_levels)
991 *cache_levels = iprv.v0;
992 if (unique_caches)
993 *unique_caches = iprv.v1;
994 return iprv.status;
995}
996
997/* Write the data and tag of a processor-controlled cache line for diags */
998static inline s64
999ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
1000{
1001 struct ia64_pal_retval iprv;
Russ Andersonb29e7132006-09-26 14:47:48 -05001002 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1003 physical_addr, data);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 return iprv.status;
1005}
1006
1007
1008/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1009static inline s64
1010ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1011 u64 *buffer_size, u64 *buffer_align)
1012{
1013 struct ia64_pal_retval iprv;
1014 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1015 if (buffer_size)
1016 *buffer_size = iprv.v0;
1017 if (buffer_align)
1018 *buffer_align = iprv.v1;
1019 return iprv.status;
1020}
1021
1022/* Copy relocatable PAL procedures from ROM to memory */
1023static inline s64
1024ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1025{
1026 struct ia64_pal_retval iprv;
1027 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1028 if (pal_proc_offset)
1029 *pal_proc_offset = iprv.v0;
1030 return iprv.status;
1031}
1032
1033/* Return the number of instruction and data debug register pairs */
1034static inline s64
1035ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1036{
1037 struct ia64_pal_retval iprv;
1038 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1039 if (inst_regs)
1040 *inst_regs = iprv.v0;
1041 if (data_regs)
1042 *data_regs = iprv.v1;
1043
1044 return iprv.status;
1045}
1046
1047#ifdef TBD
1048/* Switch from IA64-system environment to IA-32 system environment */
1049static inline s64
1050ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1051{
1052 struct ia64_pal_retval iprv;
1053 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1054 return iprv.status;
1055}
1056#endif
1057
1058/* Get unique geographical address of this processor on its bus */
1059static inline s64
1060ia64_pal_fixed_addr (u64 *global_unique_addr)
1061{
1062 struct ia64_pal_retval iprv;
1063 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1064 if (global_unique_addr)
1065 *global_unique_addr = iprv.v0;
1066 return iprv.status;
1067}
1068
1069/* Get base frequency of the platform if generated by the processor */
1070static inline s64
1071ia64_pal_freq_base (u64 *platform_base_freq)
1072{
1073 struct ia64_pal_retval iprv;
1074 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1075 if (platform_base_freq)
1076 *platform_base_freq = iprv.v0;
1077 return iprv.status;
1078}
1079
1080/*
1081 * Get the ratios for processor frequency, bus frequency and interval timer to
1082 * to base frequency of the platform
1083 */
1084static inline s64
1085ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1086 struct pal_freq_ratio *itc_ratio)
1087{
1088 struct ia64_pal_retval iprv;
1089 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1090 if (proc_ratio)
1091 *(u64 *)proc_ratio = iprv.v0;
1092 if (bus_ratio)
1093 *(u64 *)bus_ratio = iprv.v1;
1094 if (itc_ratio)
1095 *(u64 *)itc_ratio = iprv.v2;
1096 return iprv.status;
1097}
1098
Russ Anderson5b4d5682006-11-06 16:45:18 -06001099/*
1100 * Get the current hardware resource sharing policy of the processor
1101 */
1102static inline s64
1103ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1104 u64 *la)
1105{
1106 struct ia64_pal_retval iprv;
1107 PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1108 if (cur_policy)
1109 *cur_policy = iprv.v0;
1110 if (num_impacted)
1111 *num_impacted = iprv.v1;
1112 if (la)
1113 *la = iprv.v2;
1114 return iprv.status;
1115}
1116
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117/* Make the processor enter HALT or one of the implementation dependent low
1118 * power states where prefetching and execution are suspended and cache and
1119 * TLB coherency is not maintained.
1120 */
1121static inline s64
1122ia64_pal_halt (u64 halt_state)
1123{
1124 struct ia64_pal_retval iprv;
1125 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1126 return iprv.status;
1127}
1128
1129typedef union pal_power_mgmt_info_u {
1130 u64 ppmi_data;
1131 struct {
1132 u64 exit_latency : 16,
1133 entry_latency : 16,
1134 power_consumption : 28,
1135 im : 1,
1136 co : 1,
1137 reserved : 2;
1138 } pal_power_mgmt_info_s;
1139} pal_power_mgmt_info_u_t;
1140
1141/* Return information about processor's optional power management capabilities. */
1142static inline s64
1143ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1144{
1145 struct ia64_pal_retval iprv;
1146 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1147 return iprv.status;
1148}
1149
Venkatesh Pallipadi4db86992005-07-29 16:15:00 -07001150/* Get the current P-state information */
1151static inline s64
Venkatesh Pallipadi17e77b12006-12-01 15:28:14 -08001152ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
Venkatesh Pallipadi4db86992005-07-29 16:15:00 -07001153{
1154 struct ia64_pal_retval iprv;
Venkatesh Pallipadi17e77b12006-12-01 15:28:14 -08001155 PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
Venkatesh Pallipadi4db86992005-07-29 16:15:00 -07001156 *pstate_index = iprv.v0;
1157 return iprv.status;
1158}
1159
1160/* Set the P-state */
1161static inline s64
1162ia64_pal_set_pstate (u64 pstate_index)
1163{
1164 struct ia64_pal_retval iprv;
1165 PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1166 return iprv.status;
1167}
1168
Tony Luck76d08bb2006-06-05 13:54:14 -07001169/* Processor branding information*/
1170static inline s64
1171ia64_pal_get_brand_info (char *brand_info)
1172{
1173 struct ia64_pal_retval iprv;
1174 PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1175 return iprv.status;
1176}
1177
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1179 * suspended, but cache and TLB coherency is maintained.
1180 */
1181static inline s64
1182ia64_pal_halt_light (void)
1183{
1184 struct ia64_pal_retval iprv;
1185 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1186 return iprv.status;
1187}
1188
1189/* Clear all the processor error logging registers and reset the indicator that allows
1190 * the error logging registers to be written. This procedure also checks the pending
1191 * machine check bit and pending INIT bit and reports their states.
1192 */
1193static inline s64
1194ia64_pal_mc_clear_log (u64 *pending_vector)
1195{
1196 struct ia64_pal_retval iprv;
1197 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1198 if (pending_vector)
1199 *pending_vector = iprv.v0;
1200 return iprv.status;
1201}
1202
1203/* Ensure that all outstanding transactions in a processor are completed or that any
1204 * MCA due to thes outstanding transaction is taken.
1205 */
1206static inline s64
1207ia64_pal_mc_drain (void)
1208{
1209 struct ia64_pal_retval iprv;
1210 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1211 return iprv.status;
1212}
1213
1214/* Return the machine check dynamic processor state */
1215static inline s64
1216ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1217{
1218 struct ia64_pal_retval iprv;
1219 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1220 if (size)
1221 *size = iprv.v0;
1222 if (pds)
1223 *pds = iprv.v1;
1224 return iprv.status;
1225}
1226
1227/* Return processor machine check information */
1228static inline s64
1229ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1230{
1231 struct ia64_pal_retval iprv;
1232 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1233 if (size)
1234 *size = iprv.v0;
1235 if (error_info)
1236 *error_info = iprv.v1;
1237 return iprv.status;
1238}
1239
Fenghua Yu1138b7e2006-12-08 16:17:31 -08001240/* Injects the requested processor error or returns info on
1241 * supported injection capabilities for current processor implementation
1242 */
1243static inline s64
1244ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
1245 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1246{
1247 struct ia64_pal_retval iprv;
1248 PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1249 err_struct_info, err_data_buffer);
1250 if (capabilities)
1251 *capabilities= iprv.v0;
1252 if (resources)
1253 *resources= iprv.v1;
1254 return iprv.status;
1255}
1256
1257static inline s64
1258ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
1259 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1260{
1261 struct ia64_pal_retval iprv;
1262 PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1263 err_struct_info, err_data_buffer);
1264 if (capabilities)
1265 *capabilities= iprv.v0;
1266 if (resources)
1267 *resources= iprv.v1;
1268 return iprv.status;
1269}
1270
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1272 * attempt to correct any expected machine checks.
1273 */
1274static inline s64
1275ia64_pal_mc_expected (u64 expected, u64 *previous)
1276{
1277 struct ia64_pal_retval iprv;
1278 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1279 if (previous)
1280 *previous = iprv.v0;
1281 return iprv.status;
1282}
1283
1284/* Register a platform dependent location with PAL to which it can save
1285 * minimal processor state in the event of a machine check or initialization
1286 * event.
1287 */
1288static inline s64
1289ia64_pal_mc_register_mem (u64 physical_addr)
1290{
1291 struct ia64_pal_retval iprv;
1292 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1293 return iprv.status;
1294}
1295
1296/* Restore minimal architectural processor state, set CMC interrupt if necessary
1297 * and resume execution
1298 */
1299static inline s64
1300ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1301{
1302 struct ia64_pal_retval iprv;
1303 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1304 return iprv.status;
1305}
1306
1307/* Return the memory attributes implemented by the processor */
1308static inline s64
1309ia64_pal_mem_attrib (u64 *mem_attrib)
1310{
1311 struct ia64_pal_retval iprv;
1312 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1313 if (mem_attrib)
1314 *mem_attrib = iprv.v0 & 0xff;
1315 return iprv.status;
1316}
1317
1318/* Return the amount of memory needed for second phase of processor
1319 * self-test and the required alignment of memory.
1320 */
1321static inline s64
1322ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1323{
1324 struct ia64_pal_retval iprv;
1325 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1326 if (bytes_needed)
1327 *bytes_needed = iprv.v0;
1328 if (alignment)
1329 *alignment = iprv.v1;
1330 return iprv.status;
1331}
1332
1333typedef union pal_perf_mon_info_u {
1334 u64 ppmi_data;
1335 struct {
1336 u64 generic : 8,
1337 width : 8,
1338 cycles : 8,
1339 retired : 8,
1340 reserved : 32;
1341 } pal_perf_mon_info_s;
1342} pal_perf_mon_info_u_t;
1343
1344/* Return the performance monitor information about what can be counted
1345 * and how to configure the monitors to count the desired events.
1346 */
1347static inline s64
1348ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1349{
1350 struct ia64_pal_retval iprv;
1351 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1352 if (pm_info)
1353 pm_info->ppmi_data = iprv.v0;
1354 return iprv.status;
1355}
1356
1357/* Specifies the physical address of the processor interrupt block
1358 * and I/O port space.
1359 */
1360static inline s64
1361ia64_pal_platform_addr (u64 type, u64 physical_addr)
1362{
1363 struct ia64_pal_retval iprv;
1364 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1365 return iprv.status;
1366}
1367
1368/* Set the SAL PMI entrypoint in memory */
1369static inline s64
1370ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1371{
1372 struct ia64_pal_retval iprv;
1373 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1374 return iprv.status;
1375}
1376
1377struct pal_features_s;
1378/* Provide information about configurable processor features */
1379static inline s64
1380ia64_pal_proc_get_features (u64 *features_avail,
1381 u64 *features_status,
1382 u64 *features_control)
1383{
1384 struct ia64_pal_retval iprv;
1385 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1386 if (iprv.status == 0) {
1387 *features_avail = iprv.v0;
1388 *features_status = iprv.v1;
1389 *features_control = iprv.v2;
1390 }
1391 return iprv.status;
1392}
1393
1394/* Enable/disable processor dependent features */
1395static inline s64
1396ia64_pal_proc_set_features (u64 feature_select)
1397{
1398 struct ia64_pal_retval iprv;
1399 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1400 return iprv.status;
1401}
1402
1403/*
1404 * Put everything in a struct so we avoid the global offset table whenever
1405 * possible.
1406 */
1407typedef struct ia64_ptce_info_s {
1408 u64 base;
1409 u32 count[2];
1410 u32 stride[2];
1411} ia64_ptce_info_t;
1412
1413/* Return the information required for the architected loop used to purge
1414 * (initialize) the entire TC
1415 */
1416static inline s64
1417ia64_get_ptce (ia64_ptce_info_t *ptce)
1418{
1419 struct ia64_pal_retval iprv;
1420
1421 if (!ptce)
1422 return -1;
1423
1424 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1425 if (iprv.status == 0) {
1426 ptce->base = iprv.v0;
1427 ptce->count[0] = iprv.v1 >> 32;
1428 ptce->count[1] = iprv.v1 & 0xffffffff;
1429 ptce->stride[0] = iprv.v2 >> 32;
1430 ptce->stride[1] = iprv.v2 & 0xffffffff;
1431 }
1432 return iprv.status;
1433}
1434
1435/* Return info about implemented application and control registers. */
1436static inline s64
1437ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1438{
1439 struct ia64_pal_retval iprv;
1440 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1441 if (reg_info_1)
1442 *reg_info_1 = iprv.v0;
1443 if (reg_info_2)
1444 *reg_info_2 = iprv.v1;
1445 return iprv.status;
1446}
1447
1448typedef union pal_hints_u {
1449 u64 ph_data;
1450 struct {
1451 u64 si : 1,
1452 li : 1,
1453 reserved : 62;
1454 } pal_hints_s;
1455} pal_hints_u_t;
1456
1457/* Return information about the register stack and RSE for this processor
1458 * implementation.
1459 */
1460static inline s64
1461ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1462{
1463 struct ia64_pal_retval iprv;
1464 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1465 if (num_phys_stacked)
1466 *num_phys_stacked = iprv.v0;
1467 if (hints)
1468 hints->ph_data = iprv.v1;
1469 return iprv.status;
1470}
1471
Russ Anderson5b4d5682006-11-06 16:45:18 -06001472/*
1473 * Set the current hardware resource sharing policy of the processor
1474 */
1475static inline s64
1476ia64_pal_set_hw_policy (u64 policy)
1477{
1478 struct ia64_pal_retval iprv;
1479 PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1480 return iprv.status;
1481}
1482
Linus Torvalds1da177e2005-04-16 15:20:36 -07001483/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1484 * suspended, but cause cache and TLB coherency to be maintained.
1485 * This is usually called in IA-32 mode.
1486 */
1487static inline s64
1488ia64_pal_shutdown (void)
1489{
1490 struct ia64_pal_retval iprv;
1491 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1492 return iprv.status;
1493}
1494
1495/* Perform the second phase of processor self-test. */
1496static inline s64
1497ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1498{
1499 struct ia64_pal_retval iprv;
1500 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1501 if (self_test_state)
1502 *self_test_state = iprv.v0;
1503 return iprv.status;
1504}
1505
1506typedef union pal_version_u {
1507 u64 pal_version_val;
1508 struct {
1509 u64 pv_pal_b_rev : 8;
1510 u64 pv_pal_b_model : 8;
1511 u64 pv_reserved1 : 8;
1512 u64 pv_pal_vendor : 8;
1513 u64 pv_pal_a_rev : 8;
1514 u64 pv_pal_a_model : 8;
1515 u64 pv_reserved2 : 16;
1516 } pal_version_s;
1517} pal_version_u_t;
1518
1519
Matthew Wilcox1bf1eba2006-06-23 13:15:55 -06001520/*
1521 * Return PAL version information. While the documentation states that
1522 * PAL_VERSION can be called in either physical or virtual mode, some
1523 * implementations only allow physical calls. We don't call it very often,
1524 * so the overhead isn't worth eliminating.
1525 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526static inline s64
1527ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1528{
1529 struct ia64_pal_retval iprv;
1530 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1531 if (pal_min_version)
1532 pal_min_version->pal_version_val = iprv.v0;
1533
1534 if (pal_cur_version)
1535 pal_cur_version->pal_version_val = iprv.v1;
1536
1537 return iprv.status;
1538}
1539
1540typedef union pal_tc_info_u {
1541 u64 pti_val;
1542 struct {
1543 u64 num_sets : 8,
1544 associativity : 8,
1545 num_entries : 16,
1546 pf : 1,
1547 unified : 1,
1548 reduce_tr : 1,
1549 reserved : 29;
1550 } pal_tc_info_s;
1551} pal_tc_info_u_t;
1552
1553#define tc_reduce_tr pal_tc_info_s.reduce_tr
1554#define tc_unified pal_tc_info_s.unified
1555#define tc_pf pal_tc_info_s.pf
1556#define tc_num_entries pal_tc_info_s.num_entries
1557#define tc_associativity pal_tc_info_s.associativity
1558#define tc_num_sets pal_tc_info_s.num_sets
1559
1560
1561/* Return information about the virtual memory characteristics of the processor
1562 * implementation.
1563 */
1564static inline s64
1565ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1566{
1567 struct ia64_pal_retval iprv;
1568 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1569 if (tc_info)
1570 tc_info->pti_val = iprv.v0;
1571 if (tc_pages)
1572 *tc_pages = iprv.v1;
1573 return iprv.status;
1574}
1575
1576/* Get page size information about the virtual memory characteristics of the processor
1577 * implementation.
1578 */
1579static inline s64
1580ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1581{
1582 struct ia64_pal_retval iprv;
1583 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1584 if (tr_pages)
1585 *tr_pages = iprv.v0;
1586 if (vw_pages)
1587 *vw_pages = iprv.v1;
1588 return iprv.status;
1589}
1590
1591typedef union pal_vm_info_1_u {
1592 u64 pvi1_val;
1593 struct {
1594 u64 vw : 1,
1595 phys_add_size : 7,
1596 key_size : 8,
1597 max_pkr : 8,
1598 hash_tag_id : 8,
1599 max_dtr_entry : 8,
1600 max_itr_entry : 8,
1601 max_unique_tcs : 8,
1602 num_tc_levels : 8;
1603 } pal_vm_info_1_s;
1604} pal_vm_info_1_u_t;
1605
Russ Anderson5b4d5682006-11-06 16:45:18 -06001606#define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */
1607
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608typedef union pal_vm_info_2_u {
1609 u64 pvi2_val;
1610 struct {
1611 u64 impl_va_msb : 8,
1612 rid_size : 8,
Russ Anderson5b4d5682006-11-06 16:45:18 -06001613 max_purges : 16,
1614 reserved : 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615 } pal_vm_info_2_s;
1616} pal_vm_info_2_u_t;
1617
1618/* Get summary information about the virtual memory characteristics of the processor
1619 * implementation.
1620 */
1621static inline s64
1622ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1623{
1624 struct ia64_pal_retval iprv;
1625 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1626 if (vm_info_1)
1627 vm_info_1->pvi1_val = iprv.v0;
1628 if (vm_info_2)
1629 vm_info_2->pvi2_val = iprv.v1;
1630 return iprv.status;
1631}
1632
1633typedef union pal_itr_valid_u {
1634 u64 piv_val;
1635 struct {
1636 u64 access_rights_valid : 1,
1637 priv_level_valid : 1,
1638 dirty_bit_valid : 1,
1639 mem_attr_valid : 1,
1640 reserved : 60;
1641 } pal_tr_valid_s;
1642} pal_tr_valid_u_t;
1643
1644/* Read a translation register */
1645static inline s64
1646ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1647{
1648 struct ia64_pal_retval iprv;
1649 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1650 if (tr_valid)
1651 tr_valid->piv_val = iprv.v0;
1652 return iprv.status;
1653}
1654
1655/*
1656 * PAL_PREFETCH_VISIBILITY transaction types
1657 */
1658#define PAL_VISIBILITY_VIRTUAL 0
1659#define PAL_VISIBILITY_PHYSICAL 1
1660
1661/*
1662 * PAL_PREFETCH_VISIBILITY return codes
1663 */
1664#define PAL_VISIBILITY_OK 1
1665#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1666#define PAL_VISIBILITY_INVAL_ARG -2
1667#define PAL_VISIBILITY_ERROR -3
1668
1669static inline s64
1670ia64_pal_prefetch_visibility (s64 trans_type)
1671{
1672 struct ia64_pal_retval iprv;
1673 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1674 return iprv.status;
1675}
1676
Suresh Siddhae927ecb2005-04-25 13:25:06 -07001677/* data structure for getting information on logical to physical mappings */
1678typedef union pal_log_overview_u {
1679 struct {
1680 u64 num_log :16, /* Total number of logical
1681 * processors on this die
1682 */
1683 tpc :8, /* Threads per core */
1684 reserved3 :8, /* Reserved */
1685 cpp :8, /* Cores per processor */
1686 reserved2 :8, /* Reserved */
1687 ppid :8, /* Physical processor ID */
1688 reserved1 :8; /* Reserved */
1689 } overview_bits;
1690 u64 overview_data;
1691} pal_log_overview_t;
1692
1693typedef union pal_proc_n_log_info1_u{
1694 struct {
1695 u64 tid :16, /* Thread id */
1696 reserved2 :16, /* Reserved */
1697 cid :16, /* Core id */
1698 reserved1 :16; /* Reserved */
1699 } ppli1_bits;
1700 u64 ppli1_data;
1701} pal_proc_n_log_info1_t;
1702
1703typedef union pal_proc_n_log_info2_u {
1704 struct {
1705 u64 la :16, /* Logical address */
1706 reserved :48; /* Reserved */
1707 } ppli2_bits;
1708 u64 ppli2_data;
1709} pal_proc_n_log_info2_t;
1710
1711typedef struct pal_logical_to_physical_s
1712{
1713 pal_log_overview_t overview;
1714 pal_proc_n_log_info1_t ppli1;
1715 pal_proc_n_log_info2_t ppli2;
1716} pal_logical_to_physical_t;
1717
1718#define overview_num_log overview.overview_bits.num_log
1719#define overview_tpc overview.overview_bits.tpc
1720#define overview_cpp overview.overview_bits.cpp
1721#define overview_ppid overview.overview_bits.ppid
1722#define log1_tid ppli1.ppli1_bits.tid
1723#define log1_cid ppli1.ppli1_bits.cid
1724#define log2_la ppli2.ppli2_bits.la
1725
1726/* Get information on logical to physical processor mappings. */
1727static inline s64
1728ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1729{
1730 struct ia64_pal_retval iprv;
1731
1732 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1733
1734 if (iprv.status == PAL_STATUS_SUCCESS)
1735 {
Fenghua Yu4129a952006-02-27 16:16:22 -08001736 mapping->overview.overview_data = iprv.v0;
Suresh Siddhae927ecb2005-04-25 13:25:06 -07001737 mapping->ppli1.ppli1_data = iprv.v1;
1738 mapping->ppli2.ppli2_data = iprv.v2;
1739 }
1740
1741 return iprv.status;
1742}
Zhang, Yanminf1918002006-02-27 11:37:45 +08001743
1744typedef struct pal_cache_shared_info_s
1745{
1746 u64 num_shared;
1747 pal_proc_n_log_info1_t ppli1;
1748 pal_proc_n_log_info2_t ppli2;
1749} pal_cache_shared_info_t;
1750
1751/* Get information on logical to physical processor mappings. */
1752static inline s64
1753ia64_pal_cache_shared_info(u64 level,
1754 u64 type,
1755 u64 proc_number,
1756 pal_cache_shared_info_t *info)
1757{
1758 struct ia64_pal_retval iprv;
1759
1760 PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1761
1762 if (iprv.status == PAL_STATUS_SUCCESS) {
1763 info->num_shared = iprv.v0;
1764 info->ppli1.ppli1_data = iprv.v1;
1765 info->ppli2.ppli2_data = iprv.v2;
1766 }
1767
1768 return iprv.status;
1769}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770#endif /* __ASSEMBLY__ */
1771
1772#endif /* _ASM_IA64_PAL_H */