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Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000012#include <linux/dma-mapping.h>
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -070013#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/err.h>
16#include <linux/spinlock.h>
17#include <linux/delay.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <linux/vmalloc.h>
21#include <linux/string.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
Paul Gortmaker5c45ad72011-07-31 16:14:17 -040024#include <linux/module.h>
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -070025
26#include <mach/ipu.h>
27
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000028#include "../dmaengine.h"
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -070029#include "ipu_intern.h"
30
31#define FS_VF_IN_VALID 0x00000002
32#define FS_ENC_IN_VALID 0x00000001
33
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -070034static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
35 bool wait_for_stop);
36
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -070037/*
38 * There can be only one, we could allocate it dynamically, but then we'd have
39 * to add an extra parameter to some functions, and use something as ugly as
40 * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
41 * in the ISR
42 */
43static struct ipu ipu_data;
44
45#define to_ipu(id) container_of(id, struct ipu, idmac)
46
47static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
48{
49 return __raw_readl(ipu->reg_ic + reg);
50}
51
52#define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
53
54static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
55{
56 __raw_writel(value, ipu->reg_ic + reg);
57}
58
59#define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
60
61static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
62{
63 return __raw_readl(ipu->reg_ipu + reg);
64}
65
66static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
67{
68 __raw_writel(value, ipu->reg_ipu + reg);
69}
70
71/*****************************************************************************
72 * IPU / IC common functions
73 */
74static void dump_idmac_reg(struct ipu *ipu)
75{
76 dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
77 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
78 idmac_read_icreg(ipu, IDMAC_CONF),
79 idmac_read_icreg(ipu, IC_CONF),
80 idmac_read_icreg(ipu, IDMAC_CHA_EN),
81 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
82 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
83 dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
84 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
85 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
86 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
87 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
88 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
89 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
90}
91
92static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
93{
94 switch (fmt) {
95 case IPU_PIX_FMT_GENERIC: /* generic data */
96 case IPU_PIX_FMT_RGB332:
97 case IPU_PIX_FMT_YUV420P:
98 case IPU_PIX_FMT_YUV422P:
99 default:
100 return 1;
101 case IPU_PIX_FMT_RGB565:
102 case IPU_PIX_FMT_YUYV:
103 case IPU_PIX_FMT_UYVY:
104 return 2;
105 case IPU_PIX_FMT_BGR24:
106 case IPU_PIX_FMT_RGB24:
107 return 3;
108 case IPU_PIX_FMT_GENERIC_32: /* generic data */
109 case IPU_PIX_FMT_BGR32:
110 case IPU_PIX_FMT_RGB32:
111 case IPU_PIX_FMT_ABGR32:
112 return 4;
113 }
114}
115
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700116/* Enable direct write to memory by the Camera Sensor Interface */
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700117static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
118{
119 uint32_t ic_conf, mask;
120
121 switch (channel) {
122 case IDMAC_IC_0:
123 mask = IC_CONF_PRPENC_EN;
124 break;
125 case IDMAC_IC_7:
126 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
127 break;
128 default:
129 return;
130 }
131 ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
132 idmac_write_icreg(ipu, ic_conf, IC_CONF);
133}
134
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700135/* Called under spin_lock_irqsave(&ipu_data.lock) */
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700136static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
137{
138 uint32_t ic_conf, mask;
139
140 switch (channel) {
141 case IDMAC_IC_0:
142 mask = IC_CONF_PRPENC_EN;
143 break;
144 case IDMAC_IC_7:
145 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
146 break;
147 default:
148 return;
149 }
150 ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
151 idmac_write_icreg(ipu, ic_conf, IC_CONF);
152}
153
154static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
155{
156 uint32_t stat = TASK_STAT_IDLE;
157 uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
158
159 switch (channel) {
160 case IDMAC_IC_7:
161 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
162 TSTAT_CSI2MEM_OFFSET;
163 break;
164 case IDMAC_IC_0:
165 case IDMAC_SDC_0:
166 case IDMAC_SDC_1:
167 default:
168 break;
169 }
170 return stat;
171}
172
173struct chan_param_mem_planar {
174 /* Word 0 */
175 u32 xv:10;
176 u32 yv:10;
177 u32 xb:12;
178
179 u32 yb:12;
180 u32 res1:2;
181 u32 nsb:1;
182 u32 lnpb:6;
183 u32 ubo_l:11;
184
185 u32 ubo_h:15;
186 u32 vbo_l:17;
187
188 u32 vbo_h:9;
189 u32 res2:3;
190 u32 fw:12;
191 u32 fh_l:8;
192
193 u32 fh_h:4;
194 u32 res3:28;
195
196 /* Word 1 */
197 u32 eba0;
198
199 u32 eba1;
200
201 u32 bpp:3;
202 u32 sl:14;
203 u32 pfs:3;
204 u32 bam:3;
205 u32 res4:2;
206 u32 npb:6;
207 u32 res5:1;
208
209 u32 sat:2;
210 u32 res6:30;
211} __attribute__ ((packed));
212
213struct chan_param_mem_interleaved {
214 /* Word 0 */
215 u32 xv:10;
216 u32 yv:10;
217 u32 xb:12;
218
219 u32 yb:12;
220 u32 sce:1;
221 u32 res1:1;
222 u32 nsb:1;
223 u32 lnpb:6;
224 u32 sx:10;
225 u32 sy_l:1;
226
227 u32 sy_h:9;
228 u32 ns:10;
229 u32 sm:10;
230 u32 sdx_l:3;
231
232 u32 sdx_h:2;
233 u32 sdy:5;
234 u32 sdrx:1;
235 u32 sdry:1;
236 u32 sdr1:1;
237 u32 res2:2;
238 u32 fw:12;
239 u32 fh_l:8;
240
241 u32 fh_h:4;
242 u32 res3:28;
243
244 /* Word 1 */
245 u32 eba0;
246
247 u32 eba1;
248
249 u32 bpp:3;
250 u32 sl:14;
251 u32 pfs:3;
252 u32 bam:3;
253 u32 res4:2;
254 u32 npb:6;
255 u32 res5:1;
256
257 u32 sat:2;
258 u32 scc:1;
259 u32 ofs0:5;
260 u32 ofs1:5;
261 u32 ofs2:5;
262 u32 ofs3:5;
263 u32 wid0:3;
264 u32 wid1:3;
265 u32 wid2:3;
266
267 u32 wid3:3;
268 u32 dec_sel:1;
269 u32 res6:28;
270} __attribute__ ((packed));
271
272union chan_param_mem {
273 struct chan_param_mem_planar pp;
274 struct chan_param_mem_interleaved ip;
275};
276
277static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
278 u32 u_offset, u32 v_offset)
279{
280 params->pp.ubo_l = u_offset & 0x7ff;
281 params->pp.ubo_h = u_offset >> 11;
282 params->pp.vbo_l = v_offset & 0x1ffff;
283 params->pp.vbo_h = v_offset >> 17;
284}
285
286static void ipu_ch_param_set_size(union chan_param_mem *params,
287 uint32_t pixel_fmt, uint16_t width,
288 uint16_t height, uint16_t stride)
289{
290 u32 u_offset;
291 u32 v_offset;
292
293 params->pp.fw = width - 1;
294 params->pp.fh_l = height - 1;
295 params->pp.fh_h = (height - 1) >> 8;
296 params->pp.sl = stride - 1;
297
298 switch (pixel_fmt) {
299 case IPU_PIX_FMT_GENERIC:
300 /*Represents 8-bit Generic data */
301 params->pp.bpp = 3;
302 params->pp.pfs = 7;
303 params->pp.npb = 31;
304 params->pp.sat = 2; /* SAT = use 32-bit access */
305 break;
306 case IPU_PIX_FMT_GENERIC_32:
307 /*Represents 32-bit Generic data */
308 params->pp.bpp = 0;
309 params->pp.pfs = 7;
310 params->pp.npb = 7;
311 params->pp.sat = 2; /* SAT = use 32-bit access */
312 break;
313 case IPU_PIX_FMT_RGB565:
314 params->ip.bpp = 2;
315 params->ip.pfs = 4;
Sascha Hauerc99e7842011-12-01 14:58:51 +0100316 params->ip.npb = 15;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700317 params->ip.sat = 2; /* SAT = 32-bit access */
318 params->ip.ofs0 = 0; /* Red bit offset */
319 params->ip.ofs1 = 5; /* Green bit offset */
320 params->ip.ofs2 = 11; /* Blue bit offset */
321 params->ip.ofs3 = 16; /* Alpha bit offset */
322 params->ip.wid0 = 4; /* Red bit width - 1 */
323 params->ip.wid1 = 5; /* Green bit width - 1 */
324 params->ip.wid2 = 4; /* Blue bit width - 1 */
325 break;
326 case IPU_PIX_FMT_BGR24:
327 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
328 params->ip.pfs = 4;
329 params->ip.npb = 7;
330 params->ip.sat = 2; /* SAT = 32-bit access */
331 params->ip.ofs0 = 0; /* Red bit offset */
332 params->ip.ofs1 = 8; /* Green bit offset */
333 params->ip.ofs2 = 16; /* Blue bit offset */
334 params->ip.ofs3 = 24; /* Alpha bit offset */
335 params->ip.wid0 = 7; /* Red bit width - 1 */
336 params->ip.wid1 = 7; /* Green bit width - 1 */
337 params->ip.wid2 = 7; /* Blue bit width - 1 */
338 break;
339 case IPU_PIX_FMT_RGB24:
340 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
341 params->ip.pfs = 4;
342 params->ip.npb = 7;
343 params->ip.sat = 2; /* SAT = 32-bit access */
344 params->ip.ofs0 = 16; /* Red bit offset */
345 params->ip.ofs1 = 8; /* Green bit offset */
346 params->ip.ofs2 = 0; /* Blue bit offset */
347 params->ip.ofs3 = 24; /* Alpha bit offset */
348 params->ip.wid0 = 7; /* Red bit width - 1 */
349 params->ip.wid1 = 7; /* Green bit width - 1 */
350 params->ip.wid2 = 7; /* Blue bit width - 1 */
351 break;
352 case IPU_PIX_FMT_BGRA32:
353 case IPU_PIX_FMT_BGR32:
Roel Kluin9ad7bd22010-01-20 01:25:56 +0100354 case IPU_PIX_FMT_ABGR32:
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700355 params->ip.bpp = 0;
356 params->ip.pfs = 4;
357 params->ip.npb = 7;
358 params->ip.sat = 2; /* SAT = 32-bit access */
359 params->ip.ofs0 = 8; /* Red bit offset */
360 params->ip.ofs1 = 16; /* Green bit offset */
361 params->ip.ofs2 = 24; /* Blue bit offset */
362 params->ip.ofs3 = 0; /* Alpha bit offset */
363 params->ip.wid0 = 7; /* Red bit width - 1 */
364 params->ip.wid1 = 7; /* Green bit width - 1 */
365 params->ip.wid2 = 7; /* Blue bit width - 1 */
366 params->ip.wid3 = 7; /* Alpha bit width - 1 */
367 break;
368 case IPU_PIX_FMT_RGBA32:
369 case IPU_PIX_FMT_RGB32:
370 params->ip.bpp = 0;
371 params->ip.pfs = 4;
372 params->ip.npb = 7;
373 params->ip.sat = 2; /* SAT = 32-bit access */
374 params->ip.ofs0 = 24; /* Red bit offset */
375 params->ip.ofs1 = 16; /* Green bit offset */
376 params->ip.ofs2 = 8; /* Blue bit offset */
377 params->ip.ofs3 = 0; /* Alpha bit offset */
378 params->ip.wid0 = 7; /* Red bit width - 1 */
379 params->ip.wid1 = 7; /* Green bit width - 1 */
380 params->ip.wid2 = 7; /* Blue bit width - 1 */
381 params->ip.wid3 = 7; /* Alpha bit width - 1 */
382 break;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700383 case IPU_PIX_FMT_UYVY:
384 params->ip.bpp = 2;
385 params->ip.pfs = 6;
386 params->ip.npb = 7;
387 params->ip.sat = 2; /* SAT = 32-bit access */
388 break;
389 case IPU_PIX_FMT_YUV420P2:
390 case IPU_PIX_FMT_YUV420P:
391 params->ip.bpp = 3;
392 params->ip.pfs = 3;
393 params->ip.npb = 7;
394 params->ip.sat = 2; /* SAT = 32-bit access */
395 u_offset = stride * height;
396 v_offset = u_offset + u_offset / 4;
397 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
398 break;
399 case IPU_PIX_FMT_YVU422P:
400 params->ip.bpp = 3;
401 params->ip.pfs = 2;
402 params->ip.npb = 7;
403 params->ip.sat = 2; /* SAT = 32-bit access */
404 v_offset = stride * height;
405 u_offset = v_offset + v_offset / 2;
406 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
407 break;
408 case IPU_PIX_FMT_YUV422P:
409 params->ip.bpp = 3;
410 params->ip.pfs = 2;
411 params->ip.npb = 7;
412 params->ip.sat = 2; /* SAT = 32-bit access */
413 u_offset = stride * height;
414 v_offset = u_offset + u_offset / 2;
415 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
416 break;
417 default:
418 dev_err(ipu_data.dev,
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700419 "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700420 break;
421 }
422
423 params->pp.nsb = 1;
424}
425
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700426static void ipu_ch_param_set_buffer(union chan_param_mem *params,
427 dma_addr_t buf0, dma_addr_t buf1)
428{
429 params->pp.eba0 = buf0;
430 params->pp.eba1 = buf1;
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700431}
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700432
433static void ipu_ch_param_set_rotation(union chan_param_mem *params,
434 enum ipu_rotate_mode rotate)
435{
436 params->pp.bam = rotate;
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700437}
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700438
439static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
440 uint32_t num_words)
441{
442 for (; num_words > 0; num_words--) {
443 dev_dbg(ipu_data.dev,
444 "write param mem - addr = 0x%08X, data = 0x%08X\n",
445 addr, *data);
446 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
447 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
448 addr++;
449 if ((addr & 0x7) == 5) {
450 addr &= ~0x7; /* set to word 0 */
451 addr += 8; /* increment to next row */
452 }
453 }
454}
455
456static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
457 uint32_t *resize_coeff,
458 uint32_t *downsize_coeff)
459{
460 uint32_t temp_size;
461 uint32_t temp_downsize;
462
463 *resize_coeff = 1 << 13;
464 *downsize_coeff = 1 << 13;
465
466 /* Cannot downsize more than 8:1 */
467 if (out_size << 3 < in_size)
468 return -EINVAL;
469
470 /* compute downsizing coefficient */
471 temp_downsize = 0;
472 temp_size = in_size;
473 while (temp_size >= out_size * 2 && temp_downsize < 2) {
474 temp_size >>= 1;
475 temp_downsize++;
476 }
477 *downsize_coeff = temp_downsize;
478
479 /*
480 * compute resizing coefficient using the following formula:
481 * resize_coeff = M*(SI -1)/(SO - 1)
482 * where M = 2^13, SI - input size, SO - output size
483 */
484 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
485 if (*resize_coeff >= 16384L) {
486 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
487 *resize_coeff = 0x3FFF;
488 }
489
490 dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
491 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
492 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
493 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
494
495 return 0;
496}
497
498static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
499{
500 switch (fmt) {
501 case IPU_PIX_FMT_RGB565:
502 case IPU_PIX_FMT_BGR24:
503 case IPU_PIX_FMT_RGB24:
504 case IPU_PIX_FMT_BGR32:
505 case IPU_PIX_FMT_RGB32:
506 return IPU_COLORSPACE_RGB;
507 default:
508 return IPU_COLORSPACE_YCBCR;
509 }
510}
511
512static int ipu_ic_init_prpenc(struct ipu *ipu,
513 union ipu_channel_param *params, bool src_is_csi)
514{
515 uint32_t reg, ic_conf;
516 uint32_t downsize_coeff, resize_coeff;
517 enum ipu_color_space in_fmt, out_fmt;
518
519 /* Setup vertical resizing */
520 calc_resize_coeffs(params->video.in_height,
521 params->video.out_height,
522 &resize_coeff, &downsize_coeff);
523 reg = (downsize_coeff << 30) | (resize_coeff << 16);
524
525 /* Setup horizontal resizing */
526 calc_resize_coeffs(params->video.in_width,
527 params->video.out_width,
528 &resize_coeff, &downsize_coeff);
529 reg |= (downsize_coeff << 14) | resize_coeff;
530
531 /* Setup color space conversion */
532 in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
533 out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
534
535 /*
536 * Colourspace conversion unsupported yet - see _init_csc() in
537 * Freescale sources
538 */
539 if (in_fmt != out_fmt) {
540 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
541 return -EOPNOTSUPP;
542 }
543
544 idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
545
546 ic_conf = idmac_read_icreg(ipu, IC_CONF);
547
548 if (src_is_csi)
549 ic_conf &= ~IC_CONF_RWS_EN;
550 else
551 ic_conf |= IC_CONF_RWS_EN;
552
553 idmac_write_icreg(ipu, ic_conf, IC_CONF);
554
555 return 0;
556}
557
558static uint32_t dma_param_addr(uint32_t dma_ch)
559{
560 /* Channel Parameter Memory */
561 return 0x10000 | (dma_ch << 4);
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700562}
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700563
564static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
565 bool prio)
566{
567 u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
568
569 if (prio)
570 reg |= 1UL << channel;
571 else
572 reg &= ~(1UL << channel);
573
574 idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
575
576 dump_idmac_reg(ipu);
577}
578
579static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
580{
581 uint32_t mask;
582
583 switch (channel) {
584 case IDMAC_IC_0:
585 case IDMAC_IC_7:
586 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
587 break;
588 case IDMAC_SDC_0:
589 case IDMAC_SDC_1:
590 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
591 break;
592 default:
593 mask = 0;
594 break;
595 }
596
597 return mask;
598}
599
600/**
601 * ipu_enable_channel() - enable an IPU channel.
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700602 * @idmac: IPU DMAC context.
603 * @ichan: IDMAC channel.
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700604 * @return: 0 on success or negative error code on failure.
605 */
606static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
607{
608 struct ipu *ipu = to_ipu(idmac);
609 enum ipu_channel channel = ichan->dma_chan.chan_id;
610 uint32_t reg;
611 unsigned long flags;
612
613 spin_lock_irqsave(&ipu->lock, flags);
614
615 /* Reset to buffer 0 */
616 idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
617 ichan->active_buffer = 0;
618 ichan->status = IPU_CHANNEL_ENABLED;
619
620 switch (channel) {
621 case IDMAC_SDC_0:
622 case IDMAC_SDC_1:
623 case IDMAC_IC_7:
624 ipu_channel_set_priority(ipu, channel, true);
625 default:
626 break;
627 }
628
629 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
630
631 idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
632
633 ipu_ic_enable_task(ipu, channel);
634
635 spin_unlock_irqrestore(&ipu->lock, flags);
636 return 0;
637}
638
639/**
640 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700641 * @ichan: IDMAC channel.
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700642 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
643 * @width: width of buffer in pixels.
644 * @height: height of buffer in pixels.
645 * @stride: stride length of buffer in pixels.
646 * @rot_mode: rotation mode of buffer. A rotation setting other than
647 * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
648 * rotation channels.
649 * @phyaddr_0: buffer 0 physical address.
650 * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
651 * NULL enables double buffering mode.
652 * @return: 0 on success or negative error code on failure.
653 */
654static int ipu_init_channel_buffer(struct idmac_channel *ichan,
655 enum pixel_fmt pixel_fmt,
656 uint16_t width, uint16_t height,
657 uint32_t stride,
658 enum ipu_rotate_mode rot_mode,
659 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
660{
661 enum ipu_channel channel = ichan->dma_chan.chan_id;
662 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
663 struct ipu *ipu = to_ipu(idmac);
664 union chan_param_mem params = {};
665 unsigned long flags;
666 uint32_t reg;
667 uint32_t stride_bytes;
668
669 stride_bytes = stride * bytes_per_pixel(pixel_fmt);
670
671 if (stride_bytes % 4) {
672 dev_err(ipu->dev,
673 "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
674 stride, stride_bytes);
675 return -EINVAL;
676 }
677
678 /* IC channel's stride must be a multiple of 8 pixels */
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700679 if ((channel <= IDMAC_IC_13) && (stride % 8)) {
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700680 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
681 return -EINVAL;
682 }
683
684 /* Build parameter memory data for DMA channel */
685 ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
686 ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
687 ipu_ch_param_set_rotation(&params, rot_mode);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700688
689 spin_lock_irqsave(&ipu->lock, flags);
690
691 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
692
693 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
694
695 if (phyaddr_1)
696 reg |= 1UL << channel;
697 else
698 reg &= ~(1UL << channel);
699
700 idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
701
702 ichan->status = IPU_CHANNEL_READY;
703
Luotao Fuc74ef1f2009-02-26 12:29:20 +0100704 spin_unlock_irqrestore(&ipu->lock, flags);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700705
706 return 0;
707}
708
709/**
710 * ipu_select_buffer() - mark a channel's buffer as ready.
711 * @channel: channel ID.
712 * @buffer_n: buffer number to mark ready.
713 */
714static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
715{
716 /* No locking - this is a write-one-to-set register, cleared by IPU */
717 if (buffer_n == 0)
718 /* Mark buffer 0 as ready. */
719 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
720 else
721 /* Mark buffer 1 as ready. */
722 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
723}
724
725/**
726 * ipu_update_channel_buffer() - update physical address of a channel buffer.
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -0700727 * @ichan: IDMAC channel.
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700728 * @buffer_n: buffer number to update.
729 * 0 or 1 are the only valid values.
730 * @phyaddr: buffer physical address.
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700731 */
732/* Called under spin_lock(_irqsave)(&ichan->lock) */
Guennadi Liakhovetski8f987812010-02-10 17:32:38 +0100733static void ipu_update_channel_buffer(struct idmac_channel *ichan,
734 int buffer_n, dma_addr_t phyaddr)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700735{
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700736 enum ipu_channel channel = ichan->dma_chan.chan_id;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700737 uint32_t reg;
738 unsigned long flags;
739
740 spin_lock_irqsave(&ipu_data.lock, flags);
741
742 if (buffer_n == 0) {
743 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
744 if (reg & (1UL << channel)) {
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700745 ipu_ic_disable_task(&ipu_data, channel);
746 ichan->status = IPU_CHANNEL_READY;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700747 }
748
749 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
750 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
751 0x0008UL, IPU_IMA_ADDR);
752 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
753 } else {
754 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
755 if (reg & (1UL << channel)) {
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700756 ipu_ic_disable_task(&ipu_data, channel);
757 ichan->status = IPU_CHANNEL_READY;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700758 }
759
760 /* Check if double-buffering is already enabled */
761 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
762
763 if (!(reg & (1UL << channel)))
764 idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
765 IPU_CHA_DB_MODE_SEL);
766
767 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
768 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
769 0x0009UL, IPU_IMA_ADDR);
770 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
771 }
772
773 spin_unlock_irqrestore(&ipu_data.lock, flags);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700774}
775
776/* Called under spin_lock_irqsave(&ichan->lock) */
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700777static int ipu_submit_buffer(struct idmac_channel *ichan,
778 struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
779{
780 unsigned int chan_id = ichan->dma_chan.chan_id;
781 struct device *dev = &ichan->dma_chan.dev->device;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700782
783 if (async_tx_test_ack(&desc->txd))
784 return -EINTR;
785
786 /*
787 * On first invocation this shouldn't be necessary, the call to
788 * ipu_init_channel_buffer() above will set addresses for us, so we
789 * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
790 * doing it again shouldn't hurt either.
791 */
Guennadi Liakhovetski8f987812010-02-10 17:32:38 +0100792 ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700793
794 ipu_select_buffer(chan_id, buf_idx);
795 dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
796 sg, chan_id, buf_idx);
797
798 return 0;
799}
800
801/* Called under spin_lock_irqsave(&ichan->lock) */
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700802static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
803 struct idmac_tx_desc *desc)
804{
805 struct scatterlist *sg;
806 int i, ret = 0;
807
808 for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
809 if (!ichan->sg[i]) {
810 ichan->sg[i] = sg;
811
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700812 ret = ipu_submit_buffer(ichan, desc, sg, i);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700813 if (ret < 0)
814 return ret;
815
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700816 sg = sg_next(sg);
817 }
818 }
819
820 return ret;
821}
822
823static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
824{
825 struct idmac_tx_desc *desc = to_tx_desc(tx);
826 struct idmac_channel *ichan = to_idmac_chan(tx->chan);
827 struct idmac *idmac = to_idmac(tx->chan->device);
828 struct ipu *ipu = to_ipu(idmac);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700829 struct device *dev = &ichan->dma_chan.dev->device;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700830 dma_cookie_t cookie;
831 unsigned long flags;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700832 int ret;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700833
834 /* Sanity check */
835 if (!list_empty(&desc->list)) {
836 /* The descriptor doesn't belong to client */
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700837 dev_err(dev, "Descriptor %p not prepared!\n", tx);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700838 return -EBUSY;
839 }
840
841 mutex_lock(&ichan->chan_mutex);
842
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700843 async_tx_clear_ack(tx);
844
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700845 if (ichan->status < IPU_CHANNEL_READY) {
846 struct idmac_video_param *video = &ichan->params.video;
847 /*
848 * Initial buffer assignment - the first two sg-entries from
849 * the descriptor will end up in the IDMAC buffers
850 */
851 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
852 sg_dma_address(&desc->sg[1]);
853
854 WARN_ON(ichan->sg[0] || ichan->sg[1]);
855
856 cookie = ipu_init_channel_buffer(ichan,
857 video->out_pixel_fmt,
858 video->out_width,
859 video->out_height,
860 video->out_stride,
861 IPU_ROTATE_NONE,
862 sg_dma_address(&desc->sg[0]),
863 dma_1);
864 if (cookie < 0)
865 goto out;
866 }
867
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700868 dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700869
870 cookie = ichan->dma_chan.cookie;
871
872 if (++cookie < 0)
873 cookie = 1;
874
875 /* from dmaengine.h: "last cookie value returned to client" */
876 ichan->dma_chan.cookie = cookie;
877 tx->cookie = cookie;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700878
879 /* ipu->lock can be taken under ichan->lock, but not v.v. */
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700880 spin_lock_irqsave(&ichan->lock, flags);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700881
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700882 list_add_tail(&desc->list, &ichan->queue);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700883 /* submit_buffers() atomically verifies and fills empty sg slots */
884 ret = ipu_submit_channel_buffers(ichan, desc);
885
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700886 spin_unlock_irqrestore(&ichan->lock, flags);
887
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700888 if (ret < 0) {
889 cookie = ret;
890 goto dequeue;
891 }
892
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700893 if (ichan->status < IPU_CHANNEL_ENABLED) {
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700894 ret = ipu_enable_channel(idmac, ichan);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700895 if (ret < 0) {
896 cookie = ret;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700897 goto dequeue;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700898 }
899 }
900
901 dump_idmac_reg(ipu);
902
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -0700903dequeue:
904 if (cookie < 0) {
905 spin_lock_irqsave(&ichan->lock, flags);
906 list_del_init(&desc->list);
907 spin_unlock_irqrestore(&ichan->lock, flags);
908 tx->cookie = cookie;
909 ichan->dma_chan.cookie = cookie;
910 }
911
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700912out:
913 mutex_unlock(&ichan->chan_mutex);
914
915 return cookie;
916}
917
918/* Called with ichan->chan_mutex held */
919static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
920{
921 struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
922 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
923
924 if (!desc)
925 return -ENOMEM;
926
927 /* No interrupts, just disable the tasklet for a moment */
928 tasklet_disable(&to_ipu(idmac)->tasklet);
929
930 ichan->n_tx_desc = n;
931 ichan->desc = desc;
932 INIT_LIST_HEAD(&ichan->queue);
933 INIT_LIST_HEAD(&ichan->free_list);
934
935 while (n--) {
936 struct dma_async_tx_descriptor *txd = &desc->txd;
937
938 memset(txd, 0, sizeof(*txd));
939 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
940 txd->tx_submit = idmac_tx_submit;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700941
942 list_add(&desc->list, &ichan->free_list);
943
944 desc++;
945 }
946
947 tasklet_enable(&to_ipu(idmac)->tasklet);
948
949 return 0;
950}
951
952/**
953 * ipu_init_channel() - initialize an IPU channel.
954 * @idmac: IPU DMAC context.
955 * @ichan: pointer to the channel object.
956 * @return 0 on success or negative error code on failure.
957 */
958static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
959{
960 union ipu_channel_param *params = &ichan->params;
961 uint32_t ipu_conf;
962 enum ipu_channel channel = ichan->dma_chan.chan_id;
963 unsigned long flags;
964 uint32_t reg;
965 struct ipu *ipu = to_ipu(idmac);
966 int ret = 0, n_desc = 0;
967
968 dev_dbg(ipu->dev, "init channel = %d\n", channel);
969
970 if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
971 channel != IDMAC_IC_7)
972 return -EINVAL;
973
974 spin_lock_irqsave(&ipu->lock, flags);
975
976 switch (channel) {
977 case IDMAC_IC_7:
978 n_desc = 16;
979 reg = idmac_read_icreg(ipu, IC_CONF);
980 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
981 break;
982 case IDMAC_IC_0:
983 n_desc = 16;
984 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
985 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
986 ret = ipu_ic_init_prpenc(ipu, params, true);
987 break;
988 case IDMAC_SDC_0:
989 case IDMAC_SDC_1:
990 n_desc = 4;
991 default:
992 break;
993 }
994
995 ipu->channel_init_mask |= 1L << channel;
996
997 /* Enable IPU sub module */
998 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
999 ipu_channel_conf_mask(channel);
1000 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1001
1002 spin_unlock_irqrestore(&ipu->lock, flags);
1003
1004 if (n_desc && !ichan->desc)
1005 ret = idmac_desc_alloc(ichan, n_desc);
1006
1007 dump_idmac_reg(ipu);
1008
1009 return ret;
1010}
1011
1012/**
1013 * ipu_uninit_channel() - uninitialize an IPU channel.
1014 * @idmac: IPU DMAC context.
1015 * @ichan: pointer to the channel object.
1016 */
1017static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1018{
1019 enum ipu_channel channel = ichan->dma_chan.chan_id;
1020 unsigned long flags;
1021 uint32_t reg;
1022 unsigned long chan_mask = 1UL << channel;
1023 uint32_t ipu_conf;
1024 struct ipu *ipu = to_ipu(idmac);
1025
1026 spin_lock_irqsave(&ipu->lock, flags);
1027
1028 if (!(ipu->channel_init_mask & chan_mask)) {
1029 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1030 channel);
1031 spin_unlock_irqrestore(&ipu->lock, flags);
1032 return;
1033 }
1034
1035 /* Reset the double buffer */
1036 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1037 idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1038
1039 ichan->sec_chan_en = false;
1040
1041 switch (channel) {
1042 case IDMAC_IC_7:
1043 reg = idmac_read_icreg(ipu, IC_CONF);
1044 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1045 IC_CONF);
1046 break;
1047 case IDMAC_IC_0:
1048 reg = idmac_read_icreg(ipu, IC_CONF);
1049 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1050 IC_CONF);
1051 break;
1052 case IDMAC_SDC_0:
1053 case IDMAC_SDC_1:
1054 default:
1055 break;
1056 }
1057
1058 ipu->channel_init_mask &= ~(1L << channel);
1059
1060 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1061 ~ipu_channel_conf_mask(channel);
1062 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1063
1064 spin_unlock_irqrestore(&ipu->lock, flags);
1065
1066 ichan->n_tx_desc = 0;
1067 vfree(ichan->desc);
1068 ichan->desc = NULL;
1069}
1070
1071/**
1072 * ipu_disable_channel() - disable an IPU channel.
1073 * @idmac: IPU DMAC context.
1074 * @ichan: channel object pointer.
1075 * @wait_for_stop: flag to set whether to wait for channel end of frame or
1076 * return immediately.
1077 * @return: 0 on success or negative error code on failure.
1078 */
1079static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1080 bool wait_for_stop)
1081{
1082 enum ipu_channel channel = ichan->dma_chan.chan_id;
1083 struct ipu *ipu = to_ipu(idmac);
1084 uint32_t reg;
1085 unsigned long flags;
1086 unsigned long chan_mask = 1UL << channel;
1087 unsigned int timeout;
1088
1089 if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1090 timeout = 40;
1091 /* This waiting always fails. Related to spurious irq problem */
1092 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1093 (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1094 timeout--;
1095 msleep(10);
1096
1097 if (!timeout) {
1098 dev_dbg(ipu->dev,
1099 "Warning: timeout waiting for channel %u to "
1100 "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1101 "busy = 0x%08X, tstat = 0x%08X\n", channel,
1102 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1103 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1104 idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1105 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1106 break;
1107 }
1108 }
1109 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1110 }
1111 /* SDC BG and FG must be disabled before DMA is disabled */
1112 if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1113 channel == IDMAC_SDC_1)) {
1114 for (timeout = 5;
1115 timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1116 msleep(5);
1117 }
1118
1119 spin_lock_irqsave(&ipu->lock, flags);
1120
1121 /* Disable IC task */
1122 ipu_ic_disable_task(ipu, channel);
1123
1124 /* Disable DMA channel(s) */
1125 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1126 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1127
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001128 spin_unlock_irqrestore(&ipu->lock, flags);
1129
1130 return 0;
1131}
1132
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001133static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1134 struct idmac_tx_desc **desc, struct scatterlist *sg)
1135{
1136 struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1137
1138 if (sgnew)
1139 /* next sg-element in this list */
1140 return sgnew;
1141
1142 if ((*desc)->list.next == &ichan->queue)
1143 /* No more descriptors on the queue */
1144 return NULL;
1145
1146 /* Fetch next descriptor */
1147 *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1148 return (*desc)->sg;
1149}
1150
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001151/*
1152 * We have several possibilities here:
1153 * current BUF next BUF
1154 *
1155 * not last sg next not last sg
1156 * not last sg next last sg
1157 * last sg first sg from next descriptor
1158 * last sg NULL
1159 *
1160 * Besides, the descriptor queue might be empty or not. We process all these
1161 * cases carefully.
1162 */
1163static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1164{
1165 struct idmac_channel *ichan = dev_id;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001166 struct device *dev = &ichan->dma_chan.dev->device;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001167 unsigned int chan_id = ichan->dma_chan.chan_id;
1168 struct scatterlist **sg, *sgnext, *sgnew = NULL;
1169 /* Next transfer descriptor */
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001170 struct idmac_tx_desc *desc, *descnew;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001171 dma_async_tx_callback callback;
1172 void *callback_param;
1173 bool done = false;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001174 u32 ready0, ready1, curbuf, err;
1175 unsigned long flags;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001176
1177 /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1178
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001179 dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1180
1181 spin_lock_irqsave(&ipu_data.lock, flags);
1182
1183 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1184 ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1185 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1186 err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1187
1188 if (err & (1 << chan_id)) {
1189 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1190 spin_unlock_irqrestore(&ipu_data.lock, flags);
1191 /*
1192 * Doing this
1193 * ichan->sg[0] = ichan->sg[1] = NULL;
1194 * you can force channel re-enable on the next tx_submit(), but
1195 * this is dirty - think about descriptors with multiple
1196 * sg elements.
1197 */
1198 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1199 chan_id, ready0, ready1, curbuf);
1200 return IRQ_HANDLED;
1201 }
1202 spin_unlock_irqrestore(&ipu_data.lock, flags);
1203
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001204 /* Other interrupts do not interfere with this channel */
1205 spin_lock(&ichan->lock);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001206 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1207 (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1208 )) {
1209 spin_unlock(&ichan->lock);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001210 dev_dbg(dev,
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001211 "IRQ with active buffer still ready on channel %x, "
1212 "active %d, ready %x, %x!\n", chan_id,
1213 ichan->active_buffer, ready0, ready1);
1214 return IRQ_NONE;
1215 }
1216
1217 if (unlikely(list_empty(&ichan->queue))) {
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001218 ichan->sg[ichan->active_buffer] = NULL;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001219 spin_unlock(&ichan->lock);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001220 dev_err(dev,
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001221 "IRQ without queued buffers on channel %x, active %d, "
1222 "ready %x, %x!\n", chan_id,
1223 ichan->active_buffer, ready0, ready1);
1224 return IRQ_NONE;
1225 }
1226
1227 /*
1228 * active_buffer is a software flag, it shows which buffer we are
1229 * currently expecting back from the hardware, IDMAC should be
1230 * processing the other buffer already
1231 */
1232 sg = &ichan->sg[ichan->active_buffer];
1233 sgnext = ichan->sg[!ichan->active_buffer];
1234
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001235 if (!*sg) {
1236 spin_unlock(&ichan->lock);
1237 return IRQ_HANDLED;
1238 }
1239
1240 desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1241 descnew = desc;
1242
1243 dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
1244 irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
1245
1246 /* Find the descriptor of sgnext */
1247 sgnew = idmac_sg_next(ichan, &descnew, *sg);
1248 if (sgnext != sgnew)
1249 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1250
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001251 /*
1252 * if sgnext == NULL sg must be the last element in a scatterlist and
1253 * queue must be empty
1254 */
1255 if (unlikely(!sgnext)) {
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001256 if (!WARN_ON(sg_next(*sg)))
1257 dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1258 ichan->sg[!ichan->active_buffer] = sgnew;
1259
1260 if (unlikely(sgnew)) {
1261 ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001262 } else {
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001263 spin_lock_irqsave(&ipu_data.lock, flags);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001264 ipu_ic_disable_task(&ipu_data, chan_id);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001265 spin_unlock_irqrestore(&ipu_data.lock, flags);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001266 ichan->status = IPU_CHANNEL_READY;
1267 /* Continue to check for complete descriptor */
1268 }
1269 }
1270
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001271 /* Calculate and submit the next sg element */
1272 sgnew = idmac_sg_next(ichan, &descnew, sgnew);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001273
1274 if (unlikely(!sg_next(*sg)) || !sgnext) {
1275 /*
1276 * Last element in scatterlist done, remove from the queue,
1277 * _init for debugging
1278 */
1279 list_del_init(&desc->list);
1280 done = true;
1281 }
1282
1283 *sg = sgnew;
1284
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001285 if (likely(sgnew) &&
1286 ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
Guennadi Liakhovetski8f987812010-02-10 17:32:38 +01001287 callback = descnew->txd.callback;
1288 callback_param = descnew->txd.callback_param;
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001289 list_del_init(&descnew->list);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001290 spin_unlock(&ichan->lock);
Guennadi Liakhovetski8f987812010-02-10 17:32:38 +01001291 if (callback)
1292 callback(callback_param);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001293 spin_lock(&ichan->lock);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001294 }
1295
1296 /* Flip the active buffer - even if update above failed */
1297 ichan->active_buffer = !ichan->active_buffer;
1298 if (done)
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +00001299 ichan->dma_chan.completed_cookie = desc->txd.cookie;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001300
1301 callback = desc->txd.callback;
1302 callback_param = desc->txd.callback_param;
1303
1304 spin_unlock(&ichan->lock);
1305
1306 if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1307 callback(callback_param);
1308
1309 return IRQ_HANDLED;
1310}
1311
1312static void ipu_gc_tasklet(unsigned long arg)
1313{
1314 struct ipu *ipu = (struct ipu *)arg;
1315 int i;
1316
1317 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1318 struct idmac_channel *ichan = ipu->channel + i;
1319 struct idmac_tx_desc *desc;
1320 unsigned long flags;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001321 struct scatterlist *sg;
1322 int j, k;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001323
1324 for (j = 0; j < ichan->n_tx_desc; j++) {
1325 desc = ichan->desc + j;
1326 spin_lock_irqsave(&ichan->lock, flags);
1327 if (async_tx_test_ack(&desc->txd)) {
1328 list_move(&desc->list, &ichan->free_list);
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001329 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1330 if (ichan->sg[0] == sg)
1331 ichan->sg[0] = NULL;
1332 else if (ichan->sg[1] == sg)
1333 ichan->sg[1] = NULL;
1334 }
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001335 async_tx_clear_ack(&desc->txd);
1336 }
1337 spin_unlock_irqrestore(&ichan->lock, flags);
1338 }
1339 }
1340}
1341
Guennadi Liakhovetski0149f7d2009-03-25 09:13:23 -07001342/* Allocate and initialise a transfer descriptor. */
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001343static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1344 struct scatterlist *sgl, unsigned int sg_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +05301345 enum dma_transfer_direction direction, unsigned long tx_flags)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001346{
1347 struct idmac_channel *ichan = to_idmac_chan(chan);
1348 struct idmac_tx_desc *desc = NULL;
1349 struct dma_async_tx_descriptor *txd = NULL;
1350 unsigned long flags;
1351
1352 /* We only can handle these three channels so far */
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001353 if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1354 chan->chan_id != IDMAC_IC_7)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001355 return NULL;
1356
Vinod Kouldb8196d2011-10-13 22:34:23 +05301357 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001358 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1359 return NULL;
1360 }
1361
1362 mutex_lock(&ichan->chan_mutex);
1363
1364 spin_lock_irqsave(&ichan->lock, flags);
1365 if (!list_empty(&ichan->free_list)) {
1366 desc = list_entry(ichan->free_list.next,
1367 struct idmac_tx_desc, list);
1368
1369 list_del_init(&desc->list);
1370
1371 desc->sg_len = sg_len;
1372 desc->sg = sgl;
1373 txd = &desc->txd;
1374 txd->flags = tx_flags;
1375 }
1376 spin_unlock_irqrestore(&ichan->lock, flags);
1377
1378 mutex_unlock(&ichan->chan_mutex);
1379
1380 tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1381
1382 return txd;
1383}
1384
1385/* Re-select the current buffer and re-activate the channel */
1386static void idmac_issue_pending(struct dma_chan *chan)
1387{
1388 struct idmac_channel *ichan = to_idmac_chan(chan);
1389 struct idmac *idmac = to_idmac(chan->device);
1390 struct ipu *ipu = to_ipu(idmac);
1391 unsigned long flags;
1392
1393 /* This is not always needed, but doesn't hurt either */
1394 spin_lock_irqsave(&ipu->lock, flags);
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001395 ipu_select_buffer(chan->chan_id, ichan->active_buffer);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001396 spin_unlock_irqrestore(&ipu->lock, flags);
1397
1398 /*
1399 * Might need to perform some parts of initialisation from
1400 * ipu_enable_channel(), but not all, we do not want to reset to buffer
1401 * 0, don't need to set priority again either, but re-enabling the task
1402 * and the channel might be a good idea.
1403 */
1404}
1405
Linus Walleij05827632010-05-17 16:30:42 -07001406static int __idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1407 unsigned long arg)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001408{
1409 struct idmac_channel *ichan = to_idmac_chan(chan);
1410 struct idmac *idmac = to_idmac(chan->device);
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001411 struct ipu *ipu = to_ipu(idmac);
1412 struct list_head *list, *tmp;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001413 unsigned long flags;
1414 int i;
1415
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001416 switch (cmd) {
1417 case DMA_PAUSE:
1418 spin_lock_irqsave(&ipu->lock, flags);
1419 ipu_ic_disable_task(ipu, chan->chan_id);
Linus Walleijc3635c72010-03-26 16:44:01 -07001420
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001421 /* Return all descriptors into "prepared" state */
1422 list_for_each_safe(list, tmp, &ichan->queue)
1423 list_del_init(list);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001424
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001425 ichan->sg[0] = NULL;
1426 ichan->sg[1] = NULL;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001427
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001428 spin_unlock_irqrestore(&ipu->lock, flags);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001429
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001430 ichan->status = IPU_CHANNEL_INITIALIZED;
1431 break;
1432 case DMA_TERMINATE_ALL:
1433 ipu_disable_channel(idmac, ichan,
1434 ichan->status >= IPU_CHANNEL_ENABLED);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001435
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001436 tasklet_disable(&ipu->tasklet);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001437
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001438 /* ichan->queue is modified in ISR, have to spinlock */
1439 spin_lock_irqsave(&ichan->lock, flags);
1440 list_splice_init(&ichan->queue, &ichan->free_list);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001441
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001442 if (ichan->desc)
1443 for (i = 0; i < ichan->n_tx_desc; i++) {
1444 struct idmac_tx_desc *desc = ichan->desc + i;
1445 if (list_empty(&desc->list))
1446 /* Descriptor was prepared, but not submitted */
1447 list_add(&desc->list, &ichan->free_list);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001448
Guennadi Liakhovetski1d3564d2011-08-25 13:26:53 -03001449 async_tx_clear_ack(&desc->txd);
1450 }
1451
1452 ichan->sg[0] = NULL;
1453 ichan->sg[1] = NULL;
1454 spin_unlock_irqrestore(&ichan->lock, flags);
1455
1456 tasklet_enable(&ipu->tasklet);
1457
1458 ichan->status = IPU_CHANNEL_INITIALIZED;
1459 break;
1460 default:
1461 return -ENOSYS;
1462 }
Linus Walleijc3635c72010-03-26 16:44:01 -07001463
1464 return 0;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001465}
1466
Linus Walleij05827632010-05-17 16:30:42 -07001467static int idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1468 unsigned long arg)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001469{
1470 struct idmac_channel *ichan = to_idmac_chan(chan);
Linus Walleijc3635c72010-03-26 16:44:01 -07001471 int ret;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001472
1473 mutex_lock(&ichan->chan_mutex);
1474
Linus Walleij05827632010-05-17 16:30:42 -07001475 ret = __idmac_control(chan, cmd, arg);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001476
1477 mutex_unlock(&ichan->chan_mutex);
Linus Walleijc3635c72010-03-26 16:44:01 -07001478
1479 return ret;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001480}
1481
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001482#ifdef DEBUG
1483static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1484{
1485 struct idmac_channel *ichan = dev_id;
1486 printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1487 irq, ichan->dma_chan.chan_id);
Ben Nizetteca50a512009-04-16 05:54:12 +10001488 disable_irq_nosync(irq);
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001489 return IRQ_HANDLED;
1490}
1491
1492static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1493{
1494 struct idmac_channel *ichan = dev_id;
1495 printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1496 irq, ichan->dma_chan.chan_id);
Ben Nizetteca50a512009-04-16 05:54:12 +10001497 disable_irq_nosync(irq);
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001498 return IRQ_HANDLED;
1499}
1500
1501static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1502#endif
1503
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001504static int idmac_alloc_chan_resources(struct dma_chan *chan)
1505{
1506 struct idmac_channel *ichan = to_idmac_chan(chan);
1507 struct idmac *idmac = to_idmac(chan->device);
1508 int ret;
1509
1510 /* dmaengine.c now guarantees to only offer free channels */
1511 BUG_ON(chan->client_count > 1);
1512 WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1513
1514 chan->cookie = 1;
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +00001515 chan->completed_cookie = -ENXIO;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001516
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001517 ret = ipu_irq_map(chan->chan_id);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001518 if (ret < 0)
1519 goto eimap;
1520
1521 ichan->eof_irq = ret;
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001522
1523 /*
1524 * Important to first disable the channel, because maybe someone
1525 * used it before us, e.g., the bootloader
1526 */
1527 ipu_disable_channel(idmac, ichan, true);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001528
1529 ret = ipu_init_channel(idmac, ichan);
1530 if (ret < 0)
1531 goto eichan;
1532
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001533 ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1534 ichan->eof_name, ichan);
1535 if (ret < 0)
1536 goto erirq;
1537
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001538#ifdef DEBUG
1539 if (chan->chan_id == IDMAC_IC_7) {
1540 ic_sof = ipu_irq_map(69);
1541 if (ic_sof > 0)
1542 request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1543 ic_eof = ipu_irq_map(70);
1544 if (ic_eof > 0)
1545 request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1546 }
1547#endif
1548
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001549 ichan->status = IPU_CHANNEL_INITIALIZED;
1550
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001551 dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1552 chan->chan_id, ichan->eof_irq);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001553
1554 return ret;
1555
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001556erirq:
Guennadi Liakhovetski8d47bae2009-03-25 09:13:24 -07001557 ipu_uninit_channel(idmac, ichan);
1558eichan:
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001559 ipu_irq_unmap(chan->chan_id);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001560eimap:
1561 return ret;
1562}
1563
1564static void idmac_free_chan_resources(struct dma_chan *chan)
1565{
1566 struct idmac_channel *ichan = to_idmac_chan(chan);
1567 struct idmac *idmac = to_idmac(chan->device);
1568
1569 mutex_lock(&ichan->chan_mutex);
1570
Linus Walleij05827632010-05-17 16:30:42 -07001571 __idmac_control(chan, DMA_TERMINATE_ALL, 0);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001572
1573 if (ichan->status > IPU_CHANNEL_FREE) {
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001574#ifdef DEBUG
1575 if (chan->chan_id == IDMAC_IC_7) {
1576 if (ic_sof > 0) {
1577 free_irq(ic_sof, ichan);
1578 ipu_irq_unmap(69);
1579 ic_sof = -EINVAL;
1580 }
1581 if (ic_eof > 0) {
1582 free_irq(ic_eof, ichan);
1583 ipu_irq_unmap(70);
1584 ic_eof = -EINVAL;
1585 }
1586 }
1587#endif
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001588 free_irq(ichan->eof_irq, ichan);
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001589 ipu_irq_unmap(chan->chan_id);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001590 }
1591
1592 ichan->status = IPU_CHANNEL_FREE;
1593
1594 ipu_uninit_channel(idmac, ichan);
1595
1596 mutex_unlock(&ichan->chan_mutex);
1597
1598 tasklet_schedule(&to_ipu(idmac)->tasklet);
1599}
1600
Linus Walleij07934482010-03-26 16:50:49 -07001601static enum dma_status idmac_tx_status(struct dma_chan *chan,
1602 dma_cookie_t cookie, struct dma_tx_state *txstate)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001603{
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +00001604 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 0);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001605 if (cookie != chan->cookie)
1606 return DMA_ERROR;
1607 return DMA_SUCCESS;
1608}
1609
1610static int __init ipu_idmac_init(struct ipu *ipu)
1611{
1612 struct idmac *idmac = &ipu->idmac;
1613 struct dma_device *dma = &idmac->dma;
1614 int i;
1615
1616 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1617 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1618
1619 /* Compulsory common fields */
1620 dma->dev = ipu->dev;
1621 dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
1622 dma->device_free_chan_resources = idmac_free_chan_resources;
Linus Walleij07934482010-03-26 16:50:49 -07001623 dma->device_tx_status = idmac_tx_status;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001624 dma->device_issue_pending = idmac_issue_pending;
1625
1626 /* Compulsory for DMA_SLAVE fields */
1627 dma->device_prep_slave_sg = idmac_prep_slave_sg;
Linus Walleijc3635c72010-03-26 16:44:01 -07001628 dma->device_control = idmac_control;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001629
1630 INIT_LIST_HEAD(&dma->channels);
1631 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1632 struct idmac_channel *ichan = ipu->channel + i;
1633 struct dma_chan *dma_chan = &ichan->dma_chan;
1634
1635 spin_lock_init(&ichan->lock);
1636 mutex_init(&ichan->chan_mutex);
1637
1638 ichan->status = IPU_CHANNEL_FREE;
1639 ichan->sec_chan_en = false;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001640 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1641
1642 dma_chan->device = &idmac->dma;
1643 dma_chan->cookie = 1;
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +00001644 dma_chan->completed_cookie = -ENXIO;
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001645 dma_chan->chan_id = i;
Guennadi Liakhovetski8c6db1bb2009-04-02 11:36:58 +02001646 list_add_tail(&dma_chan->device_node, &dma->channels);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001647 }
1648
1649 idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1650
1651 return dma_async_device_register(&idmac->dma);
1652}
1653
Guennadi Liakhovetski234f2df2009-03-25 09:13:24 -07001654static void __exit ipu_idmac_exit(struct ipu *ipu)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001655{
1656 int i;
1657 struct idmac *idmac = &ipu->idmac;
1658
1659 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1660 struct idmac_channel *ichan = ipu->channel + i;
1661
Linus Walleij05827632010-05-17 16:30:42 -07001662 idmac_control(&ichan->dma_chan, DMA_TERMINATE_ALL, 0);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001663 }
1664
1665 dma_async_device_unregister(&idmac->dma);
1666}
1667
1668/*****************************************************************************
1669 * IPU common probe / remove
1670 */
1671
Guennadi Liakhovetski234f2df2009-03-25 09:13:24 -07001672static int __init ipu_probe(struct platform_device *pdev)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001673{
1674 struct ipu_platform_data *pdata = pdev->dev.platform_data;
1675 struct resource *mem_ipu, *mem_ic;
1676 int ret;
1677
1678 spin_lock_init(&ipu_data.lock);
1679
1680 mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1681 mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1682 if (!pdata || !mem_ipu || !mem_ic)
1683 return -EINVAL;
1684
1685 ipu_data.dev = &pdev->dev;
1686
1687 platform_set_drvdata(pdev, &ipu_data);
1688
1689 ret = platform_get_irq(pdev, 0);
1690 if (ret < 0)
1691 goto err_noirq;
1692
1693 ipu_data.irq_fn = ret;
1694 ret = platform_get_irq(pdev, 1);
1695 if (ret < 0)
1696 goto err_noirq;
1697
1698 ipu_data.irq_err = ret;
1699 ipu_data.irq_base = pdata->irq_base;
1700
1701 dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1702 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1703
1704 /* Remap IPU common registers */
H Hartley Sweeten7dab35c2011-06-01 15:10:30 -07001705 ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001706 if (!ipu_data.reg_ipu) {
1707 ret = -ENOMEM;
1708 goto err_ioremap_ipu;
1709 }
1710
1711 /* Remap Image Converter and Image DMA Controller registers */
H Hartley Sweeten7dab35c2011-06-01 15:10:30 -07001712 ipu_data.reg_ic = ioremap(mem_ic->start, resource_size(mem_ic));
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001713 if (!ipu_data.reg_ic) {
1714 ret = -ENOMEM;
1715 goto err_ioremap_ic;
1716 }
1717
1718 /* Get IPU clock */
Sascha Hauer9eb2eb82009-02-18 11:55:33 +01001719 ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001720 if (IS_ERR(ipu_data.ipu_clk)) {
1721 ret = PTR_ERR(ipu_data.ipu_clk);
1722 goto err_clk_get;
1723 }
1724
1725 /* Make sure IPU HSP clock is running */
1726 clk_enable(ipu_data.ipu_clk);
1727
1728 /* Disable all interrupts */
1729 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1730 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1731 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1732 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1733 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1734
1735 dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1736 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1737
1738 ret = ipu_irq_attach_irq(&ipu_data, pdev);
1739 if (ret < 0)
1740 goto err_attach_irq;
1741
1742 /* Initialize DMA engine */
1743 ret = ipu_idmac_init(&ipu_data);
1744 if (ret < 0)
1745 goto err_idmac_init;
1746
1747 tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1748
1749 ipu_data.dev = &pdev->dev;
1750
1751 dev_dbg(ipu_data.dev, "IPU initialized\n");
1752
1753 return 0;
1754
1755err_idmac_init:
1756err_attach_irq:
1757 ipu_irq_detach_irq(&ipu_data, pdev);
1758 clk_disable(ipu_data.ipu_clk);
1759 clk_put(ipu_data.ipu_clk);
1760err_clk_get:
1761 iounmap(ipu_data.reg_ic);
1762err_ioremap_ic:
1763 iounmap(ipu_data.reg_ipu);
1764err_ioremap_ipu:
1765err_noirq:
1766 dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1767 return ret;
1768}
1769
Guennadi Liakhovetski234f2df2009-03-25 09:13:24 -07001770static int __exit ipu_remove(struct platform_device *pdev)
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001771{
1772 struct ipu *ipu = platform_get_drvdata(pdev);
1773
1774 ipu_idmac_exit(ipu);
1775 ipu_irq_detach_irq(ipu, pdev);
1776 clk_disable(ipu->ipu_clk);
1777 clk_put(ipu->ipu_clk);
1778 iounmap(ipu->reg_ic);
1779 iounmap(ipu->reg_ipu);
1780 tasklet_kill(&ipu->tasklet);
1781 platform_set_drvdata(pdev, NULL);
1782
1783 return 0;
1784}
1785
1786/*
1787 * We need two MEM resources - with IPU-common and Image Converter registers,
1788 * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1789 */
1790static struct platform_driver ipu_platform_driver = {
1791 .driver = {
1792 .name = "ipu-core",
1793 .owner = THIS_MODULE,
1794 },
Guennadi Liakhovetski234f2df2009-03-25 09:13:24 -07001795 .remove = __exit_p(ipu_remove),
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -07001796};
1797
1798static int __init ipu_init(void)
1799{
1800 return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1801}
1802subsys_initcall(ipu_init);
1803
1804MODULE_DESCRIPTION("IPU core driver");
1805MODULE_LICENSE("GPL v2");
1806MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1807MODULE_ALIAS("platform:ipu-core");