blob: 339c210f03a67ce016c2d0a6a444f228ebc22497 [file] [log] [blame]
David Milburn02cdfcf2010-11-12 15:38:21 -06001
2/*
3 * acard-ahci.c - ACard AHCI SATA support
4 *
5 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2010 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * AHCI hardware documentation:
31 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
32 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
33 *
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/blkdev.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/dma-mapping.h>
44#include <linux/device.h>
45#include <linux/dmi.h>
46#include <linux/gfp.h>
47#include <scsi/scsi_host.h>
48#include <scsi/scsi_cmnd.h>
49#include <linux/libata.h>
50#include "ahci.h"
51
52#define DRV_NAME "acard-ahci"
53#define DRV_VERSION "1.0"
54
55/*
56 Received FIS structure limited to 80h.
57*/
58
59#define ACARD_AHCI_RX_FIS_SZ 128
60
61enum {
62 AHCI_PCI_BAR = 5,
63};
64
65enum board_ids {
66 board_acard_ahci,
67};
68
69struct acard_sg {
70 __le32 addr;
71 __le32 addr_hi;
72 __le32 reserved;
73 __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */
74};
75
76static void acard_ahci_qc_prep(struct ata_queued_cmd *qc);
77static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
78static int acard_ahci_port_start(struct ata_port *ap);
79static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
80
81#ifdef CONFIG_PM
82static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
83static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
84#endif
85
86static struct scsi_host_template acard_ahci_sht = {
87 AHCI_SHT("acard-ahci"),
88};
89
90static struct ata_port_operations acard_ops = {
91 .inherits = &ahci_ops,
92 .qc_prep = acard_ahci_qc_prep,
93 .qc_fill_rtf = acard_ahci_qc_fill_rtf,
94 .port_start = acard_ahci_port_start,
95};
96
97#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
98
99static const struct ata_port_info acard_ahci_port_info[] = {
100 [board_acard_ahci] =
101 {
102 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
103 .flags = AHCI_FLAG_COMMON,
104 .pio_mask = ATA_PIO4,
105 .udma_mask = ATA_UDMA6,
106 .port_ops = &acard_ops,
107 },
108};
109
110static const struct pci_device_id acard_ahci_pci_tbl[] = {
111 /* ACard */
112 { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */
113
114 { } /* terminate list */
115};
116
117static struct pci_driver acard_ahci_pci_driver = {
118 .name = DRV_NAME,
119 .id_table = acard_ahci_pci_tbl,
120 .probe = acard_ahci_init_one,
121 .remove = ata_pci_remove_one,
122#ifdef CONFIG_PM
123 .suspend = acard_ahci_pci_device_suspend,
124 .resume = acard_ahci_pci_device_resume,
125#endif
126};
127
128#ifdef CONFIG_PM
129static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
130{
131 struct ata_host *host = dev_get_drvdata(&pdev->dev);
132 struct ahci_host_priv *hpriv = host->private_data;
133 void __iomem *mmio = hpriv->mmio;
134 u32 ctl;
135
136 if (mesg.event & PM_EVENT_SUSPEND &&
137 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
138 dev_printk(KERN_ERR, &pdev->dev,
139 "BIOS update required for suspend/resume\n");
140 return -EIO;
141 }
142
143 if (mesg.event & PM_EVENT_SLEEP) {
144 /* AHCI spec rev1.1 section 8.3.3:
145 * Software must disable interrupts prior to requesting a
146 * transition of the HBA to D3 state.
147 */
148 ctl = readl(mmio + HOST_CTL);
149 ctl &= ~HOST_IRQ_EN;
150 writel(ctl, mmio + HOST_CTL);
151 readl(mmio + HOST_CTL); /* flush */
152 }
153
154 return ata_pci_device_suspend(pdev, mesg);
155}
156
157static int acard_ahci_pci_device_resume(struct pci_dev *pdev)
158{
159 struct ata_host *host = dev_get_drvdata(&pdev->dev);
160 int rc;
161
162 rc = ata_pci_device_do_resume(pdev);
163 if (rc)
164 return rc;
165
166 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
167 rc = ahci_reset_controller(host);
168 if (rc)
169 return rc;
170
171 ahci_init_controller(host);
172 }
173
174 ata_host_resume(host);
175
176 return 0;
177}
178#endif
179
180static int acard_ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
181{
182 int rc;
183
184 if (using_dac &&
185 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
186 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
187 if (rc) {
188 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
189 if (rc) {
190 dev_printk(KERN_ERR, &pdev->dev,
191 "64-bit DMA enable failed\n");
192 return rc;
193 }
194 }
195 } else {
196 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
197 if (rc) {
198 dev_printk(KERN_ERR, &pdev->dev,
199 "32-bit DMA enable failed\n");
200 return rc;
201 }
202 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
203 if (rc) {
204 dev_printk(KERN_ERR, &pdev->dev,
205 "32-bit consistent DMA enable failed\n");
206 return rc;
207 }
208 }
209 return 0;
210}
211
212static void acard_ahci_pci_print_info(struct ata_host *host)
213{
214 struct pci_dev *pdev = to_pci_dev(host->dev);
215 u16 cc;
216 const char *scc_s;
217
218 pci_read_config_word(pdev, 0x0a, &cc);
219 if (cc == PCI_CLASS_STORAGE_IDE)
220 scc_s = "IDE";
221 else if (cc == PCI_CLASS_STORAGE_SATA)
222 scc_s = "SATA";
223 else if (cc == PCI_CLASS_STORAGE_RAID)
224 scc_s = "RAID";
225 else
226 scc_s = "unknown";
227
228 ahci_print_info(host, scc_s);
229}
230
231static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
232{
233 struct scatterlist *sg;
234 struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
235 unsigned int si, last_si = 0;
236
237 VPRINTK("ENTER\n");
238
239 /*
240 * Next, the S/G list.
241 */
242 for_each_sg(qc->sg, sg, qc->n_elem, si) {
243 dma_addr_t addr = sg_dma_address(sg);
244 u32 sg_len = sg_dma_len(sg);
245
246 /*
247 * ACard note:
248 * We must set an end-of-table (EOT) bit,
249 * and the segment cannot exceed 64k (0x10000)
250 */
251 acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
252 acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
253 acard_sg[si].size = cpu_to_le32(sg_len);
254 last_si = si;
255 }
256
257 acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */
258
259 return si;
260}
261
262static void acard_ahci_qc_prep(struct ata_queued_cmd *qc)
263{
264 struct ata_port *ap = qc->ap;
265 struct ahci_port_priv *pp = ap->private_data;
266 int is_atapi = ata_is_atapi(qc->tf.protocol);
267 void *cmd_tbl;
268 u32 opts;
269 const u32 cmd_fis_len = 5; /* five dwords */
270 unsigned int n_elem;
271
272 /*
273 * Fill in command table information. First, the header,
274 * a SATA Register - Host to Device command FIS.
275 */
276 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
277
278 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
279 if (is_atapi) {
280 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
281 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
282 }
283
284 n_elem = 0;
285 if (qc->flags & ATA_QCFLAG_DMAMAP)
286 n_elem = acard_ahci_fill_sg(qc, cmd_tbl);
287
288 /*
289 * Fill in command slot information.
290 *
291 * ACard note: prd table length not filled in
292 */
293 opts = cmd_fis_len | (qc->dev->link->pmp << 12);
294 if (qc->tf.flags & ATA_TFLAG_WRITE)
295 opts |= AHCI_CMD_WRITE;
296 if (is_atapi)
297 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
298
299 ahci_fill_cmd_slot(pp, qc->tag, opts);
300}
301
302static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
303{
304 struct ahci_port_priv *pp = qc->ap->private_data;
305 u8 *rx_fis = pp->rx_fis;
306
307 if (pp->fbs_enabled)
308 rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ;
309
310 /*
311 * After a successful execution of an ATA PIO data-in command,
312 * the device doesn't send D2H Reg FIS to update the TF and
313 * the host should take TF and E_Status from the preceding PIO
314 * Setup FIS.
315 */
316 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
317 !(qc->flags & ATA_QCFLAG_FAILED)) {
318 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
319 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
320 } else
321 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
322
323 return true;
324}
325
326static int acard_ahci_port_start(struct ata_port *ap)
327{
328 struct ahci_host_priv *hpriv = ap->host->private_data;
329 struct device *dev = ap->host->dev;
330 struct ahci_port_priv *pp;
331 void *mem;
332 dma_addr_t mem_dma;
333 size_t dma_sz, rx_fis_sz;
334
335 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
336 if (!pp)
337 return -ENOMEM;
338
339 /* check FBS capability */
340 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
341 void __iomem *port_mmio = ahci_port_base(ap);
342 u32 cmd = readl(port_mmio + PORT_CMD);
343 if (cmd & PORT_CMD_FBSCP)
344 pp->fbs_supported = true;
345 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
346 dev_printk(KERN_INFO, dev,
347 "port %d can do FBS, forcing FBSCP\n",
348 ap->port_no);
349 pp->fbs_supported = true;
350 } else
351 dev_printk(KERN_WARNING, dev,
352 "port %d is not capable of FBS\n",
353 ap->port_no);
354 }
355
356 if (pp->fbs_supported) {
357 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
358 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16;
359 } else {
360 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
361 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ;
362 }
363
364 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
365 if (!mem)
366 return -ENOMEM;
367 memset(mem, 0, dma_sz);
368
369 /*
370 * First item in chunk of DMA memory: 32-slot command table,
371 * 32 bytes each in size
372 */
373 pp->cmd_slot = mem;
374 pp->cmd_slot_dma = mem_dma;
375
376 mem += AHCI_CMD_SLOT_SZ;
377 mem_dma += AHCI_CMD_SLOT_SZ;
378
379 /*
380 * Second item: Received-FIS area
381 */
382 pp->rx_fis = mem;
383 pp->rx_fis_dma = mem_dma;
384
385 mem += rx_fis_sz;
386 mem_dma += rx_fis_sz;
387
388 /*
389 * Third item: data area for storing a single command
390 * and its scatter-gather table
391 */
392 pp->cmd_tbl = mem;
393 pp->cmd_tbl_dma = mem_dma;
394
395 /*
396 * Save off initial list of interrupts to be enabled.
397 * This could be changed later
398 */
399 pp->intr_mask = DEF_PORT_IRQ;
400
401 ap->private_data = pp;
402
403 /* engage engines, captain */
404 return ahci_port_resume(ap);
405}
406
407static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
408{
409 static int printed_version;
410 unsigned int board_id = ent->driver_data;
411 struct ata_port_info pi = acard_ahci_port_info[board_id];
412 const struct ata_port_info *ppi[] = { &pi, NULL };
413 struct device *dev = &pdev->dev;
414 struct ahci_host_priv *hpriv;
415 struct ata_host *host;
416 int n_ports, i, rc;
417
418 VPRINTK("ENTER\n");
419
420 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
421
422 if (!printed_version++)
423 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
424
425 /* acquire resources */
426 rc = pcim_enable_device(pdev);
427 if (rc)
428 return rc;
429
430 /* AHCI controllers often implement SFF compatible interface.
431 * Grab all PCI BARs just in case.
432 */
433 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
434 if (rc == -EBUSY)
435 pcim_pin_device(pdev);
436 if (rc)
437 return rc;
438
439 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
440 if (!hpriv)
441 return -ENOMEM;
442 hpriv->flags |= (unsigned long)pi.private_data;
443
444 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
445 pci_enable_msi(pdev);
446
447 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
448
449 /* save initial config */
450 ahci_save_initial_config(&pdev->dev, hpriv, 0, 0);
451
452 /* prepare host */
453 if (hpriv->cap & HOST_CAP_NCQ)
454 pi.flags |= ATA_FLAG_NCQ;
455
456 if (hpriv->cap & HOST_CAP_PMP)
457 pi.flags |= ATA_FLAG_PMP;
458
459 ahci_set_em_messages(hpriv, &pi);
460
461 /* CAP.NP sometimes indicate the index of the last enabled
462 * port, at other times, that of the last possible port, so
463 * determining the maximum port number requires looking at
464 * both CAP.NP and port_map.
465 */
466 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
467
468 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
469 if (!host)
470 return -ENOMEM;
471 host->private_data = hpriv;
472
473 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
474 host->flags |= ATA_HOST_PARALLEL_SCAN;
475 else
476 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
477
478 for (i = 0; i < host->n_ports; i++) {
479 struct ata_port *ap = host->ports[i];
480
481 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
482 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
483 0x100 + ap->port_no * 0x80, "port");
484
485 /* set initial link pm policy */
486 /*
487 ap->pm_policy = NOT_AVAILABLE;
488 */
489 /* disabled/not-implemented port */
490 if (!(hpriv->port_map & (1 << i)))
491 ap->ops = &ata_dummy_port_ops;
492 }
493
494 /* initialize adapter */
495 rc = acard_ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
496 if (rc)
497 return rc;
498
499 rc = ahci_reset_controller(host);
500 if (rc)
501 return rc;
502
503 ahci_init_controller(host);
504 acard_ahci_pci_print_info(host);
505
506 pci_set_master(pdev);
507 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
508 &acard_ahci_sht);
509}
510
511static int __init acard_ahci_init(void)
512{
513 return pci_register_driver(&acard_ahci_pci_driver);
514}
515
516static void __exit acard_ahci_exit(void)
517{
518 pci_unregister_driver(&acard_ahci_pci_driver);
519}
520
521MODULE_AUTHOR("Jeff Garzik");
522MODULE_DESCRIPTION("ACard AHCI SATA low-level driver");
523MODULE_LICENSE("GPL");
524MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl);
525MODULE_VERSION(DRV_VERSION);
526
527module_init(acard_ahci_init);
528module_exit(acard_ahci_exit);