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Laurent Pinchartcb2025d2013-06-16 21:01:02 +02001/*
2 * rcar_du_group.c -- R-Car Display Unit Channels Pair
3 *
Laurent Pinchart2427b302015-09-07 17:34:26 +03004 * Copyright (C) 2013-2015 Renesas Electronics Corporation
Laurent Pinchartcb2025d2013-06-16 21:01:02 +02005 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14/*
15 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
16 * unit, timings generator, ...) and device-global resources (start/stop
17 * control, planes, ...) shared between the two CRTCs.
18 *
19 * The R8A7790 introduced a third CRTC with its own set of global resources.
20 * This would be modeled as two separate DU device instances if it wasn't for
21 * a handful or resources that are shared between the three CRTCs (mostly
22 * related to input and output routing). For this reason the R8A7790 DU must be
23 * modeled as a single device with three CRTCs, two sets of "semi-global"
24 * resources, and a few device-global resources.
25 *
26 * The rcar_du_group object is a driver specific object, without any real
27 * counterpart in the DU documentation, that models those semi-global resources.
28 */
29
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +020030#include <linux/clk.h>
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020031#include <linux/io.h>
32
33#include "rcar_du_drv.h"
34#include "rcar_du_group.h"
35#include "rcar_du_regs.h"
36
Laurent Pincharta5f0ef52013-06-17 00:29:25 +020037u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020038{
39 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
40}
41
Laurent Pincharta5f0ef52013-06-17 00:29:25 +020042void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020043{
44 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
45}
46
Laurent Pincharta5e18b22015-09-07 18:09:55 +030047static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
48{
49 u32 defr6 = DEFR6_CODE | DEFR6_ODPM12_DISP;
50
51 if (rgrp->num_crtcs > 1)
52 defr6 |= DEFR6_ODPM22_DISP;
53
54 rcar_du_group_write(rgrp, DEFR6, defr6);
55}
56
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +020057static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
58{
Laurent Pinchart2427b302015-09-07 17:34:26 +030059 struct rcar_du_device *rcdu = rgrp->dev;
60 unsigned int possible_crtcs =
61 rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
62 u32 defr8 = DEFR8_CODE;
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +020063
Laurent Pinchart2427b302015-09-07 17:34:26 +030064 if (rcdu->info->gen < 3) {
65 defr8 |= DEFR8_DEFE8;
66
67 /* On Gen2 the DEFR8 register for the first group also controls
68 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
69 * DU instances that support it.
70 */
71 if (rgrp->index == 0) {
72 if (possible_crtcs > 1)
73 defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
74 if (rgrp->dev->vspd1_sink == 2)
75 defr8 |= DEFR8_VSCS;
76 }
77 } else {
78 /* On Gen3 VSPD routing can't be configured, but DPAD routing
79 * needs to be set despite having a single option available.
80 */
81 u32 crtc = ffs(possible_crtcs) - 1;
82
83 if (crtc / 2 == rgrp->index)
84 defr8 |= DEFR8_DRGBS_DU(crtc);
Laurent Pinchart34a04f22013-06-21 17:54:50 +020085 }
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +020086
87 rcar_du_group_write(rgrp, DEFR8, defr8);
88}
89
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020090static void rcar_du_group_setup(struct rcar_du_group *rgrp)
91{
Laurent Pinchart2427b302015-09-07 17:34:26 +030092 struct rcar_du_device *rcdu = rgrp->dev;
93
Laurent Pinchartcb2025d2013-06-16 21:01:02 +020094 /* Enable extended features */
95 rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
Laurent Pinchart2427b302015-09-07 17:34:26 +030096 if (rcdu->info->gen < 3) {
97 rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
98 rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
99 rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
100 }
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200101 rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +0200102
Laurent Pincharta5e18b22015-09-07 18:09:55 +0300103 rcar_du_group_setup_pins(rgrp);
104
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200105 if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
Laurent Pinchart0c1c8772014-12-09 00:21:12 +0200106 rcar_du_group_setup_defr8(rgrp);
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200107
Laurent Pinchart1b30dbd2014-12-09 00:24:49 +0200108 /* Configure input dot clock routing. We currently hardcode the
109 * configuration to routing DOTCLKINn to DUn.
110 */
111 rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE |
112 DIDSR_LCDS_DCLKIN(2) |
113 DIDSR_LCDS_DCLKIN(1) |
114 DIDSR_LCDS_DCLKIN(0) |
115 DIDSR_PDCS_CLK(2, 0) |
116 DIDSR_PDCS_CLK(1, 0) |
117 DIDSR_PDCS_CLK(0, 0));
118 }
119
Laurent Pinchart2427b302015-09-07 17:34:26 +0300120 if (rcdu->info->gen >= 3)
121 rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
122
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200123 /* Use DS1PR and DS2PR to configure planes priorities and connects the
124 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
125 */
126 rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
Laurent Pinchart2a57e9b2015-04-28 18:01:45 +0300127
128 /* Apply planes to CRTCs association. */
129 mutex_lock(&rgrp->lock);
130 rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
131 rgrp->dptsr_planes);
132 mutex_unlock(&rgrp->lock);
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200133}
134
135/*
136 * rcar_du_group_get - Acquire a reference to the DU channels group
137 *
138 * Acquiring the first reference setups core registers. A reference must be held
139 * before accessing any hardware registers.
140 *
141 * This function must be called with the DRM mode_config lock held.
142 *
143 * Return 0 in case of success or a negative error code otherwise.
144 */
145int rcar_du_group_get(struct rcar_du_group *rgrp)
146{
147 if (rgrp->use_count)
148 goto done;
149
150 rcar_du_group_setup(rgrp);
151
152done:
153 rgrp->use_count++;
154 return 0;
155}
156
157/*
158 * rcar_du_group_put - Release a reference to the DU
159 *
160 * This function must be called with the DRM mode_config lock held.
161 */
162void rcar_du_group_put(struct rcar_du_group *rgrp)
163{
164 --rgrp->use_count;
165}
166
167static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
168{
169 rcar_du_group_write(rgrp, DSYSR,
170 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
171 (start ? DSYSR_DEN : DSYSR_DRES));
172}
173
174void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
175{
176 /* Many of the configuration bits are only updated when the display
177 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
178 * of those bits could be pre-configured, but others (especially the
179 * bits related to plane assignment to display timing controllers) need
180 * to be modified at runtime.
181 *
182 * Restart the display controller if a start is requested. Sorry for the
183 * flicker. It should be possible to move most of the "DRES-update" bits
184 * setup to driver initialization time and minimize the number of cases
185 * when the display controller will have to be restarted.
186 */
187 if (start) {
188 if (rgrp->used_crtcs++ != 0)
189 __rcar_du_group_start_stop(rgrp, false);
190 __rcar_du_group_start_stop(rgrp, true);
191 } else {
192 if (--rgrp->used_crtcs == 0)
193 __rcar_du_group_start_stop(rgrp, false);
194 }
195}
196
197void rcar_du_group_restart(struct rcar_du_group *rgrp)
198{
Laurent Pinchart2af03942013-08-24 02:17:03 +0200199 rgrp->need_restart = false;
200
Laurent Pinchartcb2025d2013-06-16 21:01:02 +0200201 __rcar_du_group_start_stop(rgrp, false);
202 __rcar_du_group_start_stop(rgrp, true);
203}
Laurent Pinchart2fd22db2013-06-17 00:11:05 +0200204
Laurent Pinchart34a04f22013-06-21 17:54:50 +0200205int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +0200206{
207 int ret;
208
Laurent Pinchart0c1c8772014-12-09 00:21:12 +0200209 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
210 return 0;
211
Laurent Pinchart34a04f22013-06-21 17:54:50 +0200212 /* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
213 * configured in the DEFR8 register of the first group. As this function
214 * can be called with the DU0 and DU1 CRTCs disabled, we need to enable
215 * the first group clock before accessing the register.
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +0200216 */
217 ret = clk_prepare_enable(rcdu->crtcs[0].clock);
218 if (ret < 0)
219 return ret;
220
221 rcar_du_group_setup_defr8(&rcdu->groups[0]);
222
223 clk_disable_unprepare(rcdu->crtcs[0].clock);
224
225 return 0;
226}
227
228int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
Laurent Pinchart2fd22db2013-06-17 00:11:05 +0200229{
230 struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
231 u32 dorcr = rcar_du_group_read(rgrp, DORCR);
232
233 dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
234
Laurent Pinchartef67a902013-06-17 03:13:11 +0200235 /* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
236 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
237 * by default.
Laurent Pinchart2fd22db2013-06-17 00:11:05 +0200238 */
Laurent Pinchartef67a902013-06-17 03:13:11 +0200239 if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
Laurent Pinchart2fd22db2013-06-17 00:11:05 +0200240 dorcr |= DORCR_PG2D_DS1;
241 else
242 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
243
244 rcar_du_group_write(rgrp, DORCR, dorcr);
Laurent Pinchart7cbc05c2013-06-17 03:20:08 +0200245
Laurent Pinchart34a04f22013-06-21 17:54:50 +0200246 return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
Laurent Pinchart2fd22db2013-06-17 00:11:05 +0200247}