Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 1 | /* |
| 2 | * max98095.c -- MAX98095 ALSA SoC Audio driver |
| 3 | * |
| 4 | * Copyright 2011 Maxim Integrated Products |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/moduleparam.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/pm.h> |
| 17 | #include <linux/i2c.h> |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 18 | #include <sound/core.h> |
| 19 | #include <sound/pcm.h> |
| 20 | #include <sound/pcm_params.h> |
| 21 | #include <sound/soc.h> |
| 22 | #include <sound/initval.h> |
| 23 | #include <sound/tlv.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <asm/div64.h> |
| 26 | #include <sound/max98095.h> |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 27 | #include <sound/jack.h> |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 28 | #include "max98095.h" |
| 29 | |
| 30 | enum max98095_type { |
| 31 | MAX98095, |
| 32 | }; |
| 33 | |
| 34 | struct max98095_cdata { |
| 35 | unsigned int rate; |
| 36 | unsigned int fmt; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 37 | int eq_sel; |
| 38 | int bq_sel; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | struct max98095_priv { |
| 42 | enum max98095_type devtype; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 43 | struct max98095_pdata *pdata; |
| 44 | unsigned int sysclk; |
| 45 | struct max98095_cdata dai[3]; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 46 | const char **eq_texts; |
| 47 | const char **bq_texts; |
| 48 | struct soc_enum eq_enum; |
| 49 | struct soc_enum bq_enum; |
| 50 | int eq_textcnt; |
| 51 | int bq_textcnt; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 52 | u8 lin_state; |
| 53 | unsigned int mic1pre; |
| 54 | unsigned int mic2pre; |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 55 | struct snd_soc_jack *headphone_jack; |
| 56 | struct snd_soc_jack *mic_jack; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | static const u8 max98095_reg_def[M98095_REG_CNT] = { |
| 60 | 0x00, /* 00 */ |
| 61 | 0x00, /* 01 */ |
| 62 | 0x00, /* 02 */ |
| 63 | 0x00, /* 03 */ |
| 64 | 0x00, /* 04 */ |
| 65 | 0x00, /* 05 */ |
| 66 | 0x00, /* 06 */ |
| 67 | 0x00, /* 07 */ |
| 68 | 0x00, /* 08 */ |
| 69 | 0x00, /* 09 */ |
| 70 | 0x00, /* 0A */ |
| 71 | 0x00, /* 0B */ |
| 72 | 0x00, /* 0C */ |
| 73 | 0x00, /* 0D */ |
| 74 | 0x00, /* 0E */ |
| 75 | 0x00, /* 0F */ |
| 76 | 0x00, /* 10 */ |
| 77 | 0x00, /* 11 */ |
| 78 | 0x00, /* 12 */ |
| 79 | 0x00, /* 13 */ |
| 80 | 0x00, /* 14 */ |
| 81 | 0x00, /* 15 */ |
| 82 | 0x00, /* 16 */ |
| 83 | 0x00, /* 17 */ |
| 84 | 0x00, /* 18 */ |
| 85 | 0x00, /* 19 */ |
| 86 | 0x00, /* 1A */ |
| 87 | 0x00, /* 1B */ |
| 88 | 0x00, /* 1C */ |
| 89 | 0x00, /* 1D */ |
| 90 | 0x00, /* 1E */ |
| 91 | 0x00, /* 1F */ |
| 92 | 0x00, /* 20 */ |
| 93 | 0x00, /* 21 */ |
| 94 | 0x00, /* 22 */ |
| 95 | 0x00, /* 23 */ |
| 96 | 0x00, /* 24 */ |
| 97 | 0x00, /* 25 */ |
| 98 | 0x00, /* 26 */ |
| 99 | 0x00, /* 27 */ |
| 100 | 0x00, /* 28 */ |
| 101 | 0x00, /* 29 */ |
| 102 | 0x00, /* 2A */ |
| 103 | 0x00, /* 2B */ |
| 104 | 0x00, /* 2C */ |
| 105 | 0x00, /* 2D */ |
| 106 | 0x00, /* 2E */ |
| 107 | 0x00, /* 2F */ |
| 108 | 0x00, /* 30 */ |
| 109 | 0x00, /* 31 */ |
| 110 | 0x00, /* 32 */ |
| 111 | 0x00, /* 33 */ |
| 112 | 0x00, /* 34 */ |
| 113 | 0x00, /* 35 */ |
| 114 | 0x00, /* 36 */ |
| 115 | 0x00, /* 37 */ |
| 116 | 0x00, /* 38 */ |
| 117 | 0x00, /* 39 */ |
| 118 | 0x00, /* 3A */ |
| 119 | 0x00, /* 3B */ |
| 120 | 0x00, /* 3C */ |
| 121 | 0x00, /* 3D */ |
| 122 | 0x00, /* 3E */ |
| 123 | 0x00, /* 3F */ |
| 124 | 0x00, /* 40 */ |
| 125 | 0x00, /* 41 */ |
| 126 | 0x00, /* 42 */ |
| 127 | 0x00, /* 43 */ |
| 128 | 0x00, /* 44 */ |
| 129 | 0x00, /* 45 */ |
| 130 | 0x00, /* 46 */ |
| 131 | 0x00, /* 47 */ |
| 132 | 0x00, /* 48 */ |
| 133 | 0x00, /* 49 */ |
| 134 | 0x00, /* 4A */ |
| 135 | 0x00, /* 4B */ |
| 136 | 0x00, /* 4C */ |
| 137 | 0x00, /* 4D */ |
| 138 | 0x00, /* 4E */ |
| 139 | 0x00, /* 4F */ |
| 140 | 0x00, /* 50 */ |
| 141 | 0x00, /* 51 */ |
| 142 | 0x00, /* 52 */ |
| 143 | 0x00, /* 53 */ |
| 144 | 0x00, /* 54 */ |
| 145 | 0x00, /* 55 */ |
| 146 | 0x00, /* 56 */ |
| 147 | 0x00, /* 57 */ |
| 148 | 0x00, /* 58 */ |
| 149 | 0x00, /* 59 */ |
| 150 | 0x00, /* 5A */ |
| 151 | 0x00, /* 5B */ |
| 152 | 0x00, /* 5C */ |
| 153 | 0x00, /* 5D */ |
| 154 | 0x00, /* 5E */ |
| 155 | 0x00, /* 5F */ |
| 156 | 0x00, /* 60 */ |
| 157 | 0x00, /* 61 */ |
| 158 | 0x00, /* 62 */ |
| 159 | 0x00, /* 63 */ |
| 160 | 0x00, /* 64 */ |
| 161 | 0x00, /* 65 */ |
| 162 | 0x00, /* 66 */ |
| 163 | 0x00, /* 67 */ |
| 164 | 0x00, /* 68 */ |
| 165 | 0x00, /* 69 */ |
| 166 | 0x00, /* 6A */ |
| 167 | 0x00, /* 6B */ |
| 168 | 0x00, /* 6C */ |
| 169 | 0x00, /* 6D */ |
| 170 | 0x00, /* 6E */ |
| 171 | 0x00, /* 6F */ |
| 172 | 0x00, /* 70 */ |
| 173 | 0x00, /* 71 */ |
| 174 | 0x00, /* 72 */ |
| 175 | 0x00, /* 73 */ |
| 176 | 0x00, /* 74 */ |
| 177 | 0x00, /* 75 */ |
| 178 | 0x00, /* 76 */ |
| 179 | 0x00, /* 77 */ |
| 180 | 0x00, /* 78 */ |
| 181 | 0x00, /* 79 */ |
| 182 | 0x00, /* 7A */ |
| 183 | 0x00, /* 7B */ |
| 184 | 0x00, /* 7C */ |
| 185 | 0x00, /* 7D */ |
| 186 | 0x00, /* 7E */ |
| 187 | 0x00, /* 7F */ |
| 188 | 0x00, /* 80 */ |
| 189 | 0x00, /* 81 */ |
| 190 | 0x00, /* 82 */ |
| 191 | 0x00, /* 83 */ |
| 192 | 0x00, /* 84 */ |
| 193 | 0x00, /* 85 */ |
| 194 | 0x00, /* 86 */ |
| 195 | 0x00, /* 87 */ |
| 196 | 0x00, /* 88 */ |
| 197 | 0x00, /* 89 */ |
| 198 | 0x00, /* 8A */ |
| 199 | 0x00, /* 8B */ |
| 200 | 0x00, /* 8C */ |
| 201 | 0x00, /* 8D */ |
| 202 | 0x00, /* 8E */ |
| 203 | 0x00, /* 8F */ |
| 204 | 0x00, /* 90 */ |
| 205 | 0x00, /* 91 */ |
| 206 | 0x30, /* 92 */ |
| 207 | 0xF0, /* 93 */ |
| 208 | 0x00, /* 94 */ |
| 209 | 0x00, /* 95 */ |
| 210 | 0x3F, /* 96 */ |
| 211 | 0x00, /* 97 */ |
| 212 | 0x00, /* 98 */ |
| 213 | 0x00, /* 99 */ |
| 214 | 0x00, /* 9A */ |
| 215 | 0x00, /* 9B */ |
| 216 | 0x00, /* 9C */ |
| 217 | 0x00, /* 9D */ |
| 218 | 0x00, /* 9E */ |
| 219 | 0x00, /* 9F */ |
| 220 | 0x00, /* A0 */ |
| 221 | 0x00, /* A1 */ |
| 222 | 0x00, /* A2 */ |
| 223 | 0x00, /* A3 */ |
| 224 | 0x00, /* A4 */ |
| 225 | 0x00, /* A5 */ |
| 226 | 0x00, /* A6 */ |
| 227 | 0x00, /* A7 */ |
| 228 | 0x00, /* A8 */ |
| 229 | 0x00, /* A9 */ |
| 230 | 0x00, /* AA */ |
| 231 | 0x00, /* AB */ |
| 232 | 0x00, /* AC */ |
| 233 | 0x00, /* AD */ |
| 234 | 0x00, /* AE */ |
| 235 | 0x00, /* AF */ |
| 236 | 0x00, /* B0 */ |
| 237 | 0x00, /* B1 */ |
| 238 | 0x00, /* B2 */ |
| 239 | 0x00, /* B3 */ |
| 240 | 0x00, /* B4 */ |
| 241 | 0x00, /* B5 */ |
| 242 | 0x00, /* B6 */ |
| 243 | 0x00, /* B7 */ |
| 244 | 0x00, /* B8 */ |
| 245 | 0x00, /* B9 */ |
| 246 | 0x00, /* BA */ |
| 247 | 0x00, /* BB */ |
| 248 | 0x00, /* BC */ |
| 249 | 0x00, /* BD */ |
| 250 | 0x00, /* BE */ |
| 251 | 0x00, /* BF */ |
| 252 | 0x00, /* C0 */ |
| 253 | 0x00, /* C1 */ |
| 254 | 0x00, /* C2 */ |
| 255 | 0x00, /* C3 */ |
| 256 | 0x00, /* C4 */ |
| 257 | 0x00, /* C5 */ |
| 258 | 0x00, /* C6 */ |
| 259 | 0x00, /* C7 */ |
| 260 | 0x00, /* C8 */ |
| 261 | 0x00, /* C9 */ |
| 262 | 0x00, /* CA */ |
| 263 | 0x00, /* CB */ |
| 264 | 0x00, /* CC */ |
| 265 | 0x00, /* CD */ |
| 266 | 0x00, /* CE */ |
| 267 | 0x00, /* CF */ |
| 268 | 0x00, /* D0 */ |
| 269 | 0x00, /* D1 */ |
| 270 | 0x00, /* D2 */ |
| 271 | 0x00, /* D3 */ |
| 272 | 0x00, /* D4 */ |
| 273 | 0x00, /* D5 */ |
| 274 | 0x00, /* D6 */ |
| 275 | 0x00, /* D7 */ |
| 276 | 0x00, /* D8 */ |
| 277 | 0x00, /* D9 */ |
| 278 | 0x00, /* DA */ |
| 279 | 0x00, /* DB */ |
| 280 | 0x00, /* DC */ |
| 281 | 0x00, /* DD */ |
| 282 | 0x00, /* DE */ |
| 283 | 0x00, /* DF */ |
| 284 | 0x00, /* E0 */ |
| 285 | 0x00, /* E1 */ |
| 286 | 0x00, /* E2 */ |
| 287 | 0x00, /* E3 */ |
| 288 | 0x00, /* E4 */ |
| 289 | 0x00, /* E5 */ |
| 290 | 0x00, /* E6 */ |
| 291 | 0x00, /* E7 */ |
| 292 | 0x00, /* E8 */ |
| 293 | 0x00, /* E9 */ |
| 294 | 0x00, /* EA */ |
| 295 | 0x00, /* EB */ |
| 296 | 0x00, /* EC */ |
| 297 | 0x00, /* ED */ |
| 298 | 0x00, /* EE */ |
| 299 | 0x00, /* EF */ |
| 300 | 0x00, /* F0 */ |
| 301 | 0x00, /* F1 */ |
| 302 | 0x00, /* F2 */ |
| 303 | 0x00, /* F3 */ |
| 304 | 0x00, /* F4 */ |
| 305 | 0x00, /* F5 */ |
| 306 | 0x00, /* F6 */ |
| 307 | 0x00, /* F7 */ |
| 308 | 0x00, /* F8 */ |
| 309 | 0x00, /* F9 */ |
| 310 | 0x00, /* FA */ |
| 311 | 0x00, /* FB */ |
| 312 | 0x00, /* FC */ |
| 313 | 0x00, /* FD */ |
| 314 | 0x00, /* FE */ |
| 315 | 0x00, /* FF */ |
| 316 | }; |
| 317 | |
| 318 | static struct { |
| 319 | int readable; |
| 320 | int writable; |
| 321 | } max98095_access[M98095_REG_CNT] = { |
| 322 | { 0x00, 0x00 }, /* 00 */ |
| 323 | { 0xFF, 0x00 }, /* 01 */ |
| 324 | { 0xFF, 0x00 }, /* 02 */ |
| 325 | { 0xFF, 0x00 }, /* 03 */ |
| 326 | { 0xFF, 0x00 }, /* 04 */ |
| 327 | { 0xFF, 0x00 }, /* 05 */ |
| 328 | { 0xFF, 0x00 }, /* 06 */ |
| 329 | { 0xFF, 0x00 }, /* 07 */ |
| 330 | { 0xFF, 0x00 }, /* 08 */ |
| 331 | { 0xFF, 0x00 }, /* 09 */ |
| 332 | { 0xFF, 0x00 }, /* 0A */ |
| 333 | { 0xFF, 0x00 }, /* 0B */ |
| 334 | { 0xFF, 0x00 }, /* 0C */ |
| 335 | { 0xFF, 0x00 }, /* 0D */ |
| 336 | { 0xFF, 0x00 }, /* 0E */ |
| 337 | { 0xFF, 0x9F }, /* 0F */ |
| 338 | { 0xFF, 0xFF }, /* 10 */ |
| 339 | { 0xFF, 0xFF }, /* 11 */ |
| 340 | { 0xFF, 0xFF }, /* 12 */ |
| 341 | { 0xFF, 0xFF }, /* 13 */ |
| 342 | { 0xFF, 0xFF }, /* 14 */ |
| 343 | { 0xFF, 0xFF }, /* 15 */ |
| 344 | { 0xFF, 0xFF }, /* 16 */ |
| 345 | { 0xFF, 0xFF }, /* 17 */ |
| 346 | { 0xFF, 0xFF }, /* 18 */ |
| 347 | { 0xFF, 0xFF }, /* 19 */ |
| 348 | { 0xFF, 0xFF }, /* 1A */ |
| 349 | { 0xFF, 0xFF }, /* 1B */ |
| 350 | { 0xFF, 0xFF }, /* 1C */ |
| 351 | { 0xFF, 0xFF }, /* 1D */ |
| 352 | { 0xFF, 0x77 }, /* 1E */ |
| 353 | { 0xFF, 0x77 }, /* 1F */ |
| 354 | { 0xFF, 0x77 }, /* 20 */ |
| 355 | { 0xFF, 0x77 }, /* 21 */ |
| 356 | { 0xFF, 0x77 }, /* 22 */ |
| 357 | { 0xFF, 0x77 }, /* 23 */ |
| 358 | { 0xFF, 0xFF }, /* 24 */ |
| 359 | { 0xFF, 0x7F }, /* 25 */ |
| 360 | { 0xFF, 0x31 }, /* 26 */ |
| 361 | { 0xFF, 0xFF }, /* 27 */ |
| 362 | { 0xFF, 0xFF }, /* 28 */ |
| 363 | { 0xFF, 0xFF }, /* 29 */ |
| 364 | { 0xFF, 0xF7 }, /* 2A */ |
| 365 | { 0xFF, 0x2F }, /* 2B */ |
| 366 | { 0xFF, 0xEF }, /* 2C */ |
| 367 | { 0xFF, 0xFF }, /* 2D */ |
| 368 | { 0xFF, 0xFF }, /* 2E */ |
| 369 | { 0xFF, 0xFF }, /* 2F */ |
| 370 | { 0xFF, 0xFF }, /* 30 */ |
| 371 | { 0xFF, 0xFF }, /* 31 */ |
| 372 | { 0xFF, 0xFF }, /* 32 */ |
| 373 | { 0xFF, 0xFF }, /* 33 */ |
| 374 | { 0xFF, 0xF7 }, /* 34 */ |
| 375 | { 0xFF, 0x2F }, /* 35 */ |
| 376 | { 0xFF, 0xCF }, /* 36 */ |
| 377 | { 0xFF, 0xFF }, /* 37 */ |
| 378 | { 0xFF, 0xFF }, /* 38 */ |
| 379 | { 0xFF, 0xFF }, /* 39 */ |
| 380 | { 0xFF, 0xFF }, /* 3A */ |
| 381 | { 0xFF, 0xFF }, /* 3B */ |
| 382 | { 0xFF, 0xFF }, /* 3C */ |
| 383 | { 0xFF, 0xFF }, /* 3D */ |
| 384 | { 0xFF, 0xF7 }, /* 3E */ |
| 385 | { 0xFF, 0x2F }, /* 3F */ |
| 386 | { 0xFF, 0xCF }, /* 40 */ |
| 387 | { 0xFF, 0xFF }, /* 41 */ |
| 388 | { 0xFF, 0x77 }, /* 42 */ |
| 389 | { 0xFF, 0xFF }, /* 43 */ |
| 390 | { 0xFF, 0xFF }, /* 44 */ |
| 391 | { 0xFF, 0xFF }, /* 45 */ |
| 392 | { 0xFF, 0xFF }, /* 46 */ |
| 393 | { 0xFF, 0xFF }, /* 47 */ |
| 394 | { 0xFF, 0xFF }, /* 48 */ |
| 395 | { 0xFF, 0x0F }, /* 49 */ |
| 396 | { 0xFF, 0xFF }, /* 4A */ |
| 397 | { 0xFF, 0xFF }, /* 4B */ |
| 398 | { 0xFF, 0x3F }, /* 4C */ |
| 399 | { 0xFF, 0x3F }, /* 4D */ |
| 400 | { 0xFF, 0x3F }, /* 4E */ |
| 401 | { 0xFF, 0xFF }, /* 4F */ |
| 402 | { 0xFF, 0x7F }, /* 50 */ |
| 403 | { 0xFF, 0x7F }, /* 51 */ |
| 404 | { 0xFF, 0x0F }, /* 52 */ |
| 405 | { 0xFF, 0x3F }, /* 53 */ |
| 406 | { 0xFF, 0x3F }, /* 54 */ |
| 407 | { 0xFF, 0x3F }, /* 55 */ |
| 408 | { 0xFF, 0xFF }, /* 56 */ |
| 409 | { 0xFF, 0xFF }, /* 57 */ |
| 410 | { 0xFF, 0xBF }, /* 58 */ |
| 411 | { 0xFF, 0x1F }, /* 59 */ |
| 412 | { 0xFF, 0xBF }, /* 5A */ |
| 413 | { 0xFF, 0x1F }, /* 5B */ |
| 414 | { 0xFF, 0xBF }, /* 5C */ |
| 415 | { 0xFF, 0x3F }, /* 5D */ |
| 416 | { 0xFF, 0x3F }, /* 5E */ |
| 417 | { 0xFF, 0x7F }, /* 5F */ |
| 418 | { 0xFF, 0x7F }, /* 60 */ |
| 419 | { 0xFF, 0x47 }, /* 61 */ |
| 420 | { 0xFF, 0x9F }, /* 62 */ |
| 421 | { 0xFF, 0x9F }, /* 63 */ |
| 422 | { 0xFF, 0x9F }, /* 64 */ |
| 423 | { 0xFF, 0x9F }, /* 65 */ |
| 424 | { 0xFF, 0x9F }, /* 66 */ |
| 425 | { 0xFF, 0xBF }, /* 67 */ |
| 426 | { 0xFF, 0xBF }, /* 68 */ |
| 427 | { 0xFF, 0xFF }, /* 69 */ |
| 428 | { 0xFF, 0xFF }, /* 6A */ |
| 429 | { 0xFF, 0x7F }, /* 6B */ |
| 430 | { 0xFF, 0xF7 }, /* 6C */ |
| 431 | { 0xFF, 0xFF }, /* 6D */ |
| 432 | { 0xFF, 0xFF }, /* 6E */ |
| 433 | { 0xFF, 0x1F }, /* 6F */ |
| 434 | { 0xFF, 0xF7 }, /* 70 */ |
| 435 | { 0xFF, 0xFF }, /* 71 */ |
| 436 | { 0xFF, 0xFF }, /* 72 */ |
| 437 | { 0xFF, 0x1F }, /* 73 */ |
| 438 | { 0xFF, 0xF7 }, /* 74 */ |
| 439 | { 0xFF, 0xFF }, /* 75 */ |
| 440 | { 0xFF, 0xFF }, /* 76 */ |
| 441 | { 0xFF, 0x1F }, /* 77 */ |
| 442 | { 0xFF, 0xF7 }, /* 78 */ |
| 443 | { 0xFF, 0xFF }, /* 79 */ |
| 444 | { 0xFF, 0xFF }, /* 7A */ |
| 445 | { 0xFF, 0x1F }, /* 7B */ |
| 446 | { 0xFF, 0xF7 }, /* 7C */ |
| 447 | { 0xFF, 0xFF }, /* 7D */ |
| 448 | { 0xFF, 0xFF }, /* 7E */ |
| 449 | { 0xFF, 0x1F }, /* 7F */ |
| 450 | { 0xFF, 0xF7 }, /* 80 */ |
| 451 | { 0xFF, 0xFF }, /* 81 */ |
| 452 | { 0xFF, 0xFF }, /* 82 */ |
| 453 | { 0xFF, 0x1F }, /* 83 */ |
| 454 | { 0xFF, 0x7F }, /* 84 */ |
| 455 | { 0xFF, 0x0F }, /* 85 */ |
| 456 | { 0xFF, 0xD8 }, /* 86 */ |
| 457 | { 0xFF, 0xFF }, /* 87 */ |
| 458 | { 0xFF, 0xEF }, /* 88 */ |
| 459 | { 0xFF, 0xFE }, /* 89 */ |
| 460 | { 0xFF, 0xFE }, /* 8A */ |
| 461 | { 0xFF, 0xFF }, /* 8B */ |
| 462 | { 0xFF, 0xFF }, /* 8C */ |
| 463 | { 0xFF, 0x3F }, /* 8D */ |
| 464 | { 0xFF, 0xFF }, /* 8E */ |
| 465 | { 0xFF, 0x3F }, /* 8F */ |
| 466 | { 0xFF, 0x8F }, /* 90 */ |
| 467 | { 0xFF, 0xFF }, /* 91 */ |
| 468 | { 0xFF, 0x3F }, /* 92 */ |
| 469 | { 0xFF, 0xFF }, /* 93 */ |
| 470 | { 0xFF, 0xFF }, /* 94 */ |
| 471 | { 0xFF, 0x0F }, /* 95 */ |
| 472 | { 0xFF, 0x3F }, /* 96 */ |
| 473 | { 0xFF, 0x8C }, /* 97 */ |
| 474 | { 0x00, 0x00 }, /* 98 */ |
| 475 | { 0x00, 0x00 }, /* 99 */ |
| 476 | { 0x00, 0x00 }, /* 9A */ |
| 477 | { 0x00, 0x00 }, /* 9B */ |
| 478 | { 0x00, 0x00 }, /* 9C */ |
| 479 | { 0x00, 0x00 }, /* 9D */ |
| 480 | { 0x00, 0x00 }, /* 9E */ |
| 481 | { 0x00, 0x00 }, /* 9F */ |
| 482 | { 0x00, 0x00 }, /* A0 */ |
| 483 | { 0x00, 0x00 }, /* A1 */ |
| 484 | { 0x00, 0x00 }, /* A2 */ |
| 485 | { 0x00, 0x00 }, /* A3 */ |
| 486 | { 0x00, 0x00 }, /* A4 */ |
| 487 | { 0x00, 0x00 }, /* A5 */ |
| 488 | { 0x00, 0x00 }, /* A6 */ |
| 489 | { 0x00, 0x00 }, /* A7 */ |
| 490 | { 0x00, 0x00 }, /* A8 */ |
| 491 | { 0x00, 0x00 }, /* A9 */ |
| 492 | { 0x00, 0x00 }, /* AA */ |
| 493 | { 0x00, 0x00 }, /* AB */ |
| 494 | { 0x00, 0x00 }, /* AC */ |
| 495 | { 0x00, 0x00 }, /* AD */ |
| 496 | { 0x00, 0x00 }, /* AE */ |
| 497 | { 0x00, 0x00 }, /* AF */ |
| 498 | { 0x00, 0x00 }, /* B0 */ |
| 499 | { 0x00, 0x00 }, /* B1 */ |
| 500 | { 0x00, 0x00 }, /* B2 */ |
| 501 | { 0x00, 0x00 }, /* B3 */ |
| 502 | { 0x00, 0x00 }, /* B4 */ |
| 503 | { 0x00, 0x00 }, /* B5 */ |
| 504 | { 0x00, 0x00 }, /* B6 */ |
| 505 | { 0x00, 0x00 }, /* B7 */ |
| 506 | { 0x00, 0x00 }, /* B8 */ |
| 507 | { 0x00, 0x00 }, /* B9 */ |
| 508 | { 0x00, 0x00 }, /* BA */ |
| 509 | { 0x00, 0x00 }, /* BB */ |
| 510 | { 0x00, 0x00 }, /* BC */ |
| 511 | { 0x00, 0x00 }, /* BD */ |
| 512 | { 0x00, 0x00 }, /* BE */ |
| 513 | { 0x00, 0x00 }, /* BF */ |
| 514 | { 0x00, 0x00 }, /* C0 */ |
| 515 | { 0x00, 0x00 }, /* C1 */ |
| 516 | { 0x00, 0x00 }, /* C2 */ |
| 517 | { 0x00, 0x00 }, /* C3 */ |
| 518 | { 0x00, 0x00 }, /* C4 */ |
| 519 | { 0x00, 0x00 }, /* C5 */ |
| 520 | { 0x00, 0x00 }, /* C6 */ |
| 521 | { 0x00, 0x00 }, /* C7 */ |
| 522 | { 0x00, 0x00 }, /* C8 */ |
| 523 | { 0x00, 0x00 }, /* C9 */ |
| 524 | { 0x00, 0x00 }, /* CA */ |
| 525 | { 0x00, 0x00 }, /* CB */ |
| 526 | { 0x00, 0x00 }, /* CC */ |
| 527 | { 0x00, 0x00 }, /* CD */ |
| 528 | { 0x00, 0x00 }, /* CE */ |
| 529 | { 0x00, 0x00 }, /* CF */ |
| 530 | { 0x00, 0x00 }, /* D0 */ |
| 531 | { 0x00, 0x00 }, /* D1 */ |
| 532 | { 0x00, 0x00 }, /* D2 */ |
| 533 | { 0x00, 0x00 }, /* D3 */ |
| 534 | { 0x00, 0x00 }, /* D4 */ |
| 535 | { 0x00, 0x00 }, /* D5 */ |
| 536 | { 0x00, 0x00 }, /* D6 */ |
| 537 | { 0x00, 0x00 }, /* D7 */ |
| 538 | { 0x00, 0x00 }, /* D8 */ |
| 539 | { 0x00, 0x00 }, /* D9 */ |
| 540 | { 0x00, 0x00 }, /* DA */ |
| 541 | { 0x00, 0x00 }, /* DB */ |
| 542 | { 0x00, 0x00 }, /* DC */ |
| 543 | { 0x00, 0x00 }, /* DD */ |
| 544 | { 0x00, 0x00 }, /* DE */ |
| 545 | { 0x00, 0x00 }, /* DF */ |
| 546 | { 0x00, 0x00 }, /* E0 */ |
| 547 | { 0x00, 0x00 }, /* E1 */ |
| 548 | { 0x00, 0x00 }, /* E2 */ |
| 549 | { 0x00, 0x00 }, /* E3 */ |
| 550 | { 0x00, 0x00 }, /* E4 */ |
| 551 | { 0x00, 0x00 }, /* E5 */ |
| 552 | { 0x00, 0x00 }, /* E6 */ |
| 553 | { 0x00, 0x00 }, /* E7 */ |
| 554 | { 0x00, 0x00 }, /* E8 */ |
| 555 | { 0x00, 0x00 }, /* E9 */ |
| 556 | { 0x00, 0x00 }, /* EA */ |
| 557 | { 0x00, 0x00 }, /* EB */ |
| 558 | { 0x00, 0x00 }, /* EC */ |
| 559 | { 0x00, 0x00 }, /* ED */ |
| 560 | { 0x00, 0x00 }, /* EE */ |
| 561 | { 0x00, 0x00 }, /* EF */ |
| 562 | { 0x00, 0x00 }, /* F0 */ |
| 563 | { 0x00, 0x00 }, /* F1 */ |
| 564 | { 0x00, 0x00 }, /* F2 */ |
| 565 | { 0x00, 0x00 }, /* F3 */ |
| 566 | { 0x00, 0x00 }, /* F4 */ |
| 567 | { 0x00, 0x00 }, /* F5 */ |
| 568 | { 0x00, 0x00 }, /* F6 */ |
| 569 | { 0x00, 0x00 }, /* F7 */ |
| 570 | { 0x00, 0x00 }, /* F8 */ |
| 571 | { 0x00, 0x00 }, /* F9 */ |
| 572 | { 0x00, 0x00 }, /* FA */ |
| 573 | { 0x00, 0x00 }, /* FB */ |
| 574 | { 0x00, 0x00 }, /* FC */ |
| 575 | { 0x00, 0x00 }, /* FD */ |
| 576 | { 0x00, 0x00 }, /* FE */ |
| 577 | { 0xFF, 0x00 }, /* FF */ |
| 578 | }; |
| 579 | |
| 580 | static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg) |
| 581 | { |
| 582 | if (reg >= M98095_REG_CNT) |
| 583 | return 0; |
| 584 | return max98095_access[reg].readable != 0; |
| 585 | } |
| 586 | |
| 587 | static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg) |
| 588 | { |
| 589 | if (reg > M98095_REG_MAX_CACHED) |
| 590 | return 1; |
| 591 | |
| 592 | switch (reg) { |
| 593 | case M98095_000_HOST_DATA: |
| 594 | case M98095_001_HOST_INT_STS: |
| 595 | case M98095_002_HOST_RSP_STS: |
| 596 | case M98095_003_HOST_CMD_STS: |
| 597 | case M98095_004_CODEC_STS: |
| 598 | case M98095_005_DAI1_ALC_STS: |
| 599 | case M98095_006_DAI2_ALC_STS: |
| 600 | case M98095_007_JACK_AUTO_STS: |
| 601 | case M98095_008_JACK_MANUAL_STS: |
| 602 | case M98095_009_JACK_VBAT_STS: |
| 603 | case M98095_00A_ACC_ADC_STS: |
| 604 | case M98095_00B_MIC_NG_AGC_STS: |
| 605 | case M98095_00C_SPK_L_VOLT_STS: |
| 606 | case M98095_00D_SPK_R_VOLT_STS: |
| 607 | case M98095_00E_TEMP_SENSOR_STS: |
| 608 | return 1; |
| 609 | } |
| 610 | |
| 611 | return 0; |
| 612 | } |
| 613 | |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 614 | /* |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 615 | * Load equalizer DSP coefficient configurations registers |
| 616 | */ |
| 617 | static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, |
| 618 | unsigned int band, u16 *coefs) |
| 619 | { |
| 620 | unsigned int eq_reg; |
| 621 | unsigned int i; |
| 622 | |
| 623 | BUG_ON(band > 4); |
| 624 | BUG_ON(dai > 1); |
| 625 | |
| 626 | /* Load the base register address */ |
| 627 | eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; |
| 628 | |
| 629 | /* Add the band address offset, note adjustment for word address */ |
| 630 | eq_reg += band * (M98095_COEFS_PER_BAND << 1); |
| 631 | |
| 632 | /* Step through the registers and coefs */ |
| 633 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { |
Mark Brown | d36126a | 2013-09-23 18:58:59 +0100 | [diff] [blame^] | 634 | snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); |
| 635 | snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 636 | } |
| 637 | } |
| 638 | |
| 639 | /* |
| 640 | * Load biquad filter coefficient configurations registers |
| 641 | */ |
| 642 | static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, |
| 643 | unsigned int band, u16 *coefs) |
| 644 | { |
| 645 | unsigned int bq_reg; |
| 646 | unsigned int i; |
| 647 | |
| 648 | BUG_ON(band > 1); |
| 649 | BUG_ON(dai > 1); |
| 650 | |
| 651 | /* Load the base register address */ |
| 652 | bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; |
| 653 | |
| 654 | /* Add the band address offset, note adjustment for word address */ |
| 655 | bq_reg += band * (M98095_COEFS_PER_BAND << 1); |
| 656 | |
| 657 | /* Step through the registers and coefs */ |
| 658 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { |
Mark Brown | d36126a | 2013-09-23 18:58:59 +0100 | [diff] [blame^] | 659 | snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); |
| 660 | snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 661 | } |
| 662 | } |
| 663 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 664 | static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; |
| 665 | static const struct soc_enum max98095_dai1_filter_mode_enum[] = { |
| 666 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode), |
| 667 | }; |
| 668 | static const struct soc_enum max98095_dai2_filter_mode_enum[] = { |
| 669 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode), |
| 670 | }; |
| 671 | |
| 672 | static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; |
| 673 | |
| 674 | static const struct soc_enum max98095_extmic_enum = |
| 675 | SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text); |
| 676 | |
| 677 | static const struct snd_kcontrol_new max98095_extmic_mux = |
| 678 | SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); |
| 679 | |
| 680 | static const char * const max98095_linein_text[] = { "INA", "INB" }; |
| 681 | |
| 682 | static const struct soc_enum max98095_linein_enum = |
| 683 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text); |
| 684 | |
| 685 | static const struct snd_kcontrol_new max98095_linein_mux = |
| 686 | SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); |
| 687 | |
| 688 | static const char * const max98095_line_mode_text[] = { |
| 689 | "Stereo", "Differential"}; |
| 690 | |
| 691 | static const struct soc_enum max98095_linein_mode_enum = |
| 692 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text); |
| 693 | |
| 694 | static const struct soc_enum max98095_lineout_mode_enum = |
| 695 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text); |
| 696 | |
| 697 | static const char * const max98095_dai_fltr[] = { |
| 698 | "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", |
| 699 | "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; |
| 700 | static const struct soc_enum max98095_dai1_dac_filter_enum[] = { |
| 701 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr), |
| 702 | }; |
| 703 | static const struct soc_enum max98095_dai2_dac_filter_enum[] = { |
| 704 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr), |
| 705 | }; |
| 706 | static const struct soc_enum max98095_dai3_dac_filter_enum[] = { |
| 707 | SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr), |
| 708 | }; |
| 709 | |
| 710 | static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, |
| 711 | struct snd_ctl_elem_value *ucontrol) |
| 712 | { |
| 713 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 714 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 715 | unsigned int sel = ucontrol->value.integer.value[0]; |
| 716 | |
| 717 | max98095->mic1pre = sel; |
| 718 | snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, |
| 719 | (1+sel)<<M98095_MICPRE_SHIFT); |
| 720 | |
| 721 | return 0; |
| 722 | } |
| 723 | |
| 724 | static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, |
| 725 | struct snd_ctl_elem_value *ucontrol) |
| 726 | { |
| 727 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 728 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 729 | |
| 730 | ucontrol->value.integer.value[0] = max98095->mic1pre; |
| 731 | return 0; |
| 732 | } |
| 733 | |
| 734 | static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, |
| 735 | struct snd_ctl_elem_value *ucontrol) |
| 736 | { |
| 737 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 738 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 739 | unsigned int sel = ucontrol->value.integer.value[0]; |
| 740 | |
| 741 | max98095->mic2pre = sel; |
| 742 | snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, |
| 743 | (1+sel)<<M98095_MICPRE_SHIFT); |
| 744 | |
| 745 | return 0; |
| 746 | } |
| 747 | |
| 748 | static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, |
| 749 | struct snd_ctl_elem_value *ucontrol) |
| 750 | { |
| 751 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 752 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 753 | |
| 754 | ucontrol->value.integer.value[0] = max98095->mic2pre; |
| 755 | return 0; |
| 756 | } |
| 757 | |
| 758 | static const unsigned int max98095_micboost_tlv[] = { |
| 759 | TLV_DB_RANGE_HEAD(2), |
| 760 | 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), |
| 761 | 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), |
| 762 | }; |
| 763 | |
| 764 | static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); |
| 765 | static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); |
| 766 | static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); |
| 767 | |
| 768 | static const unsigned int max98095_hp_tlv[] = { |
| 769 | TLV_DB_RANGE_HEAD(5), |
| 770 | 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), |
| 771 | 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), |
| 772 | 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), |
| 773 | 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), |
| 774 | 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), |
| 775 | }; |
| 776 | |
| 777 | static const unsigned int max98095_spk_tlv[] = { |
| 778 | TLV_DB_RANGE_HEAD(4), |
| 779 | 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), |
| 780 | 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), |
| 781 | 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), |
| 782 | 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0), |
| 783 | }; |
| 784 | |
| 785 | static const unsigned int max98095_rcv_lout_tlv[] = { |
| 786 | TLV_DB_RANGE_HEAD(5), |
| 787 | 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), |
| 788 | 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), |
| 789 | 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), |
| 790 | 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), |
| 791 | 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), |
| 792 | }; |
| 793 | |
| 794 | static const unsigned int max98095_lin_tlv[] = { |
| 795 | TLV_DB_RANGE_HEAD(3), |
| 796 | 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), |
| 797 | 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), |
| 798 | 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), |
| 799 | }; |
| 800 | |
| 801 | static const struct snd_kcontrol_new max98095_snd_controls[] = { |
| 802 | |
| 803 | SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, |
| 804 | M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), |
| 805 | |
| 806 | SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, |
| 807 | M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), |
| 808 | |
| 809 | SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, |
| 810 | 0, 31, 0, max98095_rcv_lout_tlv), |
| 811 | |
| 812 | SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, |
| 813 | M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), |
| 814 | |
| 815 | SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, |
| 816 | M98095_065_LVL_HP_R, 7, 1, 1), |
| 817 | |
| 818 | SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, |
| 819 | M98095_068_LVL_SPK_R, 7, 1, 1), |
| 820 | |
| 821 | SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), |
| 822 | |
| 823 | SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, |
| 824 | M98095_063_LVL_LINEOUT2, 7, 1, 1), |
| 825 | |
| 826 | SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, |
| 827 | max98095_mic_tlv), |
| 828 | |
| 829 | SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, |
| 830 | max98095_mic_tlv), |
| 831 | |
| 832 | SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", |
| 833 | M98095_05F_LVL_MIC1, 5, 2, 0, |
| 834 | max98095_mic1pre_get, max98095_mic1pre_set, |
| 835 | max98095_micboost_tlv), |
| 836 | SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", |
| 837 | M98095_060_LVL_MIC2, 5, 2, 0, |
| 838 | max98095_mic2pre_get, max98095_mic2pre_set, |
| 839 | max98095_micboost_tlv), |
| 840 | |
| 841 | SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, |
| 842 | max98095_lin_tlv), |
| 843 | |
| 844 | SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, |
| 845 | max98095_adc_tlv), |
| 846 | SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, |
| 847 | max98095_adc_tlv), |
| 848 | |
| 849 | SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, |
| 850 | max98095_adcboost_tlv), |
| 851 | SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, |
| 852 | max98095_adcboost_tlv), |
| 853 | |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 854 | SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), |
| 855 | SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), |
| 856 | |
| 857 | SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), |
| 858 | SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), |
| 859 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 860 | SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), |
| 861 | SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), |
| 862 | SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), |
| 863 | SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), |
| 864 | SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), |
| 865 | |
| 866 | SOC_ENUM("Linein Mode", max98095_linein_mode_enum), |
| 867 | SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), |
| 868 | }; |
| 869 | |
| 870 | /* Left speaker mixer switch */ |
| 871 | static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { |
| 872 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), |
| 873 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), |
| 874 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), |
| 875 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), |
| 876 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), |
| 877 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), |
| 878 | SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), |
| 879 | SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), |
| 880 | }; |
| 881 | |
| 882 | /* Right speaker mixer switch */ |
| 883 | static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { |
| 884 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), |
| 885 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), |
| 886 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), |
| 887 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), |
| 888 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), |
| 889 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), |
| 890 | SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), |
| 891 | SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), |
| 892 | }; |
| 893 | |
| 894 | /* Left headphone mixer switch */ |
| 895 | static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { |
| 896 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), |
| 897 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), |
| 898 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), |
| 899 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), |
| 900 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), |
| 901 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), |
| 902 | }; |
| 903 | |
| 904 | /* Right headphone mixer switch */ |
| 905 | static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { |
| 906 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), |
| 907 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), |
| 908 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), |
| 909 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), |
| 910 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), |
| 911 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), |
| 912 | }; |
| 913 | |
| 914 | /* Receiver earpiece mixer switch */ |
| 915 | static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { |
| 916 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), |
| 917 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), |
| 918 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), |
| 919 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), |
| 920 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), |
| 921 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), |
| 922 | }; |
| 923 | |
| 924 | /* Left lineout mixer switch */ |
| 925 | static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { |
| 926 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), |
| 927 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), |
| 928 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), |
| 929 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), |
| 930 | SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), |
| 931 | SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), |
| 932 | }; |
| 933 | |
| 934 | /* Right lineout mixer switch */ |
| 935 | static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { |
| 936 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), |
| 937 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), |
| 938 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), |
| 939 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), |
| 940 | SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), |
| 941 | SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), |
| 942 | }; |
| 943 | |
| 944 | /* Left ADC mixer switch */ |
| 945 | static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { |
| 946 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), |
| 947 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), |
| 948 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), |
| 949 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), |
| 950 | }; |
| 951 | |
| 952 | /* Right ADC mixer switch */ |
| 953 | static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { |
| 954 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), |
| 955 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), |
| 956 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), |
| 957 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), |
| 958 | }; |
| 959 | |
| 960 | static int max98095_mic_event(struct snd_soc_dapm_widget *w, |
| 961 | struct snd_kcontrol *kcontrol, int event) |
| 962 | { |
| 963 | struct snd_soc_codec *codec = w->codec; |
| 964 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 965 | |
| 966 | switch (event) { |
| 967 | case SND_SOC_DAPM_POST_PMU: |
| 968 | if (w->reg == M98095_05F_LVL_MIC1) { |
| 969 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, |
| 970 | (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); |
| 971 | } else { |
| 972 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, |
| 973 | (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); |
| 974 | } |
| 975 | break; |
| 976 | case SND_SOC_DAPM_POST_PMD: |
| 977 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); |
| 978 | break; |
| 979 | default: |
| 980 | return -EINVAL; |
| 981 | } |
| 982 | |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | /* |
| 987 | * The line inputs are stereo inputs with the left and right |
| 988 | * channels sharing a common PGA power control signal. |
| 989 | */ |
| 990 | static int max98095_line_pga(struct snd_soc_dapm_widget *w, |
| 991 | int event, u8 channel) |
| 992 | { |
| 993 | struct snd_soc_codec *codec = w->codec; |
| 994 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 995 | u8 *state; |
| 996 | |
| 997 | BUG_ON(!((channel == 1) || (channel == 2))); |
| 998 | |
| 999 | state = &max98095->lin_state; |
| 1000 | |
| 1001 | switch (event) { |
| 1002 | case SND_SOC_DAPM_POST_PMU: |
| 1003 | *state |= channel; |
| 1004 | snd_soc_update_bits(codec, w->reg, |
| 1005 | (1 << w->shift), (1 << w->shift)); |
| 1006 | break; |
| 1007 | case SND_SOC_DAPM_POST_PMD: |
| 1008 | *state &= ~channel; |
| 1009 | if (*state == 0) { |
| 1010 | snd_soc_update_bits(codec, w->reg, |
| 1011 | (1 << w->shift), 0); |
| 1012 | } |
| 1013 | break; |
| 1014 | default: |
| 1015 | return -EINVAL; |
| 1016 | } |
| 1017 | |
| 1018 | return 0; |
| 1019 | } |
| 1020 | |
| 1021 | static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, |
| 1022 | struct snd_kcontrol *k, int event) |
| 1023 | { |
| 1024 | return max98095_line_pga(w, event, 1); |
| 1025 | } |
| 1026 | |
| 1027 | static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, |
| 1028 | struct snd_kcontrol *k, int event) |
| 1029 | { |
| 1030 | return max98095_line_pga(w, event, 2); |
| 1031 | } |
| 1032 | |
| 1033 | /* |
| 1034 | * The stereo line out mixer outputs to two stereo line outs. |
| 1035 | * The 2nd pair has a separate set of enables. |
| 1036 | */ |
| 1037 | static int max98095_lineout_event(struct snd_soc_dapm_widget *w, |
| 1038 | struct snd_kcontrol *kcontrol, int event) |
| 1039 | { |
| 1040 | struct snd_soc_codec *codec = w->codec; |
| 1041 | |
| 1042 | switch (event) { |
| 1043 | case SND_SOC_DAPM_POST_PMU: |
| 1044 | snd_soc_update_bits(codec, w->reg, |
| 1045 | (1 << (w->shift+2)), (1 << (w->shift+2))); |
| 1046 | break; |
| 1047 | case SND_SOC_DAPM_POST_PMD: |
| 1048 | snd_soc_update_bits(codec, w->reg, |
| 1049 | (1 << (w->shift+2)), 0); |
| 1050 | break; |
| 1051 | default: |
| 1052 | return -EINVAL; |
| 1053 | } |
| 1054 | |
| 1055 | return 0; |
| 1056 | } |
| 1057 | |
| 1058 | static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { |
| 1059 | |
| 1060 | SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), |
| 1061 | SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), |
| 1062 | |
| 1063 | SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", |
| 1064 | M98095_091_PWR_EN_OUT, 0, 0), |
| 1065 | SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", |
| 1066 | M98095_091_PWR_EN_OUT, 1, 0), |
| 1067 | SND_SOC_DAPM_DAC("DACM2", "Aux Playback", |
| 1068 | M98095_091_PWR_EN_OUT, 2, 0), |
| 1069 | SND_SOC_DAPM_DAC("DACM3", "Voice Playback", |
| 1070 | M98095_091_PWR_EN_OUT, 2, 0), |
| 1071 | |
| 1072 | SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, |
| 1073 | 6, 0, NULL, 0), |
| 1074 | SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, |
| 1075 | 7, 0, NULL, 0), |
| 1076 | |
| 1077 | SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, |
| 1078 | 4, 0, NULL, 0), |
| 1079 | SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, |
| 1080 | 5, 0, NULL, 0), |
| 1081 | |
| 1082 | SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, |
| 1083 | 3, 0, NULL, 0), |
| 1084 | |
| 1085 | SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, |
| 1086 | 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), |
| 1087 | SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, |
| 1088 | 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), |
| 1089 | |
| 1090 | SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, |
| 1091 | &max98095_extmic_mux), |
| 1092 | |
| 1093 | SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, |
| 1094 | &max98095_linein_mux), |
| 1095 | |
| 1096 | SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, |
| 1097 | &max98095_left_hp_mixer_controls[0], |
| 1098 | ARRAY_SIZE(max98095_left_hp_mixer_controls)), |
| 1099 | |
| 1100 | SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, |
| 1101 | &max98095_right_hp_mixer_controls[0], |
| 1102 | ARRAY_SIZE(max98095_right_hp_mixer_controls)), |
| 1103 | |
| 1104 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, |
| 1105 | &max98095_left_speaker_mixer_controls[0], |
| 1106 | ARRAY_SIZE(max98095_left_speaker_mixer_controls)), |
| 1107 | |
| 1108 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, |
| 1109 | &max98095_right_speaker_mixer_controls[0], |
| 1110 | ARRAY_SIZE(max98095_right_speaker_mixer_controls)), |
| 1111 | |
| 1112 | SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, |
| 1113 | &max98095_mono_rcv_mixer_controls[0], |
| 1114 | ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), |
| 1115 | |
| 1116 | SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, |
| 1117 | &max98095_left_lineout_mixer_controls[0], |
| 1118 | ARRAY_SIZE(max98095_left_lineout_mixer_controls)), |
| 1119 | |
| 1120 | SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, |
| 1121 | &max98095_right_lineout_mixer_controls[0], |
| 1122 | ARRAY_SIZE(max98095_right_lineout_mixer_controls)), |
| 1123 | |
| 1124 | SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, |
| 1125 | &max98095_left_ADC_mixer_controls[0], |
| 1126 | ARRAY_SIZE(max98095_left_ADC_mixer_controls)), |
| 1127 | |
| 1128 | SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, |
| 1129 | &max98095_right_ADC_mixer_controls[0], |
| 1130 | ARRAY_SIZE(max98095_right_ADC_mixer_controls)), |
| 1131 | |
| 1132 | SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, |
| 1133 | 5, 0, NULL, 0, max98095_mic_event, |
| 1134 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 1135 | |
| 1136 | SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, |
| 1137 | 5, 0, NULL, 0, max98095_mic_event, |
| 1138 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 1139 | |
| 1140 | SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, |
| 1141 | 7, 0, NULL, 0, max98095_pga_in1_event, |
| 1142 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 1143 | |
| 1144 | SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, |
| 1145 | 7, 0, NULL, 0, max98095_pga_in2_event, |
| 1146 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 1147 | |
| 1148 | SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), |
| 1149 | SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), |
| 1150 | |
| 1151 | SND_SOC_DAPM_OUTPUT("HPL"), |
| 1152 | SND_SOC_DAPM_OUTPUT("HPR"), |
| 1153 | SND_SOC_DAPM_OUTPUT("SPKL"), |
| 1154 | SND_SOC_DAPM_OUTPUT("SPKR"), |
| 1155 | SND_SOC_DAPM_OUTPUT("RCV"), |
| 1156 | SND_SOC_DAPM_OUTPUT("OUT1"), |
| 1157 | SND_SOC_DAPM_OUTPUT("OUT2"), |
| 1158 | SND_SOC_DAPM_OUTPUT("OUT3"), |
| 1159 | SND_SOC_DAPM_OUTPUT("OUT4"), |
| 1160 | |
| 1161 | SND_SOC_DAPM_INPUT("MIC1"), |
| 1162 | SND_SOC_DAPM_INPUT("MIC2"), |
| 1163 | SND_SOC_DAPM_INPUT("INA1"), |
| 1164 | SND_SOC_DAPM_INPUT("INA2"), |
| 1165 | SND_SOC_DAPM_INPUT("INB1"), |
| 1166 | SND_SOC_DAPM_INPUT("INB2"), |
| 1167 | }; |
| 1168 | |
| 1169 | static const struct snd_soc_dapm_route max98095_audio_map[] = { |
| 1170 | /* Left headphone output mixer */ |
| 1171 | {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, |
| 1172 | {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, |
| 1173 | {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1174 | {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1175 | {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, |
| 1176 | {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, |
| 1177 | |
| 1178 | /* Right headphone output mixer */ |
| 1179 | {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, |
| 1180 | {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, |
| 1181 | {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1182 | {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1183 | {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, |
| 1184 | {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, |
| 1185 | |
| 1186 | /* Left speaker output mixer */ |
| 1187 | {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, |
| 1188 | {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, |
| 1189 | {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, |
| 1190 | {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, |
| 1191 | {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1192 | {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1193 | {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, |
| 1194 | {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, |
| 1195 | |
| 1196 | /* Right speaker output mixer */ |
| 1197 | {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, |
| 1198 | {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, |
| 1199 | {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, |
| 1200 | {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, |
| 1201 | {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1202 | {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1203 | {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, |
| 1204 | {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, |
| 1205 | |
| 1206 | /* Earpiece/Receiver output mixer */ |
| 1207 | {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, |
| 1208 | {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, |
| 1209 | {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1210 | {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1211 | {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, |
| 1212 | {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, |
| 1213 | |
| 1214 | /* Left Lineout output mixer */ |
| 1215 | {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, |
| 1216 | {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, |
| 1217 | {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1218 | {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1219 | {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, |
| 1220 | {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, |
| 1221 | |
| 1222 | /* Right lineout output mixer */ |
| 1223 | {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, |
| 1224 | {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, |
| 1225 | {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1226 | {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1227 | {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, |
| 1228 | {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, |
| 1229 | |
| 1230 | {"HP Left Out", NULL, "Left Headphone Mixer"}, |
| 1231 | {"HP Right Out", NULL, "Right Headphone Mixer"}, |
| 1232 | {"SPK Left Out", NULL, "Left Speaker Mixer"}, |
| 1233 | {"SPK Right Out", NULL, "Right Speaker Mixer"}, |
| 1234 | {"RCV Mono Out", NULL, "Receiver Mixer"}, |
| 1235 | {"LINE Left Out", NULL, "Left Lineout Mixer"}, |
| 1236 | {"LINE Right Out", NULL, "Right Lineout Mixer"}, |
| 1237 | |
| 1238 | {"HPL", NULL, "HP Left Out"}, |
| 1239 | {"HPR", NULL, "HP Right Out"}, |
| 1240 | {"SPKL", NULL, "SPK Left Out"}, |
| 1241 | {"SPKR", NULL, "SPK Right Out"}, |
| 1242 | {"RCV", NULL, "RCV Mono Out"}, |
| 1243 | {"OUT1", NULL, "LINE Left Out"}, |
| 1244 | {"OUT2", NULL, "LINE Right Out"}, |
| 1245 | {"OUT3", NULL, "LINE Left Out"}, |
| 1246 | {"OUT4", NULL, "LINE Right Out"}, |
| 1247 | |
| 1248 | /* Left ADC input mixer */ |
| 1249 | {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1250 | {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1251 | {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, |
| 1252 | {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, |
| 1253 | |
| 1254 | /* Right ADC input mixer */ |
| 1255 | {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, |
| 1256 | {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, |
| 1257 | {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, |
| 1258 | {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, |
| 1259 | |
| 1260 | /* Inputs */ |
| 1261 | {"ADCL", NULL, "Left ADC Mixer"}, |
| 1262 | {"ADCR", NULL, "Right ADC Mixer"}, |
| 1263 | |
| 1264 | {"IN1 Input", NULL, "INA1"}, |
| 1265 | {"IN2 Input", NULL, "INA2"}, |
| 1266 | |
| 1267 | {"MIC1 Input", NULL, "MIC1"}, |
| 1268 | {"MIC2 Input", NULL, "MIC2"}, |
| 1269 | }; |
| 1270 | |
| 1271 | static int max98095_add_widgets(struct snd_soc_codec *codec) |
| 1272 | { |
Liam Girdwood | 022658b | 2012-02-03 17:43:09 +0000 | [diff] [blame] | 1273 | snd_soc_add_codec_controls(codec, max98095_snd_controls, |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 1274 | ARRAY_SIZE(max98095_snd_controls)); |
| 1275 | |
| 1276 | return 0; |
| 1277 | } |
| 1278 | |
| 1279 | /* codec mclk clock divider coefficients */ |
| 1280 | static const struct { |
| 1281 | u32 rate; |
| 1282 | u8 sr; |
| 1283 | } rate_table[] = { |
| 1284 | {8000, 0x01}, |
| 1285 | {11025, 0x02}, |
| 1286 | {16000, 0x03}, |
| 1287 | {22050, 0x04}, |
| 1288 | {24000, 0x05}, |
| 1289 | {32000, 0x06}, |
| 1290 | {44100, 0x07}, |
| 1291 | {48000, 0x08}, |
| 1292 | {88200, 0x09}, |
| 1293 | {96000, 0x0A}, |
| 1294 | }; |
| 1295 | |
| 1296 | static int rate_value(int rate, u8 *value) |
| 1297 | { |
| 1298 | int i; |
| 1299 | |
| 1300 | for (i = 0; i < ARRAY_SIZE(rate_table); i++) { |
| 1301 | if (rate_table[i].rate >= rate) { |
| 1302 | *value = rate_table[i].sr; |
| 1303 | return 0; |
| 1304 | } |
| 1305 | } |
| 1306 | *value = rate_table[0].sr; |
| 1307 | return -EINVAL; |
| 1308 | } |
| 1309 | |
| 1310 | static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, |
| 1311 | struct snd_pcm_hw_params *params, |
| 1312 | struct snd_soc_dai *dai) |
| 1313 | { |
| 1314 | struct snd_soc_codec *codec = dai->codec; |
| 1315 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1316 | struct max98095_cdata *cdata; |
| 1317 | unsigned long long ni; |
| 1318 | unsigned int rate; |
| 1319 | u8 regval; |
| 1320 | |
| 1321 | cdata = &max98095->dai[0]; |
| 1322 | |
| 1323 | rate = params_rate(params); |
| 1324 | |
| 1325 | switch (params_format(params)) { |
| 1326 | case SNDRV_PCM_FORMAT_S16_LE: |
| 1327 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, |
| 1328 | M98095_DAI_WS, 0); |
| 1329 | break; |
| 1330 | case SNDRV_PCM_FORMAT_S24_LE: |
| 1331 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, |
| 1332 | M98095_DAI_WS, M98095_DAI_WS); |
| 1333 | break; |
| 1334 | default: |
| 1335 | return -EINVAL; |
| 1336 | } |
| 1337 | |
| 1338 | if (rate_value(rate, ®val)) |
| 1339 | return -EINVAL; |
| 1340 | |
| 1341 | snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, |
| 1342 | M98095_CLKMODE_MASK, regval); |
| 1343 | cdata->rate = rate; |
| 1344 | |
| 1345 | /* Configure NI when operating as master */ |
| 1346 | if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { |
| 1347 | if (max98095->sysclk == 0) { |
| 1348 | dev_err(codec->dev, "Invalid system clock frequency\n"); |
| 1349 | return -EINVAL; |
| 1350 | } |
| 1351 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) |
| 1352 | * (unsigned long long int)rate; |
| 1353 | do_div(ni, (unsigned long long int)max98095->sysclk); |
| 1354 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, |
| 1355 | (ni >> 8) & 0x7F); |
| 1356 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, |
| 1357 | ni & 0xFF); |
| 1358 | } |
| 1359 | |
| 1360 | /* Update sample rate mode */ |
| 1361 | if (rate < 50000) |
| 1362 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, |
| 1363 | M98095_DAI_DHF, 0); |
| 1364 | else |
| 1365 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, |
| 1366 | M98095_DAI_DHF, M98095_DAI_DHF); |
| 1367 | |
| 1368 | return 0; |
| 1369 | } |
| 1370 | |
| 1371 | static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, |
| 1372 | struct snd_pcm_hw_params *params, |
| 1373 | struct snd_soc_dai *dai) |
| 1374 | { |
| 1375 | struct snd_soc_codec *codec = dai->codec; |
| 1376 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1377 | struct max98095_cdata *cdata; |
| 1378 | unsigned long long ni; |
| 1379 | unsigned int rate; |
| 1380 | u8 regval; |
| 1381 | |
| 1382 | cdata = &max98095->dai[1]; |
| 1383 | |
| 1384 | rate = params_rate(params); |
| 1385 | |
| 1386 | switch (params_format(params)) { |
| 1387 | case SNDRV_PCM_FORMAT_S16_LE: |
| 1388 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, |
| 1389 | M98095_DAI_WS, 0); |
| 1390 | break; |
| 1391 | case SNDRV_PCM_FORMAT_S24_LE: |
| 1392 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, |
| 1393 | M98095_DAI_WS, M98095_DAI_WS); |
| 1394 | break; |
| 1395 | default: |
| 1396 | return -EINVAL; |
| 1397 | } |
| 1398 | |
| 1399 | if (rate_value(rate, ®val)) |
| 1400 | return -EINVAL; |
| 1401 | |
| 1402 | snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, |
| 1403 | M98095_CLKMODE_MASK, regval); |
| 1404 | cdata->rate = rate; |
| 1405 | |
| 1406 | /* Configure NI when operating as master */ |
| 1407 | if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { |
| 1408 | if (max98095->sysclk == 0) { |
| 1409 | dev_err(codec->dev, "Invalid system clock frequency\n"); |
| 1410 | return -EINVAL; |
| 1411 | } |
| 1412 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) |
| 1413 | * (unsigned long long int)rate; |
| 1414 | do_div(ni, (unsigned long long int)max98095->sysclk); |
| 1415 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, |
| 1416 | (ni >> 8) & 0x7F); |
| 1417 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, |
| 1418 | ni & 0xFF); |
| 1419 | } |
| 1420 | |
| 1421 | /* Update sample rate mode */ |
| 1422 | if (rate < 50000) |
| 1423 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, |
| 1424 | M98095_DAI_DHF, 0); |
| 1425 | else |
| 1426 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, |
| 1427 | M98095_DAI_DHF, M98095_DAI_DHF); |
| 1428 | |
| 1429 | return 0; |
| 1430 | } |
| 1431 | |
| 1432 | static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, |
| 1433 | struct snd_pcm_hw_params *params, |
| 1434 | struct snd_soc_dai *dai) |
| 1435 | { |
| 1436 | struct snd_soc_codec *codec = dai->codec; |
| 1437 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1438 | struct max98095_cdata *cdata; |
| 1439 | unsigned long long ni; |
| 1440 | unsigned int rate; |
| 1441 | u8 regval; |
| 1442 | |
| 1443 | cdata = &max98095->dai[2]; |
| 1444 | |
| 1445 | rate = params_rate(params); |
| 1446 | |
| 1447 | switch (params_format(params)) { |
| 1448 | case SNDRV_PCM_FORMAT_S16_LE: |
| 1449 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, |
| 1450 | M98095_DAI_WS, 0); |
| 1451 | break; |
| 1452 | case SNDRV_PCM_FORMAT_S24_LE: |
| 1453 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, |
| 1454 | M98095_DAI_WS, M98095_DAI_WS); |
| 1455 | break; |
| 1456 | default: |
| 1457 | return -EINVAL; |
| 1458 | } |
| 1459 | |
| 1460 | if (rate_value(rate, ®val)) |
| 1461 | return -EINVAL; |
| 1462 | |
| 1463 | snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, |
| 1464 | M98095_CLKMODE_MASK, regval); |
| 1465 | cdata->rate = rate; |
| 1466 | |
| 1467 | /* Configure NI when operating as master */ |
| 1468 | if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { |
| 1469 | if (max98095->sysclk == 0) { |
| 1470 | dev_err(codec->dev, "Invalid system clock frequency\n"); |
| 1471 | return -EINVAL; |
| 1472 | } |
| 1473 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) |
| 1474 | * (unsigned long long int)rate; |
| 1475 | do_div(ni, (unsigned long long int)max98095->sysclk); |
| 1476 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, |
| 1477 | (ni >> 8) & 0x7F); |
| 1478 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, |
| 1479 | ni & 0xFF); |
| 1480 | } |
| 1481 | |
| 1482 | /* Update sample rate mode */ |
| 1483 | if (rate < 50000) |
| 1484 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, |
| 1485 | M98095_DAI_DHF, 0); |
| 1486 | else |
| 1487 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, |
| 1488 | M98095_DAI_DHF, M98095_DAI_DHF); |
| 1489 | |
| 1490 | return 0; |
| 1491 | } |
| 1492 | |
| 1493 | static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, |
| 1494 | int clk_id, unsigned int freq, int dir) |
| 1495 | { |
| 1496 | struct snd_soc_codec *codec = dai->codec; |
| 1497 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1498 | |
| 1499 | /* Requested clock frequency is already setup */ |
| 1500 | if (freq == max98095->sysclk) |
| 1501 | return 0; |
| 1502 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 1503 | /* Setup clocks for slave mode, and using the PLL |
| 1504 | * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) |
| 1505 | * 0x02 (when master clk is 20MHz to 40MHz).. |
| 1506 | * 0x03 (when master clk is 40MHz to 60MHz).. |
| 1507 | */ |
| 1508 | if ((freq >= 10000000) && (freq < 20000000)) { |
| 1509 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); |
| 1510 | } else if ((freq >= 20000000) && (freq < 40000000)) { |
| 1511 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); |
| 1512 | } else if ((freq >= 40000000) && (freq < 60000000)) { |
| 1513 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); |
| 1514 | } else { |
| 1515 | dev_err(codec->dev, "Invalid master clock frequency\n"); |
| 1516 | return -EINVAL; |
| 1517 | } |
| 1518 | |
| 1519 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); |
| 1520 | |
| 1521 | max98095->sysclk = freq; |
| 1522 | return 0; |
| 1523 | } |
| 1524 | |
| 1525 | static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, |
| 1526 | unsigned int fmt) |
| 1527 | { |
| 1528 | struct snd_soc_codec *codec = codec_dai->codec; |
| 1529 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1530 | struct max98095_cdata *cdata; |
| 1531 | u8 regval = 0; |
| 1532 | |
| 1533 | cdata = &max98095->dai[0]; |
| 1534 | |
| 1535 | if (fmt != cdata->fmt) { |
| 1536 | cdata->fmt = fmt; |
| 1537 | |
| 1538 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1539 | case SND_SOC_DAIFMT_CBS_CFS: |
| 1540 | /* Slave mode PLL */ |
| 1541 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, |
| 1542 | 0x80); |
| 1543 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, |
| 1544 | 0x00); |
| 1545 | break; |
| 1546 | case SND_SOC_DAIFMT_CBM_CFM: |
| 1547 | /* Set to master mode */ |
| 1548 | regval |= M98095_DAI_MAS; |
| 1549 | break; |
| 1550 | case SND_SOC_DAIFMT_CBS_CFM: |
| 1551 | case SND_SOC_DAIFMT_CBM_CFS: |
| 1552 | default: |
| 1553 | dev_err(codec->dev, "Clock mode unsupported"); |
| 1554 | return -EINVAL; |
| 1555 | } |
| 1556 | |
| 1557 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1558 | case SND_SOC_DAIFMT_I2S: |
| 1559 | regval |= M98095_DAI_DLY; |
| 1560 | break; |
| 1561 | case SND_SOC_DAIFMT_LEFT_J: |
| 1562 | break; |
| 1563 | default: |
| 1564 | return -EINVAL; |
| 1565 | } |
| 1566 | |
| 1567 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1568 | case SND_SOC_DAIFMT_NB_NF: |
| 1569 | break; |
| 1570 | case SND_SOC_DAIFMT_NB_IF: |
| 1571 | regval |= M98095_DAI_WCI; |
| 1572 | break; |
| 1573 | case SND_SOC_DAIFMT_IB_NF: |
| 1574 | regval |= M98095_DAI_BCI; |
| 1575 | break; |
| 1576 | case SND_SOC_DAIFMT_IB_IF: |
| 1577 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; |
| 1578 | break; |
| 1579 | default: |
| 1580 | return -EINVAL; |
| 1581 | } |
| 1582 | |
| 1583 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, |
| 1584 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | |
| 1585 | M98095_DAI_WCI, regval); |
| 1586 | |
| 1587 | snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); |
| 1588 | } |
| 1589 | |
| 1590 | return 0; |
| 1591 | } |
| 1592 | |
| 1593 | static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, |
| 1594 | unsigned int fmt) |
| 1595 | { |
| 1596 | struct snd_soc_codec *codec = codec_dai->codec; |
| 1597 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1598 | struct max98095_cdata *cdata; |
| 1599 | u8 regval = 0; |
| 1600 | |
| 1601 | cdata = &max98095->dai[1]; |
| 1602 | |
| 1603 | if (fmt != cdata->fmt) { |
| 1604 | cdata->fmt = fmt; |
| 1605 | |
| 1606 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1607 | case SND_SOC_DAIFMT_CBS_CFS: |
| 1608 | /* Slave mode PLL */ |
| 1609 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, |
| 1610 | 0x80); |
| 1611 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, |
| 1612 | 0x00); |
| 1613 | break; |
| 1614 | case SND_SOC_DAIFMT_CBM_CFM: |
| 1615 | /* Set to master mode */ |
| 1616 | regval |= M98095_DAI_MAS; |
| 1617 | break; |
| 1618 | case SND_SOC_DAIFMT_CBS_CFM: |
| 1619 | case SND_SOC_DAIFMT_CBM_CFS: |
| 1620 | default: |
| 1621 | dev_err(codec->dev, "Clock mode unsupported"); |
| 1622 | return -EINVAL; |
| 1623 | } |
| 1624 | |
| 1625 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1626 | case SND_SOC_DAIFMT_I2S: |
| 1627 | regval |= M98095_DAI_DLY; |
| 1628 | break; |
| 1629 | case SND_SOC_DAIFMT_LEFT_J: |
| 1630 | break; |
| 1631 | default: |
| 1632 | return -EINVAL; |
| 1633 | } |
| 1634 | |
| 1635 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1636 | case SND_SOC_DAIFMT_NB_NF: |
| 1637 | break; |
| 1638 | case SND_SOC_DAIFMT_NB_IF: |
| 1639 | regval |= M98095_DAI_WCI; |
| 1640 | break; |
| 1641 | case SND_SOC_DAIFMT_IB_NF: |
| 1642 | regval |= M98095_DAI_BCI; |
| 1643 | break; |
| 1644 | case SND_SOC_DAIFMT_IB_IF: |
| 1645 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; |
| 1646 | break; |
| 1647 | default: |
| 1648 | return -EINVAL; |
| 1649 | } |
| 1650 | |
| 1651 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, |
| 1652 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | |
| 1653 | M98095_DAI_WCI, regval); |
| 1654 | |
| 1655 | snd_soc_write(codec, M98095_035_DAI2_CLOCK, |
| 1656 | M98095_DAI_BSEL64); |
| 1657 | } |
| 1658 | |
| 1659 | return 0; |
| 1660 | } |
| 1661 | |
| 1662 | static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, |
| 1663 | unsigned int fmt) |
| 1664 | { |
| 1665 | struct snd_soc_codec *codec = codec_dai->codec; |
| 1666 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1667 | struct max98095_cdata *cdata; |
| 1668 | u8 regval = 0; |
| 1669 | |
| 1670 | cdata = &max98095->dai[2]; |
| 1671 | |
| 1672 | if (fmt != cdata->fmt) { |
| 1673 | cdata->fmt = fmt; |
| 1674 | |
| 1675 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1676 | case SND_SOC_DAIFMT_CBS_CFS: |
| 1677 | /* Slave mode PLL */ |
| 1678 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, |
| 1679 | 0x80); |
| 1680 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, |
| 1681 | 0x00); |
| 1682 | break; |
| 1683 | case SND_SOC_DAIFMT_CBM_CFM: |
| 1684 | /* Set to master mode */ |
| 1685 | regval |= M98095_DAI_MAS; |
| 1686 | break; |
| 1687 | case SND_SOC_DAIFMT_CBS_CFM: |
| 1688 | case SND_SOC_DAIFMT_CBM_CFS: |
| 1689 | default: |
| 1690 | dev_err(codec->dev, "Clock mode unsupported"); |
| 1691 | return -EINVAL; |
| 1692 | } |
| 1693 | |
| 1694 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1695 | case SND_SOC_DAIFMT_I2S: |
| 1696 | regval |= M98095_DAI_DLY; |
| 1697 | break; |
| 1698 | case SND_SOC_DAIFMT_LEFT_J: |
| 1699 | break; |
| 1700 | default: |
| 1701 | return -EINVAL; |
| 1702 | } |
| 1703 | |
| 1704 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1705 | case SND_SOC_DAIFMT_NB_NF: |
| 1706 | break; |
| 1707 | case SND_SOC_DAIFMT_NB_IF: |
| 1708 | regval |= M98095_DAI_WCI; |
| 1709 | break; |
| 1710 | case SND_SOC_DAIFMT_IB_NF: |
| 1711 | regval |= M98095_DAI_BCI; |
| 1712 | break; |
| 1713 | case SND_SOC_DAIFMT_IB_IF: |
| 1714 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; |
| 1715 | break; |
| 1716 | default: |
| 1717 | return -EINVAL; |
| 1718 | } |
| 1719 | |
| 1720 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, |
| 1721 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | |
| 1722 | M98095_DAI_WCI, regval); |
| 1723 | |
| 1724 | snd_soc_write(codec, M98095_03F_DAI3_CLOCK, |
| 1725 | M98095_DAI_BSEL64); |
| 1726 | } |
| 1727 | |
| 1728 | return 0; |
| 1729 | } |
| 1730 | |
| 1731 | static int max98095_set_bias_level(struct snd_soc_codec *codec, |
| 1732 | enum snd_soc_bias_level level) |
| 1733 | { |
| 1734 | int ret; |
| 1735 | |
| 1736 | switch (level) { |
| 1737 | case SND_SOC_BIAS_ON: |
| 1738 | break; |
| 1739 | |
| 1740 | case SND_SOC_BIAS_PREPARE: |
| 1741 | break; |
| 1742 | |
| 1743 | case SND_SOC_BIAS_STANDBY: |
| 1744 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
| 1745 | ret = snd_soc_cache_sync(codec); |
| 1746 | |
| 1747 | if (ret != 0) { |
| 1748 | dev_err(codec->dev, "Failed to sync cache: %d\n", ret); |
| 1749 | return ret; |
| 1750 | } |
| 1751 | } |
| 1752 | |
| 1753 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, |
| 1754 | M98095_MBEN, M98095_MBEN); |
| 1755 | break; |
| 1756 | |
| 1757 | case SND_SOC_BIAS_OFF: |
| 1758 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, |
| 1759 | M98095_MBEN, 0); |
| 1760 | codec->cache_sync = 1; |
| 1761 | break; |
| 1762 | } |
| 1763 | codec->dapm.bias_level = level; |
| 1764 | return 0; |
| 1765 | } |
| 1766 | |
| 1767 | #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 |
| 1768 | #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) |
| 1769 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 1770 | static const struct snd_soc_dai_ops max98095_dai1_ops = { |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 1771 | .set_sysclk = max98095_dai_set_sysclk, |
| 1772 | .set_fmt = max98095_dai1_set_fmt, |
| 1773 | .hw_params = max98095_dai1_hw_params, |
| 1774 | }; |
| 1775 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 1776 | static const struct snd_soc_dai_ops max98095_dai2_ops = { |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 1777 | .set_sysclk = max98095_dai_set_sysclk, |
| 1778 | .set_fmt = max98095_dai2_set_fmt, |
| 1779 | .hw_params = max98095_dai2_hw_params, |
| 1780 | }; |
| 1781 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 1782 | static const struct snd_soc_dai_ops max98095_dai3_ops = { |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 1783 | .set_sysclk = max98095_dai_set_sysclk, |
| 1784 | .set_fmt = max98095_dai3_set_fmt, |
| 1785 | .hw_params = max98095_dai3_hw_params, |
| 1786 | }; |
| 1787 | |
| 1788 | static struct snd_soc_dai_driver max98095_dai[] = { |
| 1789 | { |
| 1790 | .name = "HiFi", |
| 1791 | .playback = { |
| 1792 | .stream_name = "HiFi Playback", |
| 1793 | .channels_min = 1, |
| 1794 | .channels_max = 2, |
| 1795 | .rates = MAX98095_RATES, |
| 1796 | .formats = MAX98095_FORMATS, |
| 1797 | }, |
| 1798 | .capture = { |
| 1799 | .stream_name = "HiFi Capture", |
| 1800 | .channels_min = 1, |
| 1801 | .channels_max = 2, |
| 1802 | .rates = MAX98095_RATES, |
| 1803 | .formats = MAX98095_FORMATS, |
| 1804 | }, |
| 1805 | .ops = &max98095_dai1_ops, |
| 1806 | }, |
| 1807 | { |
| 1808 | .name = "Aux", |
| 1809 | .playback = { |
| 1810 | .stream_name = "Aux Playback", |
| 1811 | .channels_min = 1, |
| 1812 | .channels_max = 1, |
| 1813 | .rates = MAX98095_RATES, |
| 1814 | .formats = MAX98095_FORMATS, |
| 1815 | }, |
| 1816 | .ops = &max98095_dai2_ops, |
| 1817 | }, |
| 1818 | { |
| 1819 | .name = "Voice", |
| 1820 | .playback = { |
| 1821 | .stream_name = "Voice Playback", |
| 1822 | .channels_min = 1, |
| 1823 | .channels_max = 1, |
| 1824 | .rates = MAX98095_RATES, |
| 1825 | .formats = MAX98095_FORMATS, |
| 1826 | }, |
| 1827 | .ops = &max98095_dai3_ops, |
| 1828 | } |
| 1829 | |
| 1830 | }; |
| 1831 | |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 1832 | static int max98095_get_eq_channel(const char *name) |
| 1833 | { |
| 1834 | if (strcmp(name, "EQ1 Mode") == 0) |
| 1835 | return 0; |
| 1836 | if (strcmp(name, "EQ2 Mode") == 0) |
| 1837 | return 1; |
| 1838 | return -EINVAL; |
| 1839 | } |
| 1840 | |
| 1841 | static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, |
| 1842 | struct snd_ctl_elem_value *ucontrol) |
| 1843 | { |
| 1844 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 1845 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1846 | struct max98095_pdata *pdata = max98095->pdata; |
| 1847 | int channel = max98095_get_eq_channel(kcontrol->id.name); |
| 1848 | struct max98095_cdata *cdata; |
| 1849 | int sel = ucontrol->value.integer.value[0]; |
| 1850 | struct max98095_eq_cfg *coef_set; |
| 1851 | int fs, best, best_val, i; |
| 1852 | int regmask, regsave; |
| 1853 | |
| 1854 | BUG_ON(channel > 1); |
| 1855 | |
Taylor Hutt | 5394942 | 2011-05-17 18:03:54 -0700 | [diff] [blame] | 1856 | if (!pdata || !max98095->eq_textcnt) |
| 1857 | return 0; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 1858 | |
| 1859 | if (sel >= pdata->eq_cfgcnt) |
| 1860 | return -EINVAL; |
| 1861 | |
Taylor Hutt | 5394942 | 2011-05-17 18:03:54 -0700 | [diff] [blame] | 1862 | cdata = &max98095->dai[channel]; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 1863 | cdata->eq_sel = sel; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 1864 | fs = cdata->rate; |
| 1865 | |
| 1866 | /* Find the selected configuration with nearest sample rate */ |
| 1867 | best = 0; |
| 1868 | best_val = INT_MAX; |
| 1869 | for (i = 0; i < pdata->eq_cfgcnt; i++) { |
| 1870 | if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && |
| 1871 | abs(pdata->eq_cfg[i].rate - fs) < best_val) { |
| 1872 | best = i; |
| 1873 | best_val = abs(pdata->eq_cfg[i].rate - fs); |
| 1874 | } |
| 1875 | } |
| 1876 | |
| 1877 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", |
| 1878 | pdata->eq_cfg[best].name, |
| 1879 | pdata->eq_cfg[best].rate, fs); |
| 1880 | |
| 1881 | coef_set = &pdata->eq_cfg[best]; |
| 1882 | |
| 1883 | regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; |
| 1884 | |
| 1885 | /* Disable filter while configuring, and save current on/off state */ |
| 1886 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); |
| 1887 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); |
| 1888 | |
| 1889 | mutex_lock(&codec->mutex); |
| 1890 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); |
| 1891 | m98095_eq_band(codec, channel, 0, coef_set->band1); |
| 1892 | m98095_eq_band(codec, channel, 1, coef_set->band2); |
| 1893 | m98095_eq_band(codec, channel, 2, coef_set->band3); |
| 1894 | m98095_eq_band(codec, channel, 3, coef_set->band4); |
| 1895 | m98095_eq_band(codec, channel, 4, coef_set->band5); |
| 1896 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); |
| 1897 | mutex_unlock(&codec->mutex); |
| 1898 | |
| 1899 | /* Restore the original on/off state */ |
| 1900 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); |
| 1901 | return 0; |
| 1902 | } |
| 1903 | |
| 1904 | static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, |
| 1905 | struct snd_ctl_elem_value *ucontrol) |
| 1906 | { |
| 1907 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 1908 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1909 | int channel = max98095_get_eq_channel(kcontrol->id.name); |
| 1910 | struct max98095_cdata *cdata; |
| 1911 | |
| 1912 | cdata = &max98095->dai[channel]; |
| 1913 | ucontrol->value.enumerated.item[0] = cdata->eq_sel; |
| 1914 | |
| 1915 | return 0; |
| 1916 | } |
| 1917 | |
| 1918 | static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) |
| 1919 | { |
| 1920 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1921 | struct max98095_pdata *pdata = max98095->pdata; |
| 1922 | struct max98095_eq_cfg *cfg; |
| 1923 | unsigned int cfgcnt; |
| 1924 | int i, j; |
| 1925 | const char **t; |
| 1926 | int ret; |
| 1927 | |
| 1928 | struct snd_kcontrol_new controls[] = { |
| 1929 | SOC_ENUM_EXT("EQ1 Mode", |
| 1930 | max98095->eq_enum, |
| 1931 | max98095_get_eq_enum, |
| 1932 | max98095_put_eq_enum), |
| 1933 | SOC_ENUM_EXT("EQ2 Mode", |
| 1934 | max98095->eq_enum, |
| 1935 | max98095_get_eq_enum, |
| 1936 | max98095_put_eq_enum), |
| 1937 | }; |
| 1938 | |
| 1939 | cfg = pdata->eq_cfg; |
| 1940 | cfgcnt = pdata->eq_cfgcnt; |
| 1941 | |
| 1942 | /* Setup an array of texts for the equalizer enum. |
| 1943 | * This is based on Mark Brown's equalizer driver code. |
| 1944 | */ |
| 1945 | max98095->eq_textcnt = 0; |
| 1946 | max98095->eq_texts = NULL; |
| 1947 | for (i = 0; i < cfgcnt; i++) { |
| 1948 | for (j = 0; j < max98095->eq_textcnt; j++) { |
| 1949 | if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) |
| 1950 | break; |
| 1951 | } |
| 1952 | |
| 1953 | if (j != max98095->eq_textcnt) |
| 1954 | continue; |
| 1955 | |
| 1956 | /* Expand the array */ |
| 1957 | t = krealloc(max98095->eq_texts, |
| 1958 | sizeof(char *) * (max98095->eq_textcnt + 1), |
| 1959 | GFP_KERNEL); |
| 1960 | if (t == NULL) |
| 1961 | continue; |
| 1962 | |
| 1963 | /* Store the new entry */ |
| 1964 | t[max98095->eq_textcnt] = cfg[i].name; |
| 1965 | max98095->eq_textcnt++; |
| 1966 | max98095->eq_texts = t; |
| 1967 | } |
| 1968 | |
| 1969 | /* Now point the soc_enum to .texts array items */ |
| 1970 | max98095->eq_enum.texts = max98095->eq_texts; |
| 1971 | max98095->eq_enum.max = max98095->eq_textcnt; |
| 1972 | |
Liam Girdwood | 022658b | 2012-02-03 17:43:09 +0000 | [diff] [blame] | 1973 | ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 1974 | if (ret != 0) |
| 1975 | dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); |
| 1976 | } |
| 1977 | |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 1978 | static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; |
| 1979 | |
| 1980 | static int max98095_get_bq_channel(struct snd_soc_codec *codec, |
| 1981 | const char *name) |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 1982 | { |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 1983 | int i; |
| 1984 | |
| 1985 | for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) |
| 1986 | if (strcmp(name, bq_mode_name[i]) == 0) |
| 1987 | return i; |
| 1988 | |
| 1989 | /* Shouldn't happen */ |
| 1990 | dev_err(codec->dev, "Bad biquad channel name '%s'\n", name); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 1991 | return -EINVAL; |
| 1992 | } |
| 1993 | |
| 1994 | static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, |
| 1995 | struct snd_ctl_elem_value *ucontrol) |
| 1996 | { |
| 1997 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 1998 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 1999 | struct max98095_pdata *pdata = max98095->pdata; |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 2000 | int channel = max98095_get_bq_channel(codec, kcontrol->id.name); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2001 | struct max98095_cdata *cdata; |
| 2002 | int sel = ucontrol->value.integer.value[0]; |
| 2003 | struct max98095_biquad_cfg *coef_set; |
| 2004 | int fs, best, best_val, i; |
| 2005 | int regmask, regsave; |
| 2006 | |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 2007 | if (channel < 0) |
| 2008 | return channel; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2009 | |
Taylor Hutt | 5394942 | 2011-05-17 18:03:54 -0700 | [diff] [blame] | 2010 | if (!pdata || !max98095->bq_textcnt) |
| 2011 | return 0; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2012 | |
| 2013 | if (sel >= pdata->bq_cfgcnt) |
| 2014 | return -EINVAL; |
| 2015 | |
Taylor Hutt | 5394942 | 2011-05-17 18:03:54 -0700 | [diff] [blame] | 2016 | cdata = &max98095->dai[channel]; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2017 | cdata->bq_sel = sel; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2018 | fs = cdata->rate; |
| 2019 | |
| 2020 | /* Find the selected configuration with nearest sample rate */ |
| 2021 | best = 0; |
| 2022 | best_val = INT_MAX; |
| 2023 | for (i = 0; i < pdata->bq_cfgcnt; i++) { |
| 2024 | if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && |
| 2025 | abs(pdata->bq_cfg[i].rate - fs) < best_val) { |
| 2026 | best = i; |
| 2027 | best_val = abs(pdata->bq_cfg[i].rate - fs); |
| 2028 | } |
| 2029 | } |
| 2030 | |
| 2031 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", |
| 2032 | pdata->bq_cfg[best].name, |
| 2033 | pdata->bq_cfg[best].rate, fs); |
| 2034 | |
| 2035 | coef_set = &pdata->bq_cfg[best]; |
| 2036 | |
| 2037 | regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; |
| 2038 | |
| 2039 | /* Disable filter while configuring, and save current on/off state */ |
| 2040 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); |
| 2041 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); |
| 2042 | |
| 2043 | mutex_lock(&codec->mutex); |
| 2044 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); |
| 2045 | m98095_biquad_band(codec, channel, 0, coef_set->band1); |
| 2046 | m98095_biquad_band(codec, channel, 1, coef_set->band2); |
| 2047 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); |
| 2048 | mutex_unlock(&codec->mutex); |
| 2049 | |
| 2050 | /* Restore the original on/off state */ |
| 2051 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); |
| 2052 | return 0; |
| 2053 | } |
| 2054 | |
| 2055 | static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, |
| 2056 | struct snd_ctl_elem_value *ucontrol) |
| 2057 | { |
| 2058 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 2059 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 2060 | int channel = max98095_get_bq_channel(codec, kcontrol->id.name); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2061 | struct max98095_cdata *cdata; |
| 2062 | |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 2063 | if (channel < 0) |
| 2064 | return channel; |
| 2065 | |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2066 | cdata = &max98095->dai[channel]; |
| 2067 | ucontrol->value.enumerated.item[0] = cdata->bq_sel; |
| 2068 | |
| 2069 | return 0; |
| 2070 | } |
| 2071 | |
| 2072 | static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) |
| 2073 | { |
| 2074 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2075 | struct max98095_pdata *pdata = max98095->pdata; |
| 2076 | struct max98095_biquad_cfg *cfg; |
| 2077 | unsigned int cfgcnt; |
| 2078 | int i, j; |
| 2079 | const char **t; |
| 2080 | int ret; |
| 2081 | |
| 2082 | struct snd_kcontrol_new controls[] = { |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 2083 | SOC_ENUM_EXT((char *)bq_mode_name[0], |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2084 | max98095->bq_enum, |
| 2085 | max98095_get_bq_enum, |
| 2086 | max98095_put_bq_enum), |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 2087 | SOC_ENUM_EXT((char *)bq_mode_name[1], |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2088 | max98095->bq_enum, |
| 2089 | max98095_get_bq_enum, |
| 2090 | max98095_put_bq_enum), |
| 2091 | }; |
Ryan Mallon | c855a1a | 2011-10-04 09:55:41 +1100 | [diff] [blame] | 2092 | BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2093 | |
| 2094 | cfg = pdata->bq_cfg; |
| 2095 | cfgcnt = pdata->bq_cfgcnt; |
| 2096 | |
| 2097 | /* Setup an array of texts for the biquad enum. |
| 2098 | * This is based on Mark Brown's equalizer driver code. |
| 2099 | */ |
| 2100 | max98095->bq_textcnt = 0; |
| 2101 | max98095->bq_texts = NULL; |
| 2102 | for (i = 0; i < cfgcnt; i++) { |
| 2103 | for (j = 0; j < max98095->bq_textcnt; j++) { |
| 2104 | if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) |
| 2105 | break; |
| 2106 | } |
| 2107 | |
| 2108 | if (j != max98095->bq_textcnt) |
| 2109 | continue; |
| 2110 | |
| 2111 | /* Expand the array */ |
| 2112 | t = krealloc(max98095->bq_texts, |
| 2113 | sizeof(char *) * (max98095->bq_textcnt + 1), |
| 2114 | GFP_KERNEL); |
| 2115 | if (t == NULL) |
| 2116 | continue; |
| 2117 | |
| 2118 | /* Store the new entry */ |
| 2119 | t[max98095->bq_textcnt] = cfg[i].name; |
| 2120 | max98095->bq_textcnt++; |
| 2121 | max98095->bq_texts = t; |
| 2122 | } |
| 2123 | |
| 2124 | /* Now point the soc_enum to .texts array items */ |
| 2125 | max98095->bq_enum.texts = max98095->bq_texts; |
| 2126 | max98095->bq_enum.max = max98095->bq_textcnt; |
| 2127 | |
Liam Girdwood | 022658b | 2012-02-03 17:43:09 +0000 | [diff] [blame] | 2128 | ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2129 | if (ret != 0) |
| 2130 | dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); |
| 2131 | } |
| 2132 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2133 | static void max98095_handle_pdata(struct snd_soc_codec *codec) |
| 2134 | { |
| 2135 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2136 | struct max98095_pdata *pdata = max98095->pdata; |
| 2137 | u8 regval = 0; |
| 2138 | |
| 2139 | if (!pdata) { |
| 2140 | dev_dbg(codec->dev, "No platform data\n"); |
| 2141 | return; |
| 2142 | } |
| 2143 | |
| 2144 | /* Configure mic for analog/digital mic mode */ |
| 2145 | if (pdata->digmic_left_mode) |
| 2146 | regval |= M98095_DIGMIC_L; |
| 2147 | |
| 2148 | if (pdata->digmic_right_mode) |
| 2149 | regval |= M98095_DIGMIC_R; |
| 2150 | |
| 2151 | snd_soc_write(codec, M98095_087_CFG_MIC, regval); |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2152 | |
| 2153 | /* Configure equalizers */ |
| 2154 | if (pdata->eq_cfgcnt) |
| 2155 | max98095_handle_eq_pdata(codec); |
| 2156 | |
| 2157 | /* Configure bi-quad filters */ |
| 2158 | if (pdata->bq_cfgcnt) |
| 2159 | max98095_handle_bq_pdata(codec); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2160 | } |
| 2161 | |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2162 | static irqreturn_t max98095_report_jack(int irq, void *data) |
| 2163 | { |
| 2164 | struct snd_soc_codec *codec = data; |
| 2165 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2166 | unsigned int value; |
| 2167 | int hp_report = 0; |
| 2168 | int mic_report = 0; |
| 2169 | |
| 2170 | /* Read the Jack Status Register */ |
| 2171 | value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS); |
| 2172 | |
| 2173 | /* If ddone is not set, then detection isn't finished yet */ |
| 2174 | if ((value & M98095_DDONE) == 0) |
| 2175 | return IRQ_NONE; |
| 2176 | |
| 2177 | /* if hp, check its bit, and if set, clear it */ |
| 2178 | if ((value & M98095_HP_IN || value & M98095_LO_IN) && |
| 2179 | max98095->headphone_jack) |
| 2180 | hp_report |= SND_JACK_HEADPHONE; |
| 2181 | |
| 2182 | /* if mic, check its bit, and if set, clear it */ |
| 2183 | if ((value & M98095_MIC_IN) && max98095->mic_jack) |
| 2184 | mic_report |= SND_JACK_MICROPHONE; |
| 2185 | |
| 2186 | if (max98095->headphone_jack == max98095->mic_jack) { |
| 2187 | snd_soc_jack_report(max98095->headphone_jack, |
| 2188 | hp_report | mic_report, |
| 2189 | SND_JACK_HEADSET); |
| 2190 | } else { |
| 2191 | if (max98095->headphone_jack) |
| 2192 | snd_soc_jack_report(max98095->headphone_jack, |
| 2193 | hp_report, SND_JACK_HEADPHONE); |
| 2194 | if (max98095->mic_jack) |
| 2195 | snd_soc_jack_report(max98095->mic_jack, |
| 2196 | mic_report, SND_JACK_MICROPHONE); |
| 2197 | } |
| 2198 | |
| 2199 | return IRQ_HANDLED; |
| 2200 | } |
| 2201 | |
Mark Brown | a265367 | 2012-05-31 14:47:46 +0100 | [diff] [blame] | 2202 | static int max98095_jack_detect_enable(struct snd_soc_codec *codec) |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2203 | { |
| 2204 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2205 | int ret = 0; |
| 2206 | int detect_enable = M98095_JDEN; |
| 2207 | unsigned int slew = M98095_DEFAULT_SLEW_DELAY; |
| 2208 | |
| 2209 | if (max98095->pdata->jack_detect_pin5en) |
| 2210 | detect_enable |= M98095_PIN5EN; |
| 2211 | |
Mark Brown | 0841b04 | 2012-04-02 14:53:13 +0100 | [diff] [blame] | 2212 | if (max98095->pdata->jack_detect_delay) |
| 2213 | slew = max98095->pdata->jack_detect_delay; |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2214 | |
| 2215 | ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew); |
| 2216 | if (ret < 0) { |
| 2217 | dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); |
| 2218 | return ret; |
| 2219 | } |
| 2220 | |
| 2221 | /* configure auto detection to be enabled */ |
| 2222 | ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable); |
| 2223 | if (ret < 0) { |
| 2224 | dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); |
| 2225 | return ret; |
| 2226 | } |
| 2227 | |
| 2228 | return ret; |
| 2229 | } |
| 2230 | |
Mark Brown | a265367 | 2012-05-31 14:47:46 +0100 | [diff] [blame] | 2231 | static int max98095_jack_detect_disable(struct snd_soc_codec *codec) |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2232 | { |
| 2233 | int ret = 0; |
| 2234 | |
| 2235 | /* configure auto detection to be disabled */ |
| 2236 | ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0); |
| 2237 | if (ret < 0) { |
| 2238 | dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); |
| 2239 | return ret; |
| 2240 | } |
| 2241 | |
| 2242 | return ret; |
| 2243 | } |
| 2244 | |
| 2245 | int max98095_jack_detect(struct snd_soc_codec *codec, |
| 2246 | struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack) |
| 2247 | { |
| 2248 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2249 | struct i2c_client *client = to_i2c_client(codec->dev); |
| 2250 | int ret = 0; |
| 2251 | |
| 2252 | max98095->headphone_jack = hp_jack; |
| 2253 | max98095->mic_jack = mic_jack; |
| 2254 | |
| 2255 | /* only progress if we have at least 1 jack pointer */ |
| 2256 | if (!hp_jack && !mic_jack) |
| 2257 | return -EINVAL; |
| 2258 | |
| 2259 | max98095_jack_detect_enable(codec); |
| 2260 | |
| 2261 | /* enable interrupts for headphone jack detection */ |
| 2262 | ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN, |
| 2263 | M98095_IDDONE, M98095_IDDONE); |
| 2264 | if (ret < 0) { |
| 2265 | dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret); |
| 2266 | return ret; |
| 2267 | } |
| 2268 | |
| 2269 | max98095_report_jack(client->irq, codec); |
| 2270 | return 0; |
| 2271 | } |
Mark Brown | a265367 | 2012-05-31 14:47:46 +0100 | [diff] [blame] | 2272 | EXPORT_SYMBOL_GPL(max98095_jack_detect); |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2273 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2274 | #ifdef CONFIG_PM |
Lars-Peter Clausen | 84b315e | 2011-12-02 10:18:28 +0100 | [diff] [blame] | 2275 | static int max98095_suspend(struct snd_soc_codec *codec) |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2276 | { |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2277 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2278 | |
| 2279 | if (max98095->headphone_jack || max98095->mic_jack) |
| 2280 | max98095_jack_detect_disable(codec); |
| 2281 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2282 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 2283 | |
| 2284 | return 0; |
| 2285 | } |
| 2286 | |
| 2287 | static int max98095_resume(struct snd_soc_codec *codec) |
| 2288 | { |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2289 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2290 | struct i2c_client *client = to_i2c_client(codec->dev); |
| 2291 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2292 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 2293 | |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2294 | if (max98095->headphone_jack || max98095->mic_jack) { |
| 2295 | max98095_jack_detect_enable(codec); |
| 2296 | max98095_report_jack(client->irq, codec); |
| 2297 | } |
| 2298 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2299 | return 0; |
| 2300 | } |
| 2301 | #else |
| 2302 | #define max98095_suspend NULL |
| 2303 | #define max98095_resume NULL |
| 2304 | #endif |
| 2305 | |
| 2306 | static int max98095_reset(struct snd_soc_codec *codec) |
| 2307 | { |
| 2308 | int i, ret; |
| 2309 | |
| 2310 | /* Gracefully reset the DSP core and the codec hardware |
| 2311 | * in a proper sequence */ |
| 2312 | ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); |
| 2313 | if (ret < 0) { |
| 2314 | dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); |
| 2315 | return ret; |
| 2316 | } |
| 2317 | |
| 2318 | ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); |
| 2319 | if (ret < 0) { |
| 2320 | dev_err(codec->dev, "Failed to reset codec: %d\n", ret); |
| 2321 | return ret; |
| 2322 | } |
| 2323 | |
| 2324 | /* Reset to hardware default for registers, as there is not |
| 2325 | * a soft reset hardware control register */ |
| 2326 | for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { |
| 2327 | ret = snd_soc_write(codec, i, max98095_reg_def[i]); |
| 2328 | if (ret < 0) { |
| 2329 | dev_err(codec->dev, "Failed to reset: %d\n", ret); |
| 2330 | return ret; |
| 2331 | } |
| 2332 | } |
| 2333 | |
| 2334 | return ret; |
| 2335 | } |
| 2336 | |
| 2337 | static int max98095_probe(struct snd_soc_codec *codec) |
| 2338 | { |
| 2339 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2340 | struct max98095_cdata *cdata; |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2341 | struct i2c_client *client; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2342 | int ret = 0; |
| 2343 | |
| 2344 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); |
| 2345 | if (ret != 0) { |
| 2346 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
| 2347 | return ret; |
| 2348 | } |
| 2349 | |
| 2350 | /* reset the codec, the DSP core, and disable all interrupts */ |
| 2351 | max98095_reset(codec); |
| 2352 | |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2353 | client = to_i2c_client(codec->dev); |
| 2354 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2355 | /* initialize private data */ |
| 2356 | |
| 2357 | max98095->sysclk = (unsigned)-1; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2358 | max98095->eq_textcnt = 0; |
| 2359 | max98095->bq_textcnt = 0; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2360 | |
| 2361 | cdata = &max98095->dai[0]; |
| 2362 | cdata->rate = (unsigned)-1; |
| 2363 | cdata->fmt = (unsigned)-1; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2364 | cdata->eq_sel = 0; |
| 2365 | cdata->bq_sel = 0; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2366 | |
| 2367 | cdata = &max98095->dai[1]; |
| 2368 | cdata->rate = (unsigned)-1; |
| 2369 | cdata->fmt = (unsigned)-1; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2370 | cdata->eq_sel = 0; |
| 2371 | cdata->bq_sel = 0; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2372 | |
| 2373 | cdata = &max98095->dai[2]; |
| 2374 | cdata->rate = (unsigned)-1; |
| 2375 | cdata->fmt = (unsigned)-1; |
Peter Hsiang | dad31ec | 2011-04-19 18:20:40 -0700 | [diff] [blame] | 2376 | cdata->eq_sel = 0; |
| 2377 | cdata->bq_sel = 0; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2378 | |
| 2379 | max98095->lin_state = 0; |
| 2380 | max98095->mic1pre = 0; |
| 2381 | max98095->mic2pre = 0; |
| 2382 | |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2383 | if (client->irq) { |
| 2384 | /* register an audio interrupt */ |
| 2385 | ret = request_threaded_irq(client->irq, NULL, |
| 2386 | max98095_report_jack, |
| 2387 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, |
| 2388 | "max98095", codec); |
| 2389 | if (ret) { |
| 2390 | dev_err(codec->dev, "Failed to request IRQ: %d\n", ret); |
| 2391 | goto err_access; |
| 2392 | } |
| 2393 | } |
| 2394 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2395 | ret = snd_soc_read(codec, M98095_0FF_REV_ID); |
| 2396 | if (ret < 0) { |
Taylor Hutt | bab3b59 | 2011-06-20 11:54:32 -0700 | [diff] [blame] | 2397 | dev_err(codec->dev, "Failure reading hardware revision: %d\n", |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2398 | ret); |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2399 | goto err_irq; |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2400 | } |
Taylor Hutt | bab3b59 | 2011-06-20 11:54:32 -0700 | [diff] [blame] | 2401 | dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2402 | |
| 2403 | snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); |
| 2404 | |
| 2405 | /* initialize registers cache to hardware default */ |
| 2406 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 2407 | |
| 2408 | snd_soc_write(codec, M98095_048_MIX_DAC_LR, |
| 2409 | M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); |
| 2410 | |
| 2411 | snd_soc_write(codec, M98095_049_MIX_DAC_M, |
| 2412 | M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); |
| 2413 | |
| 2414 | snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); |
| 2415 | snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); |
| 2416 | snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); |
| 2417 | |
| 2418 | snd_soc_write(codec, M98095_02C_DAI1_IOCFG, |
| 2419 | M98095_S1NORMAL|M98095_SDATA); |
| 2420 | |
| 2421 | snd_soc_write(codec, M98095_036_DAI2_IOCFG, |
| 2422 | M98095_S2NORMAL|M98095_SDATA); |
| 2423 | |
| 2424 | snd_soc_write(codec, M98095_040_DAI3_IOCFG, |
| 2425 | M98095_S3NORMAL|M98095_SDATA); |
| 2426 | |
| 2427 | max98095_handle_pdata(codec); |
| 2428 | |
| 2429 | /* take the codec out of the shut down */ |
| 2430 | snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, |
| 2431 | M98095_SHDNRUN); |
| 2432 | |
| 2433 | max98095_add_widgets(codec); |
| 2434 | |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2435 | return 0; |
| 2436 | |
| 2437 | err_irq: |
| 2438 | if (client->irq) |
| 2439 | free_irq(client->irq, codec); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2440 | err_access: |
| 2441 | return ret; |
| 2442 | } |
| 2443 | |
| 2444 | static int max98095_remove(struct snd_soc_codec *codec) |
| 2445 | { |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2446 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
| 2447 | struct i2c_client *client = to_i2c_client(codec->dev); |
| 2448 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2449 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 2450 | |
Rhyland Klein | 9dd90c5 | 2012-03-15 15:07:47 -0700 | [diff] [blame] | 2451 | if (max98095->headphone_jack || max98095->mic_jack) |
| 2452 | max98095_jack_detect_disable(codec); |
| 2453 | |
| 2454 | if (client->irq) |
| 2455 | free_irq(client->irq, codec); |
| 2456 | |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2457 | return 0; |
| 2458 | } |
| 2459 | |
| 2460 | static struct snd_soc_codec_driver soc_codec_dev_max98095 = { |
| 2461 | .probe = max98095_probe, |
| 2462 | .remove = max98095_remove, |
| 2463 | .suspend = max98095_suspend, |
| 2464 | .resume = max98095_resume, |
| 2465 | .set_bias_level = max98095_set_bias_level, |
| 2466 | .reg_cache_size = ARRAY_SIZE(max98095_reg_def), |
| 2467 | .reg_word_size = sizeof(u8), |
| 2468 | .reg_cache_default = max98095_reg_def, |
| 2469 | .readable_register = max98095_readable, |
| 2470 | .volatile_register = max98095_volatile, |
| 2471 | .dapm_widgets = max98095_dapm_widgets, |
| 2472 | .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), |
| 2473 | .dapm_routes = max98095_audio_map, |
| 2474 | .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), |
| 2475 | }; |
| 2476 | |
| 2477 | static int max98095_i2c_probe(struct i2c_client *i2c, |
| 2478 | const struct i2c_device_id *id) |
| 2479 | { |
| 2480 | struct max98095_priv *max98095; |
| 2481 | int ret; |
| 2482 | |
Axel Lin | b1b5488 | 2011-12-29 12:02:21 +0800 | [diff] [blame] | 2483 | max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv), |
| 2484 | GFP_KERNEL); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2485 | if (max98095 == NULL) |
| 2486 | return -ENOMEM; |
| 2487 | |
| 2488 | max98095->devtype = id->driver_data; |
| 2489 | i2c_set_clientdata(i2c, max98095); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2490 | max98095->pdata = i2c->dev.platform_data; |
| 2491 | |
Taylor Hutt | bab3b59 | 2011-06-20 11:54:32 -0700 | [diff] [blame] | 2492 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, |
| 2493 | max98095_dai, ARRAY_SIZE(max98095_dai)); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2494 | return ret; |
| 2495 | } |
| 2496 | |
Bill Pemberton | 7a79e94 | 2012-12-07 09:26:37 -0500 | [diff] [blame] | 2497 | static int max98095_i2c_remove(struct i2c_client *client) |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2498 | { |
| 2499 | snd_soc_unregister_codec(&client->dev); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2500 | return 0; |
| 2501 | } |
| 2502 | |
| 2503 | static const struct i2c_device_id max98095_i2c_id[] = { |
| 2504 | { "max98095", MAX98095 }, |
| 2505 | { } |
| 2506 | }; |
| 2507 | MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); |
| 2508 | |
| 2509 | static struct i2c_driver max98095_i2c_driver = { |
| 2510 | .driver = { |
| 2511 | .name = "max98095", |
| 2512 | .owner = THIS_MODULE, |
| 2513 | }, |
| 2514 | .probe = max98095_i2c_probe, |
Bill Pemberton | 7a79e94 | 2012-12-07 09:26:37 -0500 | [diff] [blame] | 2515 | .remove = max98095_i2c_remove, |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2516 | .id_table = max98095_i2c_id, |
| 2517 | }; |
| 2518 | |
Sachin Kamat | a8af02c | 2012-08-06 17:26:00 +0530 | [diff] [blame] | 2519 | module_i2c_driver(max98095_i2c_driver); |
Peter Hsiang | 82a5a93 | 2011-04-04 19:35:30 -0700 | [diff] [blame] | 2520 | |
| 2521 | MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); |
| 2522 | MODULE_AUTHOR("Peter Hsiang"); |
| 2523 | MODULE_LICENSE("GPL"); |