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gerrit-public.fairphone.software / kernel / msm-4.9 / d3ca1952e63ffbebab6f2f1c9551df7b3cb731f5 / . / arch / arm / mach-pxa / include / mach / irqs.h
blob: 6a1d95993342438cd320f8e3b1bdc527f951fb37 [file] [log] [blame]
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]1/*
2 * arch/arm/mach-pxa/include/mach/irqs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Russell King35f53aa2008-10-17 13:19:08 +0100[diff] [blame]12#ifndef __ASM_MACH_IRQS_H
13#define __ASM_MACH_IRQS_H
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]14
Marc Zyngier57a7a622008-09-01 13:03:32 +0100[diff] [blame]15#ifdef CONFIG_PXA_HAVE_ISA_IRQS
16#define PXA_ISA_IRQ(x) (x)
17#define PXA_ISA_IRQ_NUM (16)
18#else
19#define PXA_ISA_IRQ_NUM (0)
20#endif
21
22#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]23
24#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
25#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
26#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
27#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
28#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */
29#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
30#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
31#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
32#endif
33
34#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
35#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
36#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
37#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
38#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
39#define IRQ_USB PXA_IRQ(11) /* USB Service */
40#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
41#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */
42#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
43#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
44#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
45#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */
46#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
47#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
48#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
49#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
50#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
51#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
52#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
53#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
54#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
55#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
56#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
57#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
58#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
59#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
60#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
61#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
62
63#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
64#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
65#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
66#endif
67
68#ifdef CONFIG_PXA3xx
69#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */
70#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
71#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
72#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
73#define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */
74#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
75#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
76#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
77#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
78#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */
79#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
80#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
81#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
82#endif
83
Marc Zyngier57a7a622008-09-01 13:03:32 +0100[diff] [blame]84#define PXA_GPIO_IRQ_BASE PXA_IRQ(64)
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]85#define PXA_GPIO_IRQ_NUM (128)
86
87#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
88#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
89
90#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
91#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
92
93/*
Philipp Zabela01bd582009-04-17 11:47:57 +0200[diff] [blame]94 * The following interrupts are for board specific purposes. Since
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]95 * the kernel can only run on one machine at a time, we can re-use
Philipp Zabela01bd582009-04-17 11:47:57 +0200[diff] [blame]96 * these. There will be 16 IRQs by default. If it is not enough,
97 * IRQ_BOARD_END is allowed be customized for each board, but keep
98 * the numbers within sensible limits and in descending order, so
99 * when multiple config options are selected, the maximum will be
100 * used.
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]101 */
102#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
Philipp Zabela01bd582009-04-17 11:47:57 +0200[diff] [blame]103
Philipp Zabeld3ca1952009-05-28 07:05:18 +0200[diff] [blame^]104#if defined(CONFIG_MACH_H4700)
105#define IRQ_BOARD_END (IRQ_BOARD_START + 70)
106#elif defined(CONFIG_MACH_ZYLONITE)
Philipp Zabela01bd582009-04-17 11:47:57 +0200[diff] [blame]107#define IRQ_BOARD_END (IRQ_BOARD_START + 32)
108#else
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]109#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
Philipp Zabela01bd582009-04-17 11:47:57 +0200[diff] [blame]110#endif
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]111
112#define IRQ_SA1111_START (IRQ_BOARD_END)
113#define IRQ_GPAIN0 (IRQ_BOARD_END + 0)
114#define IRQ_GPAIN1 (IRQ_BOARD_END + 1)
115#define IRQ_GPAIN2 (IRQ_BOARD_END + 2)
116#define IRQ_GPAIN3 (IRQ_BOARD_END + 3)
117#define IRQ_GPBIN0 (IRQ_BOARD_END + 4)
118#define IRQ_GPBIN1 (IRQ_BOARD_END + 5)
119#define IRQ_GPBIN2 (IRQ_BOARD_END + 6)
120#define IRQ_GPBIN3 (IRQ_BOARD_END + 7)
121#define IRQ_GPBIN4 (IRQ_BOARD_END + 8)
122#define IRQ_GPBIN5 (IRQ_BOARD_END + 9)
123#define IRQ_GPCIN0 (IRQ_BOARD_END + 10)
124#define IRQ_GPCIN1 (IRQ_BOARD_END + 11)
125#define IRQ_GPCIN2 (IRQ_BOARD_END + 12)
126#define IRQ_GPCIN3 (IRQ_BOARD_END + 13)
127#define IRQ_GPCIN4 (IRQ_BOARD_END + 14)
128#define IRQ_GPCIN5 (IRQ_BOARD_END + 15)
129#define IRQ_GPCIN6 (IRQ_BOARD_END + 16)
130#define IRQ_GPCIN7 (IRQ_BOARD_END + 17)
131#define IRQ_MSTXINT (IRQ_BOARD_END + 18)
132#define IRQ_MSRXINT (IRQ_BOARD_END + 19)
133#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20)
134#define IRQ_TPTXINT (IRQ_BOARD_END + 21)
135#define IRQ_TPRXINT (IRQ_BOARD_END + 22)
136#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23)
137#define SSPXMTINT (IRQ_BOARD_END + 24)
138#define SSPRCVINT (IRQ_BOARD_END + 25)
139#define SSPROR (IRQ_BOARD_END + 26)
140#define AUDXMTDMADONEA (IRQ_BOARD_END + 32)
141#define AUDRCVDMADONEA (IRQ_BOARD_END + 33)
142#define AUDXMTDMADONEB (IRQ_BOARD_END + 34)
143#define AUDRCVDMADONEB (IRQ_BOARD_END + 35)
144#define AUDTFSR (IRQ_BOARD_END + 36)
145#define AUDRFSR (IRQ_BOARD_END + 37)
146#define AUDTUR (IRQ_BOARD_END + 38)
147#define AUDROR (IRQ_BOARD_END + 39)
148#define AUDDTS (IRQ_BOARD_END + 40)
149#define AUDRDD (IRQ_BOARD_END + 41)
150#define AUDSTO (IRQ_BOARD_END + 42)
151#define IRQ_USBPWR (IRQ_BOARD_END + 43)
152#define IRQ_HCIM (IRQ_BOARD_END + 44)
153#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45)
154#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46)
155#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47)
156#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48)
157#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49)
158#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50)
159#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51)
160#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52)
161#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53)
162#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54)
163
164#define IRQ_LOCOMO_START (IRQ_BOARD_END)
165#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0)
166#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1)
167#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2)
168#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3)
169#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4)
170#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5)
171#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6)
172#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7)
173#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8)
174#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9)
175#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10)
176#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11)
177#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12)
178#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13)
179#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14)
180#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15)
181#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16)
182#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17)
183#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18)
184#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19)
185#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20)
186#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21)
187
188/*
189 * Figure out the MAX IRQ number.
190 *
191 * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
192 * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
193 * Otherwise, we have the standard IRQs only.
194 */
195#ifdef CONFIG_SA1111
196#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
197#elif defined(CONFIG_SHARP_LOCOMO)
198#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
Russell King7a5063d2008-08-22 11:09:38 +0100[diff] [blame]199#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]200#define NR_IRQS (IRQ_BOARD_END)
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]201#else
202#define NR_IRQS (IRQ_BOARD_START)
203#endif
204
205/*
206 * Board specific IRQs. Define them here.
207 * Do not surround them with ifdefs.
208 */
209#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
210#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
211#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
212#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
213#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3)
214#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
215#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
216#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
217#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
218
219#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
220#define LPD270_USBC_IRQ LPD270_IRQ(2)
221#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
222#define LPD270_AC97_IRQ LPD270_IRQ(4)
223
224#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
225#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
226#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
227#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
228#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3)
229#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4)
230#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5)
231#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6)
232#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7)
233#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9)
234#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
235#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11)
236#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13)
237#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
238#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
239
240/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
241#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0)
242#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
243#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
244#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
245
246/* phyCORE-PXA270 (PCM027) Interrupts */
247#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
248#define PCM027_BTDET_IRQ PCM027_IRQ(0)
249#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
250#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
251#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
252
253/* ITE8152 irqs */
254/* add IT8152 IRQs beyond BOARD_END */
255#ifdef CONFIG_PCI_HOST_ITE8152
256#define IT8152_IRQ(x) (IRQ_BOARD_END + (x))
257
258/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
259#define IT8152_LD_IRQ_COUNT 9
260#define IT8152_LP_IRQ_COUNT 16
261#define IT8152_PD_IRQ_COUNT 15
262
263/* Priorities: */
264#define IT8152_PD_IRQ(i) IT8152_IRQ(i)
265#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
266#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
267
268#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
269
270#if NR_IRQS < (IT8152_LAST_IRQ+1)
271#undef NR_IRQS
272#define NR_IRQS (IT8152_LAST_IRQ+1)
273#endif
274
275#endif /* CONFIG_PCI_HOST_ITE8152 */
Russell King35f53aa2008-10-17 13:19:08 +0100[diff] [blame]276
277#endif /* __ASM_MACH_IRQS_H */