| Rob Herring | 8d4d9f5 | 2012-03-13 18:19:19 -0500 | [diff] [blame] | 1 | Device Tree Clock bindings for Calxeda highbank platform |
| 2 | |
| 3 | This binding uses the common clock binding[1]. |
| 4 | |
| 5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible : shall be one of the following: |
| 9 | "calxeda,hb-pll-clock" - for a PLL clock |
| 10 | "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the |
| 11 | A9 clock. |
| 12 | "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock. |
| 13 | "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller. |
| 14 | - reg : shall be the control register offset from SYSREGs base for the clock. |
| 15 | - clocks : shall be the input parent clock phandle for the clock. This is |
| 16 | either an oscillator or a pll output. |
| 17 | - #clock-cells : from common clock binding; shall be set to 0. |