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Russell Kingf8f98a92005-06-08 15:28:24 +01001/*
2 * linux/arch/arm/lib/copypage-xscale.S
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This handles the mini data cache, as found on SA11x0 and XScale
11 * processors. When we copy a user page page, we map it in such a way
12 * that accesses to this page will not touch the main data cache, but
13 * will be cached in the mini data cache. This prevents us thrashing
14 * the main data cache on page faults.
15 */
16#include <linux/init.h>
17#include <linux/mm.h>
Russell King063b0a42008-10-31 15:08:35 +000018#include <linux/highmem.h>
Russell Kingf8f98a92005-06-08 15:28:24 +010019
Russell Kingf8f98a92005-06-08 15:28:24 +010020#include <asm/pgtable.h>
21#include <asm/tlbflush.h>
Richard Purdie1c9d3df2006-12-30 16:08:50 +010022#include <asm/cacheflush.h>
Russell Kingf8f98a92005-06-08 15:28:24 +010023
Russell King1b2e2b72006-08-21 17:06:38 +010024#include "mm.h"
25
Russell Kingf8f98a92005-06-08 15:28:24 +010026#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
Russell Kingbb30f362008-09-06 20:04:59 +010027 L_PTE_MT_MINICACHE)
Russell Kingf8f98a92005-06-08 15:28:24 +010028
Thomas Gleixnerbd31b852009-07-03 08:44:46 -050029static DEFINE_RAW_SPINLOCK(minicache_lock);
Russell Kingf8f98a92005-06-08 15:28:24 +010030
31/*
Russell King063b0a42008-10-31 15:08:35 +000032 * XScale mini-dcache optimised copy_user_highpage
Russell Kingf8f98a92005-06-08 15:28:24 +010033 *
34 * We flush the destination cache lines just before we write the data into the
35 * corresponding address. Since the Dcache is read-allocate, this removes the
36 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
37 * and merged as appropriate.
38 */
Uwe Kleine-König446c92b2009-03-12 18:03:16 +010039static void __naked
Russell Kingf8f98a92005-06-08 15:28:24 +010040mc_copy_user_page(void *from, void *to)
41{
42 /*
43 * Strangely enough, best performance is achieved
44 * when prefetching destination as well. (NP)
45 */
46 asm volatile(
47 "stmfd sp!, {r4, r5, lr} \n\
48 mov lr, %2 \n\
49 pld [r0, #0] \n\
50 pld [r0, #32] \n\
51 pld [r1, #0] \n\
52 pld [r1, #32] \n\
531: pld [r0, #64] \n\
54 pld [r0, #96] \n\
55 pld [r1, #64] \n\
56 pld [r1, #96] \n\
572: ldrd r2, [r0], #8 \n\
58 ldrd r4, [r0], #8 \n\
59 mov ip, r1 \n\
60 strd r2, [r1], #8 \n\
61 ldrd r2, [r0], #8 \n\
62 strd r4, [r1], #8 \n\
63 ldrd r4, [r0], #8 \n\
64 strd r2, [r1], #8 \n\
65 strd r4, [r1], #8 \n\
66 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
67 ldrd r2, [r0], #8 \n\
68 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
69 ldrd r4, [r0], #8 \n\
70 mov ip, r1 \n\
71 strd r2, [r1], #8 \n\
72 ldrd r2, [r0], #8 \n\
73 strd r4, [r1], #8 \n\
74 ldrd r4, [r0], #8 \n\
75 strd r2, [r1], #8 \n\
76 strd r4, [r1], #8 \n\
77 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
78 subs lr, lr, #1 \n\
79 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
80 bgt 1b \n\
81 beq 2b \n\
82 ldmfd sp!, {r4, r5, pc} "
83 :
84 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
85}
86
Russell King063b0a42008-10-31 15:08:35 +000087void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
Russell Kingf00a75c2009-10-05 15:17:45 +010088 unsigned long vaddr, struct vm_area_struct *vma)
Russell Kingf8f98a92005-06-08 15:28:24 +010089{
Cong Wang5472e862011-11-25 23:14:15 +080090 void *kto = kmap_atomic(to);
Richard Purdie1c9d3df2006-12-30 16:08:50 +010091
Catalin Marinasc0177802010-09-13 15:57:36 +010092 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
Russell King063b0a42008-10-31 15:08:35 +000093 __flush_dcache_page(page_mapping(from), from);
Richard Purdie1c9d3df2006-12-30 16:08:50 +010094
Thomas Gleixnerbd31b852009-07-03 08:44:46 -050095 raw_spin_lock(&minicache_lock);
Russell Kingf8f98a92005-06-08 15:28:24 +010096
Russell King67ece142011-07-02 15:20:44 +010097 set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot));
Russell Kingf8f98a92005-06-08 15:28:24 +010098
99 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
100
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500101 raw_spin_unlock(&minicache_lock);
Russell King063b0a42008-10-31 15:08:35 +0000102
Cong Wang5472e862011-11-25 23:14:15 +0800103 kunmap_atomic(kto);
Russell Kingf8f98a92005-06-08 15:28:24 +0100104}
105
106/*
107 * XScale optimised clear_user_page
108 */
Russell King303c6442008-10-31 16:32:19 +0000109void
110xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
Russell Kingf8f98a92005-06-08 15:28:24 +0100111{
Cong Wang5472e862011-11-25 23:14:15 +0800112 void *ptr, *kaddr = kmap_atomic(page);
Russell Kingf8f98a92005-06-08 15:28:24 +0100113 asm volatile(
Nicolas Pitre43ae2862008-11-04 02:42:27 -0500114 "mov r1, %2 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +0100115 mov r2, #0 \n\
116 mov r3, #0 \n\
Russell King303c6442008-10-31 16:32:19 +00001171: mov ip, %0 \n\
118 strd r2, [%0], #8 \n\
119 strd r2, [%0], #8 \n\
120 strd r2, [%0], #8 \n\
121 strd r2, [%0], #8 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +0100122 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
123 subs r1, r1, #1 \n\
124 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
Russell King303c6442008-10-31 16:32:19 +0000125 bne 1b"
Nicolas Pitre43ae2862008-11-04 02:42:27 -0500126 : "=r" (ptr)
127 : "0" (kaddr), "I" (PAGE_SIZE / 32)
Russell King303c6442008-10-31 16:32:19 +0000128 : "r1", "r2", "r3", "ip");
Cong Wang5472e862011-11-25 23:14:15 +0800129 kunmap_atomic(kaddr);
Russell Kingf8f98a92005-06-08 15:28:24 +0100130}
131
132struct cpu_user_fns xscale_mc_user_fns __initdata = {
Russell King303c6442008-10-31 16:32:19 +0000133 .cpu_clear_user_highpage = xscale_mc_clear_user_highpage,
Russell King063b0a42008-10-31 15:08:35 +0000134 .cpu_copy_user_highpage = xscale_mc_copy_user_highpage,
Russell Kingf8f98a92005-06-08 15:28:24 +0100135};