Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / d43f81cbaf43531a977e8b4c4427f19acf8a5061 / . / include / uapi / drm / tegra_drm.h
blob: 6e132a2f7420ed3986f3f109e14c4281b1510a85 [file] [log] [blame]
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200[diff] [blame^]1/*
2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _UAPI_TEGRA_DRM_H_
18#define _UAPI_TEGRA_DRM_H_
19
20struct drm_tegra_gem_create {
21 __u64 size;
22 __u32 flags;
23 __u32 handle;
24};
25
26struct drm_tegra_gem_mmap {
27 __u32 handle;
28 __u32 offset;
29};
30
31struct drm_tegra_syncpt_read {
32 __u32 id;
33 __u32 value;
34};
35
36struct drm_tegra_syncpt_incr {
37 __u32 id;
38 __u32 pad;
39};
40
41struct drm_tegra_syncpt_wait {
42 __u32 id;
43 __u32 thresh;
44 __u32 timeout;
45 __u32 value;
46};
47
48#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
49
50struct drm_tegra_open_channel {
51 __u32 client;
52 __u32 pad;
53 __u64 context;
54};
55
56struct drm_tegra_close_channel {
57 __u64 context;
58};
59
60struct drm_tegra_get_syncpt {
61 __u64 context;
62 __u32 index;
63 __u32 id;
64};
65
66struct drm_tegra_syncpt {
67 __u32 id;
68 __u32 incrs;
69};
70
71struct drm_tegra_cmdbuf {
72 __u32 handle;
73 __u32 offset;
74 __u32 words;
75 __u32 pad;
76};
77
78struct drm_tegra_reloc {
79 struct {
80 __u32 handle;
81 __u32 offset;
82 } cmdbuf;
83 struct {
84 __u32 handle;
85 __u32 offset;
86 } target;
87 __u32 shift;
88 __u32 pad;
89};
90
91struct drm_tegra_waitchk {
92 __u32 handle;
93 __u32 offset;
94 __u32 syncpt;
95 __u32 thresh;
96};
97
98struct drm_tegra_submit {
99 __u64 context;
100 __u32 num_syncpts;
101 __u32 num_cmdbufs;
102 __u32 num_relocs;
103 __u32 num_waitchks;
104 __u32 waitchk_mask;
105 __u32 timeout;
106 __u32 pad;
107 __u64 syncpts;
108 __u64 cmdbufs;
109 __u64 relocs;
110 __u64 waitchks;
111 __u32 fence; /* Return value */
112
113 __u32 reserved[5]; /* future expansion */
114};
115
116#define DRM_TEGRA_GEM_CREATE 0x00
117#define DRM_TEGRA_GEM_MMAP 0x01
118#define DRM_TEGRA_SYNCPT_READ 0x02
119#define DRM_TEGRA_SYNCPT_INCR 0x03
120#define DRM_TEGRA_SYNCPT_WAIT 0x04
121#define DRM_TEGRA_OPEN_CHANNEL 0x05
122#define DRM_TEGRA_CLOSE_CHANNEL 0x06
123#define DRM_TEGRA_GET_SYNCPT 0x07
124#define DRM_TEGRA_SUBMIT 0x08
125
126#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
127#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
128#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
129#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
130#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
131#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
132#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
133#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
134#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
135
136#endif