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gerrit-public.fairphone.software / kernel / msm-4.9 / d46a3ad679c7232b72b21c6d0ca047dc4a68063f / . / drivers / scsi / megaraid / megaraid_sas_fusion.h
blob: 004c18e408c172fec572131c183e1f2647ac28ec [file] [log] [blame]
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]1/*
2 * Linux MegaRAID driver for SAS based RAID controllers
3 *
adam radfordae590572012-10-01 19:27:34 -0700[diff] [blame]4 * Copyright (c) 2009-2012 LSI Corporation.
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas_fusion.h
21 *
22 * Authors: LSI Corporation
23 * Manoj Jose
24 * Sumant Patro
25 *
26 * Send feedback to: <megaraidlinux@lsi.com>
27 *
28 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
29 * ATTN: Linuxraid
30 */
31
32#ifndef _MEGARAID_SAS_FUSION_H_
33#define _MEGARAID_SAS_FUSION_H_
34
35/* Fusion defines */
36#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024
37#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
38#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
39#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
40#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
41#define MEGASAS_LOAD_BALANCE_FLAG 0x1
42#define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
43#define HOST_DIAG_WRITE_ENABLE 0x80
44#define HOST_DIAG_RESET_ADAPTER 0x4
45#define MEGASAS_FUSION_MAX_RESET_TRIES 3
Sumit.Saxena@lsi.comd46a3ad2013-05-22 12:34:14 +0530[diff] [blame^]46#define MAX_MSIX_QUEUES_FUSION 128
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]47
adam radford36807e62011-10-08 18:15:06 -0700[diff] [blame]48/* Invader defines */
49#define MPI2_TYPE_CUDA 0x2
50#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
51#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
52#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
53#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
54#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
55
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]56/* T10 PI defines */
57#define MR_PROT_INFO_TYPE_CONTROLLER 0x8
58#define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
59#define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
60#define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
61#define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
62#define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
63#define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]64
Sumit.Saxena@lsi.comd46a3ad2013-05-22 12:34:14 +0530[diff] [blame^]65#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
66#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
67
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]68/*
69 * Raid context flags
70 */
71
72#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
73#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
74enum MR_RAID_FLAGS_IO_SUB_TYPE {
75 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
76 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
77};
78
79/*
80 * Request descriptor types
81 */
82#define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
83#define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
adam radford36807e62011-10-08 18:15:06 -0700[diff] [blame]84#define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]85#define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
86
87#define MEGASAS_FP_CMD_LEN 16
88#define MEGASAS_FUSION_IN_RESET 0
89
90/*
91 * Raid Context structure which describes MegaRAID specific IO Paramenters
92 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
93 */
94
95struct RAID_CONTEXT {
adam radford36807e62011-10-08 18:15:06 -0700[diff] [blame]96 u8 Type:4;
97 u8 nseg:4;
98 u8 resvd0;
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]99 u16 timeoutValue;
100 u8 regLockFlags;
101 u8 resvd1;
102 u16 VirtualDiskTgtId;
103 u64 regLockRowLBA;
104 u32 regLockLength;
105 u16 nextLMId;
106 u8 exStatus;
107 u8 status;
108 u8 RAIDFlags;
109 u8 numSGE;
110 u16 configSeqNum;
111 u8 spanArm;
112 u8 resvd2[3];
113};
114
115#define RAID_CTX_SPANARM_ARM_SHIFT (0)
116#define RAID_CTX_SPANARM_ARM_MASK (0x1f)
117
118#define RAID_CTX_SPANARM_SPAN_SHIFT (5)
119#define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
120
121/*
122 * define region lock types
123 */
124enum REGION_TYPE {
125 REGION_TYPE_UNUSED = 0,
126 REGION_TYPE_SHARED_READ = 1,
127 REGION_TYPE_SHARED_WRITE = 2,
128 REGION_TYPE_EXCLUSIVE = 3,
129};
130
131/* MPI2 defines */
132#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
133#define MPI2_WHOINIT_HOST_DRIVER (0x04)
134#define MPI2_VERSION_MAJOR (0x02)
135#define MPI2_VERSION_MINOR (0x00)
136#define MPI2_VERSION_MAJOR_MASK (0xFF00)
137#define MPI2_VERSION_MAJOR_SHIFT (8)
138#define MPI2_VERSION_MINOR_MASK (0x00FF)
139#define MPI2_VERSION_MINOR_SHIFT (0)
140#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
141 MPI2_VERSION_MINOR)
142#define MPI2_HEADER_VERSION_UNIT (0x10)
143#define MPI2_HEADER_VERSION_DEV (0x00)
144#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
145#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
146#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
147#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
148#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
149 MPI2_HEADER_VERSION_DEV)
150#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
151#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
152#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
153#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
154#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
155#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
156#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
157#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
158#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
159#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
160#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
161#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
162#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
163#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
164#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
165#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
166#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
167#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
168#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
169#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
170#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
171#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
172#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
173#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
174#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
175
176struct MPI25_IEEE_SGE_CHAIN64 {
177 u64 Address;
178 u32 Length;
179 u16 Reserved1;
180 u8 NextChainOffset;
181 u8 Flags;
182};
183
184struct MPI2_SGE_SIMPLE_UNION {
185 u32 FlagsLength;
186 union {
187 u32 Address32;
188 u64 Address64;
189 } u;
190};
191
192struct MPI2_SCSI_IO_CDB_EEDP32 {
193 u8 CDB[20]; /* 0x00 */
194 u32 PrimaryReferenceTag; /* 0x14 */
195 u16 PrimaryApplicationTag; /* 0x18 */
196 u16 PrimaryApplicationTagMask; /* 0x1A */
197 u32 TransferLength; /* 0x1C */
198};
199
200struct MPI2_SGE_CHAIN_UNION {
201 u16 Length;
202 u8 NextChainOffset;
203 u8 Flags;
204 union {
205 u32 Address32;
206 u64 Address64;
207 } u;
208};
209
210struct MPI2_IEEE_SGE_SIMPLE32 {
211 u32 Address;
212 u32 FlagsLength;
213};
214
215struct MPI2_IEEE_SGE_CHAIN32 {
216 u32 Address;
217 u32 FlagsLength;
218};
219
220struct MPI2_IEEE_SGE_SIMPLE64 {
221 u64 Address;
222 u32 Length;
223 u16 Reserved1;
224 u8 Reserved2;
225 u8 Flags;
226};
227
228struct MPI2_IEEE_SGE_CHAIN64 {
229 u64 Address;
230 u32 Length;
231 u16 Reserved1;
232 u8 Reserved2;
233 u8 Flags;
234};
235
236union MPI2_IEEE_SGE_SIMPLE_UNION {
237 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
238 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
239};
240
241union MPI2_IEEE_SGE_CHAIN_UNION {
242 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
243 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
244};
245
246union MPI2_SGE_IO_UNION {
247 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
248 struct MPI2_SGE_CHAIN_UNION MpiChain;
249 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
250 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
251};
252
253union MPI2_SCSI_IO_CDB_UNION {
254 u8 CDB32[32];
255 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
256 struct MPI2_SGE_SIMPLE_UNION SGE;
257};
258
259/*
260 * RAID SCSI IO Request Message
261 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
262 */
263struct MPI2_RAID_SCSI_IO_REQUEST {
264 u16 DevHandle; /* 0x00 */
265 u8 ChainOffset; /* 0x02 */
266 u8 Function; /* 0x03 */
267 u16 Reserved1; /* 0x04 */
268 u8 Reserved2; /* 0x06 */
269 u8 MsgFlags; /* 0x07 */
270 u8 VP_ID; /* 0x08 */
271 u8 VF_ID; /* 0x09 */
272 u16 Reserved3; /* 0x0A */
273 u32 SenseBufferLowAddress; /* 0x0C */
274 u16 SGLFlags; /* 0x10 */
275 u8 SenseBufferLength; /* 0x12 */
276 u8 Reserved4; /* 0x13 */
277 u8 SGLOffset0; /* 0x14 */
278 u8 SGLOffset1; /* 0x15 */
279 u8 SGLOffset2; /* 0x16 */
280 u8 SGLOffset3; /* 0x17 */
281 u32 SkipCount; /* 0x18 */
282 u32 DataLength; /* 0x1C */
283 u32 BidirectionalDataLength; /* 0x20 */
284 u16 IoFlags; /* 0x24 */
285 u16 EEDPFlags; /* 0x26 */
286 u32 EEDPBlockSize; /* 0x28 */
287 u32 SecondaryReferenceTag; /* 0x2C */
288 u16 SecondaryApplicationTag; /* 0x30 */
289 u16 ApplicationTagTranslationMask; /* 0x32 */
290 u8 LUN[8]; /* 0x34 */
291 u32 Control; /* 0x3C */
292 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
293 struct RAID_CONTEXT RaidContext; /* 0x60 */
294 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
295};
296
297/*
298 * MPT RAID MFA IO Descriptor.
299 */
300struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
301 u32 RequestFlags:8;
302 u32 MessageAddress1:24; /* bits 31:8*/
303 u32 MessageAddress2; /* bits 61:32 */
304};
305
306/* Default Request Descriptor */
307struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
308 u8 RequestFlags; /* 0x00 */
309 u8 MSIxIndex; /* 0x01 */
310 u16 SMID; /* 0x02 */
311 u16 LMID; /* 0x04 */
312 u16 DescriptorTypeDependent; /* 0x06 */
313};
314
315/* High Priority Request Descriptor */
316struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
317 u8 RequestFlags; /* 0x00 */
318 u8 MSIxIndex; /* 0x01 */
319 u16 SMID; /* 0x02 */
320 u16 LMID; /* 0x04 */
321 u16 Reserved1; /* 0x06 */
322};
323
324/* SCSI IO Request Descriptor */
325struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
326 u8 RequestFlags; /* 0x00 */
327 u8 MSIxIndex; /* 0x01 */
328 u16 SMID; /* 0x02 */
329 u16 LMID; /* 0x04 */
330 u16 DevHandle; /* 0x06 */
331};
332
333/* SCSI Target Request Descriptor */
334struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
335 u8 RequestFlags; /* 0x00 */
336 u8 MSIxIndex; /* 0x01 */
337 u16 SMID; /* 0x02 */
338 u16 LMID; /* 0x04 */
339 u16 IoIndex; /* 0x06 */
340};
341
342/* RAID Accelerator Request Descriptor */
343struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
344 u8 RequestFlags; /* 0x00 */
345 u8 MSIxIndex; /* 0x01 */
346 u16 SMID; /* 0x02 */
347 u16 LMID; /* 0x04 */
348 u16 Reserved; /* 0x06 */
349};
350
351/* union of Request Descriptors */
352union MEGASAS_REQUEST_DESCRIPTOR_UNION {
353 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
354 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
355 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
356 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
357 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
358 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
359 union {
360 struct {
361 u32 low;
362 u32 high;
363 } u;
364 u64 Words;
365 };
366};
367
368/* Default Reply Descriptor */
369struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
370 u8 ReplyFlags; /* 0x00 */
371 u8 MSIxIndex; /* 0x01 */
372 u16 DescriptorTypeDependent1; /* 0x02 */
373 u32 DescriptorTypeDependent2; /* 0x04 */
374};
375
376/* Address Reply Descriptor */
377struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
378 u8 ReplyFlags; /* 0x00 */
379 u8 MSIxIndex; /* 0x01 */
380 u16 SMID; /* 0x02 */
381 u32 ReplyFrameAddress; /* 0x04 */
382};
383
384/* SCSI IO Success Reply Descriptor */
385struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
386 u8 ReplyFlags; /* 0x00 */
387 u8 MSIxIndex; /* 0x01 */
388 u16 SMID; /* 0x02 */
389 u16 TaskTag; /* 0x04 */
390 u16 Reserved1; /* 0x06 */
391};
392
393/* TargetAssist Success Reply Descriptor */
394struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
395 u8 ReplyFlags; /* 0x00 */
396 u8 MSIxIndex; /* 0x01 */
397 u16 SMID; /* 0x02 */
398 u8 SequenceNumber; /* 0x04 */
399 u8 Reserved1; /* 0x05 */
400 u16 IoIndex; /* 0x06 */
401};
402
403/* Target Command Buffer Reply Descriptor */
404struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
405 u8 ReplyFlags; /* 0x00 */
406 u8 MSIxIndex; /* 0x01 */
407 u8 VP_ID; /* 0x02 */
408 u8 Flags; /* 0x03 */
409 u16 InitiatorDevHandle; /* 0x04 */
410 u16 IoIndex; /* 0x06 */
411};
412
413/* RAID Accelerator Success Reply Descriptor */
414struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
415 u8 ReplyFlags; /* 0x00 */
416 u8 MSIxIndex; /* 0x01 */
417 u16 SMID; /* 0x02 */
418 u32 Reserved; /* 0x04 */
419};
420
421/* union of Reply Descriptors */
422union MPI2_REPLY_DESCRIPTORS_UNION {
423 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
424 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
425 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
426 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
427 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
428 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
429 RAIDAcceleratorSuccess;
430 u64 Words;
431};
432
433/* IOCInit Request message */
434struct MPI2_IOC_INIT_REQUEST {
435 u8 WhoInit; /* 0x00 */
436 u8 Reserved1; /* 0x01 */
437 u8 ChainOffset; /* 0x02 */
438 u8 Function; /* 0x03 */
439 u16 Reserved2; /* 0x04 */
440 u8 Reserved3; /* 0x06 */
441 u8 MsgFlags; /* 0x07 */
442 u8 VP_ID; /* 0x08 */
443 u8 VF_ID; /* 0x09 */
444 u16 Reserved4; /* 0x0A */
445 u16 MsgVersion; /* 0x0C */
446 u16 HeaderVersion; /* 0x0E */
447 u32 Reserved5; /* 0x10 */
448 u16 Reserved6; /* 0x14 */
449 u8 Reserved7; /* 0x16 */
450 u8 HostMSIxVectors; /* 0x17 */
451 u16 Reserved8; /* 0x18 */
452 u16 SystemRequestFrameSize; /* 0x1A */
453 u16 ReplyDescriptorPostQueueDepth; /* 0x1C */
454 u16 ReplyFreeQueueDepth; /* 0x1E */
455 u32 SenseBufferAddressHigh; /* 0x20 */
456 u32 SystemReplyAddressHigh; /* 0x24 */
457 u64 SystemRequestFrameBaseAddress; /* 0x28 */
458 u64 ReplyDescriptorPostQueueAddress;/* 0x30 */
459 u64 ReplyFreeQueueAddress; /* 0x38 */
460 u64 TimeStamp; /* 0x40 */
461};
462
463/* mrpriv defines */
464#define MR_PD_INVALID 0xFFFF
465#define MAX_SPAN_DEPTH 8
466#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
467#define MAX_ROW_SIZE 32
468#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
469#define MAX_LOGICAL_DRIVES 64
470#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
471#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
472#define MAX_ARRAYS 128
473#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
474#define MAX_PHYSICAL_DEVICES 256
475#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
476#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
477
478struct MR_DEV_HANDLE_INFO {
479 u16 curDevHdl;
480 u8 validHandles;
481 u8 reserved;
482 u16 devHandle[2];
483};
484
485struct MR_ARRAY_INFO {
486 u16 pd[MAX_RAIDMAP_ROW_SIZE];
487};
488
489struct MR_QUAD_ELEMENT {
490 u64 logStart;
491 u64 logEnd;
492 u64 offsetInSpan;
493 u32 diff;
494 u32 reserved1;
495};
496
497struct MR_SPAN_INFO {
498 u32 noElements;
499 u32 reserved1;
500 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
501};
502
503struct MR_LD_SPAN {
504 u64 startBlk;
505 u64 numBlks;
506 u16 arrayRef;
507 u8 reserved[6];
508};
509
510struct MR_SPAN_BLOCK_INFO {
511 u64 num_rows;
512 struct MR_LD_SPAN span;
513 struct MR_SPAN_INFO block_span_info;
514};
515
516struct MR_LD_RAID {
517 struct {
518 u32 fpCapable:1;
519 u32 reserved5:3;
520 u32 ldPiMode:4;
521 u32 pdPiMode:4;
522 u32 encryptionType:8;
523 u32 fpWriteCapable:1;
524 u32 fpReadCapable:1;
525 u32 fpWriteAcrossStripe:1;
526 u32 fpReadAcrossStripe:1;
527 u32 reserved4:8;
528 } capability;
529 u32 reserved6;
530 u64 size;
531 u8 spanDepth;
532 u8 level;
533 u8 stripeShift;
534 u8 rowSize;
535 u8 rowDataSize;
536 u8 writeMode;
537 u8 PRL;
538 u8 SRL;
539 u16 targetId;
540 u8 ldState;
541 u8 regTypeReqOnWrite;
542 u8 modFactor;
adam radford36807e62011-10-08 18:15:06 -0700[diff] [blame]543 u8 regTypeReqOnRead;
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]544 u16 seqNum;
545
546 struct {
547 u32 ldSyncRequired:1;
548 u32 reserved:31;
549 } flags;
550
551 u8 reserved3[0x5C];
552};
553
554struct MR_LD_SPAN_MAP {
555 struct MR_LD_RAID ldRaid;
556 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
557 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
558};
559
560struct MR_FW_RAID_MAP {
561 u32 totalSize;
562 union {
563 struct {
564 u32 maxLd;
565 u32 maxSpanDepth;
566 u32 maxRowSize;
567 u32 maxPdCount;
568 u32 maxArrays;
569 } validationInfo;
570 u32 version[5];
571 u32 reserved1[5];
572 };
573
574 u32 ldCount;
575 u32 Reserved1;
576 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
577 MAX_RAIDMAP_VIEWS];
578 u8 fpPdIoTimeoutSec;
579 u8 reserved2[7];
580 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
581 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
582 struct MR_LD_SPAN_MAP ldSpanMap[1];
583};
584
585struct IO_REQUEST_INFO {
586 u64 ldStartBlock;
587 u32 numBlocks;
588 u16 ldTgtId;
589 u8 isRead;
590 u16 devHandle;
591 u64 pdBlock;
592 u8 fpOkForIo;
593};
594
595struct MR_LD_TARGET_SYNC {
596 u8 targetId;
597 u8 reserved;
598 u16 seqNum;
599};
600
601#define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
602#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
603#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
604#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
605#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
606#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
607#define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
608
609struct megasas_register_set;
610struct megasas_instance;
611
612union desc_word {
613 u64 word;
614 struct {
615 u32 low;
616 u32 high;
617 } u;
618};
619
620struct megasas_cmd_fusion {
621 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
622 dma_addr_t io_request_phys_addr;
623
624 union MPI2_SGE_IO_UNION *sg_frame;
625 dma_addr_t sg_frame_phys_addr;
626
627 u8 *sense;
628 dma_addr_t sense_phys_addr;
629
630 struct list_head list;
631 struct scsi_cmnd *scmd;
632 struct megasas_instance *instance;
633
634 u8 retry_for_fw_reset;
635 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
636
637 /*
638 * Context for a MFI frame.
639 * Used to get the mfi cmd from list when a MFI cmd is completed
640 */
641 u32 sync_cmd_idx;
642 u32 index;
643 u8 flags;
644};
645
646struct LD_LOAD_BALANCE_INFO {
647 u8 loadBalanceFlag;
648 u8 reserved1;
649 u16 raid1DevHandle[2];
650 atomic_t scsi_pending_cmds[2];
651 u64 last_accessed_block[2];
652};
653
654struct MR_FW_RAID_MAP_ALL {
655 struct MR_FW_RAID_MAP raidMap;
656 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
657} __attribute__ ((packed));
658
659struct fusion_context {
660 struct megasas_cmd_fusion **cmd_list;
661 struct list_head cmd_pool;
662
663 spinlock_t cmd_pool_lock;
664
665 dma_addr_t req_frames_desc_phys;
666 u8 *req_frames_desc;
667
668 struct dma_pool *io_request_frames_pool;
669 dma_addr_t io_request_frames_phys;
670 u8 *io_request_frames;
671
672 struct dma_pool *sg_dma_pool;
673 struct dma_pool *sense_dma_pool;
674
675 dma_addr_t reply_frames_desc_phys;
676 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc;
677 struct dma_pool *reply_frames_desc_pool;
678
adam radfordc8e858f2011-10-08 18:15:13 -0700[diff] [blame]679 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
adam radford9c915a82010-12-21 13:34:31 -0800[diff] [blame]680
681 u32 reply_q_depth;
682 u32 request_alloc_sz;
683 u32 reply_alloc_sz;
684 u32 io_frames_alloc_sz;
685
686 u16 max_sge_in_main_msg;
687 u16 max_sge_in_chain;
688
689 u8 chain_offset_io_request;
690 u8 chain_offset_mfi_pthru;
691
692 struct MR_FW_RAID_MAP_ALL *ld_map[2];
693 dma_addr_t ld_map_phys[2];
694
695 u32 map_sz;
696 u8 fast_path_io;
697 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
698};
699
700union desc_value {
701 u64 word;
702 struct {
703 u32 low;
704 u32 high;
705 } u;
706};
707
708#endif /* _MEGARAID_SAS_FUSION_H_ */