blob: 213317392d9b1c4066fca07e8cb7bfd1714d9ea9 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Tony Lindgrendbdf9ced2005-07-10 19:58:11 +01002 * linux/arch/arm/mach-omap1/board-perseus2.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Modified from board-generic.c
5 *
6 * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
7 * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/delay.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/partitions.h>
20
21#include <asm/hardware.h>
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/flash.h>
25#include <asm/mach/map.h>
26
27#include <asm/arch/gpio.h>
28#include <asm/arch/mux.h>
29#include <asm/arch/fpga.h>
Tony Lindgrend48af152005-07-10 19:58:17 +010030#include <asm/arch/common.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
32static struct resource smc91x_resources[] = {
33 [0] = {
34 .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
35 .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
36 .flags = IORESOURCE_MEM,
37 },
38 [1] = {
39 .start = INT_730_MPU_EXT_NIRQ,
40 .end = 0,
41 .flags = IORESOURCE_IRQ,
42 },
43};
44
45static int __initdata p2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 0};
46
47static struct mtd_partition p2_partitions[] = {
48 /* bootloader (U-Boot, etc) in first sector */
49 {
50 .name = "bootloader",
51 .offset = 0,
52 .size = SZ_128K,
53 .mask_flags = MTD_WRITEABLE, /* force read-only */
54 },
55 /* bootloader params in the next sector */
56 {
57 .name = "params",
58 .offset = MTDPART_OFS_APPEND,
59 .size = SZ_128K,
60 .mask_flags = 0,
61 },
62 /* kernel */
63 {
64 .name = "kernel",
65 .offset = MTDPART_OFS_APPEND,
66 .size = SZ_2M,
67 .mask_flags = 0
68 },
69 /* rest of flash is a file system */
70 {
71 .name = "rootfs",
72 .offset = MTDPART_OFS_APPEND,
73 .size = MTDPART_SIZ_FULL,
74 .mask_flags = 0
75 },
76};
77
78static struct flash_platform_data p2_flash_data = {
79 .map_name = "cfi_probe",
80 .width = 2,
81 .parts = p2_partitions,
82 .nr_parts = ARRAY_SIZE(p2_partitions),
83};
84
85static struct resource p2_flash_resource = {
86 .start = OMAP_FLASH_0_START,
87 .end = OMAP_FLASH_0_START + OMAP_FLASH_0_SIZE - 1,
88 .flags = IORESOURCE_MEM,
89};
90
91static struct platform_device p2_flash_device = {
92 .name = "omapflash",
93 .id = 0,
94 .dev = {
95 .platform_data = &p2_flash_data,
96 },
97 .num_resources = 1,
98 .resource = &p2_flash_resource,
99};
100
101static struct platform_device smc91x_device = {
102 .name = "smc91x",
103 .id = 0,
104 .num_resources = ARRAY_SIZE(smc91x_resources),
105 .resource = smc91x_resources,
106};
107
108static struct platform_device *devices[] __initdata = {
109 &p2_flash_device,
110 &smc91x_device,
111};
112
113static void __init omap_perseus2_init(void)
114{
115 (void) platform_add_devices(devices, ARRAY_SIZE(devices));
116}
117
118static void __init perseus2_init_smc91x(void)
119{
120 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
121 mdelay(50);
122 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
123 H2P2_DBG_FPGA_LAN_RESET);
124 mdelay(50);
125}
126
127void omap_perseus2_init_irq(void)
128{
129 omap_init_irq();
130 omap_gpio_init();
131 perseus2_init_smc91x();
132}
133
134/* Only FPGA needs to be mapped here. All others are done with ioremap */
135static struct map_desc omap_perseus2_io_desc[] __initdata = {
136 {H2P2_DBG_FPGA_BASE, H2P2_DBG_FPGA_START, H2P2_DBG_FPGA_SIZE,
137 MT_DEVICE},
138};
139
140static void __init omap_perseus2_map_io(void)
141{
Tony Lindgrend48af152005-07-10 19:58:17 +0100142 omap_map_common_io();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 iotable_init(omap_perseus2_io_desc,
144 ARRAY_SIZE(omap_perseus2_io_desc));
145
146 /* Early, board-dependent init */
147
148 /*
149 * Hold GSM Reset until needed
150 */
151 omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
152
153 /*
154 * UARTs -> done automagically by 8250 driver
155 */
156
157 /*
158 * CSx timings, GPIO Mux ... setup
159 */
160
161 /* Flash: CS0 timings setup */
162 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
163 omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
164
165 /*
166 * Ethernet support trough the debug board
167 * CS1 timings setup
168 */
169 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
170 omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
171
172 /*
173 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
174 * It is used as the Ethernet controller interrupt
175 */
176 omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
177 omap_serial_init(p2_serial_ports);
178}
179
180MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
Russell Kinge9dea0c2005-07-03 17:38:58 +0100181 /* Maintainer: Kevin Hilman <kjh@hilman.org> */
182 .phys_ram = 0x10000000,
183 .phys_io = 0xfff00000,
184 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
185 .boot_params = 0x10000100,
186 .map_io = omap_perseus2_map_io,
187 .init_irq = omap_perseus2_init_irq,
188 .init_machine = omap_perseus2_init,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 .timer = &omap_timer,
190MACHINE_END