Vijayanand Jitta | d48c408 | 2017-06-07 15:07:51 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/msm/msm-bus-ids.h> |
| 15 | |
| 16 | &soc { |
| 17 | kgsl_smmu: arm,smmu-kgsl@5040000 { |
| 18 | status = "ok"; |
| 19 | compatible = "qcom,smmu-v2"; |
| 20 | reg = <0x5040000 0x10000>; |
| 21 | #iommu-cells = <1>; |
| 22 | qcom,dynamic; |
| 23 | qcom,use-3-lvl-tables; |
| 24 | #global-interrupts = <2>; |
| 25 | qcom,regulator-names = "vdd"; |
| 26 | vdd-supply = <&gpu_cx_gdsc>; |
| 27 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
| 28 | <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |
| 29 | <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, |
| 30 | <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, |
| 31 | <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, |
| 32 | <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, |
| 33 | <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, |
| 34 | <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, |
| 35 | <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, |
| 36 | <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; |
| 37 | clock-names = "gcc_ddrss_gpu_axi_clk", |
| 38 | "gcc_gpu_memnoc_gfx_clk", |
| 39 | "gpu_cc_ahb_clk", |
| 40 | "gpu_cc_cx_gmu_clk"; |
| 41 | clocks = <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 42 | <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| 43 | <&clock_gpucc GPU_CC_AHB_CLK>, |
| 44 | <&clock_gpucc GPU_CC_CX_GMU_CLK>; |
| 45 | attach-impl-defs = |
| 46 | <0x6000 0x2378>, |
| 47 | <0x6060 0x1055>, |
| 48 | <0x678c 0x8>, |
| 49 | <0x6794 0x28>, |
| 50 | <0x6800 0x6>, |
| 51 | <0x6900 0x3ff>, |
| 52 | <0x6924 0x204>, |
| 53 | <0x6928 0x11000>, |
| 54 | <0x6930 0x800>, |
| 55 | <0x6960 0xffffffff>, |
| 56 | <0x6b64 0x1a5551>, |
| 57 | <0x6b68 0x9a82a382>; |
| 58 | }; |
| 59 | |
| 60 | apps_smmu: apps-smmu@0x15000000 { |
| 61 | compatible = "qcom,qsmmu-v500"; |
| 62 | reg = <0x15000000 0x80000>, |
| 63 | <0x150c2000 0x18>; |
| 64 | reg-names = "base", "tcu-base"; |
| 65 | #iommu-cells = <2>; |
| 66 | qcom,skip-init; |
| 67 | qcom,use-3-lvl-tables; |
| 68 | #global-interrupts = <1>; |
| 69 | #size-cells = <1>; |
| 70 | #address-cells = <1>; |
| 71 | ranges; |
| 72 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| 78 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| 79 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| 81 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 82 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 84 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 85 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 86 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 87 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 88 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 89 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 90 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 91 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 93 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 94 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 95 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 96 | <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| 97 | <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| 98 | <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| 99 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
| 100 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| 102 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| 103 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| 104 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| 107 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| 108 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| 109 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
| 110 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| 111 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
| 112 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
| 113 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| 114 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| 115 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| 116 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| 117 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| 118 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
| 119 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
| 120 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
| 121 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
| 122 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| 123 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| 124 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| 125 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| 126 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
| 127 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| 128 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| 129 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| 130 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
| 131 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
| 132 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
| 133 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
| 134 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
| 135 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
| 136 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
| 137 | qcom,msm-bus,name = "apps_smmu"; |
| 138 | qcom,msm-bus,num-cases = <2>; |
| 139 | qcom,msm-bus,active-only; |
| 140 | qcom,msm-bus,num-paths = <1>; |
| 141 | qcom,msm-bus,vectors-KBps = |
| 142 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 143 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 144 | <0 0>, |
| 145 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 146 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 147 | <0 1000>; |
| 148 | |
| 149 | anoc_1_tbu: anoc_1_tbu@0x150c5000 { |
| 150 | compatible = "qcom,qsmmuv500-tbu"; |
| 151 | reg = <0x150c5000 0x1000>, |
| 152 | <0x150c2200 0x8>; |
| 153 | reg-names = "base", "status-reg"; |
| 154 | qcom,stream-id-range = <0x0 0x400>; |
| 155 | qcom,regulator-names = "vdd"; |
| 156 | vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; |
| 157 | qcom,msm-bus,name = "apps_smmu"; |
| 158 | qcom,msm-bus,num-cases = <2>; |
| 159 | qcom,msm-bus,active-only; |
| 160 | qcom,msm-bus,num-paths = <1>; |
| 161 | qcom,msm-bus,vectors-KBps = |
| 162 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 163 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 164 | <0 0>, |
| 165 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 166 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 167 | <0 1000>; |
| 168 | }; |
| 169 | |
| 170 | anoc_2_tbu: anoc_2_tbu@0x150c9000 { |
| 171 | compatible = "qcom,qsmmuv500-tbu"; |
| 172 | reg = <0x150c9000 0x1000>, |
| 173 | <0x150c2208 0x8>; |
| 174 | reg-names = "base", "status-reg"; |
| 175 | qcom,stream-id-range = <0x400 0x400>; |
| 176 | qcom,regulator-names = "vdd"; |
| 177 | vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; |
| 178 | qcom,msm-bus,name = "apps_smmu"; |
| 179 | qcom,msm-bus,num-cases = <2>; |
| 180 | qcom,msm-bus,active-only; |
| 181 | qcom,msm-bus,num-paths = <1>; |
| 182 | qcom,msm-bus,vectors-KBps = |
| 183 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 184 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 185 | <0 0>, |
| 186 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 187 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 188 | <0 1000>; |
| 189 | }; |
| 190 | |
| 191 | mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 { |
| 192 | compatible = "qcom,qsmmuv500-tbu"; |
| 193 | reg = <0x150cd000 0x1000>, |
| 194 | <0x150c2210 0x8>; |
| 195 | reg-names = "base", "status-reg"; |
| 196 | qcom,stream-id-range = <0x800 0x400>; |
| 197 | qcom,regulator-names = "vdd"; |
| 198 | vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; |
| 199 | qcom,msm-bus,name = "mnoc_hf_0_tbu"; |
| 200 | qcom,msm-bus,num-cases = <2>; |
| 201 | qcom,msm-bus,active-only; |
| 202 | qcom,msm-bus,num-paths = <1>; |
| 203 | qcom,msm-bus,vectors-KBps = |
| 204 | <MSM_BUS_MASTER_MDP_PORT0>, |
| 205 | <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>, |
| 206 | <0 0>, |
| 207 | <MSM_BUS_MASTER_MDP_PORT0>, |
| 208 | <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>, |
| 209 | <0 1000>; |
| 210 | }; |
| 211 | |
| 212 | mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x150d1000 { |
| 213 | compatible = "qcom,qsmmuv500-tbu"; |
| 214 | reg = <0x150d1000 0x1000>, |
| 215 | <0x150c2218 0x8>; |
| 216 | reg-names = "base", "status-reg"; |
| 217 | qcom,stream-id-range = <0xc00 0x400>; |
| 218 | qcom,regulator-names = "vdd"; |
| 219 | vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; |
| 220 | qcom,msm-bus,name = "mnoc_hf_1_tbu"; |
| 221 | qcom,msm-bus,num-cases = <2>; |
| 222 | qcom,msm-bus,active-only; |
| 223 | qcom,msm-bus,num-paths = <1>; |
| 224 | qcom,msm-bus,vectors-KBps = |
| 225 | <MSM_BUS_MASTER_MDP_PORT0>, |
| 226 | <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>, |
| 227 | <0 0>, |
| 228 | <MSM_BUS_MASTER_MDP_PORT0>, |
| 229 | <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>, |
| 230 | <0 1000>; |
| 231 | }; |
| 232 | |
| 233 | mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d5000 { |
| 234 | compatible = "qcom,qsmmuv500-tbu"; |
| 235 | reg = <0x150d5000 0x1000>, |
| 236 | <0x150c2220 0x8>; |
| 237 | reg-names = "base", "status-reg"; |
| 238 | qcom,stream-id-range = <0x1000 0x400>; |
| 239 | qcom,regulator-names = "vdd"; |
| 240 | vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; |
| 241 | qcom,msm-bus,name = "mnoc_sf_0_tbu"; |
| 242 | qcom,msm-bus,num-cases = <2>; |
| 243 | qcom,msm-bus,active-only; |
| 244 | qcom,msm-bus,num-paths = <1>; |
| 245 | qcom,msm-bus,vectors-KBps = |
| 246 | <MSM_BUS_MASTER_CAMNOC_SF>, |
| 247 | <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>, |
| 248 | <0 0>, |
| 249 | <MSM_BUS_MASTER_CAMNOC_SF>, |
| 250 | <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>, |
| 251 | <0 1000>; |
| 252 | }; |
| 253 | |
| 254 | compute_dsp_tbu: compute_dsp_tbu@0x150d9000 { |
| 255 | compatible = "qcom,qsmmuv500-tbu"; |
| 256 | reg = <0x150d9000 0x1000>, |
| 257 | <0x150c2228 0x8>; |
| 258 | reg-names = "base", "status-reg"; |
| 259 | qcom,stream-id-range = <0x1400 0x400>; |
| 260 | /* No GDSC */ |
| 261 | qcom,msm-bus,name = "apps_smmu"; |
| 262 | qcom,msm-bus,num-cases = <2>; |
| 263 | qcom,msm-bus,active-only; |
| 264 | qcom,msm-bus,num-paths = <1>; |
| 265 | qcom,msm-bus,vectors-KBps = |
| 266 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 267 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 268 | <0 0>, |
| 269 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 270 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 271 | <0 1000>; |
| 272 | }; |
| 273 | |
| 274 | adsp_tbu: adsp_tbu@0x150dd000 { |
| 275 | compatible = "qcom,qsmmuv500-tbu"; |
| 276 | reg = <0x150dd000 0x1000>, |
| 277 | <0x150c2230 0x8>; |
| 278 | reg-names = "base", "status-reg"; |
| 279 | qcom,stream-id-range = <0x1800 0x400>; |
| 280 | qcom,regulator-names = "vdd"; |
| 281 | vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; |
| 282 | qcom,msm-bus,name = "apps_smmu"; |
| 283 | qcom,msm-bus,num-cases = <2>; |
| 284 | qcom,msm-bus,active-only; |
| 285 | qcom,msm-bus,num-paths = <1>; |
| 286 | qcom,msm-bus,vectors-KBps = |
| 287 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 288 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 289 | <0 0>, |
| 290 | <MSM_BUS_MASTER_GNOC_SNOC>, |
| 291 | <MSM_BUS_SLAVE_IMEM_CFG>, |
| 292 | <0 1000>; |
| 293 | }; |
| 294 | |
| 295 | }; |
| 296 | |
| 297 | kgsl_iommu_test_device { |
| 298 | compatible = "iommu-debug-test"; |
| 299 | /* |
| 300 | * 0x7 isn't a valid sid, but should pass the sid sanity check. |
| 301 | * We just need _something_ here to get this node recognized by |
| 302 | * the SMMU driver. Our test uses ATOS, which doesn't use SIDs |
| 303 | * anyways, so using a dummy value is ok. |
| 304 | */ |
| 305 | iommus = <&kgsl_smmu 0x7>; |
| 306 | }; |
| 307 | |
| 308 | apps_iommu_test_device { |
| 309 | compatible = "iommu-debug-test"; |
| 310 | /* |
| 311 | * This SID belongs to QUP1-GSI. We can't use a fake SID for |
| 312 | * the apps_smmu device. |
| 313 | */ |
| 314 | iommus = <&apps_smmu 0x16 0x0>; |
| 315 | }; |
| 316 | }; |