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gerrit-public.fairphone.software / kernel / msm-4.9 / d48fe60e06f404acf1acb346a4bf2d7b0e1d4d86 / . / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
blob: 7a571efbdc1cda144bccd8f308c4125d202d235c [file] [log] [blame]
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
45static int rtl8xxxu_debug;
46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57
58module_param_named(debug, rtl8xxxu_debug, int, 0600);
59MODULE_PARM_DESC(debug, "Set debug mask");
60module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
61MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
62
63#define USB_VENDOR_ID_REALTEK 0x0bda
64/* Minimum IEEE80211_MAX_FRAME_LEN */
65#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
66#define RTL8XXXU_RX_URBS 32
67#define RTL8XXXU_RX_URB_PENDING_WATER 8
68#define RTL8XXXU_TX_URBS 64
69#define RTL8XXXU_TX_URB_LOW_WATER 25
70#define RTL8XXXU_TX_URB_HIGH_WATER 32
71
72static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
73 struct rtl8xxxu_rx_urb *rx_urb);
74
75static struct ieee80211_rate rtl8xxxu_rates[] = {
76 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
77 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
78 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
79 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
80 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
81 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
82 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
83 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
84 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
85 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
86 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
87 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
88};
89
90static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
91 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
92 .hw_value = 1, .max_power = 30 },
93 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
94 .hw_value = 2, .max_power = 30 },
95 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
96 .hw_value = 3, .max_power = 30 },
97 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
98 .hw_value = 4, .max_power = 30 },
99 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
100 .hw_value = 5, .max_power = 30 },
101 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
102 .hw_value = 6, .max_power = 30 },
103 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
104 .hw_value = 7, .max_power = 30 },
105 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
106 .hw_value = 8, .max_power = 30 },
107 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
108 .hw_value = 9, .max_power = 30 },
109 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
110 .hw_value = 10, .max_power = 30 },
111 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
112 .hw_value = 11, .max_power = 30 },
113 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
114 .hw_value = 12, .max_power = 30 },
115 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
116 .hw_value = 13, .max_power = 30 },
117 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
118 .hw_value = 14, .max_power = 30 }
119};
120
121static struct ieee80211_supported_band rtl8xxxu_supported_band = {
122 .channels = rtl8xxxu_channels_2g,
123 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
124 .bitrates = rtl8xxxu_rates,
125 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
126};
127
128static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
129 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
130 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
131 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
132 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
133 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
134 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
135 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
136 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
137 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
138 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
139 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
140 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
141 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
142 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
143 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
144 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
145 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
146 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
147 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
148 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
149 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
150 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
151};
152
153static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
154 {0x800, 0x80040000}, {0x804, 0x00000003},
155 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
156 {0x810, 0x10001331}, {0x814, 0x020c3d10},
157 {0x818, 0x02200385}, {0x81c, 0x00000000},
158 {0x820, 0x01000100}, {0x824, 0x00390004},
159 {0x828, 0x00000000}, {0x82c, 0x00000000},
160 {0x830, 0x00000000}, {0x834, 0x00000000},
161 {0x838, 0x00000000}, {0x83c, 0x00000000},
162 {0x840, 0x00010000}, {0x844, 0x00000000},
163 {0x848, 0x00000000}, {0x84c, 0x00000000},
164 {0x850, 0x00000000}, {0x854, 0x00000000},
165 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
166 {0x860, 0x66f60110}, {0x864, 0x061f0130},
167 {0x868, 0x00000000}, {0x86c, 0x32323200},
168 {0x870, 0x07000760}, {0x874, 0x22004000},
169 {0x878, 0x00000808}, {0x87c, 0x00000000},
170 {0x880, 0xc0083070}, {0x884, 0x000004d5},
171 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
172 {0x890, 0x00000800}, {0x894, 0xfffffffe},
173 {0x898, 0x40302010}, {0x89c, 0x00706050},
174 {0x900, 0x00000000}, {0x904, 0x00000023},
175 {0x908, 0x00000000}, {0x90c, 0x81121111},
176 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
177 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
178 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
179 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
180 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
181 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
182 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
183 {0xa78, 0x00000900},
184 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
185 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
186 {0xc10, 0x08800000}, {0xc14, 0x40000100},
187 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
188 {0xc20, 0x00000000}, {0xc24, 0x00000000},
189 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
190 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
191 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
192 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
193 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
194 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
195 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
196 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
197 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
198 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
199 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
200 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
201 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
202 {0xc90, 0x00121820}, {0xc94, 0x00000000},
203 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
204 {0xca0, 0x00000000}, {0xca4, 0x00000080},
205 {0xca8, 0x00000000}, {0xcac, 0x00000000},
206 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
207 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
208 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
209 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
210 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
211 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
212 {0xce0, 0x00222222}, {0xce4, 0x00000000},
213 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
214 {0xd00, 0x00080740}, {0xd04, 0x00020401},
215 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
216 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
217 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
218 {0xd30, 0x00000000}, {0xd34, 0x80608000},
219 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
220 {0xd40, 0x00000000}, {0xd44, 0x00000000},
221 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
222 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
223 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
224 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
225 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
226 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
227 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
228 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
229 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
230 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
231 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
232 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
233 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
234 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
235 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
236 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
237 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
238 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
239 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
240 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
241 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
242 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
243 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
244 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
245 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
246 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
247 {0xf00, 0x00000300},
248 {0xffff, 0xffffffff},
249};
250
251static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
252 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
253 {0x800, 0x80040002}, {0x804, 0x00000003},
254 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
255 {0x810, 0x10000330}, {0x814, 0x020c3d10},
256 {0x818, 0x02200385}, {0x81c, 0x00000000},
257 {0x820, 0x01000100}, {0x824, 0x00390004},
258 {0x828, 0x01000100}, {0x82c, 0x00390004},
259 {0x830, 0x27272727}, {0x834, 0x27272727},
260 {0x838, 0x27272727}, {0x83c, 0x27272727},
261 {0x840, 0x00010000}, {0x844, 0x00010000},
262 {0x848, 0x27272727}, {0x84c, 0x27272727},
263 {0x850, 0x00000000}, {0x854, 0x00000000},
264 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
265 {0x860, 0x66e60230}, {0x864, 0x061f0130},
266 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
267 {0x870, 0x07000700}, {0x874, 0x22184000},
268 {0x878, 0x08080808}, {0x87c, 0x00000000},
269 {0x880, 0xc0083070}, {0x884, 0x000004d5},
270 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
271 {0x890, 0x00000800}, {0x894, 0xfffffffe},
272 {0x898, 0x40302010}, {0x89c, 0x00706050},
273 {0x900, 0x00000000}, {0x904, 0x00000023},
274 {0x908, 0x00000000}, {0x90c, 0x81121313},
275 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
276 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
277 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
278 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
279 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
280 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
281 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
282 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
283 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
284 {0xc10, 0x08800000}, {0xc14, 0x40000100},
285 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
286 {0xc20, 0x00000000}, {0xc24, 0x00000000},
287 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
288 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
289 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
290 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
291 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
292 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
293 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
294 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
295 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
296 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
297 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
298 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
299 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
300 {0xc90, 0x00121820}, {0xc94, 0x00000000},
301 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
302 {0xca0, 0x00000000}, {0xca4, 0x00000080},
303 {0xca8, 0x00000000}, {0xcac, 0x00000000},
304 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
305 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
306 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
307 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
308 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
309 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
310 {0xce0, 0x00222222}, {0xce4, 0x00000000},
311 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
312 {0xd00, 0x00080740}, {0xd04, 0x00020403},
313 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
314 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
315 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
316 {0xd30, 0x00000000}, {0xd34, 0x80608000},
317 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
318 {0xd40, 0x00000000}, {0xd44, 0x00000000},
319 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
320 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
321 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
322 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
323 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
324 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
325 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
326 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
327 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
328 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
329 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
330 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
331 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
332 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
333 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
334 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
335 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
336 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
337 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
338 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
339 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
340 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
341 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
342 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
343 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
344 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
345 {0xf00, 0x00000300},
346 {0xffff, 0xffffffff},
347};
348
349static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
350 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
351 {0x040, 0x000c0004}, {0x800, 0x80040000},
352 {0x804, 0x00000001}, {0x808, 0x0000fc00},
353 {0x80c, 0x0000000a}, {0x810, 0x10005388},
354 {0x814, 0x020c3d10}, {0x818, 0x02200385},
355 {0x81c, 0x00000000}, {0x820, 0x01000100},
356 {0x824, 0x00390204}, {0x828, 0x00000000},
357 {0x82c, 0x00000000}, {0x830, 0x00000000},
358 {0x834, 0x00000000}, {0x838, 0x00000000},
359 {0x83c, 0x00000000}, {0x840, 0x00010000},
360 {0x844, 0x00000000}, {0x848, 0x00000000},
361 {0x84c, 0x00000000}, {0x850, 0x00000000},
362 {0x854, 0x00000000}, {0x858, 0x569a569a},
363 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
364 {0x864, 0x061f0130}, {0x868, 0x00000000},
365 {0x86c, 0x20202000}, {0x870, 0x03000300},
366 {0x874, 0x22004000}, {0x878, 0x00000808},
367 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
368 {0x884, 0x000004d5}, {0x888, 0x00000000},
369 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
370 {0x894, 0xfffffffe}, {0x898, 0x40302010},
371 {0x89c, 0x00706050}, {0x900, 0x00000000},
372 {0x904, 0x00000023}, {0x908, 0x00000000},
373 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
374 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
375 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
376 {0xa14, 0x11144028}, {0xa18, 0x00881117},
377 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
378 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
379 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
380 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
381 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
382 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
383 {0xc14, 0x40000100}, {0xc18, 0x08800000},
384 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
385 {0xc24, 0x00000000}, {0xc28, 0x00000000},
386 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
387 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
388 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
389 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
390 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
391 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
392 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
393 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
394 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
395 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
396 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
397 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
398 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
399 {0xc94, 0x00000000}, {0xc98, 0x00121820},
400 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
401 {0xca4, 0x00000080}, {0xca8, 0x00000000},
402 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
403 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
404 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
405 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
406 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
407 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
408 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
409 {0xce4, 0x00000000}, {0xce8, 0x37644302},
410 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
411 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
412 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
413 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
414 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
415 {0xd34, 0x80608000}, {0xd38, 0x00000000},
416 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
417 {0xd44, 0x00000000}, {0xd48, 0x00000000},
418 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
419 {0xd54, 0x00000000}, {0xd58, 0x00000000},
420 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
421 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
422 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
423 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
424 {0xe00, 0x24242424}, {0xe04, 0x24242424},
425 {0xe08, 0x03902024}, {0xe10, 0x24242424},
426 {0xe14, 0x24242424}, {0xe18, 0x24242424},
427 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
428 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
429 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
430 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
431 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
432 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
433 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
434 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
435 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
436 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
437 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
438 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
439 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
440 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
441 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
442 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
443 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
444 {0xf00, 0x00000300},
445 {0xffff, 0xffffffff},
446};
447
448static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
449 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
450 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
451 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
452 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
453 {0xc78, 0x78080001}, {0xc78, 0x77090001},
454 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
455 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
456 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
457 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
458 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
459 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
460 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
461 {0xc78, 0x68180001}, {0xc78, 0x67190001},
462 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
463 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
464 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
465 {0xc78, 0x60200001}, {0xc78, 0x49210001},
466 {0xc78, 0x48220001}, {0xc78, 0x47230001},
467 {0xc78, 0x46240001}, {0xc78, 0x45250001},
468 {0xc78, 0x44260001}, {0xc78, 0x43270001},
469 {0xc78, 0x42280001}, {0xc78, 0x41290001},
470 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
471 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
472 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
473 {0xc78, 0x21300001}, {0xc78, 0x20310001},
474 {0xc78, 0x06320001}, {0xc78, 0x05330001},
475 {0xc78, 0x04340001}, {0xc78, 0x03350001},
476 {0xc78, 0x02360001}, {0xc78, 0x01370001},
477 {0xc78, 0x00380001}, {0xc78, 0x00390001},
478 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
479 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
480 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
481 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
482 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
483 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
484 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
485 {0xc78, 0x78480001}, {0xc78, 0x77490001},
486 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
487 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
488 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
489 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
490 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
491 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
492 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
493 {0xc78, 0x68580001}, {0xc78, 0x67590001},
494 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
495 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
496 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
497 {0xc78, 0x60600001}, {0xc78, 0x49610001},
498 {0xc78, 0x48620001}, {0xc78, 0x47630001},
499 {0xc78, 0x46640001}, {0xc78, 0x45650001},
500 {0xc78, 0x44660001}, {0xc78, 0x43670001},
501 {0xc78, 0x42680001}, {0xc78, 0x41690001},
502 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
503 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
504 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
505 {0xc78, 0x21700001}, {0xc78, 0x20710001},
506 {0xc78, 0x06720001}, {0xc78, 0x05730001},
507 {0xc78, 0x04740001}, {0xc78, 0x03750001},
508 {0xc78, 0x02760001}, {0xc78, 0x01770001},
509 {0xc78, 0x00780001}, {0xc78, 0x00790001},
510 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
511 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
512 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
513 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
514 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
515 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
516 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
517 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
518 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
519 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
520 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
521 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
522 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
523 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
524 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
525 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
526 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
527 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
528 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
529 {0xffff, 0xffffffff}
530};
531
532static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
533 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
534 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
535 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
536 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
537 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
538 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
539 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
540 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
541 {0xc78, 0x73100001}, {0xc78, 0x72110001},
542 {0xc78, 0x71120001}, {0xc78, 0x70130001},
543 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
544 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
545 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
546 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
547 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
548 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
549 {0xc78, 0x63200001}, {0xc78, 0x62210001},
550 {0xc78, 0x61220001}, {0xc78, 0x60230001},
551 {0xc78, 0x46240001}, {0xc78, 0x45250001},
552 {0xc78, 0x44260001}, {0xc78, 0x43270001},
553 {0xc78, 0x42280001}, {0xc78, 0x41290001},
554 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
555 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
556 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
557 {0xc78, 0x21300001}, {0xc78, 0x20310001},
558 {0xc78, 0x06320001}, {0xc78, 0x05330001},
559 {0xc78, 0x04340001}, {0xc78, 0x03350001},
560 {0xc78, 0x02360001}, {0xc78, 0x01370001},
561 {0xc78, 0x00380001}, {0xc78, 0x00390001},
562 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
563 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
564 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
565 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
566 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
567 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
568 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
569 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
570 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
571 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
572 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
573 {0xc78, 0x73500001}, {0xc78, 0x72510001},
574 {0xc78, 0x71520001}, {0xc78, 0x70530001},
575 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
576 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
577 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
578 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
579 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
580 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
581 {0xc78, 0x63600001}, {0xc78, 0x62610001},
582 {0xc78, 0x61620001}, {0xc78, 0x60630001},
583 {0xc78, 0x46640001}, {0xc78, 0x45650001},
584 {0xc78, 0x44660001}, {0xc78, 0x43670001},
585 {0xc78, 0x42680001}, {0xc78, 0x41690001},
586 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
587 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
588 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
589 {0xc78, 0x21700001}, {0xc78, 0x20710001},
590 {0xc78, 0x06720001}, {0xc78, 0x05730001},
591 {0xc78, 0x04740001}, {0xc78, 0x03750001},
592 {0xc78, 0x02760001}, {0xc78, 0x01770001},
593 {0xc78, 0x00780001}, {0xc78, 0x00790001},
594 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
595 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
596 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
597 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
598 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
599 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
600 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
601 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
602 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
603 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
604 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
605 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
606 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
607 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
608 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
609 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
610 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
611 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
612 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
613 {0xffff, 0xffffffff}
614};
615
616static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
617 {0x00, 0x00030159}, {0x01, 0x00031284},
618 {0x02, 0x00098000}, {0x03, 0x00039c63},
619 {0x04, 0x000210e7}, {0x09, 0x0002044f},
620 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
621 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
622 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
623 {0x19, 0x00000000}, {0x1a, 0x00030355},
624 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
625 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
626 {0x1f, 0x00000000}, {0x20, 0x0000b614},
627 {0x21, 0x0006c000}, {0x22, 0x00000000},
628 {0x23, 0x00001558}, {0x24, 0x00000060},
629 {0x25, 0x00000483}, {0x26, 0x0004f000},
630 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
631 {0x29, 0x00004783}, {0x2a, 0x00000001},
632 {0x2b, 0x00021334}, {0x2a, 0x00000000},
633 {0x2b, 0x00000054}, {0x2a, 0x00000001},
634 {0x2b, 0x00000808}, {0x2b, 0x00053333},
635 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
636 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
637 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
638 {0x2b, 0x00000808}, {0x2b, 0x00063333},
639 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
640 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
641 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
642 {0x2b, 0x00000808}, {0x2b, 0x00073333},
643 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
644 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
645 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
646 {0x2b, 0x00000709}, {0x2b, 0x00063333},
647 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
648 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
649 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
650 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
651 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
652 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
653 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
654 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
655 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
656 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
657 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
658 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
659 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
660 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
661 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
662 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
663 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
664 {0x10, 0x0002000f}, {0x11, 0x000203f9},
665 {0x10, 0x0003000f}, {0x11, 0x000ff500},
666 {0x10, 0x00000000}, {0x11, 0x00000000},
667 {0x10, 0x0008000f}, {0x11, 0x0003f100},
668 {0x10, 0x0009000f}, {0x11, 0x00023100},
669 {0x12, 0x00032000}, {0x12, 0x00071000},
670 {0x12, 0x000b0000}, {0x12, 0x000fc000},
671 {0x13, 0x000287b3}, {0x13, 0x000244b7},
672 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
673 {0x13, 0x00018493}, {0x13, 0x0001429b},
674 {0x13, 0x00010299}, {0x13, 0x0000c29c},
675 {0x13, 0x000081a0}, {0x13, 0x000040ac},
676 {0x13, 0x00000020}, {0x14, 0x0001944c},
677 {0x14, 0x00059444}, {0x14, 0x0009944c},
678 {0x14, 0x000d9444}, {0x15, 0x0000f474},
679 {0x15, 0x0004f477}, {0x15, 0x0008f455},
680 {0x15, 0x000cf455}, {0x16, 0x00000339},
681 {0x16, 0x00040339}, {0x16, 0x00080339},
682 {0x16, 0x000c0366}, {0x00, 0x00010159},
683 {0x18, 0x0000f401}, {0xfe, 0x00000000},
684 {0xfe, 0x00000000}, {0x1f, 0x00000003},
685 {0xfe, 0x00000000}, {0xfe, 0x00000000},
686 {0x1e, 0x00000247}, {0x1f, 0x00000000},
687 {0x00, 0x00030159},
688 {0xff, 0xffffffff}
689};
690
691static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
692 {0x00, 0x00030159}, {0x01, 0x00031284},
693 {0x02, 0x00098000}, {0x03, 0x00018c63},
694 {0x04, 0x000210e7}, {0x09, 0x0002044f},
695 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
696 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
697 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
698 {0x19, 0x00000000}, {0x1a, 0x00010255},
699 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
700 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
701 {0x1f, 0x00080001}, {0x20, 0x0000b614},
702 {0x21, 0x0006c000}, {0x22, 0x00000000},
703 {0x23, 0x00001558}, {0x24, 0x00000060},
704 {0x25, 0x00000483}, {0x26, 0x0004f000},
705 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
706 {0x29, 0x00004783}, {0x2a, 0x00000001},
707 {0x2b, 0x00021334}, {0x2a, 0x00000000},
708 {0x2b, 0x00000054}, {0x2a, 0x00000001},
709 {0x2b, 0x00000808}, {0x2b, 0x00053333},
710 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
711 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
712 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
713 {0x2b, 0x00000808}, {0x2b, 0x00063333},
714 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
715 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
716 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
717 {0x2b, 0x00000808}, {0x2b, 0x00073333},
718 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
719 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
720 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
721 {0x2b, 0x00000709}, {0x2b, 0x00063333},
722 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
723 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
724 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
725 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
726 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
727 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
728 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
729 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
730 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
731 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
732 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
733 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
734 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
735 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
736 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
737 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
738 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
739 {0x10, 0x0002000f}, {0x11, 0x000203f9},
740 {0x10, 0x0003000f}, {0x11, 0x000ff500},
741 {0x10, 0x00000000}, {0x11, 0x00000000},
742 {0x10, 0x0008000f}, {0x11, 0x0003f100},
743 {0x10, 0x0009000f}, {0x11, 0x00023100},
744 {0x12, 0x00032000}, {0x12, 0x00071000},
745 {0x12, 0x000b0000}, {0x12, 0x000fc000},
746 {0x13, 0x000287b3}, {0x13, 0x000244b7},
747 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
748 {0x13, 0x00018493}, {0x13, 0x0001429b},
749 {0x13, 0x00010299}, {0x13, 0x0000c29c},
750 {0x13, 0x000081a0}, {0x13, 0x000040ac},
751 {0x13, 0x00000020}, {0x14, 0x0001944c},
752 {0x14, 0x00059444}, {0x14, 0x0009944c},
753 {0x14, 0x000d9444}, {0x15, 0x0000f424},
754 {0x15, 0x0004f424}, {0x15, 0x0008f424},
755 {0x15, 0x000cf424}, {0x16, 0x000e0330},
756 {0x16, 0x000a0330}, {0x16, 0x00060330},
757 {0x16, 0x00020330}, {0x00, 0x00010159},
758 {0x18, 0x0000f401}, {0xfe, 0x00000000},
759 {0xfe, 0x00000000}, {0x1f, 0x00080003},
760 {0xfe, 0x00000000}, {0xfe, 0x00000000},
761 {0x1e, 0x00044457}, {0x1f, 0x00080000},
762 {0x00, 0x00030159},
763 {0xff, 0xffffffff}
764};
765
766static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
767 {0x00, 0x00030159}, {0x01, 0x00031284},
768 {0x02, 0x00098000}, {0x03, 0x00018c63},
769 {0x04, 0x000210e7}, {0x09, 0x0002044f},
770 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
771 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
772 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
773 {0x12, 0x00032000}, {0x12, 0x00071000},
774 {0x12, 0x000b0000}, {0x12, 0x000fc000},
775 {0x13, 0x000287af}, {0x13, 0x000244b7},
776 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
777 {0x13, 0x00018493}, {0x13, 0x00014297},
778 {0x13, 0x00010295}, {0x13, 0x0000c298},
779 {0x13, 0x0000819c}, {0x13, 0x000040a8},
780 {0x13, 0x0000001c}, {0x14, 0x0001944c},
781 {0x14, 0x00059444}, {0x14, 0x0009944c},
782 {0x14, 0x000d9444}, {0x15, 0x0000f424},
783 {0x15, 0x0004f424}, {0x15, 0x0008f424},
784 {0x15, 0x000cf424}, {0x16, 0x000e0330},
785 {0x16, 0x000a0330}, {0x16, 0x00060330},
786 {0x16, 0x00020330},
787 {0xff, 0xffffffff}
788};
789
790static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
791 {0x00, 0x00030159}, {0x01, 0x00031284},
792 {0x02, 0x00098000}, {0x03, 0x00018c63},
793 {0x04, 0x000210e7}, {0x09, 0x0002044f},
794 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
795 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
796 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
797 {0x19, 0x00000000}, {0x1a, 0x00010255},
798 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
799 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
800 {0x1f, 0x00080001}, {0x20, 0x0000b614},
801 {0x21, 0x0006c000}, {0x22, 0x00000000},
802 {0x23, 0x00001558}, {0x24, 0x00000060},
803 {0x25, 0x00000483}, {0x26, 0x0004f000},
804 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
805 {0x29, 0x00004783}, {0x2a, 0x00000001},
806 {0x2b, 0x00021334}, {0x2a, 0x00000000},
807 {0x2b, 0x00000054}, {0x2a, 0x00000001},
808 {0x2b, 0x00000808}, {0x2b, 0x00053333},
809 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
810 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
811 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
812 {0x2b, 0x00000808}, {0x2b, 0x00063333},
813 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
814 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
815 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
816 {0x2b, 0x00000808}, {0x2b, 0x00073333},
817 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
818 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
819 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
820 {0x2b, 0x00000709}, {0x2b, 0x00063333},
821 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
822 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
823 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
824 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
825 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
826 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
827 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
828 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
829 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
830 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
831 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
832 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
833 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
834 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
835 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
836 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
837 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
838 {0x10, 0x0002000f}, {0x11, 0x000203f9},
839 {0x10, 0x0003000f}, {0x11, 0x000ff500},
840 {0x10, 0x00000000}, {0x11, 0x00000000},
841 {0x10, 0x0008000f}, {0x11, 0x0003f100},
842 {0x10, 0x0009000f}, {0x11, 0x00023100},
843 {0x12, 0x00032000}, {0x12, 0x00071000},
844 {0x12, 0x000b0000}, {0x12, 0x000fc000},
845 {0x13, 0x000287b3}, {0x13, 0x000244b7},
846 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
847 {0x13, 0x00018493}, {0x13, 0x0001429b},
848 {0x13, 0x00010299}, {0x13, 0x0000c29c},
849 {0x13, 0x000081a0}, {0x13, 0x000040ac},
850 {0x13, 0x00000020}, {0x14, 0x0001944c},
851 {0x14, 0x00059444}, {0x14, 0x0009944c},
852 {0x14, 0x000d9444}, {0x15, 0x0000f405},
853 {0x15, 0x0004f405}, {0x15, 0x0008f405},
854 {0x15, 0x000cf405}, {0x16, 0x000e0330},
855 {0x16, 0x000a0330}, {0x16, 0x00060330},
856 {0x16, 0x00020330}, {0x00, 0x00010159},
857 {0x18, 0x0000f401}, {0xfe, 0x00000000},
858 {0xfe, 0x00000000}, {0x1f, 0x00080003},
859 {0xfe, 0x00000000}, {0xfe, 0x00000000},
860 {0x1e, 0x00044457}, {0x1f, 0x00080000},
861 {0x00, 0x00030159},
862 {0xff, 0xffffffff}
863};
864
865static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
866 {0x00, 0x00030159}, {0x01, 0x00031284},
867 {0x02, 0x00098000}, {0x03, 0x00018c63},
868 {0x04, 0x000210e7}, {0x09, 0x0002044f},
869 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
870 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
871 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
872 {0x19, 0x00000000}, {0x1a, 0x00000255},
873 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
874 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
875 {0x1f, 0x00080001}, {0x20, 0x0000b614},
876 {0x21, 0x0006c000}, {0x22, 0x0000083c},
877 {0x23, 0x00001558}, {0x24, 0x00000060},
878 {0x25, 0x00000483}, {0x26, 0x0004f000},
879 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
880 {0x29, 0x00004783}, {0x2a, 0x00000001},
881 {0x2b, 0x00021334}, {0x2a, 0x00000000},
882 {0x2b, 0x00000054}, {0x2a, 0x00000001},
883 {0x2b, 0x00000808}, {0x2b, 0x00053333},
884 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
885 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
886 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
887 {0x2b, 0x00000808}, {0x2b, 0x00063333},
888 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
889 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
890 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
891 {0x2b, 0x00000808}, {0x2b, 0x00073333},
892 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
893 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
894 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
895 {0x2b, 0x00000709}, {0x2b, 0x00063333},
896 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
897 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
898 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
899 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
900 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
901 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
902 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
903 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
904 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
905 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
906 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
907 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
908 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
909 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
910 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
911 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
912 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
913 {0x10, 0x0002000f}, {0x11, 0x000203f9},
914 {0x10, 0x0003000f}, {0x11, 0x000ff500},
915 {0x10, 0x00000000}, {0x11, 0x00000000},
916 {0x10, 0x0008000f}, {0x11, 0x0003f100},
917 {0x10, 0x0009000f}, {0x11, 0x00023100},
918 {0x12, 0x000d8000}, {0x12, 0x00090000},
919 {0x12, 0x00051000}, {0x12, 0x00012000},
920 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
921 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
922 {0x13, 0x000183a4}, {0x13, 0x00014398},
923 {0x13, 0x000101a4}, {0x13, 0x0000c198},
924 {0x13, 0x000080a4}, {0x13, 0x00004098},
925 {0x13, 0x00000000}, {0x14, 0x0001944c},
926 {0x14, 0x00059444}, {0x14, 0x0009944c},
927 {0x14, 0x000d9444}, {0x15, 0x0000f405},
928 {0x15, 0x0004f405}, {0x15, 0x0008f405},
929 {0x15, 0x000cf405}, {0x16, 0x000e0330},
930 {0x16, 0x000a0330}, {0x16, 0x00060330},
931 {0x16, 0x00020330}, {0x00, 0x00010159},
932 {0x18, 0x0000f401}, {0xfe, 0x00000000},
933 {0xfe, 0x00000000}, {0x1f, 0x00080003},
934 {0xfe, 0x00000000}, {0xfe, 0x00000000},
935 {0x1e, 0x00044457}, {0x1f, 0x00080000},
936 {0x00, 0x00030159},
937 {0xff, 0xffffffff}
938};
939
940static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
941 { /* RF_A */
942 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
943 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
944 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
945 .hspiread = REG_HSPI_XA_READBACK,
946 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
947 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
948 },
949 { /* RF_B */
950 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
951 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
952 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
953 .hspiread = REG_HSPI_XB_READBACK,
954 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
955 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
956 },
957};
958
959static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
960 REG_OFDM0_XA_RX_IQ_IMBALANCE,
961 REG_OFDM0_XB_RX_IQ_IMBALANCE,
962 REG_OFDM0_ENERGY_CCA_THRES,
963 REG_OFDM0_AGCR_SSI_TABLE,
964 REG_OFDM0_XA_TX_IQ_IMBALANCE,
965 REG_OFDM0_XB_TX_IQ_IMBALANCE,
966 REG_OFDM0_XC_TX_AFE,
967 REG_OFDM0_XD_TX_AFE,
968 REG_OFDM0_RX_IQ_EXT_ANTA
969};
970
971static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
972{
973 struct usb_device *udev = priv->udev;
974 int len;
975 u8 data;
976
977 mutex_lock(&priv->usb_buf_mutex);
978 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
979 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
980 addr, 0, &priv->usb_buf.val8, sizeof(u8),
981 RTW_USB_CONTROL_MSG_TIMEOUT);
982 data = priv->usb_buf.val8;
983 mutex_unlock(&priv->usb_buf_mutex);
984
985 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
986 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
987 __func__, addr, data, len);
988 return data;
989}
990
991static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
992{
993 struct usb_device *udev = priv->udev;
994 int len;
995 u16 data;
996
997 mutex_lock(&priv->usb_buf_mutex);
998 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
999 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1000 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1001 RTW_USB_CONTROL_MSG_TIMEOUT);
1002 data = le16_to_cpu(priv->usb_buf.val16);
1003 mutex_unlock(&priv->usb_buf_mutex);
1004
1005 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1006 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1007 __func__, addr, data, len);
1008 return data;
1009}
1010
1011static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1012{
1013 struct usb_device *udev = priv->udev;
1014 int len;
1015 u32 data;
1016
1017 mutex_lock(&priv->usb_buf_mutex);
1018 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1019 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1020 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1021 RTW_USB_CONTROL_MSG_TIMEOUT);
1022 data = le32_to_cpu(priv->usb_buf.val32);
1023 mutex_unlock(&priv->usb_buf_mutex);
1024
1025 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1026 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1027 __func__, addr, data, len);
1028 return data;
1029}
1030
1031static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1032{
1033 struct usb_device *udev = priv->udev;
1034 int ret;
1035
1036 mutex_lock(&priv->usb_buf_mutex);
1037 priv->usb_buf.val8 = val;
1038 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1039 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1040 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1041 RTW_USB_CONTROL_MSG_TIMEOUT);
1042
1043 mutex_unlock(&priv->usb_buf_mutex);
1044
1045 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1046 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1047 __func__, addr, val);
1048 return ret;
1049}
1050
1051static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1052{
1053 struct usb_device *udev = priv->udev;
1054 int ret;
1055
1056 mutex_lock(&priv->usb_buf_mutex);
1057 priv->usb_buf.val16 = cpu_to_le16(val);
1058 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1059 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1060 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1061 RTW_USB_CONTROL_MSG_TIMEOUT);
1062 mutex_unlock(&priv->usb_buf_mutex);
1063
1064 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1065 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1066 __func__, addr, val);
1067 return ret;
1068}
1069
1070static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1071{
1072 struct usb_device *udev = priv->udev;
1073 int ret;
1074
1075 mutex_lock(&priv->usb_buf_mutex);
1076 priv->usb_buf.val32 = cpu_to_le32(val);
1077 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1078 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1079 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1080 RTW_USB_CONTROL_MSG_TIMEOUT);
1081 mutex_unlock(&priv->usb_buf_mutex);
1082
1083 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1084 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1085 __func__, addr, val);
1086 return ret;
1087}
1088
1089static int
1090rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1091{
1092 struct usb_device *udev = priv->udev;
1093 int blocksize = priv->fops->writeN_block_size;
1094 int ret, i, count, remainder;
1095
1096 count = len / blocksize;
1097 remainder = len % blocksize;
1098
1099 for (i = 0; i < count; i++) {
1100 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1101 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1102 addr, 0, buf, blocksize,
1103 RTW_USB_CONTROL_MSG_TIMEOUT);
1104 if (ret != blocksize)
1105 goto write_error;
1106
1107 addr += blocksize;
1108 buf += blocksize;
1109 }
1110
1111 if (remainder) {
1112 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1113 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1114 addr, 0, buf, remainder,
1115 RTW_USB_CONTROL_MSG_TIMEOUT);
1116 if (ret != remainder)
1117 goto write_error;
1118 }
1119
1120 return len;
1121
1122write_error:
1123 dev_info(&udev->dev,
1124 "%s: Failed to write block at addr: %04x size: %04x\n",
1125 __func__, addr, blocksize);
1126 return -EAGAIN;
1127}
1128
1129static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1130 enum rtl8xxxu_rfpath path, u8 reg)
1131{
1132 u32 hssia, val32, retval;
1133
1134 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1135 if (path != RF_A)
1136 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1137 else
1138 val32 = hssia;
1139
1140 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1141 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1142 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1143 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1144 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1145
1146 udelay(10);
1147
1148 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1149 udelay(100);
1150
1151 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1152 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1153 udelay(10);
1154
1155 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1156 if (val32 & FPGA0_HSSI_PARM1_PI)
1157 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1158 else
1159 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1160
1161 retval &= 0xfffff;
1162
1163 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1164 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1165 __func__, reg, retval);
1166 return retval;
1167}
1168
1169static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1170 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1171{
1172 int ret, retval;
1173 u32 dataaddr;
1174
1175 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1176 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1177 __func__, reg, data);
1178
1179 data &= FPGA0_LSSI_PARM_DATA_MASK;
1180 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1181
1182 /* Use XB for path B */
1183 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1184 if (ret != sizeof(dataaddr))
1185 retval = -EIO;
1186 else
1187 retval = 0;
1188
1189 udelay(1);
1190
1191 return retval;
1192}
1193
1194static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1195{
1196 struct device *dev = &priv->udev->dev;
1197 int mbox_nr, retry, retval = 0;
1198 int mbox_reg, mbox_ext_reg;
1199 u8 val8;
1200
1201 mutex_lock(&priv->h2c_mutex);
1202
1203 mbox_nr = priv->next_mbox;
1204 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1205 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1206
1207 /*
1208 * MBOX ready?
1209 */
1210 retry = 100;
1211 do {
1212 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1213 if (!(val8 & BIT(mbox_nr)))
1214 break;
1215 } while (retry--);
1216
1217 if (!retry) {
1218 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1219 retval = -EBUSY;
1220 goto error;
1221 }
1222
1223 /*
1224 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1225 */
1226 if (h2c->cmd.cmd & H2C_EXT) {
1227 rtl8xxxu_write16(priv, mbox_ext_reg,
1228 le16_to_cpu(h2c->raw.ext));
1229 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1230 dev_info(dev, "H2C_EXT %04x\n",
1231 le16_to_cpu(h2c->raw.ext));
1232 }
1233 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1234 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1235 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1236
1237 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1238
1239error:
1240 mutex_unlock(&priv->h2c_mutex);
1241 return retval;
1242}
1243
1244static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1245{
1246 u8 val8;
1247 u32 val32;
1248
1249 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1250 val8 |= BIT(0) | BIT(3);
1251 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1252
1253 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1254 val32 &= ~(BIT(4) | BIT(5));
1255 val32 |= BIT(3);
1256 if (priv->rf_paths == 2) {
1257 val32 &= ~(BIT(20) | BIT(21));
1258 val32 |= BIT(19);
1259 }
1260 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1261
1262 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1263 val32 &= ~OFDM_RF_PATH_TX_MASK;
1264 if (priv->tx_paths == 2)
1265 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1266 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1267 val32 |= OFDM_RF_PATH_TX_B;
1268 else
1269 val32 |= OFDM_RF_PATH_TX_A;
1270 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1271
1272 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1273 val32 &= ~FPGA_RF_MODE_JAPAN;
1274 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1275
1276 if (priv->rf_paths == 2)
1277 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1278 else
1279 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1280
1281 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1282 if (priv->rf_paths == 2)
1283 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1284
1285 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1286}
1287
1288static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1289{
1290 u8 sps0;
1291 u32 val32;
1292
1293 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1294
1295 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1296
1297 /* RF RX code for preamble power saving */
1298 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1299 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1300 if (priv->rf_paths == 2)
1301 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1302 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1303
1304 /* Disable TX for four paths */
1305 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1306 val32 &= ~OFDM_RF_PATH_TX_MASK;
1307 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1308
1309 /* Enable power saving */
1310 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1311 val32 |= FPGA_RF_MODE_JAPAN;
1312 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1313
1314 /* AFE control register to power down bits [30:22] */
1315 if (priv->rf_paths == 2)
1316 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1317 else
1318 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1319
1320 /* Power down RF module */
1321 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1322 if (priv->rf_paths == 2)
1323 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1324
1325 sps0 &= ~(BIT(0) | BIT(3));
1326 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1327}
1328
1329
1330static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1331{
1332 u8 val8;
1333
1334 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1335 val8 &= ~BIT(6);
1336 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1337
1338 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1339 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1340 val8 &= ~BIT(0);
1341 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1342}
1343
1344
1345/*
1346 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1347 * supports the 2.4GHz band, so channels 1 - 14:
1348 * group 0: channels 1 - 3
1349 * group 1: channels 4 - 9
1350 * group 2: channels 10 - 14
1351 *
1352 * Note: We index from 0 in the code
1353 */
1354static int rtl8723a_channel_to_group(int channel)
1355{
1356 int group;
1357
1358 if (channel < 4)
1359 group = 0;
1360 else if (channel < 10)
1361 group = 1;
1362 else
1363 group = 2;
1364
1365 return group;
1366}
1367
1368static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1369{
1370 struct rtl8xxxu_priv *priv = hw->priv;
1371 u32 val32, rsr;
1372 u8 val8, opmode;
1373 bool ht = true;
1374 int sec_ch_above, channel;
1375 int i;
1376
1377 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1378 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1379 channel = hw->conf.chandef.chan->hw_value;
1380
1381 switch (hw->conf.chandef.width) {
1382 case NL80211_CHAN_WIDTH_20_NOHT:
1383 ht = false;
1384 case NL80211_CHAN_WIDTH_20:
1385 opmode |= BW_OPMODE_20MHZ;
1386 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1387
1388 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1389 val32 &= ~FPGA_RF_MODE;
1390 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1391
1392 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1393 val32 &= ~FPGA_RF_MODE;
1394 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1395
1396 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1397 val32 |= FPGA0_ANALOG2_20MHZ;
1398 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1399 break;
1400 case NL80211_CHAN_WIDTH_40:
1401 if (hw->conf.chandef.center_freq1 >
1402 hw->conf.chandef.chan->center_freq) {
1403 sec_ch_above = 1;
1404 channel += 2;
1405 } else {
1406 sec_ch_above = 0;
1407 channel -= 2;
1408 }
1409
1410 opmode &= ~BW_OPMODE_20MHZ;
1411 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1412 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1413 if (sec_ch_above)
1414 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1415 else
1416 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1417 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1418
1419 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1420 val32 |= FPGA_RF_MODE;
1421 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1422
1423 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1424 val32 |= FPGA_RF_MODE;
1425 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1426
1427 /*
1428 * Set Control channel to upper or lower. These settings
1429 * are required only for 40MHz
1430 */
1431 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1432 val32 &= ~CCK0_SIDEBAND;
1433 if (!sec_ch_above)
1434 val32 |= CCK0_SIDEBAND;
1435 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1436
1437 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1438 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1439 if (sec_ch_above)
1440 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1441 else
1442 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1443 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1444
1445 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1446 val32 &= ~FPGA0_ANALOG2_20MHZ;
1447 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1448
1449 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1450 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1451 if (sec_ch_above)
1452 val32 |= FPGA0_PS_UPPER_CHANNEL;
1453 else
1454 val32 |= FPGA0_PS_LOWER_CHANNEL;
1455 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1456 break;
1457
1458 default:
1459 break;
1460 }
1461
1462 for (i = RF_A; i < priv->rf_paths; i++) {
1463 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1464 val32 &= ~MODE_AG_CHANNEL_MASK;
1465 val32 |= channel;
1466 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1467 }
1468
1469 if (ht)
1470 val8 = 0x0e;
1471 else
1472 val8 = 0x0a;
1473
1474 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1475 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1476
1477 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1478 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1479
1480 for (i = RF_A; i < priv->rf_paths; i++) {
1481 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1482 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1483 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1484 else
1485 val32 |= MODE_AG_CHANNEL_20MHZ;
1486 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1487 }
1488}
1489
1490static void
1491rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1492{
1493 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1494 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1495 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1496 u8 val8;
1497 int group, i;
1498
1499 group = rtl8723a_channel_to_group(channel);
1500
1501 cck[0] = priv->cck_tx_power_index_A[group];
1502 cck[1] = priv->cck_tx_power_index_B[group];
1503
1504 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1505 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1506
1507 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1508 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1509
1510 mcsbase[0] = ofdm[0];
1511 mcsbase[1] = ofdm[1];
1512 if (!ht40) {
1513 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1514 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1515 }
1516
1517 if (priv->tx_paths > 1) {
1518 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1519 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1520 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1521 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1522 }
1523
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1525 dev_info(&priv->udev->dev,
1526 "%s: Setting TX power CCK A: %02x, "
1527 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1528 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1529
1530 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1531 if (cck[i] > RF6052_MAX_TX_PWR)
1532 cck[i] = RF6052_MAX_TX_PWR;
1533 if (ofdm[i] > RF6052_MAX_TX_PWR)
1534 ofdm[i] = RF6052_MAX_TX_PWR;
1535 }
1536
1537 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1538 val32 &= 0xffff00ff;
1539 val32 |= (cck[0] << 8);
1540 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1541
1542 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1543 val32 &= 0xff;
1544 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1545 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1546
1547 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1548 val32 &= 0xffffff00;
1549 val32 |= cck[1];
1550 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1551
1552 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1553 val32 &= 0xff;
1554 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1555 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1556
1557 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1558 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1559 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1560 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1561 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1562 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1563
1564 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1565 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1566
1567 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1568 mcsbase[0] << 16 | mcsbase[0] << 24;
1569 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1570 mcsbase[1] << 16 | mcsbase[1] << 24;
1571
1572 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1573 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1574
1575 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1576 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1577
1578 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1579 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1580
1581 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1582 for (i = 0; i < 3; i++) {
1583 if (i != 2)
1584 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1585 else
1586 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1587 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1588 }
1589 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1590 for (i = 0; i < 3; i++) {
1591 if (i != 2)
1592 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1593 else
1594 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1595 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1596 }
1597}
1598
1599static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1600 enum nl80211_iftype linktype)
1601{
1602 u16 val8;
1603
1604 val8 = rtl8xxxu_read16(priv, REG_MSR);
1605 val8 &= ~MSR_LINKTYPE_MASK;
1606
1607 switch (linktype) {
1608 case NL80211_IFTYPE_UNSPECIFIED:
1609 val8 |= MSR_LINKTYPE_NONE;
1610 break;
1611 case NL80211_IFTYPE_ADHOC:
1612 val8 |= MSR_LINKTYPE_ADHOC;
1613 break;
1614 case NL80211_IFTYPE_STATION:
1615 val8 |= MSR_LINKTYPE_STATION;
1616 break;
1617 case NL80211_IFTYPE_AP:
1618 val8 |= MSR_LINKTYPE_AP;
1619 break;
1620 default:
1621 goto out;
1622 }
1623
1624 rtl8xxxu_write8(priv, REG_MSR, val8);
1625out:
1626 return;
1627}
1628
1629static void
1630rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1631{
1632 u16 val16;
1633
1634 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1635 RETRY_LIMIT_SHORT_MASK) |
1636 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1637 RETRY_LIMIT_LONG_MASK);
1638
1639 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1640}
1641
1642static void
1643rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1644{
1645 u16 val16;
1646
1647 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1648 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1649
1650 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1651}
1652
1653static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1654{
1655 struct device *dev = &priv->udev->dev;
1656 char *cut;
1657
1658 switch (priv->chip_cut) {
1659 case 0:
1660 cut = "A";
1661 break;
1662 case 1:
1663 cut = "B";
1664 break;
1665 default:
1666 cut = "unknown";
1667 }
1668
1669 dev_info(dev,
1670 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1671 priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC",
1672 priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1673 priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1674 priv->hi_pa);
1675
1676 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1677}
1678
1679static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1680{
1681 struct device *dev = &priv->udev->dev;
1682 u32 val32, bonding;
1683 u16 val16;
1684
1685 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1686 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1687 SYS_CFG_CHIP_VERSION_SHIFT;
1688 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1689 dev_info(dev, "Unsupported test chip\n");
1690 return -ENOTSUPP;
1691 }
1692
1693 if (val32 & SYS_CFG_BT_FUNC) {
1694 sprintf(priv->chip_name, "8723AU");
1695 priv->rf_paths = 1;
1696 priv->rx_paths = 1;
1697 priv->tx_paths = 1;
1698 priv->rtlchip = 0x8723a;
1699
1700 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1701 if (val32 & MULTI_WIFI_FUNC_EN)
1702 priv->has_wifi = 1;
1703 if (val32 & MULTI_BT_FUNC_EN)
1704 priv->has_bluetooth = 1;
1705 if (val32 & MULTI_GPS_FUNC_EN)
1706 priv->has_gps = 1;
1707 } else if (val32 & SYS_CFG_TYPE_ID) {
1708 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1709 bonding &= HPON_FSM_BONDING_MASK;
1710 if (bonding == HPON_FSM_BONDING_1T2R) {
1711 sprintf(priv->chip_name, "8191CU");
1712 priv->rf_paths = 2;
1713 priv->rx_paths = 2;
1714 priv->tx_paths = 1;
1715 priv->rtlchip = 0x8191c;
1716 } else {
1717 sprintf(priv->chip_name, "8192CU");
1718 priv->rf_paths = 2;
1719 priv->rx_paths = 2;
1720 priv->tx_paths = 2;
1721 priv->rtlchip = 0x8192c;
1722 }
1723 priv->has_wifi = 1;
1724 } else {
1725 sprintf(priv->chip_name, "8188CU");
1726 priv->rf_paths = 1;
1727 priv->rx_paths = 1;
1728 priv->tx_paths = 1;
1729 priv->rtlchip = 0x8188c;
1730 priv->has_wifi = 1;
1731 }
1732
1733 if (val32 & SYS_CFG_VENDOR_ID)
1734 priv->vendor_umc = 1;
1735
1736 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1737 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1738
1739 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1740 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1741 priv->ep_tx_high_queue = 1;
1742 priv->ep_tx_count++;
1743 }
1744
1745 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1746 priv->ep_tx_normal_queue = 1;
1747 priv->ep_tx_count++;
1748 }
1749
1750 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1751 priv->ep_tx_low_queue = 1;
1752 priv->ep_tx_count++;
1753 }
1754
1755 /*
1756 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1757 */
1758 if (!priv->ep_tx_count) {
1759 switch (priv->nr_out_eps) {
1760 case 3:
1761 priv->ep_tx_low_queue = 1;
1762 priv->ep_tx_count++;
1763 case 2:
1764 priv->ep_tx_normal_queue = 1;
1765 priv->ep_tx_count++;
1766 case 1:
1767 priv->ep_tx_high_queue = 1;
1768 priv->ep_tx_count++;
1769 break;
1770 default:
1771 dev_info(dev, "Unsupported USB TX end-points\n");
1772 return -ENOTSUPP;
1773 }
1774 }
1775
1776 return 0;
1777}
1778
1779static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1780{
1781 if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1782 return -EINVAL;
1783
1784 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1785
1786 memcpy(priv->cck_tx_power_index_A,
1787 priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1788 sizeof(priv->cck_tx_power_index_A));
1789 memcpy(priv->cck_tx_power_index_B,
1790 priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1791 sizeof(priv->cck_tx_power_index_B));
1792
1793 memcpy(priv->ht40_1s_tx_power_index_A,
1794 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1795 sizeof(priv->ht40_1s_tx_power_index_A));
1796 memcpy(priv->ht40_1s_tx_power_index_B,
1797 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1798 sizeof(priv->ht40_1s_tx_power_index_B));
1799
1800 memcpy(priv->ht20_tx_power_index_diff,
1801 priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1802 sizeof(priv->ht20_tx_power_index_diff));
1803 memcpy(priv->ofdm_tx_power_index_diff,
1804 priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1805 sizeof(priv->ofdm_tx_power_index_diff));
1806
1807 memcpy(priv->ht40_max_power_offset,
1808 priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1809 sizeof(priv->ht40_max_power_offset));
1810 memcpy(priv->ht20_max_power_offset,
1811 priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1812 sizeof(priv->ht20_max_power_offset));
1813
1814 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1815 priv->efuse_wifi.efuse8723.vendor_name);
1816 dev_info(&priv->udev->dev, "Product: %.41s\n",
1817 priv->efuse_wifi.efuse8723.device_name);
1818 return 0;
1819}
1820
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1821#ifdef CONFIG_RTL8XXXU_UNTESTED
1822
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1823static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1824{
1825 int i;
1826
1827 if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1828 return -EINVAL;
1829
1830 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1831
1832 memcpy(priv->cck_tx_power_index_A,
1833 priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1834 sizeof(priv->cck_tx_power_index_A));
1835 memcpy(priv->cck_tx_power_index_B,
1836 priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1837 sizeof(priv->cck_tx_power_index_B));
1838
1839 memcpy(priv->ht40_1s_tx_power_index_A,
1840 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1841 sizeof(priv->ht40_1s_tx_power_index_A));
1842 memcpy(priv->ht40_1s_tx_power_index_B,
1843 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1844 sizeof(priv->ht40_1s_tx_power_index_B));
1845 memcpy(priv->ht40_2s_tx_power_index_diff,
1846 priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1847 sizeof(priv->ht40_2s_tx_power_index_diff));
1848
1849 memcpy(priv->ht20_tx_power_index_diff,
1850 priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1851 sizeof(priv->ht20_tx_power_index_diff));
1852 memcpy(priv->ofdm_tx_power_index_diff,
1853 priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1854 sizeof(priv->ofdm_tx_power_index_diff));
1855
1856 memcpy(priv->ht40_max_power_offset,
1857 priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1858 sizeof(priv->ht40_max_power_offset));
1859 memcpy(priv->ht20_max_power_offset,
1860 priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1861 sizeof(priv->ht20_max_power_offset));
1862
1863 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1864 priv->efuse_wifi.efuse8192.vendor_name);
1865 dev_info(&priv->udev->dev, "Product: %.20s\n",
1866 priv->efuse_wifi.efuse8192.device_name);
1867
1868 if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1869 sprintf(priv->chip_name, "8188RU");
1870 priv->hi_pa = 1;
1871 }
1872
1873 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1874 unsigned char *raw = priv->efuse_wifi.raw;
1875
1876 dev_info(&priv->udev->dev,
1877 "%s: dumping efuse (0x%02zx bytes):\n",
1878 __func__, sizeof(struct rtl8192cu_efuse));
1879 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1880 dev_info(&priv->udev->dev, "%02x: "
1881 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1882 raw[i], raw[i + 1], raw[i + 2],
1883 raw[i + 3], raw[i + 4], raw[i + 5],
1884 raw[i + 6], raw[i + 7]);
1885 }
1886 }
1887 return 0;
1888}
1889
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1890#endif
1891
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1892static int
1893rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1894{
1895 int i;
1896 u8 val8;
1897 u32 val32;
1898
1899 /* Write Address */
1900 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1901 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1902 val8 &= 0xfc;
1903 val8 |= (offset >> 8) & 0x03;
1904 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1905
1906 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1907 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1908
1909 /* Poll for data read */
1910 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1911 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1912 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1913 if (val32 & BIT(31))
1914 break;
1915 }
1916
1917 if (i == RTL8XXXU_MAX_REG_POLL)
1918 return -EIO;
1919
1920 udelay(50);
1921 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1922
1923 *data = val32 & 0xff;
1924 return 0;
1925}
1926
1927static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1928{
1929 struct device *dev = &priv->udev->dev;
1930 int i, ret = 0;
1931 u8 val8, word_mask, header, extheader;
1932 u16 val16, efuse_addr, offset;
1933 u32 val32;
1934
1935 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1936 if (val16 & EEPROM_ENABLE)
1937 priv->has_eeprom = 1;
1938 if (val16 & EEPROM_BOOT)
1939 priv->boot_eeprom = 1;
1940
1941 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1942 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1943 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1944
1945 dev_dbg(dev, "Booting from %s\n",
1946 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1947
1948 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1949
1950 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1951 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1952 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1953 val16 |= SYS_ISO_PWC_EV12V;
1954 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1955 }
1956 /* Reset: 0x0000[28], default valid */
1957 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1958 if (!(val16 & SYS_FUNC_ELDR)) {
1959 val16 |= SYS_FUNC_ELDR;
1960 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1961 }
1962
1963 /*
1964 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1965 */
1966 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1967 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1968 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1969 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1970 }
1971
1972 /* Default value is 0xff */
1973 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A);
1974
1975 efuse_addr = 0;
1976 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1977 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1978 if (ret || header == 0xff)
1979 goto exit;
1980
1981 if ((header & 0x1f) == 0x0f) { /* extended header */
1982 offset = (header & 0xe0) >> 5;
1983
1984 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1985 &extheader);
1986 if (ret)
1987 goto exit;
1988 /* All words disabled */
1989 if ((extheader & 0x0f) == 0x0f)
1990 continue;
1991
1992 offset |= ((extheader & 0xf0) >> 1);
1993 word_mask = extheader & 0x0f;
1994 } else {
1995 offset = (header >> 4) & 0x0f;
1996 word_mask = header & 0x0f;
1997 }
1998
1999 if (offset < EFUSE_MAX_SECTION_8723A) {
2000 u16 map_addr;
2001 /* Get word enable value from PG header */
2002
2003 /* We have 8 bits to indicate validity */
2004 map_addr = offset * 8;
2005 if (map_addr >= EFUSE_MAP_LEN_8723A) {
2006 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2007 "efuse corrupt!\n",
2008 __func__, map_addr);
2009 ret = -EINVAL;
2010 goto exit;
2011 }
2012 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2013 /* Check word enable condition in the section */
2014 if (!(word_mask & BIT(i))) {
2015 ret = rtl8xxxu_read_efuse8(priv,
2016 efuse_addr++,
2017 &val8);
2018 if (ret)
2019 goto exit;
2020 priv->efuse_wifi.raw[map_addr++] = val8;
2021
2022 ret = rtl8xxxu_read_efuse8(priv,
2023 efuse_addr++,
2024 &val8);
2025 if (ret)
2026 goto exit;
2027 priv->efuse_wifi.raw[map_addr++] = val8;
2028 } else
2029 map_addr += 2;
2030 }
2031 } else {
2032 dev_warn(dev,
2033 "%s: Illegal offset (%04x), efuse corrupt!\n",
2034 __func__, offset);
2035 ret = -EINVAL;
2036 goto exit;
2037 }
2038 }
2039
2040exit:
2041 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2042
2043 return ret;
2044}
2045
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame^]2046static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2047{
2048 u8 val8;
2049 u16 sys_func;
2050
2051 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2052 val8 &= ~BIT(3);
2053 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2054 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2055 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2056 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2057 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2058 val8 |= BIT(3);
2059 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2060 sys_func |= SYS_FUNC_CPU_ENABLE;
2061 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2062}
2063
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2064static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2065{
2066 struct device *dev = &priv->udev->dev;
2067 int ret = 0, i;
2068 u32 val32;
2069
2070 /* Poll checksum report */
2071 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2072 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2073 if (val32 & MCU_FW_DL_CSUM_REPORT)
2074 break;
2075 }
2076
2077 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2078 dev_warn(dev, "Firmware checksum poll timed out\n");
2079 ret = -EAGAIN;
2080 goto exit;
2081 }
2082
2083 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2084 val32 |= MCU_FW_DL_READY;
2085 val32 &= ~MCU_WINT_INIT_READY;
2086 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2087
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame^]2088 /*
2089 * Reset the 8051 in order for the firmware to start running,
2090 * otherwise it won't come up on the 8192eu
2091 */
2092 rtl8xxxu_reset_8051(priv);
2093
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2094 /* Wait for firmware to become ready */
2095 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2096 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2097 if (val32 & MCU_WINT_INIT_READY)
2098 break;
2099
2100 udelay(100);
2101 }
2102
2103 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2104 dev_warn(dev, "Firmware failed to start\n");
2105 ret = -EAGAIN;
2106 goto exit;
2107 }
2108
2109exit:
2110 return ret;
2111}
2112
2113static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2114{
2115 int pages, remainder, i, ret;
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame^]2116 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2117 u16 val16;
2118 u32 val32;
2119 u8 *fwptr;
2120
2121 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2122 val8 |= 4;
2123 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2124
2125 /* 8051 enable */
2126 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
Jes Sorensen43154f62016-02-03 13:39:35 -0500[diff] [blame]2127 val16 |= SYS_FUNC_CPU_ENABLE;
2128 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2129
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2130 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2131 if (val8 & MCU_FW_RAM_SEL) {
2132 pr_info("do the RAM reset\n");
2133 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame^]2134 rtl8xxxu_reset_8051(priv);
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2135 }
2136
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2137 /* MCU firmware download enable */
2138 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2139 val8 |= MCU_FW_DL_ENABLE;
2140 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2141
2142 /* 8051 reset */
2143 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2144 val32 &= ~BIT(19);
2145 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2146
2147 /* Reset firmware download checksum */
2148 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2149 val8 |= MCU_FW_DL_CSUM_REPORT;
2150 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2151
2152 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2153 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2154
2155 fwptr = priv->fw_data->data;
2156
2157 for (i = 0; i < pages; i++) {
2158 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2159 val8 |= i;
2160 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2161
2162 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2163 fwptr, RTL_FW_PAGE_SIZE);
2164 if (ret != RTL_FW_PAGE_SIZE) {
2165 ret = -EAGAIN;
2166 goto fw_abort;
2167 }
2168
2169 fwptr += RTL_FW_PAGE_SIZE;
2170 }
2171
2172 if (remainder) {
2173 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2174 val8 |= i;
2175 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2176 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2177 fwptr, remainder);
2178 if (ret != remainder) {
2179 ret = -EAGAIN;
2180 goto fw_abort;
2181 }
2182 }
2183
2184 ret = 0;
2185fw_abort:
2186 /* MCU firmware download disable */
2187 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2188 val16 &= ~MCU_FW_DL_ENABLE;
2189 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2190
2191 return ret;
2192}
2193
2194static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2195{
2196 struct device *dev = &priv->udev->dev;
2197 const struct firmware *fw;
2198 int ret = 0;
2199 u16 signature;
2200
2201 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2202 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2203 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2204 ret = -EAGAIN;
2205 goto exit;
2206 }
2207 if (!fw) {
2208 dev_warn(dev, "Firmware data not available\n");
2209 ret = -EINVAL;
2210 goto exit;
2211 }
2212
2213 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
Tobias Klauser98e27cb2016-02-03 13:39:43 -0500[diff] [blame]2214 if (!priv->fw_data) {
2215 ret = -ENOMEM;
2216 goto exit;
2217 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2218 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2219
2220 signature = le16_to_cpu(priv->fw_data->signature);
2221 switch (signature & 0xfff0) {
2222 case 0x92c0:
2223 case 0x88c0:
2224 case 0x2300:
2225 break;
2226 default:
2227 ret = -EINVAL;
2228 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2229 __func__, signature);
2230 }
2231
2232 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2233 le16_to_cpu(priv->fw_data->major_version),
2234 priv->fw_data->minor_version, signature);
2235
2236exit:
2237 release_firmware(fw);
2238 return ret;
2239}
2240
2241static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2242{
2243 char *fw_name;
2244 int ret;
2245
2246 switch (priv->chip_cut) {
2247 case 0:
2248 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2249 break;
2250 case 1:
2251 if (priv->enable_bluetooth)
2252 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2253 else
2254 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2255
2256 break;
2257 default:
2258 return -EINVAL;
2259 }
2260
2261 ret = rtl8xxxu_load_firmware(priv, fw_name);
2262 return ret;
2263}
2264
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2265#ifdef CONFIG_RTL8XXXU_UNTESTED
2266
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2267static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2268{
2269 char *fw_name;
2270 int ret;
2271
2272 if (!priv->vendor_umc)
2273 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2274 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2275 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2276 else
2277 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2278
2279 ret = rtl8xxxu_load_firmware(priv, fw_name);
2280
2281 return ret;
2282}
2283
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2284#endif
2285
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2286static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2287{
2288 u16 val16;
2289 int i = 100;
2290
2291 /* Inform 8051 to perform reset */
2292 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2293
2294 for (i = 100; i > 0; i--) {
2295 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2296
2297 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2298 dev_dbg(&priv->udev->dev,
2299 "%s: Firmware self reset success!\n", __func__);
2300 break;
2301 }
2302 udelay(50);
2303 }
2304
2305 if (!i) {
2306 /* Force firmware reset */
2307 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2308 val16 &= ~SYS_FUNC_CPU_ENABLE;
2309 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2310 }
2311}
2312
2313static int
2314rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2315{
2316 int i, ret;
2317 u16 reg;
2318 u8 val;
2319
2320 for (i = 0; ; i++) {
2321 reg = array[i].reg;
2322 val = array[i].val;
2323
2324 if (reg == 0xffff && val == 0xff)
2325 break;
2326
2327 ret = rtl8xxxu_write8(priv, reg, val);
2328 if (ret != 1) {
2329 dev_warn(&priv->udev->dev,
2330 "Failed to initialize MAC\n");
2331 return -EAGAIN;
2332 }
2333 }
2334
2335 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2336
2337 return 0;
2338}
2339
2340static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2341 struct rtl8xxxu_reg32val *array)
2342{
2343 int i, ret;
2344 u16 reg;
2345 u32 val;
2346
2347 for (i = 0; ; i++) {
2348 reg = array[i].reg;
2349 val = array[i].val;
2350
2351 if (reg == 0xffff && val == 0xffffffff)
2352 break;
2353
2354 ret = rtl8xxxu_write32(priv, reg, val);
2355 if (ret != sizeof(val)) {
2356 dev_warn(&priv->udev->dev,
2357 "Failed to initialize PHY\n");
2358 return -EAGAIN;
2359 }
2360 udelay(1);
2361 }
2362
2363 return 0;
2364}
2365
2366/*
2367 * Most of this is black magic retrieved from the old rtl8723au driver
2368 */
2369static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2370{
2371 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2372 u32 val32;
2373
2374 /*
2375 * Todo: The vendor driver maintains a table of PHY register
2376 * addresses, which is initialized here. Do we need this?
2377 */
2378
2379 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2380 udelay(2);
2381 val8 |= AFE_PLL_320_ENABLE;
2382 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2383 udelay(2);
2384
2385 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2386 udelay(2);
2387
2388 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2389 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2390 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2391
2392 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2393 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2394 val32 &= ~AFE_XTAL_RF_GATE;
2395 if (priv->has_bluetooth)
2396 val32 &= ~AFE_XTAL_BT_GATE;
2397 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2398
2399 /* 6. 0x1f[7:0] = 0x07 */
2400 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2401 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2402
2403 if (priv->hi_pa)
2404 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2405 else if (priv->tx_paths == 2)
2406 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2407 else
2408 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2409
2410
2411 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2412 priv->vendor_umc && priv->chip_cut == 1)
2413 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2414
2415 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2416 /*
2417 * For 1T2R boards, patch the registers.
2418 *
2419 * It looks like 8191/2 1T2R boards use path B for TX
2420 */
2421 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2422 val32 &= ~(BIT(0) | BIT(1));
2423 val32 |= BIT(1);
2424 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2425
2426 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2427 val32 &= ~0x300033;
2428 val32 |= 0x200022;
2429 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2430
2431 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2432 val32 &= 0xff000000;
2433 val32 |= 0x45000000;
2434 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2435
2436 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2437 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2438 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2439 OFDM_RF_PATH_TX_B);
2440 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2441
2442 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2443 val32 &= ~(BIT(4) | BIT(5));
2444 val32 |= BIT(4);
2445 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2446
2447 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2448 val32 &= ~(BIT(27) | BIT(26));
2449 val32 |= BIT(27);
2450 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2451
2452 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2453 val32 &= ~(BIT(27) | BIT(26));
2454 val32 |= BIT(27);
2455 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2456
2457 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2458 val32 &= ~(BIT(27) | BIT(26));
2459 val32 |= BIT(27);
2460 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2461
2462 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2463 val32 &= ~(BIT(27) | BIT(26));
2464 val32 |= BIT(27);
2465 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2466
2467 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2468 val32 &= ~(BIT(27) | BIT(26));
2469 val32 |= BIT(27);
2470 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2471 }
2472
2473 if (priv->hi_pa)
2474 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2475 else
2476 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2477
2478 if (priv->rtlchip == 0x8723a &&
2479 priv->efuse_wifi.efuse8723.version >= 0x01) {
2480 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2481
2482 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2483 val32 &= 0xff000fff;
2484 val32 |= ((val8 | (val8 << 6)) << 12);
2485
2486 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2487 }
2488
2489 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2490 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2491 ldohci12 = 0x57;
2492 lpldo = 1;
2493 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2494
2495 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2496
2497 return 0;
2498}
2499
2500static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2501 struct rtl8xxxu_rfregval *array,
2502 enum rtl8xxxu_rfpath path)
2503{
2504 int i, ret;
2505 u8 reg;
2506 u32 val;
2507
2508 for (i = 0; ; i++) {
2509 reg = array[i].reg;
2510 val = array[i].val;
2511
2512 if (reg == 0xff && val == 0xffffffff)
2513 break;
2514
2515 switch (reg) {
2516 case 0xfe:
2517 msleep(50);
2518 continue;
2519 case 0xfd:
2520 mdelay(5);
2521 continue;
2522 case 0xfc:
2523 mdelay(1);
2524 continue;
2525 case 0xfb:
2526 udelay(50);
2527 continue;
2528 case 0xfa:
2529 udelay(5);
2530 continue;
2531 case 0xf9:
2532 udelay(1);
2533 continue;
2534 }
2535
2536 reg &= 0x3f;
2537
2538 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2539 if (ret) {
2540 dev_warn(&priv->udev->dev,
2541 "Failed to initialize RF\n");
2542 return -EAGAIN;
2543 }
2544 udelay(1);
2545 }
2546
2547 return 0;
2548}
2549
2550static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2551 struct rtl8xxxu_rfregval *table,
2552 enum rtl8xxxu_rfpath path)
2553{
2554 u32 val32;
2555 u16 val16, rfsi_rfenv;
2556 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2557
2558 switch (path) {
2559 case RF_A:
2560 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2561 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2562 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2563 break;
2564 case RF_B:
2565 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2566 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2567 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2568 break;
2569 default:
2570 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2571 __func__, path + 'A');
2572 return -EINVAL;
2573 }
2574 /* For path B, use XB */
2575 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2576 rfsi_rfenv &= FPGA0_RF_RFENV;
2577
2578 /*
2579 * These two we might be able to optimize into one
2580 */
2581 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2582 val32 |= BIT(20); /* 0x10 << 16 */
2583 rtl8xxxu_write32(priv, reg_int_oe, val32);
2584 udelay(1);
2585
2586 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2587 val32 |= BIT(4);
2588 rtl8xxxu_write32(priv, reg_int_oe, val32);
2589 udelay(1);
2590
2591 /*
2592 * These two we might be able to optimize into one
2593 */
2594 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2595 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2596 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2597 udelay(1);
2598
2599 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2600 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2601 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2602 udelay(1);
2603
2604 rtl8xxxu_init_rf_regs(priv, table, path);
2605
2606 /* For path B, use XB */
2607 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2608 val16 &= ~FPGA0_RF_RFENV;
2609 val16 |= rfsi_rfenv;
2610 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2611
2612 return 0;
2613}
2614
2615static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2616{
2617 int ret = -EBUSY;
2618 int count = 0;
2619 u32 value;
2620
2621 value = LLT_OP_WRITE | address << 8 | data;
2622
2623 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2624
2625 do {
2626 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2627 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2628 ret = 0;
2629 break;
2630 }
2631 } while (count++ < 20);
2632
2633 return ret;
2634}
2635
2636static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2637{
2638 int ret;
2639 int i;
2640
2641 for (i = 0; i < last_tx_page; i++) {
2642 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2643 if (ret)
2644 goto exit;
2645 }
2646
2647 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2648 if (ret)
2649 goto exit;
2650
2651 /* Mark remaining pages as a ring buffer */
2652 for (i = last_tx_page + 1; i < 0xff; i++) {
2653 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2654 if (ret)
2655 goto exit;
2656 }
2657
2658 /* Let last entry point to the start entry of ring buffer */
2659 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2660 if (ret)
2661 goto exit;
2662
2663exit:
2664 return ret;
2665}
2666
2667static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2668{
2669 u16 val16, hi, lo;
2670 u16 hiq, mgq, bkq, beq, viq, voq;
2671 int hip, mgp, bkp, bep, vip, vop;
2672 int ret = 0;
2673
2674 switch (priv->ep_tx_count) {
2675 case 1:
2676 if (priv->ep_tx_high_queue) {
2677 hi = TRXDMA_QUEUE_HIGH;
2678 } else if (priv->ep_tx_low_queue) {
2679 hi = TRXDMA_QUEUE_LOW;
2680 } else if (priv->ep_tx_normal_queue) {
2681 hi = TRXDMA_QUEUE_NORMAL;
2682 } else {
2683 hi = 0;
2684 ret = -EINVAL;
2685 }
2686
2687 hiq = hi;
2688 mgq = hi;
2689 bkq = hi;
2690 beq = hi;
2691 viq = hi;
2692 voq = hi;
2693
2694 hip = 0;
2695 mgp = 0;
2696 bkp = 0;
2697 bep = 0;
2698 vip = 0;
2699 vop = 0;
2700 break;
2701 case 2:
2702 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2703 hi = TRXDMA_QUEUE_HIGH;
2704 lo = TRXDMA_QUEUE_LOW;
2705 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2706 hi = TRXDMA_QUEUE_NORMAL;
2707 lo = TRXDMA_QUEUE_LOW;
2708 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2709 hi = TRXDMA_QUEUE_HIGH;
2710 lo = TRXDMA_QUEUE_NORMAL;
2711 } else {
2712 ret = -EINVAL;
2713 hi = 0;
2714 lo = 0;
2715 }
2716
2717 hiq = hi;
2718 mgq = hi;
2719 bkq = lo;
2720 beq = lo;
2721 viq = hi;
2722 voq = hi;
2723
2724 hip = 0;
2725 mgp = 0;
2726 bkp = 1;
2727 bep = 1;
2728 vip = 0;
2729 vop = 0;
2730 break;
2731 case 3:
2732 beq = TRXDMA_QUEUE_LOW;
2733 bkq = TRXDMA_QUEUE_LOW;
2734 viq = TRXDMA_QUEUE_NORMAL;
2735 voq = TRXDMA_QUEUE_HIGH;
2736 mgq = TRXDMA_QUEUE_HIGH;
2737 hiq = TRXDMA_QUEUE_HIGH;
2738
2739 hip = hiq ^ 3;
2740 mgp = mgq ^ 3;
2741 bkp = bkq ^ 3;
2742 bep = beq ^ 3;
2743 vip = viq ^ 3;
2744 vop = viq ^ 3;
2745 break;
2746 default:
2747 ret = -EINVAL;
2748 }
2749
2750 /*
2751 * None of the vendor drivers are configuring the beacon
2752 * queue here .... why?
2753 */
2754 if (!ret) {
2755 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2756 val16 &= 0x7;
2757 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2758 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2759 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2760 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2761 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2762 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2763 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2764
2765 priv->pipe_out[TXDESC_QUEUE_VO] =
2766 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2767 priv->pipe_out[TXDESC_QUEUE_VI] =
2768 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2769 priv->pipe_out[TXDESC_QUEUE_BE] =
2770 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2771 priv->pipe_out[TXDESC_QUEUE_BK] =
2772 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2773 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2774 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2775 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2776 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2777 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2778 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2779 priv->pipe_out[TXDESC_QUEUE_CMD] =
2780 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2781 }
2782
2783 return ret;
2784}
2785
2786static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2787 bool iqk_ok, int result[][8],
2788 int candidate, bool tx_only)
2789{
2790 u32 oldval, x, tx0_a, reg;
2791 int y, tx0_c;
2792 u32 val32;
2793
2794 if (!iqk_ok)
2795 return;
2796
2797 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2798 oldval = val32 >> 22;
2799
2800 x = result[candidate][0];
2801 if ((x & 0x00000200) != 0)
2802 x = x | 0xfffffc00;
2803 tx0_a = (x * oldval) >> 8;
2804
2805 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2806 val32 &= ~0x3ff;
2807 val32 |= tx0_a;
2808 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2809
2810 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2811 val32 &= ~BIT(31);
2812 if ((x * oldval >> 7) & 0x1)
2813 val32 |= BIT(31);
2814 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2815
2816 y = result[candidate][1];
2817 if ((y & 0x00000200) != 0)
2818 y = y | 0xfffffc00;
2819 tx0_c = (y * oldval) >> 8;
2820
2821 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2822 val32 &= ~0xf0000000;
2823 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2824 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2825
2826 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2827 val32 &= ~0x003f0000;
2828 val32 |= ((tx0_c & 0x3f) << 16);
2829 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2830
2831 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2832 val32 &= ~BIT(29);
2833 if ((y * oldval >> 7) & 0x1)
2834 val32 |= BIT(29);
2835 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2836
2837 if (tx_only) {
2838 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2839 return;
2840 }
2841
2842 reg = result[candidate][2];
2843
2844 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2845 val32 &= ~0x3ff;
2846 val32 |= (reg & 0x3ff);
2847 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2848
2849 reg = result[candidate][3] & 0x3F;
2850
2851 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2852 val32 &= ~0xfc00;
2853 val32 |= ((reg << 10) & 0xfc00);
2854 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2855
2856 reg = (result[candidate][3] >> 6) & 0xF;
2857
2858 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2859 val32 &= ~0xf0000000;
2860 val32 |= (reg << 28);
2861 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2862}
2863
2864static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2865 bool iqk_ok, int result[][8],
2866 int candidate, bool tx_only)
2867{
2868 u32 oldval, x, tx1_a, reg;
2869 int y, tx1_c;
2870 u32 val32;
2871
2872 if (!iqk_ok)
2873 return;
2874
2875 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2876 oldval = val32 >> 22;
2877
2878 x = result[candidate][4];
2879 if ((x & 0x00000200) != 0)
2880 x = x | 0xfffffc00;
2881 tx1_a = (x * oldval) >> 8;
2882
2883 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2884 val32 &= ~0x3ff;
2885 val32 |= tx1_a;
2886 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2887
2888 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2889 val32 &= ~BIT(27);
2890 if ((x * oldval >> 7) & 0x1)
2891 val32 |= BIT(27);
2892 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2893
2894 y = result[candidate][5];
2895 if ((y & 0x00000200) != 0)
2896 y = y | 0xfffffc00;
2897 tx1_c = (y * oldval) >> 8;
2898
2899 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2900 val32 &= ~0xf0000000;
2901 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2902 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2903
2904 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2905 val32 &= ~0x003f0000;
2906 val32 |= ((tx1_c & 0x3f) << 16);
2907 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2908
2909 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2910 val32 &= ~BIT(25);
2911 if ((y * oldval >> 7) & 0x1)
2912 val32 |= BIT(25);
2913 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2914
2915 if (tx_only) {
2916 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2917 return;
2918 }
2919
2920 reg = result[candidate][6];
2921
2922 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2923 val32 &= ~0x3ff;
2924 val32 |= (reg & 0x3ff);
2925 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2926
2927 reg = result[candidate][7] & 0x3f;
2928
2929 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2930 val32 &= ~0xfc00;
2931 val32 |= ((reg << 10) & 0xfc00);
2932 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2933
2934 reg = (result[candidate][7] >> 6) & 0xf;
2935
2936 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2937 val32 &= ~0x0000f000;
2938 val32 |= (reg << 12);
2939 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2940}
2941
2942#define MAX_TOLERANCE 5
2943
2944static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2945 int result[][8], int c1, int c2)
2946{
2947 u32 i, j, diff, simubitmap, bound = 0;
2948 int candidate[2] = {-1, -1}; /* for path A and path B */
2949 bool retval = true;
2950
2951 if (priv->tx_paths > 1)
2952 bound = 8;
2953 else
2954 bound = 4;
2955
2956 simubitmap = 0;
2957
2958 for (i = 0; i < bound; i++) {
2959 diff = (result[c1][i] > result[c2][i]) ?
2960 (result[c1][i] - result[c2][i]) :
2961 (result[c2][i] - result[c1][i]);
2962 if (diff > MAX_TOLERANCE) {
2963 if ((i == 2 || i == 6) && !simubitmap) {
2964 if (result[c1][i] + result[c1][i + 1] == 0)
2965 candidate[(i / 4)] = c2;
2966 else if (result[c2][i] + result[c2][i + 1] == 0)
2967 candidate[(i / 4)] = c1;
2968 else
2969 simubitmap = simubitmap | (1 << i);
2970 } else {
2971 simubitmap = simubitmap | (1 << i);
2972 }
2973 }
2974 }
2975
2976 if (simubitmap == 0) {
2977 for (i = 0; i < (bound / 4); i++) {
2978 if (candidate[i] >= 0) {
2979 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2980 result[3][j] = result[candidate[i]][j];
2981 retval = false;
2982 }
2983 }
2984 return retval;
2985 } else if (!(simubitmap & 0x0f)) {
2986 /* path A OK */
2987 for (i = 0; i < 4; i++)
2988 result[3][i] = result[c1][i];
2989 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2990 /* path B OK */
2991 for (i = 4; i < 8; i++)
2992 result[3][i] = result[c1][i];
2993 }
2994
2995 return false;
2996}
2997
2998static void
2999rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3000{
3001 int i;
3002
3003 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3004 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3005
3006 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3007}
3008
3009static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3010 const u32 *reg, u32 *backup)
3011{
3012 int i;
3013
3014 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3015 rtl8xxxu_write8(priv, reg[i], backup[i]);
3016
3017 rtl8xxxu_write32(priv, reg[i], backup[i]);
3018}
3019
3020static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3021 u32 *backup, int count)
3022{
3023 int i;
3024
3025 for (i = 0; i < count; i++)
3026 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3027}
3028
3029static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3030 u32 *backup, int count)
3031{
3032 int i;
3033
3034 for (i = 0; i < count; i++)
3035 rtl8xxxu_write32(priv, regs[i], backup[i]);
3036}
3037
3038
3039static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3040 bool path_a_on)
3041{
3042 u32 path_on;
3043 int i;
3044
3045 path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3046 if (priv->tx_paths == 1) {
3047 path_on = 0x0bdb25a0;
3048 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3049 } else {
3050 rtl8xxxu_write32(priv, regs[0], path_on);
3051 }
3052
3053 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3054 rtl8xxxu_write32(priv, regs[i], path_on);
3055}
3056
3057static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3058 const u32 *regs, u32 *backup)
3059{
3060 int i = 0;
3061
3062 rtl8xxxu_write8(priv, regs[i], 0x3f);
3063
3064 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3065 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3066
3067 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3068}
3069
3070static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3071{
3072 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3073 int result = 0;
3074
3075 /* path-A IQK setting */
3076 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3077 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3078 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3079
3080 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3081 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3082 0x28160502;
3083 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3084
3085 /* path-B IQK setting */
3086 if (priv->rf_paths > 1) {
3087 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3088 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3089 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3090 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3091 }
3092
3093 /* LO calibration setting */
3094 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3095
3096 /* One shot, path A LOK & IQK */
3097 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3098 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3099
3100 mdelay(1);
3101
3102 /* Check failed */
3103 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3104 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3105 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3106 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3107
3108 if (!(reg_eac & BIT(28)) &&
3109 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3110 ((reg_e9c & 0x03ff0000) != 0x00420000))
3111 result |= 0x01;
3112 else /* If TX not OK, ignore RX */
3113 goto out;
3114
3115 /* If TX is OK, check whether RX is OK */
3116 if (!(reg_eac & BIT(27)) &&
3117 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3118 ((reg_eac & 0x03ff0000) != 0x00360000))
3119 result |= 0x02;
3120 else
3121 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3122 __func__);
3123out:
3124 return result;
3125}
3126
3127static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3128{
3129 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3130 int result = 0;
3131
3132 /* One shot, path B LOK & IQK */
3133 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3134 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3135
3136 mdelay(1);
3137
3138 /* Check failed */
3139 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3140 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3141 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3142 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3143 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3144
3145 if (!(reg_eac & BIT(31)) &&
3146 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3147 ((reg_ebc & 0x03ff0000) != 0x00420000))
3148 result |= 0x01;
3149 else
3150 goto out;
3151
3152 if (!(reg_eac & BIT(30)) &&
3153 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3154 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3155 result |= 0x02;
3156 else
3157 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3158 __func__);
3159out:
3160 return result;
3161}
3162
3163static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3164 int result[][8], int t)
3165{
3166 struct device *dev = &priv->udev->dev;
3167 u32 i, val32;
3168 int path_a_ok, path_b_ok;
3169 int retry = 2;
3170 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3171 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3172 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3173 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3174 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3175 REG_TX_TO_TX, REG_RX_CCK,
3176 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3177 REG_RX_TO_RX, REG_STANDBY,
3178 REG_SLEEP, REG_PMPD_ANAEN
3179 };
3180 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3181 REG_TXPAUSE, REG_BEACON_CTRL,
3182 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3183 };
3184 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3185 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3186 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3187 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3188 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3189 };
3190
3191 /*
3192 * Note: IQ calibration must be performed after loading
3193 * PHY_REG.txt , and radio_a, radio_b.txt
3194 */
3195
3196 if (t == 0) {
3197 /* Save ADDA parameters, turn Path A ADDA on */
3198 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3199 RTL8XXXU_ADDA_REGS);
3200 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3201 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3202 priv->bb_backup, RTL8XXXU_BB_REGS);
3203 }
3204
3205 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3206
3207 if (t == 0) {
3208 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3209 if (val32 & FPGA0_HSSI_PARM1_PI)
3210 priv->pi_enabled = 1;
3211 }
3212
3213 if (!priv->pi_enabled) {
3214 /* Switch BB to PI mode to do IQ Calibration. */
3215 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3216 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3217 }
3218
3219 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3220 val32 &= ~FPGA_RF_MODE_CCK;
3221 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3222
3223 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3224 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3225 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3226
3227 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3228 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3229 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3230
3231 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3232 val32 &= ~BIT(10);
3233 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3234 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3235 val32 &= ~BIT(10);
3236 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3237
3238 if (priv->tx_paths > 1) {
3239 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3240 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3241 }
3242
3243 /* MAC settings */
3244 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3245
3246 /* Page B init */
3247 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3248
3249 if (priv->tx_paths > 1)
3250 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3251
3252 /* IQ calibration setting */
3253 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3254 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3255 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3256
3257 for (i = 0; i < retry; i++) {
3258 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3259 if (path_a_ok == 0x03) {
3260 val32 = rtl8xxxu_read32(priv,
3261 REG_TX_POWER_BEFORE_IQK_A);
3262 result[t][0] = (val32 >> 16) & 0x3ff;
3263 val32 = rtl8xxxu_read32(priv,
3264 REG_TX_POWER_AFTER_IQK_A);
3265 result[t][1] = (val32 >> 16) & 0x3ff;
3266 val32 = rtl8xxxu_read32(priv,
3267 REG_RX_POWER_BEFORE_IQK_A_2);
3268 result[t][2] = (val32 >> 16) & 0x3ff;
3269 val32 = rtl8xxxu_read32(priv,
3270 REG_RX_POWER_AFTER_IQK_A_2);
3271 result[t][3] = (val32 >> 16) & 0x3ff;
3272 break;
3273 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3274 /* TX IQK OK */
3275 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3276 __func__);
3277
3278 val32 = rtl8xxxu_read32(priv,
3279 REG_TX_POWER_BEFORE_IQK_A);
3280 result[t][0] = (val32 >> 16) & 0x3ff;
3281 val32 = rtl8xxxu_read32(priv,
3282 REG_TX_POWER_AFTER_IQK_A);
3283 result[t][1] = (val32 >> 16) & 0x3ff;
3284 }
3285 }
3286
3287 if (!path_a_ok)
3288 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3289
3290 if (priv->tx_paths > 1) {
3291 /*
3292 * Path A into standby
3293 */
3294 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3295 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3296 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3297
3298 /* Turn Path B ADDA on */
3299 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3300
3301 for (i = 0; i < retry; i++) {
3302 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3303 if (path_b_ok == 0x03) {
3304 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3305 result[t][4] = (val32 >> 16) & 0x3ff;
3306 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3307 result[t][5] = (val32 >> 16) & 0x3ff;
3308 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3309 result[t][6] = (val32 >> 16) & 0x3ff;
3310 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3311 result[t][7] = (val32 >> 16) & 0x3ff;
3312 break;
3313 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3314 /* TX IQK OK */
3315 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3316 result[t][4] = (val32 >> 16) & 0x3ff;
3317 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3318 result[t][5] = (val32 >> 16) & 0x3ff;
3319 }
3320 }
3321
3322 if (!path_b_ok)
3323 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3324 }
3325
3326 /* Back to BB mode, load original value */
3327 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3328
3329 if (t) {
3330 if (!priv->pi_enabled) {
3331 /*
3332 * Switch back BB to SI mode after finishing
3333 * IQ Calibration
3334 */
3335 val32 = 0x01000000;
3336 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3337 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3338 }
3339
3340 /* Reload ADDA power saving parameters */
3341 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3342 RTL8XXXU_ADDA_REGS);
3343
3344 /* Reload MAC parameters */
3345 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3346
3347 /* Reload BB parameters */
3348 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3349 priv->bb_backup, RTL8XXXU_BB_REGS);
3350
3351 /* Restore RX initial gain */
3352 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3353
3354 if (priv->tx_paths > 1) {
3355 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3356 0x00032ed3);
3357 }
3358
3359 /* Load 0xe30 IQC default value */
3360 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3361 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3362 }
3363}
3364
3365static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3366{
3367 struct device *dev = &priv->udev->dev;
3368 int result[4][8]; /* last is final result */
3369 int i, candidate;
3370 bool path_a_ok, path_b_ok;
3371 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3372 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3373 s32 reg_tmp = 0;
3374 bool simu;
3375
3376 memset(result, 0, sizeof(result));
3377 candidate = -1;
3378
3379 path_a_ok = false;
3380 path_b_ok = false;
3381
3382 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3383
3384 for (i = 0; i < 3; i++) {
3385 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3386
3387 if (i == 1) {
3388 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3389 if (simu) {
3390 candidate = 0;
3391 break;
3392 }
3393 }
3394
3395 if (i == 2) {
3396 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3397 if (simu) {
3398 candidate = 0;
3399 break;
3400 }
3401
3402 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3403 if (simu) {
3404 candidate = 1;
3405 } else {
3406 for (i = 0; i < 8; i++)
3407 reg_tmp += result[3][i];
3408
3409 if (reg_tmp)
3410 candidate = 3;
3411 else
3412 candidate = -1;
3413 }
3414 }
3415 }
3416
3417 for (i = 0; i < 4; i++) {
3418 reg_e94 = result[i][0];
3419 reg_e9c = result[i][1];
3420 reg_ea4 = result[i][2];
3421 reg_eac = result[i][3];
3422 reg_eb4 = result[i][4];
3423 reg_ebc = result[i][5];
3424 reg_ec4 = result[i][6];
3425 reg_ecc = result[i][7];
3426 }
3427
3428 if (candidate >= 0) {
3429 reg_e94 = result[candidate][0];
3430 priv->rege94 = reg_e94;
3431 reg_e9c = result[candidate][1];
3432 priv->rege9c = reg_e9c;
3433 reg_ea4 = result[candidate][2];
3434 reg_eac = result[candidate][3];
3435 reg_eb4 = result[candidate][4];
3436 priv->regeb4 = reg_eb4;
3437 reg_ebc = result[candidate][5];
3438 priv->regebc = reg_ebc;
3439 reg_ec4 = result[candidate][6];
3440 reg_ecc = result[candidate][7];
3441 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3442 dev_dbg(dev,
3443 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3444 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3445 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3446 path_a_ok = true;
3447 path_b_ok = true;
3448 } else {
3449 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3450 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3451 }
3452
3453 if (reg_e94 && candidate >= 0)
3454 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3455 candidate, (reg_ea4 == 0));
3456
3457 if (priv->tx_paths > 1 && reg_eb4)
3458 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3459 candidate, (reg_ec4 == 0));
3460
3461 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3462 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3463}
3464
3465static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3466{
3467 u32 val32;
3468 u32 rf_amode, rf_bmode = 0, lstf;
3469
3470 /* Check continuous TX and Packet TX */
3471 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3472
3473 if (lstf & OFDM_LSTF_MASK) {
3474 /* Disable all continuous TX */
3475 val32 = lstf & ~OFDM_LSTF_MASK;
3476 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3477
3478 /* Read original RF mode Path A */
3479 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3480
3481 /* Set RF mode to standby Path A */
3482 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3483 (rf_amode & 0x8ffff) | 0x10000);
3484
3485 /* Path-B */
3486 if (priv->tx_paths > 1) {
3487 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3488 RF6052_REG_AC);
3489
3490 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3491 (rf_bmode & 0x8ffff) | 0x10000);
3492 }
3493 } else {
3494 /* Deal with Packet TX case */
3495 /* block all queues */
3496 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3497 }
3498
3499 /* Start LC calibration */
3500 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3501 val32 |= 0x08000;
3502 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3503
3504 msleep(100);
3505
3506 /* Restore original parameters */
3507 if (lstf & OFDM_LSTF_MASK) {
3508 /* Path-A */
3509 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3510 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3511
3512 /* Path-B */
3513 if (priv->tx_paths > 1)
3514 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3515 rf_bmode);
3516 } else /* Deal with Packet TX case */
3517 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3518}
3519
3520static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3521{
3522 int i;
3523 u16 reg;
3524
3525 reg = REG_MACID;
3526
3527 for (i = 0; i < ETH_ALEN; i++)
3528 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3529
3530 return 0;
3531}
3532
3533static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3534{
3535 int i;
3536 u16 reg;
3537
3538 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3539
3540 reg = REG_BSSID;
3541
3542 for (i = 0; i < ETH_ALEN; i++)
3543 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3544
3545 return 0;
3546}
3547
3548static void
3549rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3550{
3551 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3552 u8 max_agg = 0xf;
3553 int i;
3554
3555 ampdu_factor = 1 << (ampdu_factor + 2);
3556 if (ampdu_factor > max_agg)
3557 ampdu_factor = max_agg;
3558
3559 for (i = 0; i < 4; i++) {
3560 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3561 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3562
3563 if ((vals[i] & 0x0f) > ampdu_factor)
3564 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3565
3566 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3567 }
3568}
3569
3570static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3571{
3572 u8 val8;
3573
3574 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3575 val8 &= 0xf8;
3576 val8 |= density;
3577 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3578}
3579
3580static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3581{
3582 u8 val8;
3583 int count, ret;
3584
3585 /* Start of rtl8723AU_card_enable_flow */
3586 /* Act to Cardemu sequence*/
3587 /* Turn off RF */
3588 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3589
3590 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3591 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3592 val8 &= ~LEDCFG2_DPDT_SELECT;
3593 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3594
3595 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3596 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3597 val8 |= BIT(1);
3598 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3599
3600 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3601 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3602 if ((val8 & BIT(1)) == 0)
3603 break;
3604 udelay(10);
3605 }
3606
3607 if (!count) {
3608 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3609 __func__);
3610 ret = -EBUSY;
3611 goto exit;
3612 }
3613
3614 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3615 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3616 val8 |= SYS_ISO_ANALOG_IPS;
3617 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3618
3619 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3620 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3621 val8 &= ~LDOA15_ENABLE;
3622 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3623
3624exit:
3625 return ret;
3626}
3627
3628static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3629{
3630 u8 val8;
3631 u8 val32;
3632 int count, ret;
3633
3634 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3635
3636 /*
3637 * Poll - wait for RX packet to complete
3638 */
3639 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3640 val32 = rtl8xxxu_read32(priv, 0x5f8);
3641 if (!val32)
3642 break;
3643 udelay(10);
3644 }
3645
3646 if (!count) {
3647 dev_warn(&priv->udev->dev,
3648 "%s: RX poll timed out (0x05f8)\n", __func__);
3649 ret = -EBUSY;
3650 goto exit;
3651 }
3652
3653 /* Disable CCK and OFDM, clock gated */
3654 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3655 val8 &= ~SYS_FUNC_BBRSTB;
3656 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3657
3658 udelay(2);
3659
3660 /* Reset baseband */
3661 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3662 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3663 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3664
3665 /* Reset MAC TRX */
3666 val8 = rtl8xxxu_read8(priv, REG_CR);
3667 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3668 rtl8xxxu_write8(priv, REG_CR, val8);
3669
3670 /* Reset MAC TRX */
3671 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3672 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3673 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3674
3675 /* Respond TX OK to scheduler */
3676 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3677 val8 |= DUAL_TSF_TX_OK;
3678 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3679
3680exit:
3681 return ret;
3682}
3683
3684static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3685{
3686 u8 val8;
3687
3688 /* Clear suspend enable and power down enable*/
3689 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3690 val8 &= ~(BIT(3) | BIT(7));
3691 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3692
3693 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3694 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3695 val8 &= ~BIT(0);
3696 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3697
3698 /* 0x04[12:11] = 11 enable WL suspend*/
3699 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3700 val8 &= ~(BIT(3) | BIT(4));
3701 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3702}
3703
3704static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3705{
3706 u8 val8;
3707 u32 val32;
3708 int count, ret = 0;
3709
3710 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3711 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3712 val8 |= LDOA15_ENABLE;
3713 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3714
3715 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3716 val8 = rtl8xxxu_read8(priv, 0x0067);
3717 val8 &= ~BIT(4);
3718 rtl8xxxu_write8(priv, 0x0067, val8);
3719
3720 mdelay(1);
3721
3722 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3723 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3724 val8 &= ~SYS_ISO_ANALOG_IPS;
3725 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3726
3727 /* disable SW LPS 0x04[10]= 0 */
3728 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3729 val8 &= ~BIT(2);
3730 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3731
3732 /* wait till 0x04[17] = 1 power ready*/
3733 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3734 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3735 if (val32 & BIT(17))
3736 break;
3737
3738 udelay(10);
3739 }
3740
3741 if (!count) {
3742 ret = -EBUSY;
3743 goto exit;
3744 }
3745
3746 /* We should be able to optimize the following three entries into one */
3747
3748 /* release WLON reset 0x04[16]= 1*/
3749 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3750 val8 |= BIT(0);
3751 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3752
3753 /* disable HWPDN 0x04[15]= 0*/
3754 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3755 val8 &= ~BIT(7);
3756 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3757
3758 /* disable WL suspend*/
3759 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3760 val8 &= ~(BIT(3) | BIT(4));
3761 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3762
3763 /* set, then poll until 0 */
3764 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3765 val32 |= APS_FSMCO_MAC_ENABLE;
3766 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3767
3768 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3769 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3770 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3771 ret = 0;
3772 break;
3773 }
3774 udelay(10);
3775 }
3776
3777 if (!count) {
3778 ret = -EBUSY;
3779 goto exit;
3780 }
3781
3782 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3783 /*
3784 * Note: Vendor driver actually clears this bit, despite the
3785 * documentation claims it's being set!
3786 */
3787 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3788 val8 |= LEDCFG2_DPDT_SELECT;
3789 val8 &= ~LEDCFG2_DPDT_SELECT;
3790 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3791
3792exit:
3793 return ret;
3794}
3795
3796static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3797{
3798 u8 val8;
3799
3800 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3801 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3802
3803 /* 0x04[12:11] = 01 enable WL suspend */
3804 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3805 val8 &= ~BIT(4);
3806 val8 |= BIT(3);
3807 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3808
3809 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3810 val8 |= BIT(7);
3811 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3812
3813 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3814 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3815 val8 |= BIT(0);
3816 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3817
3818 return 0;
3819}
3820
3821static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3822{
3823 u8 val8;
3824 u16 val16;
3825 u32 val32;
3826 int ret;
3827
3828 /*
3829 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3830 */
3831 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3832
3833 rtl8xxxu_disabled_to_emu(priv);
3834
3835 ret = rtl8xxxu_emu_to_active(priv);
3836 if (ret)
3837 goto exit;
3838
3839 /*
3840 * 0x0004[19] = 1, reset 8051
3841 */
3842 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3843 val8 |= BIT(3);
3844 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3845
3846 /*
3847 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3848 * Set CR bit10 to enable 32k calibration.
3849 */
3850 val16 = rtl8xxxu_read16(priv, REG_CR);
3851 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3852 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3853 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3854 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3855 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3856 rtl8xxxu_write16(priv, REG_CR, val16);
3857
3858 /* For EFuse PG */
3859 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3860 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3861 val32 |= (0x06 << 28);
3862 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3863exit:
3864 return ret;
3865}
3866
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3867#ifdef CONFIG_RTL8XXXU_UNTESTED
3868
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3869static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3870{
3871 u8 val8;
3872 u16 val16;
3873 u32 val32;
3874 int i;
3875
3876 for (i = 100; i; i--) {
3877 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3878 if (val8 & APS_FSMCO_PFM_ALDN)
3879 break;
3880 }
3881
3882 if (!i) {
3883 pr_info("%s: Poll failed\n", __func__);
3884 return -ENODEV;
3885 }
3886
3887 /*
3888 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3889 */
3890 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3891 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
3892 udelay(100);
3893
3894 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
3895 if (!(val8 & LDOV12D_ENABLE)) {
3896 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
3897 val8 |= LDOV12D_ENABLE;
3898 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
3899
3900 udelay(100);
3901
3902 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3903 val8 &= ~SYS_ISO_MD2PP;
3904 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3905 }
3906
3907 /*
3908 * Auto enable WLAN
3909 */
3910 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3911 val16 |= APS_FSMCO_MAC_ENABLE;
3912 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3913
3914 for (i = 1000; i; i--) {
3915 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3916 if (!(val16 & APS_FSMCO_MAC_ENABLE))
3917 break;
3918 }
3919 if (!i) {
3920 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
3921 return -EBUSY;
3922 }
3923
3924 /*
3925 * Enable radio, GPIO, LED
3926 */
3927 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
3928 APS_FSMCO_PFM_ALDN;
3929 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3930
3931 /*
3932 * Release RF digital isolation
3933 */
3934 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3935 val16 &= ~SYS_ISO_DIOR;
3936 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3937
3938 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3939 val8 &= ~APSD_CTRL_OFF;
3940 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
3941 for (i = 200; i; i--) {
3942 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3943 if (!(val8 & APSD_CTRL_OFF_STATUS))
3944 break;
3945 }
3946
3947 if (!i) {
3948 pr_info("%s: APSD_CTRL poll failed\n", __func__);
3949 return -EBUSY;
3950 }
3951
3952 /*
3953 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3954 */
3955 val16 = rtl8xxxu_read16(priv, REG_CR);
3956 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3957 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
3958 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
3959 rtl8xxxu_write16(priv, REG_CR, val16);
3960
3961 /*
3962 * Workaround for 8188RU LNA power leakage problem.
3963 */
3964 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3965 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3966 val32 &= ~BIT(1);
3967 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3968 }
3969 return 0;
3970}
3971
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3972#endif
3973
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3974static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3975{
3976 u8 val8;
3977 u16 val16;
3978 u32 val32;
3979
3980 /*
3981 * Workaround for 8188RU LNA power leakage problem.
3982 */
3983 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3984 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3985 val32 |= BIT(1);
3986 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3987 }
3988
3989 rtl8xxxu_active_to_lps(priv);
3990
3991 /* Turn off RF */
3992 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3993
3994 /* Reset Firmware if running in RAM */
3995 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3996 rtl8xxxu_firmware_self_reset(priv);
3997
3998 /* Reset MCU */
3999 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4000 val16 &= ~SYS_FUNC_CPU_ENABLE;
4001 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4002
4003 /* Reset MCU ready status */
4004 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4005
4006 rtl8xxxu_active_to_emu(priv);
4007 rtl8xxxu_emu_to_disabled(priv);
4008
4009 /* Reset MCU IO Wrapper */
4010 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4011 val8 &= ~BIT(0);
4012 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4013
4014 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4015 val8 |= BIT(0);
4016 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4017
4018 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
4019 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4020}
4021
4022static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4023{
4024 if (!priv->has_bluetooth)
4025 return;
4026}
4027
4028static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4029{
4030 struct rtl8xxxu_priv *priv = hw->priv;
4031 struct device *dev = &priv->udev->dev;
4032 struct rtl8xxxu_rfregval *rftable;
4033 bool macpower;
4034 int ret;
4035 u8 val8;
4036 u16 val16;
4037 u32 val32;
4038
4039 /* Check if MAC is already powered on */
4040 val8 = rtl8xxxu_read8(priv, REG_CR);
4041
4042 /*
4043 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4044 * initialized. First MAC returns 0xea, second MAC returns 0x00
4045 */
4046 if (val8 == 0xea)
4047 macpower = false;
4048 else
4049 macpower = true;
4050
4051 ret = priv->fops->power_on(priv);
4052 if (ret < 0) {
4053 dev_warn(dev, "%s: Failed power on\n", __func__);
4054 goto exit;
4055 }
4056
4057 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4058 if (!macpower) {
4059 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4060 if (ret) {
4061 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4062 goto exit;
4063 }
4064 }
4065
4066 ret = rtl8xxxu_download_firmware(priv);
4067 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4068 if (ret)
4069 goto exit;
4070 ret = rtl8xxxu_start_firmware(priv);
4071 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4072 if (ret)
4073 goto exit;
4074
4075 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4076 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4077 if (ret)
4078 goto exit;
4079
4080 ret = rtl8xxxu_init_phy_bb(priv);
4081 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4082 if (ret)
4083 goto exit;
4084
4085 switch(priv->rtlchip) {
4086 case 0x8723a:
4087 rftable = rtl8723au_radioa_1t_init_table;
4088 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4089 break;
4090 case 0x8188c:
4091 if (priv->hi_pa)
4092 rftable = rtl8188ru_radioa_1t_highpa_table;
4093 else
4094 rftable = rtl8192cu_radioa_1t_init_table;
4095 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4096 break;
4097 case 0x8191c:
4098 rftable = rtl8192cu_radioa_1t_init_table;
4099 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4100 break;
4101 case 0x8192c:
4102 rftable = rtl8192cu_radioa_2t_init_table;
4103 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4104 if (ret)
4105 break;
4106 rftable = rtl8192cu_radiob_2t_init_table;
4107 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4108 break;
4109 default:
4110 ret = -EINVAL;
4111 }
4112
4113 if (ret)
4114 goto exit;
4115
4116 /* Reduce 80M spur */
4117 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4118 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4119 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4120 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4121
4122 /* RFSW Control - clear bit 14 ?? */
4123 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4124 /* 0x07000760 */
4125 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4126 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4127 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4128 FPGA0_RF_BD_CTRL_SHIFT);
4129 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4130 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4131 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4132
4133 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4134 RF6052_REG_MODE_AG);
4135
4136 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4137 if (!macpower) {
4138 if (priv->ep_tx_normal_queue)
4139 val8 = TX_PAGE_NUM_NORM_PQ;
4140 else
4141 val8 = 0;
4142
4143 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4144
4145 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4146
4147 if (priv->ep_tx_high_queue)
4148 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4149 if (priv->ep_tx_low_queue)
4150 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4151
4152 rtl8xxxu_write32(priv, REG_RQPN, val32);
4153
4154 /*
4155 * Set TX buffer boundary
4156 */
4157 val8 = TX_TOTAL_PAGE_NUM + 1;
4158 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4159 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4160 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4161 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4162 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4163 }
4164
4165 ret = rtl8xxxu_init_queue_priority(priv);
4166 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4167 if (ret)
4168 goto exit;
4169
4170 /*
4171 * Set RX page boundary
4172 */
4173 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4174 /*
4175 * Transfer page size is always 128
4176 */
4177 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4178 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4179 rtl8xxxu_write8(priv, REG_PBP, val8);
4180
4181 /*
4182 * Unit in 8 bytes, not obvious what it is used for
4183 */
4184 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4185
4186 /*
4187 * Enable all interrupts - not obvious USB needs to do this
4188 */
4189 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4190 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4191
4192 rtl8xxxu_set_mac(priv);
4193 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4194
4195 /*
4196 * Configure initial WMAC settings
4197 */
4198 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4199 /* RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON | */
4200 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4201 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4202 rtl8xxxu_write32(priv, REG_RCR, val32);
4203
4204 /*
4205 * Accept all multicast
4206 */
4207 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4208 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4209
4210 /*
4211 * Init adaptive controls
4212 */
4213 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4214 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4215 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4216 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4217
4218 /* CCK = 0x0a, OFDM = 0x10 */
4219 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4220 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4221 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4222
4223 /*
4224 * Init EDCA
4225 */
4226 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4227
4228 /* Set CCK SIFS */
4229 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4230
4231 /* Set OFDM SIFS */
4232 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4233
4234 /* TXOP */
4235 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4236 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4237 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4238 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4239
4240 /* Set data auto rate fallback retry count */
4241 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4242 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4243 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4244 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4245
4246 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4247 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4248 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4249
4250 /* Set ACK timeout */
4251 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4252
4253 /*
4254 * Initialize beacon parameters
4255 */
4256 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4257 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4258 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4259 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4260 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4261 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4262
4263 /*
4264 * Enable CCK and OFDM block
4265 */
4266 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4267 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4268 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4269
4270 /*
4271 * Invalidate all CAM entries - bit 30 is undocumented
4272 */
4273 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4274
4275 /*
4276 * Start out with default power levels for channel 6, 20MHz
4277 */
4278 rtl8723a_set_tx_power(priv, 1, false);
4279
4280 /* Let the 8051 take control of antenna setting */
4281 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4282 val8 |= LEDCFG2_DPDT_SELECT;
4283 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4284
4285 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4286
4287 /* Disable BAR - not sure if this has any effect on USB */
4288 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4289
4290 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4291
4292 /*
4293 * Not sure if we should get into this at all
4294 */
4295 if (priv->iqk_initialized) {
4296 rtl8xxxu_restore_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4297 priv->bb_recovery_backup,
4298 RTL8XXXU_BB_REGS);
4299 } else {
4300 rtl8723a_phy_iq_calibrate(priv);
4301 priv->iqk_initialized = true;
4302 }
4303
4304 /*
4305 * This should enable thermal meter
4306 */
4307 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4308
4309 rtl8723a_phy_lc_calibrate(priv);
4310
4311 /* fix USB interface interference issue */
4312 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4313 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4314 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4315 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4316
4317 /* Solve too many protocol error on USB bus */
4318 /* Can't do this for 8188/8192 UMC A cut parts */
4319 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4320 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4321 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4322
4323 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4324 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4325 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4326
4327 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4328 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4329 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4330
4331 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4332 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4333 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4334
4335 /* Init BT hw config. */
4336 rtl8xxxu_init_bt(priv);
4337
4338 /*
4339 * Not sure if we really need to save these parameters, but the
4340 * vendor driver does
4341 */
4342 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4343 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4344 priv->path_a_hi_power = 1;
4345
4346 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4347 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4348
4349 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4350 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4351
4352 /* Set NAV_UPPER to 30000us */
4353 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4354 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4355
4356 /*
4357 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4358 * but we need to fin root cause.
4359 */
4360 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4361 if ((val32 & 0xff000000) != 0x83000000) {
4362 val32 |= FPGA_RF_MODE_CCK;
4363 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4364 }
4365
4366 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4367 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4368 /* ack for xmit mgmt frames. */
4369 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4370
4371exit:
4372 return ret;
4373}
4374
4375static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4376{
4377 struct rtl8xxxu_priv *priv = hw->priv;
4378
4379 rtl8xxxu_power_off(priv);
4380}
4381
4382static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4383 struct ieee80211_key_conf *key, const u8 *mac)
4384{
4385 u32 cmd, val32, addr, ctrl;
4386 int j, i, tmp_debug;
4387
4388 tmp_debug = rtl8xxxu_debug;
4389 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4390 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4391
4392 /*
4393 * This is a bit of a hack - the lower bits of the cipher
4394 * suite selector happens to match the cipher index in the CAM
4395 */
4396 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4397 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4398
4399 for (j = 5; j >= 0; j--) {
4400 switch (j) {
4401 case 0:
4402 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4403 break;
4404 case 1:
4405 val32 = mac[2] | (mac[3] << 8) |
4406 (mac[4] << 16) | (mac[5] << 24);
4407 break;
4408 default:
4409 i = (j - 2) << 2;
4410 val32 = key->key[i] | (key->key[i + 1] << 8) |
4411 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4412 break;
4413 }
4414
4415 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4416 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4417 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4418 udelay(100);
4419 }
4420
4421 rtl8xxxu_debug = tmp_debug;
4422}
4423
4424static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4425 struct ieee80211_vif *vif, const u8* mac)
4426{
4427 struct rtl8xxxu_priv *priv = hw->priv;
4428 u8 val8;
4429
4430 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4431 val8 |= BEACON_DISABLE_TSF_UPDATE;
4432 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4433}
4434
4435static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4436 struct ieee80211_vif *vif)
4437{
4438 struct rtl8xxxu_priv *priv = hw->priv;
4439 u8 val8;
4440
4441 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4442 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4443 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4444}
4445
4446static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4447 u32 ramask, int sgi)
4448{
4449 struct h2c_cmd h2c;
4450
4451 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4452 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4453 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4454
4455 h2c.ramask.arg = 0x80;
4456 if (sgi)
4457 h2c.ramask.arg |= 0x20;
4458
4459 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4460 ramask, h2c.ramask.arg);
4461 rtl8723a_h2c_cmd(priv, &h2c);
4462}
4463
4464static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4465{
4466 u32 val32;
4467 u8 rate_idx = 0;
4468
4469 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4470
4471 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4472 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4473 val32 |= rate_cfg;
4474 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4475
4476 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4477
4478 while (rate_cfg) {
4479 rate_cfg = (rate_cfg >> 1);
4480 rate_idx++;
4481 }
4482 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4483}
4484
4485static void
4486rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4487 struct ieee80211_bss_conf *bss_conf, u32 changed)
4488{
4489 struct rtl8xxxu_priv *priv = hw->priv;
4490 struct device *dev = &priv->udev->dev;
4491 struct ieee80211_sta *sta;
4492 u32 val32;
4493 u8 val8;
4494
4495 if (changed & BSS_CHANGED_ASSOC) {
4496 struct h2c_cmd h2c;
4497
4498 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4499
4500 memset(&h2c, 0, sizeof(struct h2c_cmd));
4501 rtl8xxxu_set_linktype(priv, vif->type);
4502
4503 if (bss_conf->assoc) {
4504 u32 ramask;
4505 int sgi = 0;
4506
4507 rcu_read_lock();
4508 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4509 if (!sta) {
4510 dev_info(dev, "%s: ASSOC no sta found\n",
4511 __func__);
4512 rcu_read_unlock();
4513 goto error;
4514 }
4515
4516 if (sta->ht_cap.ht_supported)
4517 dev_info(dev, "%s: HT supported\n", __func__);
4518 if (sta->vht_cap.vht_supported)
4519 dev_info(dev, "%s: VHT supported\n", __func__);
4520
4521 /* TODO: Set bits 28-31 for rate adaptive id */
4522 ramask = (sta->supp_rates[0] & 0xfff) |
4523 sta->ht_cap.mcs.rx_mask[0] << 12 |
4524 sta->ht_cap.mcs.rx_mask[1] << 20;
4525 if (sta->ht_cap.cap &
4526 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4527 sgi = 1;
4528 rcu_read_unlock();
4529
4530 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4531
4532 val32 = rtl8xxxu_read32(priv, REG_RCR);
4533 val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON;
4534 rtl8xxxu_write32(priv, REG_RCR, val32);
4535
4536 /* Enable RX of data frames */
4537 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4538
4539 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4540
4541 rtl8723a_stop_tx_beacon(priv);
4542
4543 /* joinbss sequence */
4544 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4545 0xc000 | bss_conf->aid);
4546
4547 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4548 } else {
4549 val32 = rtl8xxxu_read32(priv, REG_RCR);
4550 val32 &= ~(RCR_CHECK_BSSID_MATCH |
4551 RCR_CHECK_BSSID_BEACON);
4552 rtl8xxxu_write32(priv, REG_RCR, val32);
4553
4554 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4555 val8 |= BEACON_DISABLE_TSF_UPDATE;
4556 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4557
4558 /* Disable RX of data frames */
4559 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
4560 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4561 }
4562 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4563 rtl8723a_h2c_cmd(priv, &h2c);
4564 }
4565
4566 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4567 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4568 bss_conf->use_short_preamble);
4569 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4570 if (bss_conf->use_short_preamble)
4571 val32 |= RSR_ACK_SHORT_PREAMBLE;
4572 else
4573 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4574 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4575 }
4576
4577 if (changed & BSS_CHANGED_ERP_SLOT) {
4578 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4579 bss_conf->use_short_slot);
4580
4581 if (bss_conf->use_short_slot)
4582 val8 = 9;
4583 else
4584 val8 = 20;
4585 rtl8xxxu_write8(priv, REG_SLOT, val8);
4586 }
4587
4588 if (changed & BSS_CHANGED_BSSID) {
4589 dev_dbg(dev, "Changed BSSID!\n");
4590 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4591 }
4592
4593 if (changed & BSS_CHANGED_BASIC_RATES) {
4594 dev_dbg(dev, "Changed BASIC_RATES!\n");
4595 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4596 }
4597error:
4598 return;
4599}
4600
4601static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4602{
4603 u32 rtlqueue;
4604
4605 switch (queue) {
4606 case IEEE80211_AC_VO:
4607 rtlqueue = TXDESC_QUEUE_VO;
4608 break;
4609 case IEEE80211_AC_VI:
4610 rtlqueue = TXDESC_QUEUE_VI;
4611 break;
4612 case IEEE80211_AC_BE:
4613 rtlqueue = TXDESC_QUEUE_BE;
4614 break;
4615 case IEEE80211_AC_BK:
4616 rtlqueue = TXDESC_QUEUE_BK;
4617 break;
4618 default:
4619 rtlqueue = TXDESC_QUEUE_BE;
4620 }
4621
4622 return rtlqueue;
4623}
4624
4625static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4626{
4627 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4628 u32 queue;
4629
4630 if (ieee80211_is_mgmt(hdr->frame_control))
4631 queue = TXDESC_QUEUE_MGNT;
4632 else
4633 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4634
4635 return queue;
4636}
4637
4638static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4639{
4640 __le16 *ptr = (__le16 *)tx_desc;
4641 u16 csum = 0;
4642 int i;
4643
4644 /*
4645 * Clear csum field before calculation, as the csum field is
4646 * in the middle of the struct.
4647 */
4648 tx_desc->csum = cpu_to_le16(0);
4649
4650 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4651 csum = csum ^ le16_to_cpu(ptr[i]);
4652
4653 tx_desc->csum |= cpu_to_le16(csum);
4654}
4655
4656static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4657{
4658 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4659 unsigned long flags;
4660
4661 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4662 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4663 list_del(&tx_urb->list);
4664 priv->tx_urb_free_count--;
4665 usb_free_urb(&tx_urb->urb);
4666 }
4667 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4668}
4669
4670static struct rtl8xxxu_tx_urb *
4671rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4672{
4673 struct rtl8xxxu_tx_urb *tx_urb;
4674 unsigned long flags;
4675
4676 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4677 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4678 struct rtl8xxxu_tx_urb, list);
4679 if (tx_urb) {
4680 list_del(&tx_urb->list);
4681 priv->tx_urb_free_count--;
4682 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4683 !priv->tx_stopped) {
4684 priv->tx_stopped = true;
4685 ieee80211_stop_queues(priv->hw);
4686 }
4687 }
4688
4689 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4690
4691 return tx_urb;
4692}
4693
4694static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4695 struct rtl8xxxu_tx_urb *tx_urb)
4696{
4697 unsigned long flags;
4698
4699 INIT_LIST_HEAD(&tx_urb->list);
4700
4701 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4702
4703 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4704 priv->tx_urb_free_count++;
4705 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4706 priv->tx_stopped) {
4707 priv->tx_stopped = false;
4708 ieee80211_wake_queues(priv->hw);
4709 }
4710
4711 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4712}
4713
4714static void rtl8xxxu_tx_complete(struct urb *urb)
4715{
4716 struct sk_buff *skb = (struct sk_buff *)urb->context;
4717 struct ieee80211_tx_info *tx_info;
4718 struct ieee80211_hw *hw;
4719 struct rtl8xxxu_tx_urb *tx_urb =
4720 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4721
4722 tx_info = IEEE80211_SKB_CB(skb);
4723 hw = tx_info->rate_driver_data[0];
4724
4725 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4726
4727 ieee80211_tx_info_clear_status(tx_info);
4728 tx_info->status.rates[0].idx = -1;
4729 tx_info->status.rates[0].count = 0;
4730
4731 if (!urb->status)
4732 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4733
4734 ieee80211_tx_status_irqsafe(hw, skb);
4735
4736 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4737}
4738
4739static void rtl8xxxu_dump_action(struct device *dev,
4740 struct ieee80211_hdr *hdr)
4741{
4742 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4743 u16 cap, timeout;
4744
4745 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4746 return;
4747
4748 switch (mgmt->u.action.u.addba_resp.action_code) {
4749 case WLAN_ACTION_ADDBA_RESP:
4750 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4751 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4752 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4753 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4754 "status %02x\n",
4755 timeout,
4756 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4757 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4758 (cap >> 1) & 0x1,
4759 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4760 break;
4761 case WLAN_ACTION_ADDBA_REQ:
4762 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4763 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4764 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4765 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4766 timeout,
4767 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4768 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4769 (cap >> 1) & 0x1);
4770 break;
4771 default:
4772 dev_info(dev, "action frame %02x\n",
4773 mgmt->u.action.u.addba_resp.action_code);
4774 break;
4775 }
4776}
4777
4778static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4779 struct ieee80211_tx_control *control,
4780 struct sk_buff *skb)
4781{
4782 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4783 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4784 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4785 struct rtl8xxxu_priv *priv = hw->priv;
4786 struct rtl8xxxu_tx_desc *tx_desc;
4787 struct rtl8xxxu_tx_urb *tx_urb;
4788 struct ieee80211_sta *sta = NULL;
4789 struct ieee80211_vif *vif = tx_info->control.vif;
4790 struct device *dev = &priv->udev->dev;
4791 u32 queue, rate;
4792 u16 pktlen = skb->len;
4793 u16 seq_number;
4794 u16 rate_flag = tx_info->control.rates[0].flags;
4795 int ret;
4796
4797 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4798 dev_warn(dev,
4799 "%s: Not enough headroom (%i) for tx descriptor\n",
4800 __func__, skb_headroom(skb));
4801 goto error;
4802 }
4803
4804 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4805 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4806 __func__, skb->len);
4807 goto error;
4808 }
4809
4810 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4811 if (!tx_urb) {
4812 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4813 goto error;
4814 }
4815
4816 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4817 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4818 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4819
4820 if (ieee80211_is_action(hdr->frame_control))
4821 rtl8xxxu_dump_action(dev, hdr);
4822
4823 tx_info->rate_driver_data[0] = hw;
4824
4825 if (control && control->sta)
4826 sta = control->sta;
4827
4828 tx_desc = (struct rtl8xxxu_tx_desc *)
4829 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4830
4831 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4832 tx_desc->pkt_size = cpu_to_le16(pktlen);
4833 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4834
4835 tx_desc->txdw0 =
4836 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4837 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4838 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4839 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4840
4841 queue = rtl8xxxu_queue_select(hw, skb);
4842 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4843
4844 if (tx_info->control.hw_key) {
4845 switch (tx_info->control.hw_key->cipher) {
4846 case WLAN_CIPHER_SUITE_WEP40:
4847 case WLAN_CIPHER_SUITE_WEP104:
4848 case WLAN_CIPHER_SUITE_TKIP:
4849 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4850 break;
4851 case WLAN_CIPHER_SUITE_CCMP:
4852 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4853 break;
4854 default:
4855 break;
4856 }
4857 }
4858
4859 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4860 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4861
4862 if (rate_flag & IEEE80211_TX_RC_MCS)
4863 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4864 else
4865 rate = tx_rate->hw_value;
4866 tx_desc->txdw5 = cpu_to_le32(rate);
4867
4868 if (ieee80211_is_data(hdr->frame_control))
4869 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4870
4871 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4872 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4873 if (sta->ht_cap.ht_supported) {
4874 u32 ampdu, val32;
4875
4876 ampdu = (u32)sta->ht_cap.ampdu_density;
4877 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4878 tx_desc->txdw2 |= cpu_to_le32(val32);
4879 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4880 } else
4881 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4882 } else
4883 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4884
4885 if (ieee80211_is_data_qos(hdr->frame_control))
4886 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4887 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4888 (sta && vif && vif->bss_conf.use_short_preamble))
4889 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4890 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4891 (ieee80211_is_data_qos(hdr->frame_control) &&
4892 sta && sta->ht_cap.cap &
4893 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4894 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4895 }
4896 if (ieee80211_is_mgmt(hdr->frame_control)) {
4897 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4898 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4899 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4900 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4901 }
4902
4903 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4904 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4905 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4906 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4907 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4908 }
4909
4910 rtl8xxxu_calc_tx_desc_csum(tx_desc);
4911
4912 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4913 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4914
4915 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4916 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4917 if (ret) {
4918 usb_unanchor_urb(&tx_urb->urb);
4919 rtl8xxxu_free_tx_urb(priv, tx_urb);
4920 goto error;
4921 }
4922 return;
4923error:
4924 dev_kfree_skb(skb);
4925}
4926
4927static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4928 struct ieee80211_rx_status *rx_status,
4929 struct rtl8xxxu_rx_desc *rx_desc,
4930 struct rtl8723au_phy_stats *phy_stats)
4931{
4932 if (phy_stats->sgi_en)
4933 rx_status->flag |= RX_FLAG_SHORT_GI;
4934
4935 if (rx_desc->rxmcs < DESC_RATE_6M) {
4936 /*
4937 * Handle PHY stats for CCK rates
4938 */
4939 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
4940
4941 switch (cck_agc_rpt & 0xc0) {
4942 case 0xc0:
4943 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
4944 break;
4945 case 0x80:
4946 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
4947 break;
4948 case 0x40:
4949 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
4950 break;
4951 case 0x00:
4952 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
4953 break;
4954 }
4955 } else {
4956 rx_status->signal =
4957 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
4958 }
4959}
4960
4961static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
4962{
4963 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4964 unsigned long flags;
4965
4966 spin_lock_irqsave(&priv->rx_urb_lock, flags);
4967
4968 list_for_each_entry_safe(rx_urb, tmp,
4969 &priv->rx_urb_pending_list, list) {
4970 list_del(&rx_urb->list);
4971 priv->rx_urb_pending_count--;
4972 usb_free_urb(&rx_urb->urb);
4973 }
4974
4975 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4976}
4977
4978static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
4979 struct rtl8xxxu_rx_urb *rx_urb)
4980{
4981 struct sk_buff *skb;
4982 unsigned long flags;
4983 int pending = 0;
4984
4985 spin_lock_irqsave(&priv->rx_urb_lock, flags);
4986
4987 if (!priv->shutdown) {
4988 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
4989 priv->rx_urb_pending_count++;
4990 pending = priv->rx_urb_pending_count;
4991 } else {
4992 skb = (struct sk_buff *)rx_urb->urb.context;
4993 dev_kfree_skb(skb);
4994 usb_free_urb(&rx_urb->urb);
4995 }
4996
4997 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4998
4999 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5000 schedule_work(&priv->rx_urb_wq);
5001}
5002
5003static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5004{
5005 struct rtl8xxxu_priv *priv;
5006 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5007 struct list_head local;
5008 struct sk_buff *skb;
5009 unsigned long flags;
5010 int ret;
5011
5012 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5013 INIT_LIST_HEAD(&local);
5014
5015 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5016
5017 list_splice_init(&priv->rx_urb_pending_list, &local);
5018 priv->rx_urb_pending_count = 0;
5019
5020 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5021
5022 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5023 list_del_init(&rx_urb->list);
5024 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5025 /*
5026 * If out of memory or temporary error, put it back on the
5027 * queue and try again. Otherwise the device is dead/gone
5028 * and we should drop it.
5029 */
5030 switch (ret) {
5031 case 0:
5032 break;
5033 case -ENOMEM:
5034 case -EAGAIN:
5035 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5036 break;
5037 default:
5038 pr_info("failed to requeue urb %i\n", ret);
5039 skb = (struct sk_buff *)rx_urb->urb.context;
5040 dev_kfree_skb(skb);
5041 usb_free_urb(&rx_urb->urb);
5042 }
5043 }
5044}
5045
5046static void rtl8xxxu_rx_complete(struct urb *urb)
5047{
5048 struct rtl8xxxu_rx_urb *rx_urb =
5049 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5050 struct ieee80211_hw *hw = rx_urb->hw;
5051 struct rtl8xxxu_priv *priv = hw->priv;
5052 struct sk_buff *skb = (struct sk_buff *)urb->context;
5053 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5054 struct rtl8723au_phy_stats *phy_stats;
5055 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5056 struct ieee80211_mgmt *mgmt;
5057 struct device *dev = &priv->udev->dev;
5058 __le32 *_rx_desc_le = (__le32 *)skb->data;
5059 u32 *_rx_desc = (u32 *)skb->data;
5060 int cnt, len, drvinfo_sz, desc_shift, i;
5061
5062 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5063 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5064
5065 cnt = rx_desc->frag;
5066 len = rx_desc->pktlen;
5067 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5068 desc_shift = rx_desc->shift;
5069 skb_put(skb, urb->actual_length);
5070
5071 if (urb->status == 0) {
5072 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5073 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5074
5075 skb_pull(skb, drvinfo_sz + desc_shift);
5076
5077 mgmt = (struct ieee80211_mgmt *)skb->data;
5078
5079 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5080
5081 if (rx_desc->phy_stats)
5082 rtl8xxxu_rx_parse_phystats(priv, rx_status,
5083 rx_desc, phy_stats);
5084
5085 rx_status->freq = hw->conf.chandef.chan->center_freq;
5086 rx_status->band = hw->conf.chandef.chan->band;
5087
5088 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5089 rx_status->flag |= RX_FLAG_MACTIME_START;
5090
5091 if (!rx_desc->swdec)
5092 rx_status->flag |= RX_FLAG_DECRYPTED;
5093 if (rx_desc->crc32)
5094 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5095 if (rx_desc->bw)
5096 rx_status->flag |= RX_FLAG_40MHZ;
5097
5098 if (rx_desc->rxht) {
5099 rx_status->flag |= RX_FLAG_HT;
5100 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5101 } else {
5102 rx_status->rate_idx = rx_desc->rxmcs;
5103 }
5104
5105 ieee80211_rx_irqsafe(hw, skb);
5106 skb = NULL;
5107 rx_urb->urb.context = NULL;
5108 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5109 } else {
5110 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5111 goto cleanup;
5112 }
5113 return;
5114
5115cleanup:
5116 usb_free_urb(urb);
5117 dev_kfree_skb(skb);
5118 return;
5119}
5120
5121static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5122 struct rtl8xxxu_rx_urb *rx_urb)
5123{
5124 struct sk_buff *skb;
5125 int skb_size;
5126 int ret;
5127
5128 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5129 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5130 if (!skb)
5131 return -ENOMEM;
5132
5133 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5134 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5135 skb_size, rtl8xxxu_rx_complete, skb);
5136 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5137 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5138 if (ret)
5139 usb_unanchor_urb(&rx_urb->urb);
5140 return ret;
5141}
5142
5143static void rtl8xxxu_int_complete(struct urb *urb)
5144{
5145 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5146 struct device *dev = &priv->udev->dev;
5147 int ret;
5148
5149 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5150 if (urb->status == 0) {
5151 usb_anchor_urb(urb, &priv->int_anchor);
5152 ret = usb_submit_urb(urb, GFP_ATOMIC);
5153 if (ret)
5154 usb_unanchor_urb(urb);
5155 } else {
5156 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5157 }
5158}
5159
5160
5161static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5162{
5163 struct rtl8xxxu_priv *priv = hw->priv;
5164 struct urb *urb;
5165 u32 val32;
5166 int ret;
5167
5168 urb = usb_alloc_urb(0, GFP_KERNEL);
5169 if (!urb)
5170 return -ENOMEM;
5171
5172 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5173 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5174 rtl8xxxu_int_complete, priv, 1);
5175 usb_anchor_urb(urb, &priv->int_anchor);
5176 ret = usb_submit_urb(urb, GFP_KERNEL);
5177 if (ret) {
5178 usb_unanchor_urb(urb);
5179 goto error;
5180 }
5181
5182 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5183 val32 |= USB_HIMR_CPWM;
5184 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5185
5186error:
5187 return ret;
5188}
5189
5190static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5191 struct ieee80211_vif *vif)
5192{
5193 struct rtl8xxxu_priv *priv = hw->priv;
5194 int ret;
5195 u8 val8;
5196
5197 switch (vif->type) {
5198 case NL80211_IFTYPE_STATION:
5199 rtl8723a_stop_tx_beacon(priv);
5200
5201 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5202 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5203 BEACON_DISABLE_TSF_UPDATE;
5204 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5205 ret = 0;
5206 break;
5207 default:
5208 ret = -EOPNOTSUPP;
5209 }
5210
5211 rtl8xxxu_set_linktype(priv, vif->type);
5212
5213 return ret;
5214}
5215
5216static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5217 struct ieee80211_vif *vif)
5218{
5219 struct rtl8xxxu_priv *priv = hw->priv;
5220
5221 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5222}
5223
5224static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5225{
5226 struct rtl8xxxu_priv *priv = hw->priv;
5227 struct device *dev = &priv->udev->dev;
5228 u16 val16;
5229 int ret = 0, channel;
5230 bool ht40;
5231
5232 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5233 dev_info(dev,
5234 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5235 __func__, hw->conf.chandef.chan->hw_value,
5236 changed, hw->conf.chandef.width);
5237
5238 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5239 val16 = ((hw->conf.long_frame_max_tx_count <<
5240 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5241 ((hw->conf.short_frame_max_tx_count <<
5242 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5243 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5244 }
5245
5246 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5247 switch (hw->conf.chandef.width) {
5248 case NL80211_CHAN_WIDTH_20_NOHT:
5249 case NL80211_CHAN_WIDTH_20:
5250 ht40 = false;
5251 break;
5252 case NL80211_CHAN_WIDTH_40:
5253 ht40 = true;
5254 break;
5255 default:
5256 ret = -ENOTSUPP;
5257 goto exit;
5258 }
5259
5260 channel = hw->conf.chandef.chan->hw_value;
5261
5262 rtl8723a_set_tx_power(priv, channel, ht40);
5263
5264 rtl8723au_config_channel(hw);
5265 }
5266
5267exit:
5268 return ret;
5269}
5270
5271static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5272 struct ieee80211_vif *vif, u16 queue,
5273 const struct ieee80211_tx_queue_params *param)
5274{
5275 struct rtl8xxxu_priv *priv = hw->priv;
5276 struct device *dev = &priv->udev->dev;
5277 u32 val32;
5278 u8 aifs, acm_ctrl, acm_bit;
5279
5280 aifs = param->aifs;
5281
5282 val32 = aifs |
5283 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5284 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5285 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5286
5287 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5288 dev_dbg(dev,
5289 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5290 __func__, queue, val32, param->acm, acm_ctrl);
5291
5292 switch (queue) {
5293 case IEEE80211_AC_VO:
5294 acm_bit = ACM_HW_CTRL_VO;
5295 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5296 break;
5297 case IEEE80211_AC_VI:
5298 acm_bit = ACM_HW_CTRL_VI;
5299 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5300 break;
5301 case IEEE80211_AC_BE:
5302 acm_bit = ACM_HW_CTRL_BE;
5303 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5304 break;
5305 case IEEE80211_AC_BK:
5306 acm_bit = ACM_HW_CTRL_BK;
5307 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5308 break;
5309 default:
5310 acm_bit = 0;
5311 break;
5312 }
5313
5314 if (param->acm)
5315 acm_ctrl |= acm_bit;
5316 else
5317 acm_ctrl &= ~acm_bit;
5318 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5319
5320 return 0;
5321}
5322
5323static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5324 unsigned int changed_flags,
5325 unsigned int *total_flags, u64 multicast)
5326{
5327 struct rtl8xxxu_priv *priv = hw->priv;
5328
5329 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5330 __func__, changed_flags, *total_flags);
5331
5332 *total_flags &= (FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC);
5333}
5334
5335static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5336{
5337 if (rts > 2347)
5338 return -EINVAL;
5339
5340 return 0;
5341}
5342
5343static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5344 struct ieee80211_vif *vif,
5345 struct ieee80211_sta *sta,
5346 struct ieee80211_key_conf *key)
5347{
5348 struct rtl8xxxu_priv *priv = hw->priv;
5349 struct device *dev = &priv->udev->dev;
5350 u8 mac_addr[ETH_ALEN];
5351 u8 val8;
5352 u16 val16;
5353 u32 val32;
5354 int retval = -EOPNOTSUPP;
5355
5356 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5357 __func__, cmd, key->cipher, key->keyidx);
5358
5359 if (vif->type != NL80211_IFTYPE_STATION)
5360 return -EOPNOTSUPP;
5361
5362 if (key->keyidx > 3)
5363 return -EOPNOTSUPP;
5364
5365 switch (key->cipher) {
5366 case WLAN_CIPHER_SUITE_WEP40:
5367 case WLAN_CIPHER_SUITE_WEP104:
5368
5369 break;
5370 case WLAN_CIPHER_SUITE_CCMP:
5371 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5372 break;
5373 case WLAN_CIPHER_SUITE_TKIP:
5374 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5375 default:
5376 return -EOPNOTSUPP;
5377 }
5378
5379 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5380 dev_dbg(dev, "%s: pairwise key\n", __func__);
5381 ether_addr_copy(mac_addr, sta->addr);
5382 } else {
5383 dev_dbg(dev, "%s: group key\n", __func__);
5384 eth_broadcast_addr(mac_addr);
5385 }
5386
5387 val16 = rtl8xxxu_read16(priv, REG_CR);
5388 val16 |= CR_SECURITY_ENABLE;
5389 rtl8xxxu_write16(priv, REG_CR, val16);
5390
5391 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5392 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5393 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5394 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5395
5396 switch (cmd) {
5397 case SET_KEY:
5398 key->hw_key_idx = key->keyidx;
5399 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5400 rtl8xxxu_cam_write(priv, key, mac_addr);
5401 retval = 0;
5402 break;
5403 case DISABLE_KEY:
5404 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5405 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5406 key->keyidx << CAM_CMD_KEY_SHIFT;
5407 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5408 retval = 0;
5409 break;
5410 default:
5411 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5412 }
5413
5414 return retval;
5415}
5416
5417static int
5418rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5419 enum ieee80211_ampdu_mlme_action action,
5420 struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size,
5421 bool amsdu)
5422{
5423 struct rtl8xxxu_priv *priv = hw->priv;
5424 struct device *dev = &priv->udev->dev;
5425 u8 ampdu_factor, ampdu_density;
5426
5427 switch (action) {
5428 case IEEE80211_AMPDU_TX_START:
5429 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5430 ampdu_factor = sta->ht_cap.ampdu_factor;
5431 ampdu_density = sta->ht_cap.ampdu_density;
5432 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5433 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5434 dev_dbg(dev,
5435 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5436 ampdu_factor, ampdu_density);
5437 break;
5438 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5439 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5440 rtl8xxxu_set_ampdu_factor(priv, 0);
5441 rtl8xxxu_set_ampdu_min_space(priv, 0);
5442 break;
5443 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5444 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5445 __func__);
5446 rtl8xxxu_set_ampdu_factor(priv, 0);
5447 rtl8xxxu_set_ampdu_min_space(priv, 0);
5448 break;
5449 case IEEE80211_AMPDU_RX_START:
5450 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5451 break;
5452 case IEEE80211_AMPDU_RX_STOP:
5453 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5454 break;
5455 default:
5456 break;
5457 }
5458 return 0;
5459}
5460
5461static int rtl8xxxu_start(struct ieee80211_hw *hw)
5462{
5463 struct rtl8xxxu_priv *priv = hw->priv;
5464 struct rtl8xxxu_rx_urb *rx_urb;
5465 struct rtl8xxxu_tx_urb *tx_urb;
5466 unsigned long flags;
5467 int ret, i;
5468
5469 ret = 0;
5470
5471 init_usb_anchor(&priv->rx_anchor);
5472 init_usb_anchor(&priv->tx_anchor);
5473 init_usb_anchor(&priv->int_anchor);
5474
5475 rtl8723a_enable_rf(priv);
5476 ret = rtl8xxxu_submit_int_urb(hw);
5477 if (ret)
5478 goto exit;
5479
5480 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5481 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5482 if (!tx_urb) {
5483 if (!i)
5484 ret = -ENOMEM;
5485
5486 goto error_out;
5487 }
5488 usb_init_urb(&tx_urb->urb);
5489 INIT_LIST_HEAD(&tx_urb->list);
5490 tx_urb->hw = hw;
5491 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5492 priv->tx_urb_free_count++;
5493 }
5494
5495 priv->tx_stopped = false;
5496
5497 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5498 priv->shutdown = false;
5499 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5500
5501 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5502 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5503 if (!rx_urb) {
5504 if (!i)
5505 ret = -ENOMEM;
5506
5507 goto error_out;
5508 }
5509 usb_init_urb(&rx_urb->urb);
5510 INIT_LIST_HEAD(&rx_urb->list);
5511 rx_urb->hw = hw;
5512
5513 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5514 }
5515exit:
5516 /*
5517 * Disable all data frames
5518 */
5519 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5520 /*
5521 * Accept all mgmt frames
5522 */
5523 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5524
5525 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5526
5527 return ret;
5528
5529error_out:
5530 rtl8xxxu_free_tx_resources(priv);
5531 /*
5532 * Disable all data and mgmt frames
5533 */
5534 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5535 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5536
5537 return ret;
5538}
5539
5540static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5541{
5542 struct rtl8xxxu_priv *priv = hw->priv;
5543 unsigned long flags;
5544
5545 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5546
5547 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5548 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5549
5550 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5551 priv->shutdown = true;
5552 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5553
5554 usb_kill_anchored_urbs(&priv->rx_anchor);
5555 usb_kill_anchored_urbs(&priv->tx_anchor);
5556 usb_kill_anchored_urbs(&priv->int_anchor);
5557
5558 rtl8723a_disable_rf(priv);
5559
5560 /*
5561 * Disable interrupts
5562 */
5563 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5564
5565 rtl8xxxu_free_rx_resources(priv);
5566 rtl8xxxu_free_tx_resources(priv);
5567}
5568
5569static const struct ieee80211_ops rtl8xxxu_ops = {
5570 .tx = rtl8xxxu_tx,
5571 .add_interface = rtl8xxxu_add_interface,
5572 .remove_interface = rtl8xxxu_remove_interface,
5573 .config = rtl8xxxu_config,
5574 .conf_tx = rtl8xxxu_conf_tx,
5575 .bss_info_changed = rtl8xxxu_bss_info_changed,
5576 .configure_filter = rtl8xxxu_configure_filter,
5577 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5578 .start = rtl8xxxu_start,
5579 .stop = rtl8xxxu_stop,
5580 .sw_scan_start = rtl8xxxu_sw_scan_start,
5581 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5582 .set_key = rtl8xxxu_set_key,
5583 .ampdu_action = rtl8xxxu_ampdu_action,
5584};
5585
5586static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5587 struct usb_interface *interface)
5588{
5589 struct usb_interface_descriptor *interface_desc;
5590 struct usb_host_interface *host_interface;
5591 struct usb_endpoint_descriptor *endpoint;
5592 struct device *dev = &priv->udev->dev;
5593 int i, j = 0, endpoints;
5594 u8 dir, xtype, num;
5595 int ret = 0;
5596
5597 host_interface = &interface->altsetting[0];
5598 interface_desc = &host_interface->desc;
5599 endpoints = interface_desc->bNumEndpoints;
5600
5601 for (i = 0; i < endpoints; i++) {
5602 endpoint = &host_interface->endpoint[i].desc;
5603
5604 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5605 num = usb_endpoint_num(endpoint);
5606 xtype = usb_endpoint_type(endpoint);
5607 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5608 dev_dbg(dev,
5609 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5610 __func__, dir, num, xtype);
5611 if (usb_endpoint_dir_in(endpoint) &&
5612 usb_endpoint_xfer_bulk(endpoint)) {
5613 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5614 dev_dbg(dev, "%s: in endpoint num %i\n",
5615 __func__, num);
5616
5617 if (priv->pipe_in) {
5618 dev_warn(dev,
5619 "%s: Too many IN pipes\n", __func__);
5620 ret = -EINVAL;
5621 goto exit;
5622 }
5623
5624 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5625 }
5626
5627 if (usb_endpoint_dir_in(endpoint) &&
5628 usb_endpoint_xfer_int(endpoint)) {
5629 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5630 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5631 __func__, num);
5632
5633 if (priv->pipe_interrupt) {
5634 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5635 __func__);
5636 ret = -EINVAL;
5637 goto exit;
5638 }
5639
5640 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5641 }
5642
5643 if (usb_endpoint_dir_out(endpoint) &&
5644 usb_endpoint_xfer_bulk(endpoint)) {
5645 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5646 dev_dbg(dev, "%s: out endpoint num %i\n",
5647 __func__, num);
5648 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5649 dev_warn(dev,
5650 "%s: Too many OUT pipes\n", __func__);
5651 ret = -EINVAL;
5652 goto exit;
5653 }
5654 priv->out_ep[j++] = num;
5655 }
5656 }
5657exit:
5658 priv->nr_out_eps = j;
5659 return ret;
5660}
5661
5662static int rtl8xxxu_probe(struct usb_interface *interface,
5663 const struct usb_device_id *id)
5664{
5665 struct rtl8xxxu_priv *priv;
5666 struct ieee80211_hw *hw;
5667 struct usb_device *udev;
5668 struct ieee80211_supported_band *sband;
5669 int ret = 0;
5670 int untested = 1;
5671
5672 udev = usb_get_dev(interface_to_usbdev(interface));
5673
5674 switch (id->idVendor) {
5675 case USB_VENDOR_ID_REALTEK:
5676 switch(id->idProduct) {
5677 case 0x1724:
5678 case 0x8176:
5679 case 0x8178:
5680 case 0x817f:
5681 untested = 0;
5682 break;
5683 }
5684 break;
5685 case 0x7392:
5686 if (id->idProduct == 0x7811)
5687 untested = 0;
5688 break;
5689 default:
5690 break;
5691 }
5692
5693 if (untested) {
5694 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5695 dev_info(&udev->dev,
5696 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5697 id->idVendor, id->idProduct);
5698 dev_info(&udev->dev,
5699 "Please report results to Jes.Sorensen@gmail.com\n");
5700 }
5701
5702 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5703 if (!hw) {
5704 ret = -ENOMEM;
5705 goto exit;
5706 }
5707
5708 priv = hw->priv;
5709 priv->hw = hw;
5710 priv->udev = udev;
5711 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5712 mutex_init(&priv->usb_buf_mutex);
5713 mutex_init(&priv->h2c_mutex);
5714 INIT_LIST_HEAD(&priv->tx_urb_free_list);
5715 spin_lock_init(&priv->tx_urb_lock);
5716 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5717 spin_lock_init(&priv->rx_urb_lock);
5718 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5719
5720 usb_set_intfdata(interface, hw);
5721
5722 ret = rtl8xxxu_parse_usb(priv, interface);
5723 if (ret)
5724 goto exit;
5725
5726 ret = rtl8xxxu_identify_chip(priv);
5727 if (ret) {
5728 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5729 goto exit;
5730 }
5731
5732 ret = rtl8xxxu_read_efuse(priv);
5733 if (ret) {
5734 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5735 goto exit;
5736 }
5737
5738 ret = priv->fops->parse_efuse(priv);
5739 if (ret) {
5740 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5741 goto exit;
5742 }
5743
5744 rtl8xxxu_print_chipinfo(priv);
5745
5746 ret = priv->fops->load_firmware(priv);
5747 if (ret) {
5748 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5749 goto exit;
5750 }
5751
5752 ret = rtl8xxxu_init_device(hw);
5753
5754 hw->wiphy->max_scan_ssids = 1;
5755 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5756 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5757 hw->queues = 4;
5758
5759 sband = &rtl8xxxu_supported_band;
5760 sband->ht_cap.ht_supported = true;
5761 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5762 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5763 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5764 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5765 sband->ht_cap.mcs.rx_mask[0] = 0xff;
5766 sband->ht_cap.mcs.rx_mask[4] = 0x01;
5767 if (priv->rf_paths > 1) {
5768 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5769 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5770 }
5771 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5772 /*
5773 * Some APs will negotiate HT20_40 in a noisy environment leading
5774 * to miserable performance. Rather than defaulting to this, only
5775 * enable it if explicitly requested at module load time.
5776 */
5777 if (rtl8xxxu_ht40_2g) {
5778 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5779 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5780 }
5781 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5782
5783 hw->wiphy->rts_threshold = 2347;
5784
5785 SET_IEEE80211_DEV(priv->hw, &interface->dev);
5786 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5787
5788 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5789 ieee80211_hw_set(hw, SIGNAL_DBM);
5790 /*
5791 * The firmware handles rate control
5792 */
5793 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5794 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5795
5796 ret = ieee80211_register_hw(priv->hw);
5797 if (ret) {
5798 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5799 __func__, ret);
5800 goto exit;
5801 }
5802
5803exit:
5804 if (ret < 0)
5805 usb_put_dev(udev);
5806 return ret;
5807}
5808
5809static void rtl8xxxu_disconnect(struct usb_interface *interface)
5810{
5811 struct rtl8xxxu_priv *priv;
5812 struct ieee80211_hw *hw;
5813
5814 hw = usb_get_intfdata(interface);
5815 priv = hw->priv;
5816
5817 rtl8xxxu_disable_device(hw);
5818 usb_set_intfdata(interface, NULL);
5819
5820 dev_info(&priv->udev->dev, "disconnecting\n");
5821
5822 ieee80211_unregister_hw(hw);
5823
5824 kfree(priv->fw_data);
5825 mutex_destroy(&priv->usb_buf_mutex);
5826 mutex_destroy(&priv->h2c_mutex);
5827
5828 usb_put_dev(priv->udev);
5829 ieee80211_free_hw(hw);
5830}
5831
5832static struct rtl8xxxu_fileops rtl8723au_fops = {
5833 .parse_efuse = rtl8723au_parse_efuse,
5834 .load_firmware = rtl8723au_load_firmware,
5835 .power_on = rtl8723au_power_on,
5836 .writeN_block_size = 1024,
5837};
5838
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5839#ifdef CONFIG_RTL8XXXU_UNTESTED
5840
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5841static struct rtl8xxxu_fileops rtl8192cu_fops = {
5842 .parse_efuse = rtl8192cu_parse_efuse,
5843 .load_firmware = rtl8192cu_load_firmware,
5844 .power_on = rtl8192cu_power_on,
5845 .writeN_block_size = 128,
5846};
5847
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5848#endif
5849
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5850static struct usb_device_id dev_table[] = {
5851{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5852 .driver_info = (unsigned long)&rtl8723au_fops},
5853{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5854 .driver_info = (unsigned long)&rtl8723au_fops},
5855{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5856 .driver_info = (unsigned long)&rtl8723au_fops},
Kalle Valo033695b2015-10-23 20:27:58 +0300[diff] [blame]5857#ifdef CONFIG_RTL8XXXU_UNTESTED
5858/* Still supported by rtlwifi */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5859{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5860 .driver_info = (unsigned long)&rtl8192cu_fops},
5861{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5862 .driver_info = (unsigned long)&rtl8192cu_fops},
5863{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5864 .driver_info = (unsigned long)&rtl8192cu_fops},
5865/* Tested by Larry Finger */
5866{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
5867 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5868/* Currently untested 8188 series devices */
5869{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
5870 .driver_info = (unsigned long)&rtl8192cu_fops},
5871{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
5872 .driver_info = (unsigned long)&rtl8192cu_fops},
5873{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
5874 .driver_info = (unsigned long)&rtl8192cu_fops},
5875{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
5876 .driver_info = (unsigned long)&rtl8192cu_fops},
5877{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
5878 .driver_info = (unsigned long)&rtl8192cu_fops},
5879{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
5880 .driver_info = (unsigned long)&rtl8192cu_fops},
5881{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
5882 .driver_info = (unsigned long)&rtl8192cu_fops},
5883{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
5884 .driver_info = (unsigned long)&rtl8192cu_fops},
5885{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5886 .driver_info = (unsigned long)&rtl8192cu_fops},
5887{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
5888 .driver_info = (unsigned long)&rtl8192cu_fops},
5889{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
5890 .driver_info = (unsigned long)&rtl8192cu_fops},
5891{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
5892 .driver_info = (unsigned long)&rtl8192cu_fops},
5893{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
5894 .driver_info = (unsigned long)&rtl8192cu_fops},
5895{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
5896 .driver_info = (unsigned long)&rtl8192cu_fops},
5897{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
5898 .driver_info = (unsigned long)&rtl8192cu_fops},
5899{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
5900 .driver_info = (unsigned long)&rtl8192cu_fops},
5901{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
5902 .driver_info = (unsigned long)&rtl8192cu_fops},
5903{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
5904 .driver_info = (unsigned long)&rtl8192cu_fops},
5905{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
5906 .driver_info = (unsigned long)&rtl8192cu_fops},
5907{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
5908 .driver_info = (unsigned long)&rtl8192cu_fops},
5909{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
5910 .driver_info = (unsigned long)&rtl8192cu_fops},
5911{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
5912 .driver_info = (unsigned long)&rtl8192cu_fops},
5913{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
5914 .driver_info = (unsigned long)&rtl8192cu_fops},
5915{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
5916 .driver_info = (unsigned long)&rtl8192cu_fops},
5917{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
5918 .driver_info = (unsigned long)&rtl8192cu_fops},
5919{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
5920 .driver_info = (unsigned long)&rtl8192cu_fops},
5921{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
5922 .driver_info = (unsigned long)&rtl8192cu_fops},
5923{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
5924 .driver_info = (unsigned long)&rtl8192cu_fops},
5925{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
5926 .driver_info = (unsigned long)&rtl8192cu_fops},
5927{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
5928 .driver_info = (unsigned long)&rtl8192cu_fops},
5929{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
5930 .driver_info = (unsigned long)&rtl8192cu_fops},
5931{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
5932 .driver_info = (unsigned long)&rtl8192cu_fops},
5933{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
5934 .driver_info = (unsigned long)&rtl8192cu_fops},
5935{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5936 .driver_info = (unsigned long)&rtl8192cu_fops}, /* Netcore 8188RU */
5937{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
5938 .driver_info = (unsigned long)&rtl8192cu_fops},
5939{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
5940 .driver_info = (unsigned long)&rtl8192cu_fops},
5941{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
5942 .driver_info = (unsigned long)&rtl8192cu_fops},
5943{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
5944 .driver_info = (unsigned long)&rtl8192cu_fops},
5945{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
5946 .driver_info = (unsigned long)&rtl8192cu_fops},
5947{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
5948 .driver_info = (unsigned long)&rtl8192cu_fops},
5949{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
5950 .driver_info = (unsigned long)&rtl8192cu_fops},
5951/* Currently untested 8192 series devices */
5952{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
5953 .driver_info = (unsigned long)&rtl8192cu_fops},
5954{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
5955 .driver_info = (unsigned long)&rtl8192cu_fops},
5956{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
5957 .driver_info = (unsigned long)&rtl8192cu_fops},
5958{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
5959 .driver_info = (unsigned long)&rtl8192cu_fops},
5960{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
5961 .driver_info = (unsigned long)&rtl8192cu_fops},
5962{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
5963 .driver_info = (unsigned long)&rtl8192cu_fops},
5964{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
5965 .driver_info = (unsigned long)&rtl8192cu_fops},
5966{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
5967 .driver_info = (unsigned long)&rtl8192cu_fops},
5968{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
5969 .driver_info = (unsigned long)&rtl8192cu_fops},
5970{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
5971 .driver_info = (unsigned long)&rtl8192cu_fops},
5972{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
5973 .driver_info = (unsigned long)&rtl8192cu_fops},
5974{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
5975 .driver_info = (unsigned long)&rtl8192cu_fops},
5976{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
5977 .driver_info = (unsigned long)&rtl8192cu_fops},
5978{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
5979 .driver_info = (unsigned long)&rtl8192cu_fops},
5980{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
5981 .driver_info = (unsigned long)&rtl8192cu_fops},
5982{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
5983 .driver_info = (unsigned long)&rtl8192cu_fops},
5984{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
5985 .driver_info = (unsigned long)&rtl8192cu_fops},
5986{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
5987 .driver_info = (unsigned long)&rtl8192cu_fops},
5988{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
5989 .driver_info = (unsigned long)&rtl8192cu_fops},
5990{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
5991 .driver_info = (unsigned long)&rtl8192cu_fops},
5992{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
5993 .driver_info = (unsigned long)&rtl8192cu_fops},
5994{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
5995 .driver_info = (unsigned long)&rtl8192cu_fops},
5996{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
5997 .driver_info = (unsigned long)&rtl8192cu_fops},
5998{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
5999 .driver_info = (unsigned long)&rtl8192cu_fops},
6000{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6001 .driver_info = (unsigned long)&rtl8192cu_fops},
6002#endif
6003{ }
6004};
6005
6006static struct usb_driver rtl8xxxu_driver = {
6007 .name = DRIVER_NAME,
6008 .probe = rtl8xxxu_probe,
6009 .disconnect = rtl8xxxu_disconnect,
6010 .id_table = dev_table,
6011 .disable_hub_initiated_lpm = 1,
6012};
6013
6014static int __init rtl8xxxu_module_init(void)
6015{
6016 int res;
6017
6018 res = usb_register(&rtl8xxxu_driver);
6019 if (res < 0)
6020 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6021
6022 return res;
6023}
6024
6025static void __exit rtl8xxxu_module_exit(void)
6026{
6027 usb_deregister(&rtl8xxxu_driver);
6028}
6029
6030
6031MODULE_DEVICE_TABLE(usb, dev_table);
6032
6033module_init(rtl8xxxu_module_init);
6034module_exit(rtl8xxxu_module_exit);