| Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Ethernet driver for the Atmel AT91RM9200 (Thunder) |
| 3 | * |
| 4 | * Copyright (C) SAN People (Pty) Ltd |
| 5 | * |
| 6 | * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. |
| 7 | * Initial version by Rick Bronson. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef AT91_ETHERNET |
| 16 | #define AT91_ETHERNET |
| 17 | |
| 18 | |
| 19 | /* Davicom 9161 PHY */ |
| 20 | #define MII_DM9161_ID 0x0181b880 |
| 21 | #define MII_DM9161A_ID 0x0181b8a0 |
| 22 | |
| 23 | /* Davicom specific registers */ |
| 24 | #define MII_DSCR_REG 16 |
| 25 | #define MII_DSCSR_REG 17 |
| 26 | #define MII_DSINTR_REG 21 |
| 27 | |
| 28 | /* Intel LXT971A PHY */ |
| 29 | #define MII_LXT971A_ID 0x001378E0 |
| 30 | |
| 31 | /* Intel specific registers */ |
| 32 | #define MII_ISINTE_REG 18 |
| 33 | #define MII_ISINTS_REG 19 |
| 34 | #define MII_LEDCTRL_REG 20 |
| 35 | |
| 36 | /* Realtek RTL8201 PHY */ |
| 37 | #define MII_RTL8201_ID 0x00008200 |
| 38 | |
| 39 | /* Broadcom BCM5221 PHY */ |
| 40 | #define MII_BCM5221_ID 0x004061e0 |
| 41 | |
| 42 | /* Broadcom specific registers */ |
| 43 | #define MII_BCMINTR_REG 26 |
| 44 | |
| 45 | /* National Semiconductor DP83847 */ |
| 46 | #define MII_DP83847_ID 0x20005c30 |
| 47 | |
| 48 | /* Altima AC101L PHY */ |
| 49 | #define MII_AC101L_ID 0x00225520 |
| 50 | |
| 51 | /* Micrel KS8721 PHY */ |
| 52 | #define MII_KS8721_ID 0x00221610 |
| 53 | |
| 54 | /* ........................................................................ */ |
| 55 | |
| 56 | #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */ |
| 57 | #define MAX_RX_DESCR 9 /* max number of receive buffers */ |
| 58 | |
| 59 | #define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */ |
| 60 | #define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ |
| 61 | |
| 62 | #define EMAC_BROADCAST 0x80000000 /* broadcast address */ |
| 63 | #define EMAC_MULTICAST 0x40000000 /* multicast address */ |
| 64 | #define EMAC_UNICAST 0x20000000 /* unicast address */ |
| 65 | |
| 66 | struct rbf_t |
| 67 | { |
| 68 | unsigned int addr; |
| 69 | unsigned long size; |
| 70 | }; |
| 71 | |
| 72 | struct recv_desc_bufs |
| 73 | { |
| 74 | struct rbf_t descriptors[MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */ |
| 75 | char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ]; /* must be on long boundary */ |
| 76 | }; |
| 77 | |
| 78 | struct at91_private |
| 79 | { |
| 80 | struct net_device_stats stats; |
| 81 | struct mii_if_info mii; /* ethtool support */ |
| 82 | struct at91_eth_data board_data; /* board-specific configuration */ |
| 83 | |
| 84 | /* PHY */ |
| 85 | unsigned long phy_type; /* type of PHY (PHY_ID) */ |
| 86 | spinlock_t lock; /* lock for MDI interface */ |
| 87 | short phy_media; /* media interface type */ |
| 88 | unsigned short phy_address; /* 5-bit MDI address of PHY (0..31) */ |
| 89 | |
| 90 | /* Transmit */ |
| 91 | struct sk_buff *skb; /* holds skb until xmit interrupt completes */ |
| 92 | dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ |
| 93 | int skb_length; /* saved skb length for pci_unmap_single */ |
| 94 | |
| 95 | /* Receive */ |
| 96 | int rxBuffIndex; /* index into receive descriptor list */ |
| 97 | struct recv_desc_bufs *dlist; /* descriptor list address */ |
| 98 | struct recv_desc_bufs *dlist_phys; /* descriptor list physical address */ |
| 99 | }; |
| 100 | |
| 101 | #endif |