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Hong Xucce783c2012-04-17 14:26:29 +08001/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 gpio0 = &pioA;
24 gpio1 = &pioB;
25 gpio2 = &pioC;
26 gpio3 = &pioD;
27 tcb0 = &tcb0;
28 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020029 i2c0 = &i2c0;
30 i2c1 = &i2c1;
Hong Xucce783c2012-04-17 14:26:29 +080031 };
32 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 memory {
39 reg = <0x20000000 0x10000000>;
40 };
41
42 ahb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 apb {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020055 #interrupt-cells = <3>;
Hong Xucce783c2012-04-17 14:26:29 +080056 compatible = "atmel,at91rm9200-aic";
57 interrupt-controller;
58 reg = <0xfffff000 0x200>;
59 };
60
61 ramc0: ramc@ffffe800 {
62 compatible = "atmel,at91sam9g45-ddramc";
63 reg = <0xffffe800 0x200>;
64 };
65
66 pmc: pmc@fffffc00 {
67 compatible = "atmel,at91rm9200-pmc";
68 reg = <0xfffffc00 0x100>;
69 };
70
71 rstc@fffffe00 {
72 compatible = "atmel,at91sam9g45-rstc";
73 reg = <0xfffffe00 0x10>;
74 };
75
76 pit: timer@fffffe30 {
77 compatible = "atmel,at91sam9260-pit";
78 reg = <0xfffffe30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020079 interrupts = <1 4 7>;
Hong Xucce783c2012-04-17 14:26:29 +080080 };
81
82 shdwc@fffffe10 {
83 compatible = "atmel,at91sam9x5-shdwc";
84 reg = <0xfffffe10 0x10>;
85 };
86
Ludovic Desroches98731372012-11-19 12:23:36 +010087 mmc0: mmc@f0008000 {
88 compatible = "atmel,hsmci";
89 reg = <0xf0008000 0x600>;
90 interrupts = <12 4 0>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 status = "disabled";
94 };
95
Hong Xucce783c2012-04-17 14:26:29 +080096 tcb0: timer@f8008000 {
97 compatible = "atmel,at91sam9x5-tcb";
98 reg = <0xf8008000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020099 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800100 };
101
102 tcb1: timer@f800c000 {
103 compatible = "atmel,at91sam9x5-tcb";
104 reg = <0xf800c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200105 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800106 };
107
108 dma: dma-controller@ffffec00 {
109 compatible = "atmel,at91sam9g45-dma";
110 reg = <0xffffec00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200111 interrupts = <20 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800112 };
113
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800114 pinctrl@fffff400 {
115 #address-cells = <1>;
116 #size-cells = <1>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800117 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800118 ranges = <0xfffff400 0xfffff400 0x800>;
Hong Xucce783c2012-04-17 14:26:29 +0800119
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800120 atmel,mux-mask = <
121 /* A B C */
122 0xffffffff 0xffe07983 0x00000000 /* pioA */
123 0x00040000 0x00047e0f 0x00000000 /* pioB */
124 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
125 0x003fffff 0x003f8000 0x00000000 /* pioD */
126 >;
127
128 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800129 dbgu {
130 pinctrl_dbgu: dbgu-0 {
131 atmel,pins =
132 <0 9 0x1 0x0 /* PA9 periph A */
133 0 10 0x1 0x1>; /* PA10 periph with pullup */
134 };
135 };
136
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800137 usart0 {
138 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800139 atmel,pins =
140 <0 1 0x1 0x1 /* PA1 periph A with pullup */
141 0 0 0x1 0x0>; /* PA0 periph A */
142 };
143
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800144 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800145 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800146 <0 2 0x1 0x0>; /* PA2 periph A */
147 };
148
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <0 3 0x1 0x0>; /* PA3 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800152 };
153 };
154
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800155 usart1 {
156 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800157 atmel,pins =
158 <0 6 0x1 0x1 /* PA6 periph A with pullup */
159 0 5 0x1 0x0>; /* PA5 periph A */
160 };
161 };
162
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800163 usart2 {
164 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800165 atmel,pins =
166 <0 8 0x1 0x1 /* PA8 periph A with pullup */
167 0 7 0x1 0x0>; /* PA7 periph A */
168 };
169
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800170 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800171 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800172 <1 0 0x2 0x0>; /* PB0 periph B */
173 };
174
175 pinctrl_usart2_cts: usart2_cts-0 {
176 atmel,pins =
177 <1 1 0x2 0x0>; /* PB1 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800178 };
179 };
180
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800181 usart3 {
182 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800183 atmel,pins =
184 <2 23 0x2 0x1 /* PC23 periph B with pullup */
185 2 22 0x2 0x0>; /* PC22 periph B */
186 };
187
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800188 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800189 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800190 <2 24 0x2 0x0>; /* PC24 periph B */
191 };
192
193 pinctrl_usart3_cts: usart3_cts-0 {
194 atmel,pins =
195 <2 25 0x2 0x0>; /* PC25 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800196 };
197 };
198
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800199 uart0 {
200 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800201 atmel,pins =
202 <2 9 0x3 0x1 /* PC9 periph C with pullup */
203 2 8 0x3 0x0>; /* PC8 periph C */
204 };
205 };
206
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800207 uart1 {
208 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800209 atmel,pins =
210 <2 16 0x3 0x1 /* PC17 periph C with pullup */
211 2 17 0x3 0x0>; /* PC16 periph C */
212 };
213 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800214
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800215 nand {
216 pinctrl_nand: nand-0 {
217 atmel,pins =
218 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
219 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
220 };
221 };
222
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800223 pioA: gpio@fffff400 {
224 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
225 reg = <0xfffff400 0x200>;
226 interrupts = <2 4 1>;
227 #gpio-cells = <2>;
228 gpio-controller;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 };
Hong Xucce783c2012-04-17 14:26:29 +0800232
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800233 pioB: gpio@fffff600 {
234 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
235 reg = <0xfffff600 0x200>;
236 interrupts = <2 4 1>;
237 #gpio-cells = <2>;
238 gpio-controller;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 };
Hong Xucce783c2012-04-17 14:26:29 +0800242
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800243 pioC: gpio@fffff800 {
244 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
245 reg = <0xfffff800 0x200>;
246 interrupts = <3 4 1>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 pioD: gpio@fffffa00 {
254 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
255 reg = <0xfffffa00 0x200>;
256 interrupts = <3 4 1>;
257 #gpio-cells = <2>;
258 gpio-controller;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 };
Hong Xucce783c2012-04-17 14:26:29 +0800262 };
263
264 dbgu: serial@fffff200 {
265 compatible = "atmel,at91sam9260-usart";
266 reg = <0xfffff200 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200267 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_dbgu>;
Hong Xucce783c2012-04-17 14:26:29 +0800270 status = "disabled";
271 };
272
273 usart0: serial@f801c000 {
274 compatible = "atmel,at91sam9260-usart";
275 reg = <0xf801c000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200276 interrupts = <5 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800277 atmel,use-dma-rx;
278 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800279 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800280 pinctrl-0 = <&pinctrl_usart0>;
Hong Xucce783c2012-04-17 14:26:29 +0800281 status = "disabled";
282 };
283
284 usart1: serial@f8020000 {
285 compatible = "atmel,at91sam9260-usart";
286 reg = <0xf8020000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200287 interrupts = <6 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800288 atmel,use-dma-rx;
289 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800290 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800291 pinctrl-0 = <&pinctrl_usart1>;
Hong Xucce783c2012-04-17 14:26:29 +0800292 status = "disabled";
293 };
294
295 usart2: serial@f8024000 {
296 compatible = "atmel,at91sam9260-usart";
297 reg = <0xf8024000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200298 interrupts = <7 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800299 atmel,use-dma-rx;
300 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800301 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800302 pinctrl-0 = <&pinctrl_usart2>;
Hong Xucce783c2012-04-17 14:26:29 +0800303 status = "disabled";
304 };
305
306 usart3: serial@f8028000 {
307 compatible = "atmel,at91sam9260-usart";
308 reg = <0xf8028000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200309 interrupts = <8 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800310 atmel,use-dma-rx;
311 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800312 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800313 pinctrl-0 = <&pinctrl_usart3>;
Hong Xucce783c2012-04-17 14:26:29 +0800314 status = "disabled";
315 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200316
317 i2c0: i2c@f8010000 {
318 compatible = "atmel,at91sam9x5-i2c";
319 reg = <0xf8010000 0x100>;
320 interrupts = <9 4 6>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 status = "disabled";
324 };
325
326 i2c1: i2c@f8014000 {
327 compatible = "atmel,at91sam9x5-i2c";
328 reg = <0xf8014000 0x100>;
329 interrupts = <10 4 6>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 status = "disabled";
333 };
Hong Xucce783c2012-04-17 14:26:29 +0800334 };
335
336 nand0: nand@40000000 {
337 compatible = "atmel,at91rm9200-nand";
338 #address-cells = <1>;
339 #size-cells = <1>;
340 reg = < 0x40000000 0x10000000
341 0xffffe000 0x00000600
342 0xffffe600 0x00000200
343 0x00100000 0x00100000
344 >;
345 atmel,nand-addr-offset = <21>;
346 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_nand>;
Hong Xucce783c2012-04-17 14:26:29 +0800349 gpios = <&pioD 5 0
350 &pioD 4 0
351 0
352 >;
353 status = "disabled";
354 };
355
356 usb0: ohci@00500000 {
357 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
358 reg = <0x00500000 0x00100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200359 interrupts = <22 4 2>;
Hong Xucce783c2012-04-17 14:26:29 +0800360 status = "disabled";
361 };
362 };
363
364 i2c@0 {
365 compatible = "i2c-gpio";
366 gpios = <&pioA 30 0 /* sda */
367 &pioA 31 0 /* scl */
368 >;
369 i2c-gpio,sda-open-drain;
370 i2c-gpio,scl-open-drain;
371 i2c-gpio,delay-us = <2>; /* ~100 kHz */
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
376};