Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_CPUTYPE_H |
| 17 | #define __ASM_CPUTYPE_H |
| 18 | |
Javi Merino | 3e98fda | 2013-01-31 20:09:04 +0000 | [diff] [blame] | 19 | #define INVALID_HWID ULONG_MAX |
| 20 | |
Zi Shen Lim | 4e6f708 | 2014-06-07 01:55:27 +0100 | [diff] [blame] | 21 | #define MPIDR_UP_BITMASK (0x1 << 30) |
| 22 | #define MPIDR_MT_BITMASK (0x1 << 24) |
Javi Merino | 4c7aa00 | 2012-08-29 09:47:19 +0100 | [diff] [blame] | 23 | #define MPIDR_HWID_BITMASK 0xff00ffffff |
| 24 | |
Lorenzo Pieralisi | b058450 | 2013-08-05 15:24:27 +0100 | [diff] [blame] | 25 | #define MPIDR_LEVEL_BITS_SHIFT 3 |
| 26 | #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) |
| 27 | #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) |
| 28 | |
| 29 | #define MPIDR_LEVEL_SHIFT(level) \ |
| 30 | (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) |
| 31 | |
| 32 | #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ |
| 33 | ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) |
| 34 | |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 35 | #define read_cpuid(reg) ({ \ |
| 36 | u64 __val; \ |
Ard Biesheuvel | 148eb0a | 2013-12-16 21:04:35 +0000 | [diff] [blame] | 37 | asm("mrs %0, " #reg : "=r" (__val)); \ |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 38 | __val; \ |
| 39 | }) |
| 40 | |
Mark Rutland | 89c4a30 | 2014-07-16 16:32:43 +0100 | [diff] [blame] | 41 | #define MIDR_REVISION_MASK 0xf |
| 42 | #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) |
| 43 | #define MIDR_PARTNUM_SHIFT 4 |
| 44 | #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) |
| 45 | #define MIDR_PARTNUM(midr) \ |
| 46 | (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) |
| 47 | #define MIDR_ARCHITECTURE_SHIFT 16 |
| 48 | #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) |
| 49 | #define MIDR_ARCHITECTURE(midr) \ |
| 50 | (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) |
| 51 | #define MIDR_VARIANT_SHIFT 20 |
| 52 | #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) |
| 53 | #define MIDR_VARIANT(midr) \ |
| 54 | (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) |
| 55 | #define MIDR_IMPLEMENTOR_SHIFT 24 |
| 56 | #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) |
| 57 | #define MIDR_IMPLEMENTOR(midr) \ |
| 58 | (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) |
| 59 | |
Will Deacon | d5370f7 | 2016-02-02 12:46:24 +0000 | [diff] [blame^] | 60 | #define MIDR_CPU_MODEL(imp, partnum) \ |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 61 | (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ |
| 62 | (0xf << MIDR_ARCHITECTURE_SHIFT) | \ |
| 63 | ((partnum) << MIDR_PARTNUM_SHIFT)) |
| 64 | |
Will Deacon | d5370f7 | 2016-02-02 12:46:24 +0000 | [diff] [blame^] | 65 | #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ |
| 66 | MIDR_ARCHITECTURE_MASK) |
| 67 | |
| 68 | #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ |
| 69 | ({ \ |
| 70 | u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ |
| 71 | u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ |
| 72 | \ |
| 73 | _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ |
| 74 | }) |
| 75 | |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 76 | #define ARM_CPU_IMP_ARM 0x41 |
| 77 | #define ARM_CPU_IMP_APM 0x50 |
| 78 | #define ARM_CPU_IMP_CAVIUM 0x43 |
Marc Zyngier | d9c1951 | 2013-02-27 18:05:59 +0000 | [diff] [blame] | 79 | |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 80 | #define ARM_CPU_PART_AEM_V8 0xD0F |
| 81 | #define ARM_CPU_PART_FOUNDATION 0xD00 |
| 82 | #define ARM_CPU_PART_CORTEX_A57 0xD07 |
| 83 | #define ARM_CPU_PART_CORTEX_A53 0xD03 |
Marc Zyngier | d9c1951 | 2013-02-27 18:05:59 +0000 | [diff] [blame] | 84 | |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 85 | #define APM_CPU_PART_POTENZA 0x000 |
| 86 | |
| 87 | #define CAVIUM_CPU_PART_THUNDERX 0x0A1 |
Vinayak Kale | 4ad637a | 2013-04-24 10:06:59 +0100 | [diff] [blame] | 88 | |
Will Deacon | d5370f7 | 2016-02-02 12:46:24 +0000 | [diff] [blame^] | 89 | #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) |
| 90 | #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) |
| 91 | #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) |
| 92 | |
Javi Merino | 0359b0e | 2012-08-29 18:32:18 +0100 | [diff] [blame] | 93 | #ifndef __ASSEMBLY__ |
| 94 | |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 95 | /* |
| 96 | * The CPU ID never changes at run time, so we might as well tell the |
| 97 | * compiler that it's constant. Use this function to read the CPU ID |
| 98 | * rather than directly reading processor_id or read_cpuid() directly. |
| 99 | */ |
| 100 | static inline u32 __attribute_const__ read_cpuid_id(void) |
| 101 | { |
Ard Biesheuvel | 148eb0a | 2013-12-16 21:04:35 +0000 | [diff] [blame] | 102 | return read_cpuid(MIDR_EL1); |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 103 | } |
| 104 | |
Marc Zyngier | d9c1951 | 2013-02-27 18:05:59 +0000 | [diff] [blame] | 105 | static inline u64 __attribute_const__ read_cpuid_mpidr(void) |
| 106 | { |
Ard Biesheuvel | 148eb0a | 2013-12-16 21:04:35 +0000 | [diff] [blame] | 107 | return read_cpuid(MPIDR_EL1); |
Marc Zyngier | d9c1951 | 2013-02-27 18:05:59 +0000 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | static inline unsigned int __attribute_const__ read_cpuid_implementor(void) |
| 111 | { |
Mark Rutland | 89c4a30 | 2014-07-16 16:32:43 +0100 | [diff] [blame] | 112 | return MIDR_IMPLEMENTOR(read_cpuid_id()); |
Marc Zyngier | d9c1951 | 2013-02-27 18:05:59 +0000 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | static inline unsigned int __attribute_const__ read_cpuid_part_number(void) |
| 116 | { |
Mark Rutland | 89c4a30 | 2014-07-16 16:32:43 +0100 | [diff] [blame] | 117 | return MIDR_PARTNUM(read_cpuid_id()); |
Marc Zyngier | d9c1951 | 2013-02-27 18:05:59 +0000 | [diff] [blame] | 118 | } |
| 119 | |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 120 | static inline u32 __attribute_const__ read_cpuid_cachetype(void) |
| 121 | { |
Ard Biesheuvel | 148eb0a | 2013-12-16 21:04:35 +0000 | [diff] [blame] | 122 | return read_cpuid(CTR_EL0); |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 123 | } |
Javi Merino | 0359b0e | 2012-08-29 18:32:18 +0100 | [diff] [blame] | 124 | #endif /* __ASSEMBLY__ */ |
| 125 | |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 126 | #endif |