Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>. |
| 5 | * |
| 6 | * Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl> |
| 7 | * based on pm2fb.c |
| 8 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * Based on code written by: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 10 | * Sven Luther, <luther@dpt-info.u-strasbg.fr> |
| 11 | * Alan Hourihane, <alanh@fairlite.demon.co.uk> |
| 12 | * Russell King, <rmk@arm.linux.org.uk> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * Based on linux/drivers/video/skeletonfb.c: |
| 14 | * Copyright (C) 1997 Geert Uytterhoeven |
| 15 | * Based on linux/driver/video/pm2fb.c: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 16 | * Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) |
| 17 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | * |
| 19 | * This file is subject to the terms and conditions of the GNU General Public |
| 20 | * License. See the file COPYING in the main directory of this archive for |
| 21 | * more details. |
| 22 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | */ |
| 24 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <linux/module.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/errno.h> |
| 28 | #include <linux/string.h> |
| 29 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include <linux/delay.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <linux/fb.h> |
| 33 | #include <linux/init.h> |
| 34 | #include <linux/pci.h> |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 35 | #ifdef CONFIG_MTRR |
| 36 | #include <asm/mtrr.h> |
| 37 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | #include <video/pm3fb.h> |
| 40 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 41 | #if !defined(CONFIG_PCI) |
| 42 | #error "Only generic PCI cards supported." |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #endif |
| 44 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 45 | #undef PM3FB_MASTER_DEBUG |
| 46 | #ifdef PM3FB_MASTER_DEBUG |
| 47 | #define DPRINTK(a,b...) printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b) |
| 48 | #else |
| 49 | #define DPRINTK(a,b...) |
| 50 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 52 | #define PM3_PIXMAP_SIZE (2048 * 4) |
| 53 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 54 | /* |
| 55 | * Driver data |
| 56 | */ |
| 57 | static char *mode_option __devinitdata; |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 58 | static int noaccel __devinitdata = 0; |
| 59 | |
| 60 | /* mtrr option */ |
| 61 | #ifdef CONFIG_MTRR |
| 62 | static int nomtrr __devinitdata = 0; |
| 63 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 65 | /* |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 66 | * This structure defines the hardware state of the graphics card. Normally |
| 67 | * you place this in a header file in linux/include/video. This file usually |
| 68 | * also includes register information. That allows other driver subsystems |
| 69 | * and userland applications the ability to use the same header file to |
| 70 | * avoid duplicate work and easy porting of software. |
| 71 | */ |
| 72 | struct pm3_par { |
| 73 | unsigned char __iomem *v_regs;/* virtual address of p_regs */ |
| 74 | u32 video; /* video flags before blanking */ |
| 75 | u32 base; /* screen base (xoffset+yoffset) in 128 bits unit */ |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 76 | u32 palette[16]; |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 77 | int mtrr_handle; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | }; |
| 79 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 80 | /* |
| 81 | * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo |
| 82 | * if we don't use modedb. If we do use modedb see pm3fb_init how to use it |
| 83 | * to get a fb_var_screeninfo. Otherwise define a default var as well. |
| 84 | */ |
| 85 | static struct fb_fix_screeninfo pm3fb_fix __devinitdata = { |
| 86 | .id = "Permedia3", |
| 87 | .type = FB_TYPE_PACKED_PIXELS, |
| 88 | .visual = FB_VISUAL_PSEUDOCOLOR, |
| 89 | .xpanstep = 1, |
| 90 | .ypanstep = 1, |
| 91 | .ywrapstep = 0, |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 92 | .accel = FB_ACCEL_3DLABS_PERMEDIA3, |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | /* |
| 96 | * Utility functions |
| 97 | */ |
| 98 | |
| 99 | static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 101 | return fb_readl(par->v_regs + off); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | } |
| 103 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 104 | static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 106 | fb_writel(v, par->v_regs + off); |
| 107 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 109 | static inline void PM3_WAIT(struct pm3_par *par, u32 n) |
| 110 | { |
| 111 | while (PM3_READ_REG(par, PM3InFIFOSpace) < n); |
| 112 | } |
| 113 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 114 | static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | { |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 116 | PM3_WAIT(par, 3); |
| 117 | PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff); |
| 118 | PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 119 | wmb(); |
| 120 | PM3_WRITE_REG(par, PM3RD_IndexedData, v); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 121 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | } |
| 123 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 124 | static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno, |
| 125 | unsigned char r, unsigned char g, unsigned char b) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | { |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 127 | PM3_WAIT(par, 4); |
| 128 | PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno); |
| 129 | wmb(); |
| 130 | PM3_WRITE_REG(par, PM3RD_PaletteData, r); |
| 131 | wmb(); |
| 132 | PM3_WRITE_REG(par, PM3RD_PaletteData, g); |
| 133 | wmb(); |
| 134 | PM3_WRITE_REG(par, PM3RD_PaletteData, b); |
| 135 | wmb(); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void pm3fb_clear_colormap(struct pm3_par *par, |
| 139 | unsigned char r, unsigned char g, unsigned char b) |
| 140 | { |
| 141 | int i; |
| 142 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 143 | for (i = 0; i < 256 ; i++) |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 144 | pm3fb_set_color(par, i, r, g, b); |
| 145 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | } |
| 147 | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 148 | /* Calculating various clock parameters */ |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 149 | static void pm3fb_calculate_clock(unsigned long reqclock, |
| 150 | unsigned char *prescale, |
| 151 | unsigned char *feedback, |
| 152 | unsigned char *postscale) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | { |
| 154 | int f, pre, post; |
| 155 | unsigned long freq; |
| 156 | long freqerr = 1000; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 157 | long currerr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | |
| 159 | for (f = 1; f < 256; f++) { |
| 160 | for (pre = 1; pre < 256; pre++) { |
| 161 | for (post = 0; post < 5; post++) { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 162 | freq = ((2*PM3_REF_CLOCK * f) >> post) / pre; |
| 163 | currerr = (reqclock > freq) |
| 164 | ? reqclock - freq |
| 165 | : freq - reqclock; |
| 166 | if (currerr < freqerr) { |
| 167 | freqerr = currerr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | *feedback = f; |
| 169 | *prescale = pre; |
| 170 | *postscale = post; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | } |
| 172 | } |
| 173 | } |
| 174 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | } |
| 176 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 177 | static inline int pm3fb_depth(const struct fb_var_screeninfo *var) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | { |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 179 | if (var->bits_per_pixel == 16) |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 180 | return var->red.length + var->green.length |
| 181 | + var->blue.length; |
| 182 | |
| 183 | return var->bits_per_pixel; |
| 184 | } |
| 185 | |
| 186 | static inline int pm3fb_shift_bpp(unsigned bpp, int v) |
| 187 | { |
| 188 | switch (bpp) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | case 8: |
| 190 | return (v >> 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 191 | case 16: |
| 192 | return (v >> 3); |
| 193 | case 32: |
| 194 | return (v >> 2); |
| 195 | } |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 196 | DPRINTK("Unsupported depth %u\n", bpp); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 197 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | } |
| 199 | |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 200 | /* acceleration */ |
| 201 | static int pm3fb_sync(struct fb_info *info) |
| 202 | { |
| 203 | struct pm3_par *par = info->par; |
| 204 | |
| 205 | PM3_WAIT(par, 2); |
| 206 | PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync); |
| 207 | PM3_WRITE_REG(par, PM3Sync, 0); |
| 208 | mb(); |
| 209 | do { |
| 210 | while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0); |
| 211 | rmb(); |
| 212 | } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag); |
| 213 | |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | static void pm3fb_init_engine(struct fb_info *info) |
| 218 | { |
| 219 | struct pm3_par *par = info->par; |
| 220 | const u32 width = (info->var.xres_virtual + 7) & ~7; |
| 221 | |
| 222 | PM3_WAIT(par, 50); |
| 223 | PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync); |
| 224 | PM3_WRITE_REG(par, PM3StatisticMode, 0x0); |
| 225 | PM3_WRITE_REG(par, PM3DeltaMode, 0x0); |
| 226 | PM3_WRITE_REG(par, PM3RasterizerMode, 0x0); |
| 227 | PM3_WRITE_REG(par, PM3ScissorMode, 0x0); |
| 228 | PM3_WRITE_REG(par, PM3LineStippleMode, 0x0); |
| 229 | PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0); |
| 230 | PM3_WRITE_REG(par, PM3GIDMode, 0x0); |
| 231 | PM3_WRITE_REG(par, PM3DepthMode, 0x0); |
| 232 | PM3_WRITE_REG(par, PM3StencilMode, 0x0); |
| 233 | PM3_WRITE_REG(par, PM3StencilData, 0x0); |
| 234 | PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0); |
| 235 | PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0); |
| 236 | PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0); |
| 237 | PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0); |
| 238 | PM3_WRITE_REG(par, PM3TextureReadMode, 0x0); |
| 239 | PM3_WRITE_REG(par, PM3LUTMode, 0x0); |
| 240 | PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0); |
| 241 | PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0); |
| 242 | PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0); |
| 243 | PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0); |
| 244 | PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0); |
| 245 | PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0); |
| 246 | PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0); |
| 247 | PM3_WRITE_REG(par, PM3FogMode, 0x0); |
| 248 | PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0); |
| 249 | PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0); |
| 250 | PM3_WRITE_REG(par, PM3AntialiasMode, 0x0); |
| 251 | PM3_WRITE_REG(par, PM3YUVMode, 0x0); |
| 252 | PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0); |
| 253 | PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0); |
| 254 | PM3_WRITE_REG(par, PM3DitherMode, 0x0); |
| 255 | PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0); |
| 256 | PM3_WRITE_REG(par, PM3RouterMode, 0x0); |
| 257 | PM3_WRITE_REG(par, PM3Window, 0x0); |
| 258 | |
| 259 | PM3_WRITE_REG(par, PM3Config2D, 0x0); |
| 260 | |
| 261 | PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff); |
| 262 | |
| 263 | PM3_WRITE_REG(par, PM3XBias, 0x0); |
| 264 | PM3_WRITE_REG(par, PM3YBias, 0x0); |
| 265 | PM3_WRITE_REG(par, PM3DeltaControl, 0x0); |
| 266 | |
| 267 | PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff); |
| 268 | |
| 269 | PM3_WRITE_REG(par, PM3FBDestReadEnables, |
| 270 | PM3FBDestReadEnables_E(0xff) | |
| 271 | PM3FBDestReadEnables_R(0xff) | |
| 272 | PM3FBDestReadEnables_ReferenceAlpha(0xff)); |
| 273 | PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0); |
| 274 | PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0); |
| 275 | PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0, |
| 276 | PM3FBDestReadBufferWidth_Width(width)); |
| 277 | |
| 278 | PM3_WRITE_REG(par, PM3FBDestReadMode, |
| 279 | PM3FBDestReadMode_ReadEnable | |
| 280 | PM3FBDestReadMode_Enable0); |
| 281 | PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0); |
| 282 | PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0); |
| 283 | PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth, |
| 284 | PM3FBSourceReadBufferWidth_Width(width)); |
| 285 | PM3_WRITE_REG(par, PM3FBSourceReadMode, |
| 286 | PM3FBSourceReadMode_Blocking | |
| 287 | PM3FBSourceReadMode_ReadEnable); |
| 288 | |
| 289 | PM3_WAIT(par, 2); |
| 290 | { |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 291 | /* invert bits in bitmask */ |
| 292 | unsigned long rm = 1 | (3 << 7); |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 293 | switch (info->var.bits_per_pixel) { |
| 294 | case 8: |
| 295 | PM3_WRITE_REG(par, PM3PixelSize, |
| 296 | PM3PixelSize_GLOBAL_8BIT); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 297 | #ifdef __BIG_ENDIAN |
| 298 | rm |= 3 << 15; |
| 299 | #endif |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 300 | break; |
| 301 | case 16: |
| 302 | PM3_WRITE_REG(par, PM3PixelSize, |
| 303 | PM3PixelSize_GLOBAL_16BIT); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 304 | #ifdef __BIG_ENDIAN |
| 305 | rm |= 2 << 15; |
| 306 | #endif |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 307 | break; |
| 308 | case 32: |
| 309 | PM3_WRITE_REG(par, PM3PixelSize, |
| 310 | PM3PixelSize_GLOBAL_32BIT); |
| 311 | break; |
| 312 | default: |
| 313 | DPRINTK(1, "Unsupported depth %d\n", |
| 314 | info->var.bits_per_pixel); |
| 315 | break; |
| 316 | } |
| 317 | PM3_WRITE_REG(par, PM3RasterizerMode, rm); |
| 318 | } |
| 319 | |
| 320 | PM3_WAIT(par, 20); |
| 321 | PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff); |
| 322 | PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff); |
| 323 | PM3_WRITE_REG(par, PM3FBWriteMode, |
| 324 | PM3FBWriteMode_WriteEnable | |
| 325 | PM3FBWriteMode_OpaqueSpan | |
| 326 | PM3FBWriteMode_Enable0); |
| 327 | PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0); |
| 328 | PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0); |
| 329 | PM3_WRITE_REG(par, PM3FBWriteBufferWidth0, |
| 330 | PM3FBWriteBufferWidth_Width(width)); |
| 331 | |
| 332 | PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0); |
| 333 | { |
| 334 | /* size in lines of FB */ |
| 335 | unsigned long sofb = info->screen_size / |
| 336 | info->fix.line_length; |
| 337 | if (sofb > 4095) |
| 338 | PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095); |
| 339 | else |
| 340 | PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb); |
| 341 | |
| 342 | switch (info->var.bits_per_pixel) { |
| 343 | case 8: |
| 344 | PM3_WRITE_REG(par, PM3DitherMode, |
| 345 | (1 << 10) | (2 << 3)); |
| 346 | break; |
| 347 | case 16: |
| 348 | PM3_WRITE_REG(par, PM3DitherMode, |
| 349 | (1 << 10) | (1 << 3)); |
| 350 | break; |
| 351 | case 32: |
| 352 | PM3_WRITE_REG(par, PM3DitherMode, |
| 353 | (1 << 10) | (0 << 3)); |
| 354 | break; |
| 355 | default: |
| 356 | DPRINTK(1, "Unsupported depth %d\n", |
| 357 | info->current_par->depth); |
| 358 | break; |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | PM3_WRITE_REG(par, PM3dXDom, 0x0); |
| 363 | PM3_WRITE_REG(par, PM3dXSub, 0x0); |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 364 | PM3_WRITE_REG(par, PM3dY, 1 << 16); |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 365 | PM3_WRITE_REG(par, PM3StartXDom, 0x0); |
| 366 | PM3_WRITE_REG(par, PM3StartXSub, 0x0); |
| 367 | PM3_WRITE_REG(par, PM3StartY, 0x0); |
| 368 | PM3_WRITE_REG(par, PM3Count, 0x0); |
| 369 | |
| 370 | /* Disable LocalBuffer. better safe than sorry */ |
| 371 | PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0); |
| 372 | PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0); |
| 373 | PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0); |
| 374 | PM3_WRITE_REG(par, PM3LBWriteMode, 0x0); |
| 375 | |
| 376 | pm3fb_sync(info); |
| 377 | } |
| 378 | |
| 379 | static void pm3fb_fillrect (struct fb_info *info, |
| 380 | const struct fb_fillrect *region) |
| 381 | { |
| 382 | struct pm3_par *par = info->par; |
| 383 | struct fb_fillrect modded; |
| 384 | int vxres, vyres; |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 385 | int rop; |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 386 | u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? |
| 387 | ((u32*)info->pseudo_palette)[region->color] : region->color; |
| 388 | |
| 389 | if (info->state != FBINFO_STATE_RUNNING) |
| 390 | return; |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 391 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 392 | cfb_fillrect(info, region); |
| 393 | return; |
| 394 | } |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 395 | if (region->rop == ROP_COPY ) |
| 396 | rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */ |
| 397 | else |
| 398 | rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */ |
| 399 | PM3Config2D_FBDestReadEnable; |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 400 | |
| 401 | vxres = info->var.xres_virtual; |
| 402 | vyres = info->var.yres_virtual; |
| 403 | |
| 404 | memcpy(&modded, region, sizeof(struct fb_fillrect)); |
| 405 | |
| 406 | if(!modded.width || !modded.height || |
| 407 | modded.dx >= vxres || modded.dy >= vyres) |
| 408 | return; |
| 409 | |
| 410 | if(modded.dx + modded.width > vxres) |
| 411 | modded.width = vxres - modded.dx; |
| 412 | if(modded.dy + modded.height > vyres) |
| 413 | modded.height = vyres - modded.dy; |
| 414 | |
| 415 | if(info->var.bits_per_pixel == 8) |
| 416 | color |= color << 8; |
| 417 | if(info->var.bits_per_pixel <= 16) |
| 418 | color |= color << 16; |
| 419 | |
| 420 | PM3_WAIT(par, 4); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 421 | /* ROP Ox3 is GXcopy */ |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 422 | PM3_WRITE_REG(par, PM3Config2D, |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 423 | PM3Config2D_UseConstantSource | |
| 424 | PM3Config2D_ForegroundROPEnable | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 425 | rop | |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 426 | PM3Config2D_FBWriteEnable); |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 427 | |
| 428 | PM3_WRITE_REG(par, PM3ForegroundColor, color); |
| 429 | |
| 430 | PM3_WRITE_REG(par, PM3RectanglePosition, |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 431 | PM3RectanglePosition_XOffset(modded.dx) | |
| 432 | PM3RectanglePosition_YOffset(modded.dy)); |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 433 | |
| 434 | PM3_WRITE_REG(par, PM3Render2D, |
| 435 | PM3Render2D_XPositive | |
| 436 | PM3Render2D_YPositive | |
| 437 | PM3Render2D_Operation_Normal | |
| 438 | PM3Render2D_SpanOperation | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 439 | PM3Render2D_Width(modded.width) | |
| 440 | PM3Render2D_Height(modded.height)); |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 441 | } |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 442 | |
| 443 | static void pm3fb_copyarea(struct fb_info *info, |
| 444 | const struct fb_copyarea *area) |
| 445 | { |
| 446 | struct pm3_par *par = info->par; |
| 447 | struct fb_copyarea modded; |
| 448 | u32 vxres, vyres; |
| 449 | int x_align, o_x, o_y; |
| 450 | |
| 451 | if (info->state != FBINFO_STATE_RUNNING) |
| 452 | return; |
| 453 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
| 454 | cfb_copyarea(info, area); |
| 455 | return; |
| 456 | } |
| 457 | |
| 458 | memcpy(&modded, area, sizeof(struct fb_copyarea)); |
| 459 | |
| 460 | vxres = info->var.xres_virtual; |
| 461 | vyres = info->var.yres_virtual; |
| 462 | |
| 463 | if(!modded.width || !modded.height || |
| 464 | modded.sx >= vxres || modded.sy >= vyres || |
| 465 | modded.dx >= vxres || modded.dy >= vyres) |
| 466 | return; |
| 467 | |
| 468 | if(modded.sx + modded.width > vxres) |
| 469 | modded.width = vxres - modded.sx; |
| 470 | if(modded.dx + modded.width > vxres) |
| 471 | modded.width = vxres - modded.dx; |
| 472 | if(modded.sy + modded.height > vyres) |
| 473 | modded.height = vyres - modded.sy; |
| 474 | if(modded.dy + modded.height > vyres) |
| 475 | modded.height = vyres - modded.dy; |
| 476 | |
| 477 | o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */ |
| 478 | o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */ |
| 479 | |
| 480 | x_align = (modded.sx & 0x1f); |
| 481 | |
| 482 | PM3_WAIT(par, 6); |
| 483 | |
| 484 | PM3_WRITE_REG(par, PM3Config2D, |
| 485 | PM3Config2D_UserScissorEnable | |
| 486 | PM3Config2D_ForegroundROPEnable | |
| 487 | PM3Config2D_Blocking | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 488 | PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */ |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 489 | PM3Config2D_FBWriteEnable); |
| 490 | |
| 491 | PM3_WRITE_REG(par, PM3ScissorMinXY, |
| 492 | ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff)); |
| 493 | PM3_WRITE_REG(par, PM3ScissorMaxXY, |
| 494 | (((modded.dy + modded.height) & 0x0fff) << 16) | |
| 495 | ((modded.dx + modded.width) & 0x0fff)); |
| 496 | |
| 497 | PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, |
| 498 | PM3FBSourceReadBufferOffset_XOffset(o_x) | |
| 499 | PM3FBSourceReadBufferOffset_YOffset(o_y)); |
| 500 | |
| 501 | PM3_WRITE_REG(par, PM3RectanglePosition, |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 502 | PM3RectanglePosition_XOffset(modded.dx - x_align) | |
| 503 | PM3RectanglePosition_YOffset(modded.dy)); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 504 | |
| 505 | PM3_WRITE_REG(par, PM3Render2D, |
| 506 | ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) | |
| 507 | ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) | |
| 508 | PM3Render2D_Operation_Normal | |
| 509 | PM3Render2D_SpanOperation | |
| 510 | PM3Render2D_FBSourceReadEnable | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 511 | PM3Render2D_Width(modded.width + x_align) | |
| 512 | PM3Render2D_Height(modded.height)); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image) |
| 516 | { |
| 517 | struct pm3_par *par = info->par; |
| 518 | u32 height = image->height; |
| 519 | u32 fgx, bgx; |
| 520 | const u32 *src = (const u32*)image->data; |
| 521 | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 522 | if (info->state != FBINFO_STATE_RUNNING) |
| 523 | return; |
| 524 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
| 525 | cfb_imageblit(info, image); |
| 526 | return; |
| 527 | } |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 528 | switch (info->fix.visual) { |
| 529 | case FB_VISUAL_PSEUDOCOLOR: |
| 530 | fgx = image->fg_color; |
| 531 | bgx = image->bg_color; |
| 532 | break; |
| 533 | case FB_VISUAL_TRUECOLOR: |
| 534 | default: |
| 535 | fgx = par->palette[image->fg_color]; |
| 536 | bgx = par->palette[image->bg_color]; |
| 537 | break; |
| 538 | } |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 539 | if (image->depth != 1) { |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 540 | return cfb_imageblit(info, image); |
| 541 | } |
| 542 | if (info->var.bits_per_pixel == 8) { |
| 543 | fgx |= fgx << 8; |
| 544 | bgx |= bgx << 8; |
| 545 | } |
| 546 | if (info->var.bits_per_pixel <= 16) { |
| 547 | fgx |= fgx << 16; |
| 548 | bgx |= bgx << 16; |
| 549 | } |
| 550 | |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 551 | PM3_WAIT(par, 7); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 552 | |
| 553 | PM3_WRITE_REG(par, PM3ForegroundColor, fgx); |
| 554 | PM3_WRITE_REG(par, PM3BackgroundColor, bgx); |
| 555 | |
| 556 | /* ROP Ox3 is GXcopy */ |
| 557 | PM3_WRITE_REG(par, PM3Config2D, |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 558 | PM3Config2D_UserScissorEnable | |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 559 | PM3Config2D_UseConstantSource | |
| 560 | PM3Config2D_ForegroundROPEnable | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 561 | PM3Config2D_ForegroundROP(0x3) | |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 562 | PM3Config2D_OpaqueSpan | |
| 563 | PM3Config2D_FBWriteEnable); |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 564 | PM3_WRITE_REG(par, PM3ScissorMinXY, |
| 565 | ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff)); |
| 566 | PM3_WRITE_REG(par, PM3ScissorMaxXY, |
| 567 | (((image->dy + image->height) & 0x0fff) << 16) | |
| 568 | ((image->dx + image->width) & 0x0fff)); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 569 | PM3_WRITE_REG(par, PM3RectanglePosition, |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 570 | PM3RectanglePosition_XOffset(image->dx) | |
| 571 | PM3RectanglePosition_YOffset(image->dy)); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 572 | PM3_WRITE_REG(par, PM3Render2D, |
| 573 | PM3Render2D_XPositive | |
| 574 | PM3Render2D_YPositive | |
| 575 | PM3Render2D_Operation_SyncOnBitMask | |
| 576 | PM3Render2D_SpanOperation | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 577 | PM3Render2D_Width(image->width) | |
| 578 | PM3Render2D_Height(image->height)); |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 579 | |
| 580 | |
| 581 | while (height--) { |
Krzysztof Helt | c79ba28 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 582 | int width = ((image->width + 7) >> 3) |
| 583 | + info->pixmap.scan_align - 1; |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 584 | width >>= 2; |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 585 | |
| 586 | while (width >= PM3_FIFO_SIZE) { |
| 587 | int i = PM3_FIFO_SIZE - 1; |
| 588 | |
| 589 | PM3_WAIT(par, PM3_FIFO_SIZE); |
| 590 | while (i--) { |
| 591 | PM3_WRITE_REG(par, PM3BitMaskPattern, *src); |
| 592 | src++; |
| 593 | } |
| 594 | width -= PM3_FIFO_SIZE - 1; |
| 595 | } |
| 596 | |
| 597 | PM3_WAIT(par, width + 1); |
| 598 | while (width--) { |
| 599 | PM3_WRITE_REG(par, PM3BitMaskPattern, *src); |
| 600 | src++; |
| 601 | } |
| 602 | } |
| 603 | } |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 604 | /* end of acceleration functions */ |
| 605 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | /* write the mode to registers */ |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 607 | static void pm3fb_write_mode(struct fb_info *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 609 | struct pm3_par *par = info->par; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | char tempsync = 0x00, tempmisc = 0x00; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 611 | const u32 hsstart = info->var.right_margin; |
| 612 | const u32 hsend = hsstart + info->var.hsync_len; |
| 613 | const u32 hbend = hsend + info->var.left_margin; |
| 614 | const u32 xres = (info->var.xres + 31) & ~31; |
| 615 | const u32 htotal = xres + hbend; |
| 616 | const u32 vsstart = info->var.lower_margin; |
| 617 | const u32 vsend = vsstart + info->var.vsync_len; |
| 618 | const u32 vbend = vsend + info->var.upper_margin; |
| 619 | const u32 vtotal = info->var.yres + vbend; |
| 620 | const u32 width = (info->var.xres_virtual + 7) & ~7; |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 621 | const unsigned bpp = info->var.bits_per_pixel; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 623 | PM3_WAIT(par, 20); |
| 624 | PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff); |
| 625 | PM3_WRITE_REG(par, PM3Aperture0, 0x00000000); |
| 626 | PM3_WRITE_REG(par, PM3Aperture1, 0x00000000); |
| 627 | PM3_WRITE_REG(par, PM3FIFODis, 0x00000007); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 629 | PM3_WRITE_REG(par, PM3HTotal, |
| 630 | pm3fb_shift_bpp(bpp, htotal - 1)); |
| 631 | PM3_WRITE_REG(par, PM3HsEnd, |
| 632 | pm3fb_shift_bpp(bpp, hsend)); |
| 633 | PM3_WRITE_REG(par, PM3HsStart, |
| 634 | pm3fb_shift_bpp(bpp, hsstart)); |
| 635 | PM3_WRITE_REG(par, PM3HbEnd, |
| 636 | pm3fb_shift_bpp(bpp, hbend)); |
| 637 | PM3_WRITE_REG(par, PM3HgEnd, |
| 638 | pm3fb_shift_bpp(bpp, hbend)); |
| 639 | PM3_WRITE_REG(par, PM3ScreenStride, |
| 640 | pm3fb_shift_bpp(bpp, width)); |
| 641 | PM3_WRITE_REG(par, PM3VTotal, vtotal - 1); |
| 642 | PM3_WRITE_REG(par, PM3VsEnd, vsend - 1); |
| 643 | PM3_WRITE_REG(par, PM3VsStart, vsstart - 1); |
| 644 | PM3_WRITE_REG(par, PM3VbEnd, vbend); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 645 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 646 | switch (bpp) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | case 8: |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 648 | PM3_WRITE_REG(par, PM3ByAperture1Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 649 | PM3ByApertureMode_PIXELSIZE_8BIT); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 650 | PM3_WRITE_REG(par, PM3ByAperture2Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | PM3ByApertureMode_PIXELSIZE_8BIT); |
| 652 | break; |
| 653 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | case 16: |
| 655 | #ifndef __BIG_ENDIAN |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 656 | PM3_WRITE_REG(par, PM3ByAperture1Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 657 | PM3ByApertureMode_PIXELSIZE_16BIT); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 658 | PM3_WRITE_REG(par, PM3ByAperture2Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 659 | PM3ByApertureMode_PIXELSIZE_16BIT); |
| 660 | #else |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 661 | PM3_WRITE_REG(par, PM3ByAperture1Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | PM3ByApertureMode_PIXELSIZE_16BIT | |
| 663 | PM3ByApertureMode_BYTESWAP_BADC); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 664 | PM3_WRITE_REG(par, PM3ByAperture2Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | PM3ByApertureMode_PIXELSIZE_16BIT | |
| 666 | PM3ByApertureMode_BYTESWAP_BADC); |
| 667 | #endif /* ! __BIG_ENDIAN */ |
| 668 | break; |
| 669 | |
| 670 | case 32: |
| 671 | #ifndef __BIG_ENDIAN |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 672 | PM3_WRITE_REG(par, PM3ByAperture1Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 673 | PM3ByApertureMode_PIXELSIZE_32BIT); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 674 | PM3_WRITE_REG(par, PM3ByAperture2Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | PM3ByApertureMode_PIXELSIZE_32BIT); |
| 676 | #else |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 677 | PM3_WRITE_REG(par, PM3ByAperture1Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 678 | PM3ByApertureMode_PIXELSIZE_32BIT | |
| 679 | PM3ByApertureMode_BYTESWAP_DCBA); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 680 | PM3_WRITE_REG(par, PM3ByAperture2Mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 681 | PM3ByApertureMode_PIXELSIZE_32BIT | |
| 682 | PM3ByApertureMode_BYTESWAP_DCBA); |
| 683 | #endif /* ! __BIG_ENDIAN */ |
| 684 | break; |
| 685 | |
| 686 | default: |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 687 | DPRINTK("Unsupported depth %d\n", bpp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | break; |
| 689 | } |
| 690 | |
| 691 | /* |
| 692 | * Oxygen VX1 - it appears that setting PM3VideoControl and |
| 693 | * then PM3RD_SyncControl to the same SYNC settings undoes |
| 694 | * any net change - they seem to xor together. Only set the |
| 695 | * sync options in PM3RD_SyncControl. --rmk |
| 696 | */ |
| 697 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 698 | unsigned int video = par->video; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | |
| 700 | video &= ~(PM3VideoControl_HSYNC_MASK | |
| 701 | PM3VideoControl_VSYNC_MASK); |
| 702 | video |= PM3VideoControl_HSYNC_ACTIVE_HIGH | |
| 703 | PM3VideoControl_VSYNC_ACTIVE_HIGH; |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 704 | PM3_WRITE_REG(par, PM3VideoControl, video); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | } |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 706 | PM3_WRITE_REG(par, PM3VClkCtl, |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 707 | (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC)); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 708 | PM3_WRITE_REG(par, PM3ScreenBase, par->base); |
| 709 | PM3_WRITE_REG(par, PM3ChipConfig, |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 710 | (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 711 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 712 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 714 | unsigned char uninitialized_var(m); /* ClkPreScale */ |
| 715 | unsigned char uninitialized_var(n); /* ClkFeedBackScale */ |
| 716 | unsigned char uninitialized_var(p); /* ClkPostScale */ |
| 717 | unsigned long pixclock = PICOS2KHZ(info->var.pixclock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 718 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 719 | (void)pm3fb_calculate_clock(pixclock, &m, &n, &p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 721 | DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n", |
| 722 | pixclock, (int) m, (int) n, (int) p); |
| 723 | |
| 724 | PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m); |
| 725 | PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n); |
| 726 | PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | } |
| 728 | /* |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 729 | PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | */ |
| 731 | /* |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 732 | PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | */ |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 734 | if ((par->video & PM3VideoControl_HSYNC_MASK) == |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | PM3VideoControl_HSYNC_ACTIVE_HIGH) |
| 736 | tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 737 | if ((par->video & PM3VideoControl_VSYNC_MASK) == |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | PM3VideoControl_VSYNC_ACTIVE_HIGH) |
| 739 | tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 741 | PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync); |
| 742 | DPRINTK("PM3RD_SyncControl: %d\n", tempsync); |
| 743 | |
| 744 | PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00); |
| 745 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 746 | switch (pm3fb_depth(&info->var)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | case 8: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 748 | PM3_WRITE_DAC_REG(par, PM3RD_PixelSize, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | PM3RD_PixelSize_8_BIT_PIXELS); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 750 | PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | PM3RD_ColorFormat_CI8_COLOR | |
| 752 | PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW); |
| 753 | tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE; |
| 754 | break; |
| 755 | case 12: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 756 | PM3_WRITE_DAC_REG(par, PM3RD_PixelSize, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 757 | PM3RD_PixelSize_16_BIT_PIXELS); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 758 | PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | PM3RD_ColorFormat_4444_COLOR | |
| 760 | PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW | |
| 761 | PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE); |
| 762 | tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE | |
| 763 | PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 764 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 765 | case 15: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 766 | PM3_WRITE_DAC_REG(par, PM3RD_PixelSize, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | PM3RD_PixelSize_16_BIT_PIXELS); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 768 | PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 769 | PM3RD_ColorFormat_5551_FRONT_COLOR | |
| 770 | PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW | |
| 771 | PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE); |
| 772 | tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE | |
| 773 | PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 774 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | case 16: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 776 | PM3_WRITE_DAC_REG(par, PM3RD_PixelSize, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 777 | PM3RD_PixelSize_16_BIT_PIXELS); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 778 | PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | PM3RD_ColorFormat_565_FRONT_COLOR | |
| 780 | PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW | |
| 781 | PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE); |
| 782 | tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE | |
| 783 | PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE; |
| 784 | break; |
| 785 | case 32: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 786 | PM3_WRITE_DAC_REG(par, PM3RD_PixelSize, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | PM3RD_PixelSize_32_BIT_PIXELS); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 788 | PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | PM3RD_ColorFormat_8888_COLOR | |
| 790 | PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW); |
| 791 | tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE | |
| 792 | PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE; |
| 793 | break; |
| 794 | } |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 795 | PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 796 | } |
| 797 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 798 | /* |
| 799 | * hardware independent functions |
| 800 | */ |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 801 | static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 803 | u32 lpitch; |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 804 | unsigned bpp = var->red.length + var->green.length |
| 805 | + var->blue.length + var->transp.length; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 806 | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 807 | if (bpp != var->bits_per_pixel) { |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 808 | /* set predefined mode for bits_per_pixel settings */ |
| 809 | |
| 810 | switch(var->bits_per_pixel) { |
| 811 | case 8: |
| 812 | var->red.length = var->green.length = var->blue.length = 8; |
| 813 | var->red.offset = var->green.offset = var->blue.offset = 0; |
| 814 | var->transp.offset = 0; |
| 815 | var->transp.length = 0; |
| 816 | break; |
| 817 | case 16: |
| 818 | var->red.length = var->blue.length = 5; |
| 819 | var->green.length = 6; |
| 820 | var->transp.length = 0; |
| 821 | break; |
| 822 | case 32: |
| 823 | var->red.length = var->green.length = var->blue.length = 8; |
| 824 | var->transp.length = 8; |
| 825 | break; |
| 826 | default: |
| 827 | DPRINTK("depth not supported: %u\n", var->bits_per_pixel); |
| 828 | return -EINVAL; |
| 829 | } |
| 830 | } |
| 831 | /* it is assumed BGRA order */ |
| 832 | if (var->bits_per_pixel > 8 ) |
| 833 | { |
| 834 | var->blue.offset = 0; |
| 835 | var->green.offset = var->blue.length; |
| 836 | var->red.offset = var->green.offset + var->green.length; |
| 837 | var->transp.offset = var->red.offset + var->red.length; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 838 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | var->height = var->width = -1; |
| 840 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 841 | if (var->xres != var->xres_virtual) { |
| 842 | DPRINTK("virtual x resolution != physical x resolution not supported\n"); |
| 843 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 844 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 845 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 846 | if (var->yres > var->yres_virtual) { |
| 847 | DPRINTK("virtual y resolution < physical y resolution not possible\n"); |
| 848 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 849 | } |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 850 | |
| 851 | if (var->xoffset) { |
| 852 | DPRINTK("xoffset not supported\n"); |
| 853 | return -EINVAL; |
| 854 | } |
| 855 | |
| 856 | if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { |
| 857 | DPRINTK("interlace not supported\n"); |
| 858 | return -EINVAL; |
| 859 | } |
| 860 | |
| 861 | var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */ |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 862 | lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 863 | |
| 864 | if (var->xres < 200 || var->xres > 2048) { |
| 865 | DPRINTK("width not supported: %u\n", var->xres); |
| 866 | return -EINVAL; |
| 867 | } |
| 868 | |
| 869 | if (var->yres < 200 || var->yres > 4095) { |
| 870 | DPRINTK("height not supported: %u\n", var->yres); |
| 871 | return -EINVAL; |
| 872 | } |
| 873 | |
| 874 | if (lpitch * var->yres_virtual > info->fix.smem_len) { |
| 875 | DPRINTK("no memory for screen (%ux%ux%u)\n", |
| 876 | var->xres, var->yres_virtual, var->bits_per_pixel); |
| 877 | return -EINVAL; |
| 878 | } |
| 879 | |
| 880 | if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) { |
| 881 | DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock)); |
| 882 | return -EINVAL; |
| 883 | } |
| 884 | |
| 885 | var->accel_flags = 0; /* Can't mmap if this is on */ |
| 886 | |
| 887 | DPRINTK("Checking graphics mode at %dx%d depth %d\n", |
| 888 | var->xres, var->yres, var->bits_per_pixel); |
| 889 | return 0; |
| 890 | } |
| 891 | |
| 892 | static int pm3fb_set_par(struct fb_info *info) |
| 893 | { |
| 894 | struct pm3_par *par = info->par; |
| 895 | const u32 xres = (info->var.xres + 31) & ~31; |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 896 | const unsigned bpp = info->var.bits_per_pixel; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 897 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 898 | par->base = pm3fb_shift_bpp(bpp,(info->var.yoffset * xres) |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 899 | + info->var.xoffset); |
| 900 | par->video = 0; |
| 901 | |
| 902 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) |
| 903 | par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH; |
| 904 | else |
| 905 | par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW; |
| 906 | |
| 907 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) |
| 908 | par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH; |
| 909 | else |
| 910 | par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW; |
| 911 | |
| 912 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) |
| 913 | par->video |= PM3VideoControl_LINE_DOUBLE_ON; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 914 | |
Krzysztof Helt | 0bd327e | 2007-06-01 00:47:09 -0700 | [diff] [blame] | 915 | if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 916 | par->video |= PM3VideoControl_ENABLE; |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 917 | else |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 918 | DPRINTK("PM3Video disabled\n"); |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 919 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 920 | switch (bpp) { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 921 | case 8: |
| 922 | par->video |= PM3VideoControl_PIXELSIZE_8BIT; |
| 923 | break; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 924 | case 16: |
| 925 | par->video |= PM3VideoControl_PIXELSIZE_16BIT; |
| 926 | break; |
| 927 | case 32: |
| 928 | par->video |= PM3VideoControl_PIXELSIZE_32BIT; |
| 929 | break; |
| 930 | default: |
| 931 | DPRINTK("Unsupported depth\n"); |
| 932 | break; |
| 933 | } |
| 934 | |
| 935 | info->fix.visual = |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 936 | (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 937 | info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 938 | |
| 939 | /* pm3fb_clear_memory(info, 0);*/ |
| 940 | pm3fb_clear_colormap(par, 0, 0, 0); |
Krzysztof Helt | f259ebb | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 941 | PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0); |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 942 | pm3fb_init_engine(info); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 943 | pm3fb_write_mode(info); |
| 944 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 945 | } |
| 946 | |
| 947 | static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
| 948 | unsigned blue, unsigned transp, |
| 949 | struct fb_info *info) |
| 950 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 951 | struct pm3_par *par = info->par; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 952 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 953 | if (regno >= 256) /* no. of hw registers */ |
| 954 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 956 | /* grayscale works only partially under directcolor */ |
| 957 | if (info->var.grayscale) { |
| 958 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ |
| 959 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; |
| 960 | } |
| 961 | |
| 962 | /* Directcolor: |
| 963 | * var->{color}.offset contains start of bitfield |
| 964 | * var->{color}.length contains length of bitfield |
| 965 | * {hardwarespecific} contains width of DAC |
| 966 | * pseudo_palette[X] is programmed to (X << red.offset) | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 967 | * (X << green.offset) | |
| 968 | * (X << blue.offset) |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 969 | * RAMDAC[X] is programmed to (red, green, blue) |
| 970 | * color depth = SUM(var->{color}.length) |
| 971 | * |
| 972 | * Pseudocolor: |
| 973 | * var->{color}.offset is 0 |
| 974 | * var->{color}.length contains width of DAC or the number of unique |
| 975 | * colors available (color depth) |
| 976 | * pseudo_palette is not used |
| 977 | * RAMDAC[X] is programmed to (red, green, blue) |
| 978 | * color depth = var->{color}.length |
| 979 | */ |
| 980 | |
| 981 | /* |
| 982 | * This is the point where the color is converted to something that |
| 983 | * is acceptable by the hardware. |
| 984 | */ |
| 985 | #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) |
| 986 | red = CNVT_TOHW(red, info->var.red.length); |
| 987 | green = CNVT_TOHW(green, info->var.green.length); |
| 988 | blue = CNVT_TOHW(blue, info->var.blue.length); |
| 989 | transp = CNVT_TOHW(transp, info->var.transp.length); |
| 990 | #undef CNVT_TOHW |
| 991 | |
| 992 | if (info->fix.visual == FB_VISUAL_TRUECOLOR || |
| 993 | info->fix.visual == FB_VISUAL_DIRECTCOLOR) { |
| 994 | u32 v; |
| 995 | |
| 996 | if (regno >= 16) |
| 997 | return -EINVAL; |
| 998 | |
| 999 | v = (red << info->var.red.offset) | |
| 1000 | (green << info->var.green.offset) | |
| 1001 | (blue << info->var.blue.offset) | |
| 1002 | (transp << info->var.transp.offset); |
| 1003 | |
| 1004 | switch (info->var.bits_per_pixel) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1005 | case 8: |
| 1006 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1007 | case 16: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | case 32: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1009 | ((u32*)(info->pseudo_palette))[regno] = v; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | break; |
| 1011 | } |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1012 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1013 | } |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1014 | else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) |
| 1015 | pm3fb_set_color(par, regno, red, green, blue); |
| 1016 | |
| 1017 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | } |
| 1019 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1020 | static int pm3fb_pan_display(struct fb_var_screeninfo *var, |
| 1021 | struct fb_info *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1022 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1023 | struct pm3_par *par = info->par; |
| 1024 | const u32 xres = (var->xres + 31) & ~31; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1025 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1026 | par->base = pm3fb_shift_bpp(var->bits_per_pixel, |
| 1027 | (var->yoffset * xres) |
| 1028 | + var->xoffset); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1029 | PM3_WAIT(par, 1); |
| 1030 | PM3_WRITE_REG(par, PM3ScreenBase, par->base); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1031 | return 0; |
| 1032 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1033 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1034 | static int pm3fb_blank(int blank_mode, struct fb_info *info) |
| 1035 | { |
| 1036 | struct pm3_par *par = info->par; |
| 1037 | u32 video = par->video; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1038 | |
| 1039 | /* |
| 1040 | * Oxygen VX1 - it appears that setting PM3VideoControl and |
| 1041 | * then PM3RD_SyncControl to the same SYNC settings undoes |
| 1042 | * any net change - they seem to xor together. Only set the |
| 1043 | * sync options in PM3RD_SyncControl. --rmk |
| 1044 | */ |
| 1045 | video &= ~(PM3VideoControl_HSYNC_MASK | |
| 1046 | PM3VideoControl_VSYNC_MASK); |
| 1047 | video |= PM3VideoControl_HSYNC_ACTIVE_HIGH | |
| 1048 | PM3VideoControl_VSYNC_ACTIVE_HIGH; |
| 1049 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1050 | switch (blank_mode) { |
| 1051 | case FB_BLANK_UNBLANK: |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1052 | video |= PM3VideoControl_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | break; |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1054 | case FB_BLANK_NORMAL: |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 1055 | video &= ~PM3VideoControl_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1056 | break; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1057 | case FB_BLANK_HSYNC_SUSPEND: |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1058 | video &= ~(PM3VideoControl_HSYNC_MASK | |
| 1059 | PM3VideoControl_BLANK_ACTIVE_LOW); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1060 | break; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1061 | case FB_BLANK_VSYNC_SUSPEND: |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1062 | video &= ~(PM3VideoControl_VSYNC_MASK | |
| 1063 | PM3VideoControl_BLANK_ACTIVE_LOW); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | break; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1065 | case FB_BLANK_POWERDOWN: |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1066 | video &= ~(PM3VideoControl_HSYNC_MASK | |
| 1067 | PM3VideoControl_VSYNC_MASK | |
| 1068 | PM3VideoControl_BLANK_ACTIVE_LOW); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1069 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1070 | default: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1071 | DPRINTK("Unsupported blanking %d\n", blank_mode); |
| 1072 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1073 | } |
| 1074 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1075 | PM3_WAIT(par, 1); |
| 1076 | PM3_WRITE_REG(par,PM3VideoControl, video); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1077 | return 0; |
| 1078 | } |
| 1079 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1080 | /* |
| 1081 | * Frame buffer operations |
| 1082 | */ |
| 1083 | |
| 1084 | static struct fb_ops pm3fb_ops = { |
| 1085 | .owner = THIS_MODULE, |
| 1086 | .fb_check_var = pm3fb_check_var, |
| 1087 | .fb_set_par = pm3fb_set_par, |
| 1088 | .fb_setcolreg = pm3fb_setcolreg, |
| 1089 | .fb_pan_display = pm3fb_pan_display, |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 1090 | .fb_fillrect = pm3fb_fillrect, |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 1091 | .fb_copyarea = pm3fb_copyarea, |
| 1092 | .fb_imageblit = pm3fb_imageblit, |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1093 | .fb_blank = pm3fb_blank, |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 1094 | .fb_sync = pm3fb_sync, |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1095 | }; |
| 1096 | |
| 1097 | /* ------------------------------------------------------------------------- */ |
| 1098 | |
| 1099 | /* |
| 1100 | * Initialization |
| 1101 | */ |
| 1102 | |
| 1103 | /* mmio register are already mapped when this function is called */ |
| 1104 | /* the pm3fb_fix.smem_start is also set */ |
| 1105 | static unsigned long pm3fb_size_memory(struct pm3_par *par) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1106 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1107 | unsigned long memsize = 0, tempBypass, i, temp1, temp2; |
| 1108 | unsigned char __iomem *screen_mem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1109 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1110 | pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */ |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1111 | /* Linear frame buffer - request region and map it. */ |
| 1112 | if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len, |
| 1113 | "pm3fb smem")) { |
| 1114 | printk(KERN_WARNING "pm3fb: Can't reserve smem.\n"); |
| 1115 | return 0; |
| 1116 | } |
| 1117 | screen_mem = |
| 1118 | ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len); |
| 1119 | if (!screen_mem) { |
| 1120 | printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n"); |
| 1121 | release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len); |
| 1122 | return 0; |
| 1123 | } |
| 1124 | |
| 1125 | /* TODO: card-specific stuff, *before* accessing *any* FB memory */ |
| 1126 | /* For Appian Jeronimo 2000 board second head */ |
| 1127 | |
| 1128 | tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask); |
| 1129 | |
| 1130 | DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass); |
| 1131 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1132 | PM3_WAIT(par, 1); |
| 1133 | PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1134 | |
| 1135 | /* pm3 split up memory, replicates, and do a lot of nasty stuff IMHO ;-) */ |
| 1136 | for (i = 0; i < 32; i++) { |
| 1137 | fb_writel(i * 0x00345678, |
| 1138 | (screen_mem + (i * 1048576))); |
| 1139 | mb(); |
| 1140 | temp1 = fb_readl((screen_mem + (i * 1048576))); |
| 1141 | |
| 1142 | /* Let's check for wrapover, write will fail at 16MB boundary */ |
| 1143 | if (temp1 == (i * 0x00345678)) |
| 1144 | memsize = i; |
| 1145 | else |
| 1146 | break; |
| 1147 | } |
| 1148 | |
| 1149 | DPRINTK("First detect pass already got %ld MB\n", memsize + 1); |
| 1150 | |
| 1151 | if (memsize + 1 == i) { |
| 1152 | for (i = 0; i < 32; i++) { |
| 1153 | /* Clear first 32MB ; 0 is 0, no need to byteswap */ |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1154 | writel(0x0000000, (screen_mem + (i * 1048576))); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1155 | } |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1156 | wmb(); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1157 | |
| 1158 | for (i = 32; i < 64; i++) { |
| 1159 | fb_writel(i * 0x00345678, |
| 1160 | (screen_mem + (i * 1048576))); |
| 1161 | mb(); |
| 1162 | temp1 = |
| 1163 | fb_readl((screen_mem + (i * 1048576))); |
| 1164 | temp2 = |
| 1165 | fb_readl((screen_mem + ((i - 32) * 1048576))); |
| 1166 | /* different value, different RAM... */ |
| 1167 | if ((temp1 == (i * 0x00345678)) && (temp2 == 0)) |
| 1168 | memsize = i; |
| 1169 | else |
| 1170 | break; |
| 1171 | } |
| 1172 | } |
| 1173 | DPRINTK("Second detect pass got %ld MB\n", memsize + 1); |
| 1174 | |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1175 | PM3_WAIT(par, 1); |
| 1176 | PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1177 | |
| 1178 | iounmap(screen_mem); |
| 1179 | release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len); |
| 1180 | memsize = 1048576 * (memsize + 1); |
| 1181 | |
| 1182 | DPRINTK("Returning 0x%08lx bytes\n", memsize); |
| 1183 | |
| 1184 | return memsize; |
| 1185 | } |
| 1186 | |
| 1187 | static int __devinit pm3fb_probe(struct pci_dev *dev, |
| 1188 | const struct pci_device_id *ent) |
| 1189 | { |
| 1190 | struct fb_info *info; |
| 1191 | struct pm3_par *par; |
| 1192 | struct device* device = &dev->dev; /* for pci drivers */ |
| 1193 | int err, retval = -ENXIO; |
| 1194 | |
| 1195 | err = pci_enable_device(dev); |
| 1196 | if (err) { |
| 1197 | printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err); |
| 1198 | return err; |
| 1199 | } |
| 1200 | /* |
| 1201 | * Dynamically allocate info and par |
| 1202 | */ |
| 1203 | info = framebuffer_alloc(sizeof(struct pm3_par), device); |
| 1204 | |
| 1205 | if (!info) |
| 1206 | return -ENOMEM; |
| 1207 | par = info->par; |
| 1208 | |
| 1209 | /* |
| 1210 | * Here we set the screen_base to the virtual memory address |
| 1211 | * for the framebuffer. |
| 1212 | */ |
| 1213 | pm3fb_fix.mmio_start = pci_resource_start(dev, 0); |
| 1214 | pm3fb_fix.mmio_len = PM3_REGS_SIZE; |
Krzysztof Helt | c79ba28 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 1215 | #if defined(__BIG_ENDIAN) |
| 1216 | pm3fb_fix.mmio_start += PM3_REGS_SIZE; |
| 1217 | DPRINTK("Adjusting register base for big-endian.\n"); |
| 1218 | #endif |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1219 | |
| 1220 | /* Registers - request region and map it. */ |
| 1221 | if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len, |
| 1222 | "pm3fb regbase")) { |
| 1223 | printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n"); |
| 1224 | goto err_exit_neither; |
| 1225 | } |
| 1226 | par->v_regs = |
| 1227 | ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len); |
| 1228 | if (!par->v_regs) { |
| 1229 | printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n", |
| 1230 | pm3fb_fix.id); |
| 1231 | release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len); |
| 1232 | goto err_exit_neither; |
| 1233 | } |
| 1234 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1235 | /* Linear frame buffer - request region and map it. */ |
| 1236 | pm3fb_fix.smem_start = pci_resource_start(dev, 1); |
| 1237 | pm3fb_fix.smem_len = pm3fb_size_memory(par); |
| 1238 | if (!pm3fb_fix.smem_len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1239 | { |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1240 | printk(KERN_WARNING "pm3fb: Can't find memory on board.\n"); |
| 1241 | goto err_exit_mmio; |
| 1242 | } |
| 1243 | if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len, |
| 1244 | "pm3fb smem")) { |
| 1245 | printk(KERN_WARNING "pm3fb: Can't reserve smem.\n"); |
| 1246 | goto err_exit_mmio; |
| 1247 | } |
| 1248 | info->screen_base = |
| 1249 | ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len); |
| 1250 | if (!info->screen_base) { |
| 1251 | printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n"); |
| 1252 | release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len); |
| 1253 | goto err_exit_mmio; |
| 1254 | } |
| 1255 | info->screen_size = pm3fb_fix.smem_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1256 | |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1257 | #ifdef CONFIG_MTRR |
| 1258 | if (!nomtrr) { |
| 1259 | par->mtrr_handle = mtrr_add(pm3fb_fix.smem_start, |
| 1260 | pm3fb_fix.smem_len, |
| 1261 | MTRR_TYPE_WRCOMB, 1); |
| 1262 | } |
| 1263 | #endif |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1264 | info->fbops = &pm3fb_ops; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1265 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1266 | par->video = PM3_READ_REG(par, PM3VideoControl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1267 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1268 | info->fix = pm3fb_fix; |
| 1269 | info->pseudo_palette = par->palette; |
Krzysztof Helt | a58d67c | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 1270 | info->flags = FBINFO_DEFAULT | |
Krzysztof Helt | c79ba28 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 1271 | FBINFO_HWACCEL_XPAN | |
| 1272 | FBINFO_HWACCEL_YPAN | |
Krzysztof Helt | e7f76df | 2007-10-16 01:28:29 -0700 | [diff] [blame] | 1273 | FBINFO_HWACCEL_COPYAREA | |
| 1274 | FBINFO_HWACCEL_IMAGEBLIT | |
| 1275 | FBINFO_HWACCEL_FILLRECT; |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1276 | |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1277 | if (noaccel) { |
| 1278 | printk(KERN_DEBUG "disabling acceleration\n"); |
| 1279 | info->flags |= FBINFO_HWACCEL_DISABLED; |
| 1280 | } |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 1281 | info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL); |
| 1282 | if (!info->pixmap.addr) { |
| 1283 | retval = -ENOMEM; |
| 1284 | goto err_exit_pixmap; |
| 1285 | } |
| 1286 | info->pixmap.size = PM3_PIXMAP_SIZE; |
| 1287 | info->pixmap.buf_align = 4; |
| 1288 | info->pixmap.scan_align = 4; |
| 1289 | info->pixmap.access_align = 32; |
| 1290 | info->pixmap.flags = FB_PIXMAP_SYSTEM; |
| 1291 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1292 | /* |
| 1293 | * This should give a reasonable default video mode. The following is |
| 1294 | * done when we can set a video mode. |
| 1295 | */ |
| 1296 | if (!mode_option) |
| 1297 | mode_option = "640x480@60"; |
| 1298 | |
| 1299 | retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); |
| 1300 | |
| 1301 | if (!retval || retval == 4) { |
| 1302 | retval = -EINVAL; |
| 1303 | goto err_exit_both; |
| 1304 | } |
| 1305 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1306 | if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { |
| 1307 | retval = -ENOMEM; |
| 1308 | goto err_exit_both; |
| 1309 | } |
| 1310 | |
| 1311 | /* |
| 1312 | * For drivers that can... |
| 1313 | */ |
| 1314 | pm3fb_check_var(&info->var, info); |
| 1315 | |
| 1316 | if (register_framebuffer(info) < 0) { |
| 1317 | retval = -EINVAL; |
| 1318 | goto err_exit_all; |
| 1319 | } |
| 1320 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, |
| 1321 | info->fix.id); |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1322 | pci_set_drvdata(dev, info); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1323 | return 0; |
| 1324 | |
| 1325 | err_exit_all: |
| 1326 | fb_dealloc_cmap(&info->cmap); |
| 1327 | err_exit_both: |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 1328 | kfree(info->pixmap.addr); |
| 1329 | err_exit_pixmap: |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1330 | iounmap(info->screen_base); |
| 1331 | release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len); |
| 1332 | err_exit_mmio: |
| 1333 | iounmap(par->v_regs); |
| 1334 | release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len); |
| 1335 | err_exit_neither: |
| 1336 | framebuffer_release(info); |
| 1337 | return retval; |
| 1338 | } |
| 1339 | |
| 1340 | /* |
| 1341 | * Cleanup |
| 1342 | */ |
| 1343 | static void __devexit pm3fb_remove(struct pci_dev *dev) |
| 1344 | { |
| 1345 | struct fb_info *info = pci_get_drvdata(dev); |
| 1346 | |
| 1347 | if (info) { |
| 1348 | struct fb_fix_screeninfo *fix = &info->fix; |
| 1349 | struct pm3_par *par = info->par; |
| 1350 | |
| 1351 | unregister_framebuffer(info); |
| 1352 | fb_dealloc_cmap(&info->cmap); |
| 1353 | |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1354 | #ifdef CONFIG_MTRR |
| 1355 | if (par->mtrr_handle >= 0) |
| 1356 | mtrr_del(par->mtrr_handle, info->fix.smem_start, |
| 1357 | info->fix.smem_len); |
| 1358 | #endif /* CONFIG_MTRR */ |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1359 | iounmap(info->screen_base); |
| 1360 | release_mem_region(fix->smem_start, fix->smem_len); |
| 1361 | iounmap(par->v_regs); |
| 1362 | release_mem_region(fix->mmio_start, fix->mmio_len); |
| 1363 | |
| 1364 | pci_set_drvdata(dev, NULL); |
Krzysztof Helt | b0a318e | 2007-10-16 01:28:31 -0700 | [diff] [blame] | 1365 | kfree(info->pixmap.addr); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1366 | framebuffer_release(info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1367 | } |
| 1368 | } |
| 1369 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1370 | static struct pci_device_id pm3fb_id_table[] = { |
| 1371 | { PCI_VENDOR_ID_3DLABS, 0x0a, |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1372 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1373 | { 0, } |
| 1374 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1375 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1376 | /* For PCI drivers */ |
| 1377 | static struct pci_driver pm3fb_driver = { |
| 1378 | .name = "pm3fb", |
| 1379 | .id_table = pm3fb_id_table, |
| 1380 | .probe = pm3fb_probe, |
| 1381 | .remove = __devexit_p(pm3fb_remove), |
| 1382 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1383 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1384 | MODULE_DEVICE_TABLE(pci, pm3fb_id_table); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1385 | |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1386 | #ifndef MODULE |
| 1387 | /* |
| 1388 | * Setup |
| 1389 | */ |
| 1390 | |
| 1391 | /* |
| 1392 | * Only necessary if your driver takes special options, |
| 1393 | * otherwise we fall back on the generic fb_setup(). |
| 1394 | */ |
| 1395 | static int __init pm3fb_setup(char *options) |
| 1396 | { |
| 1397 | char *this_opt; |
| 1398 | |
| 1399 | /* Parse user speficied options (`video=pm3fb:') */ |
| 1400 | if (!options || !*options) |
| 1401 | return 0; |
| 1402 | |
| 1403 | while ((this_opt = strsep(&options, ",")) != NULL) { |
| 1404 | if (!*this_opt) |
| 1405 | continue; |
| 1406 | else if (!strncmp(this_opt, "noaccel", 7)) { |
| 1407 | noaccel = 1; |
| 1408 | #ifdef CONFIG_MTRR |
| 1409 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
| 1410 | nomtrr = 1; |
| 1411 | #endif |
| 1412 | } else { |
| 1413 | mode_option = this_opt; |
| 1414 | } |
| 1415 | } |
| 1416 | return 0; |
| 1417 | } |
| 1418 | #endif /* MODULE */ |
| 1419 | |
Adrian Bunk | b309c05 | 2007-07-17 04:05:46 -0700 | [diff] [blame] | 1420 | static int __init pm3fb_init(void) |
Krzysztof Helt | 2686ba8 | 2007-05-23 13:57:48 -0700 | [diff] [blame] | 1421 | { |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1422 | /* |
| 1423 | * For kernel boot options (in 'video=pm3fb:<options>' format) |
| 1424 | */ |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1425 | #ifndef MODULE |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1426 | char *option = NULL; |
| 1427 | |
| 1428 | if (fb_get_options("pm3fb", &option)) |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1429 | return -ENODEV; |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1430 | pm3fb_setup(option); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1431 | #endif |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1432 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1433 | return pci_register_driver(&pm3fb_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1434 | } |
| 1435 | |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1436 | #ifdef MODULE |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1437 | static void __exit pm3fb_exit(void) |
| 1438 | { |
| 1439 | pci_unregister_driver(&pm3fb_driver); |
| 1440 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1441 | |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1442 | module_exit(pm3fb_exit); |
Krzysztof Helt | d5383fc | 2007-10-16 01:28:33 -0700 | [diff] [blame^] | 1443 | #endif |
| 1444 | module_init(pm3fb_init); |
| 1445 | |
| 1446 | module_param(noaccel, bool, 0); |
| 1447 | MODULE_PARM_DESC(noaccel, "Disable acceleration"); |
| 1448 | #ifdef CONFIG_MTRR |
| 1449 | module_param(nomtrr, bool, 0); |
| 1450 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); |
| 1451 | #endif |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1452 | |
Krzysztof Helt | 0ddf784 | 2007-10-16 01:28:32 -0700 | [diff] [blame] | 1453 | MODULE_DESCRIPTION("Permedia3 framebuffer device driver"); |
Krzysztof Helt | f23a06f | 2007-05-10 22:23:25 -0700 | [diff] [blame] | 1454 | MODULE_LICENSE("GPL"); |