Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> |
| 3 | * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> |
| 4 | * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org> |
| 5 | * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu> |
| 6 | * Copyright (c) 2007 Pavel Roskin <proski@gnu.org> |
| 7 | * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> |
| 8 | * |
| 9 | * Permission to use, copy, modify, and distribute this software for any |
| 10 | * purpose with or without fee is hereby granted, provided that the above |
| 11 | * copyright notice and this permission notice appear in all copies. |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * HW related functions for Atheros Wireless LAN devices. |
| 25 | */ |
| 26 | |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/delay.h> |
| 29 | |
| 30 | #include "reg.h" |
| 31 | #include "base.h" |
| 32 | #include "debug.h" |
| 33 | |
| 34 | /*Rate tables*/ |
| 35 | static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A; |
| 36 | static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B; |
| 37 | static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G; |
| 38 | static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO; |
| 39 | static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR; |
| 40 | |
| 41 | /*Prototypes*/ |
| 42 | static int ath5k_hw_nic_reset(struct ath5k_hw *, u32); |
| 43 | static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool); |
| 44 | static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *, |
| 45 | unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, |
| 46 | unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, |
| 47 | unsigned int, unsigned int); |
Jiri Slaby | b988763 | 2008-02-15 21:58:52 +0100 | [diff] [blame] | 48 | static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 49 | unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, |
| 50 | unsigned int); |
| 51 | static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *); |
| 52 | static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *, |
| 53 | unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, |
| 54 | unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, |
| 55 | unsigned int, unsigned int); |
| 56 | static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *); |
| 57 | static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *, struct ath5k_desc *); |
| 58 | static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *, struct ath5k_desc *); |
| 59 | static int ath5k_hw_get_capabilities(struct ath5k_hw *); |
| 60 | |
| 61 | static int ath5k_eeprom_init(struct ath5k_hw *); |
| 62 | static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *); |
| 63 | |
| 64 | static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16); |
| 65 | static int ath5k_hw_disable_pspoll(struct ath5k_hw *); |
| 66 | |
| 67 | /* |
| 68 | * Enable to overwrite the country code (use "00" for debug) |
| 69 | */ |
| 70 | #if 0 |
| 71 | #define COUNTRYCODE "00" |
| 72 | #endif |
| 73 | |
| 74 | /*******************\ |
| 75 | General Functions |
| 76 | \*******************/ |
| 77 | |
| 78 | /* |
| 79 | * Functions used internaly |
| 80 | */ |
| 81 | |
| 82 | static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) |
| 83 | { |
| 84 | return turbo == true ? (usec * 80) : (usec * 40); |
| 85 | } |
| 86 | |
| 87 | static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) |
| 88 | { |
| 89 | return turbo == true ? (clock / 80) : (clock / 40); |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Check if a register write has been completed |
| 94 | */ |
| 95 | int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, |
| 96 | bool is_set) |
| 97 | { |
| 98 | int i; |
| 99 | u32 data; |
| 100 | |
| 101 | for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { |
| 102 | data = ath5k_hw_reg_read(ah, reg); |
| 103 | if ((is_set == true) && (data & flag)) |
| 104 | break; |
| 105 | else if ((data & flag) == val) |
| 106 | break; |
| 107 | udelay(15); |
| 108 | } |
| 109 | |
| 110 | return (i <= 0) ? -EAGAIN : 0; |
| 111 | } |
| 112 | |
| 113 | |
| 114 | /***************************************\ |
| 115 | Attach/Detach Functions |
| 116 | \***************************************/ |
| 117 | |
| 118 | /* |
| 119 | * Check if the device is supported and initialize the needed structs |
| 120 | */ |
| 121 | struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) |
| 122 | { |
| 123 | struct ath5k_hw *ah; |
| 124 | u8 mac[ETH_ALEN]; |
| 125 | int ret; |
| 126 | u32 srev; |
| 127 | |
| 128 | /*If we passed the test malloc a ath5k_hw struct*/ |
| 129 | ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); |
| 130 | if (ah == NULL) { |
| 131 | ret = -ENOMEM; |
| 132 | ATH5K_ERR(sc, "out of memory\n"); |
| 133 | goto err; |
| 134 | } |
| 135 | |
| 136 | ah->ah_sc = sc; |
| 137 | ah->ah_iobase = sc->iobase; |
| 138 | |
| 139 | /* |
| 140 | * HW information |
| 141 | */ |
| 142 | |
| 143 | /* Get reg domain from eeprom */ |
| 144 | ath5k_get_regdomain(ah); |
| 145 | |
| 146 | ah->ah_op_mode = IEEE80211_IF_TYPE_STA; |
| 147 | ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; |
| 148 | ah->ah_turbo = false; |
| 149 | ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; |
| 150 | ah->ah_imr = 0; |
| 151 | ah->ah_atim_window = 0; |
| 152 | ah->ah_aifs = AR5K_TUNE_AIFS; |
| 153 | ah->ah_cw_min = AR5K_TUNE_CWMIN; |
| 154 | ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; |
| 155 | ah->ah_software_retry = false; |
| 156 | ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; |
| 157 | |
| 158 | /* |
| 159 | * Set the mac revision based on the pci id |
| 160 | */ |
| 161 | ah->ah_version = mac_version; |
| 162 | |
| 163 | /*Fill the ath5k_hw struct with the needed functions*/ |
| 164 | if (ah->ah_version == AR5K_AR5212) |
| 165 | ah->ah_magic = AR5K_EEPROM_MAGIC_5212; |
| 166 | else if (ah->ah_version == AR5K_AR5211) |
| 167 | ah->ah_magic = AR5K_EEPROM_MAGIC_5211; |
| 168 | |
| 169 | if (ah->ah_version == AR5K_AR5212) { |
| 170 | ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; |
| 171 | ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; |
| 172 | ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; |
| 173 | } else { |
| 174 | ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; |
| 175 | ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc; |
| 176 | ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; |
| 177 | } |
| 178 | |
| 179 | if (ah->ah_version == AR5K_AR5212) |
| 180 | ah->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status; |
| 181 | else if (ah->ah_version <= AR5K_AR5211) |
| 182 | ah->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status; |
| 183 | |
| 184 | /* Bring device out of sleep and reset it's units */ |
| 185 | ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true); |
| 186 | if (ret) |
| 187 | goto err_free; |
| 188 | |
| 189 | /* Get MAC, PHY and RADIO revisions */ |
| 190 | srev = ath5k_hw_reg_read(ah, AR5K_SREV); |
| 191 | ah->ah_mac_srev = srev; |
| 192 | ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); |
| 193 | ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); |
| 194 | ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) & |
| 195 | 0xffffffff; |
| 196 | ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, |
| 197 | CHANNEL_5GHZ); |
| 198 | |
| 199 | if (ah->ah_version == AR5K_AR5210) |
| 200 | ah->ah_radio_2ghz_revision = 0; |
| 201 | else |
| 202 | ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, |
| 203 | CHANNEL_2GHZ); |
| 204 | |
| 205 | /* Return on unsuported chips (unsupported eeprom etc) */ |
| 206 | if(srev >= AR5K_SREV_VER_AR5416){ |
| 207 | ATH5K_ERR(sc, "Device not yet supported.\n"); |
| 208 | ret = -ENODEV; |
| 209 | goto err_free; |
| 210 | } |
| 211 | |
| 212 | /* Identify single chip solutions */ |
| 213 | if((srev <= AR5K_SREV_VER_AR5414) && |
| 214 | (srev >= AR5K_SREV_VER_AR2424)) { |
| 215 | ah->ah_single_chip = true; |
| 216 | } else { |
| 217 | ah->ah_single_chip = false; |
| 218 | } |
| 219 | |
| 220 | /* Single chip radio */ |
| 221 | if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision) |
| 222 | ah->ah_radio_2ghz_revision = 0; |
| 223 | |
| 224 | /* Identify the radio chip*/ |
| 225 | if (ah->ah_version == AR5K_AR5210) { |
| 226 | ah->ah_radio = AR5K_RF5110; |
| 227 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) { |
| 228 | ah->ah_radio = AR5K_RF5111; |
| 229 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) { |
| 230 | ah->ah_radio = AR5K_RF5112; |
| 231 | } else { |
| 232 | ah->ah_radio = AR5K_RF5413; |
| 233 | } |
| 234 | |
| 235 | ah->ah_phy = AR5K_PHY(0); |
| 236 | |
| 237 | /* |
| 238 | * Get card capabilities, values, ... |
| 239 | */ |
| 240 | |
| 241 | ret = ath5k_eeprom_init(ah); |
| 242 | if (ret) { |
| 243 | ATH5K_ERR(sc, "unable to init EEPROM\n"); |
| 244 | goto err_free; |
| 245 | } |
| 246 | |
| 247 | /* Get misc capabilities */ |
| 248 | ret = ath5k_hw_get_capabilities(ah); |
| 249 | if (ret) { |
| 250 | ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n", |
| 251 | sc->pdev->device); |
| 252 | goto err_free; |
| 253 | } |
| 254 | |
| 255 | /* Get MAC address */ |
| 256 | ret = ath5k_eeprom_read_mac(ah, mac); |
| 257 | if (ret) { |
| 258 | ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n", |
| 259 | sc->pdev->device); |
| 260 | goto err_free; |
| 261 | } |
| 262 | |
| 263 | ath5k_hw_set_lladdr(ah, mac); |
| 264 | /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ |
| 265 | memset(ah->ah_bssid, 0xff, ETH_ALEN); |
| 266 | ath5k_hw_set_associd(ah, ah->ah_bssid, 0); |
| 267 | ath5k_hw_set_opmode(ah); |
| 268 | |
| 269 | ath5k_hw_set_rfgain_opt(ah); |
| 270 | |
| 271 | return ah; |
| 272 | err_free: |
| 273 | kfree(ah); |
| 274 | err: |
| 275 | return ERR_PTR(ret); |
| 276 | } |
| 277 | |
| 278 | /* |
| 279 | * Bring up MAC + PHY Chips |
| 280 | */ |
| 281 | static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) |
| 282 | { |
| 283 | u32 turbo, mode, clock; |
| 284 | int ret; |
| 285 | |
| 286 | turbo = 0; |
| 287 | mode = 0; |
| 288 | clock = 0; |
| 289 | |
| 290 | ATH5K_TRACE(ah->ah_sc); |
| 291 | |
| 292 | /* Wakeup the device */ |
| 293 | ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); |
| 294 | if (ret) { |
| 295 | ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); |
| 296 | return ret; |
| 297 | } |
| 298 | |
| 299 | if (ah->ah_version != AR5K_AR5210) { |
| 300 | /* |
| 301 | * Get channel mode flags |
| 302 | */ |
| 303 | |
| 304 | if (ah->ah_radio >= AR5K_RF5112) { |
| 305 | mode = AR5K_PHY_MODE_RAD_RF5112; |
| 306 | clock = AR5K_PHY_PLL_RF5112; |
| 307 | } else { |
| 308 | mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ |
| 309 | clock = AR5K_PHY_PLL_RF5111; /*Zero*/ |
| 310 | } |
| 311 | |
| 312 | if (flags & CHANNEL_2GHZ) { |
| 313 | mode |= AR5K_PHY_MODE_FREQ_2GHZ; |
| 314 | clock |= AR5K_PHY_PLL_44MHZ; |
| 315 | |
| 316 | if (flags & CHANNEL_CCK) { |
| 317 | mode |= AR5K_PHY_MODE_MOD_CCK; |
| 318 | } else if (flags & CHANNEL_OFDM) { |
| 319 | /* XXX Dynamic OFDM/CCK is not supported by the |
| 320 | * AR5211 so we set MOD_OFDM for plain g (no |
| 321 | * CCK headers) operation. We need to test |
| 322 | * this, 5211 might support ofdm-only g after |
| 323 | * all, there are also initial register values |
| 324 | * in the code for g mode (see initvals.c). */ |
| 325 | if (ah->ah_version == AR5K_AR5211) |
| 326 | mode |= AR5K_PHY_MODE_MOD_OFDM; |
| 327 | else |
| 328 | mode |= AR5K_PHY_MODE_MOD_DYN; |
| 329 | } else { |
| 330 | ATH5K_ERR(ah->ah_sc, |
| 331 | "invalid radio modulation mode\n"); |
| 332 | return -EINVAL; |
| 333 | } |
| 334 | } else if (flags & CHANNEL_5GHZ) { |
| 335 | mode |= AR5K_PHY_MODE_FREQ_5GHZ; |
| 336 | clock |= AR5K_PHY_PLL_40MHZ; |
| 337 | |
| 338 | if (flags & CHANNEL_OFDM) |
| 339 | mode |= AR5K_PHY_MODE_MOD_OFDM; |
| 340 | else { |
| 341 | ATH5K_ERR(ah->ah_sc, |
| 342 | "invalid radio modulation mode\n"); |
| 343 | return -EINVAL; |
| 344 | } |
| 345 | } else { |
| 346 | ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n"); |
| 347 | return -EINVAL; |
| 348 | } |
| 349 | |
| 350 | if (flags & CHANNEL_TURBO) |
| 351 | turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; |
| 352 | } else { /* Reset the device */ |
| 353 | |
| 354 | /* ...enable Atheros turbo mode if requested */ |
| 355 | if (flags & CHANNEL_TURBO) |
| 356 | ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, |
| 357 | AR5K_PHY_TURBO); |
| 358 | } |
| 359 | |
| 360 | /* ...reset chipset and PCI device */ |
| 361 | if (ah->ah_single_chip == false && ath5k_hw_nic_reset(ah, |
| 362 | AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) { |
| 363 | ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip + PCI\n"); |
| 364 | return -EIO; |
| 365 | } |
| 366 | |
| 367 | if (ah->ah_version == AR5K_AR5210) |
| 368 | udelay(2300); |
| 369 | |
| 370 | /* ...wakeup again!*/ |
| 371 | ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); |
| 372 | if (ret) { |
| 373 | ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n"); |
| 374 | return ret; |
| 375 | } |
| 376 | |
| 377 | /* ...final warm reset */ |
| 378 | if (ath5k_hw_nic_reset(ah, 0)) { |
| 379 | ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n"); |
| 380 | return -EIO; |
| 381 | } |
| 382 | |
| 383 | if (ah->ah_version != AR5K_AR5210) { |
| 384 | /* ...set the PHY operating mode */ |
| 385 | ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); |
| 386 | udelay(300); |
| 387 | |
| 388 | ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); |
| 389 | ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); |
| 390 | } |
| 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | /* |
| 396 | * Get the rate table for a specific operation mode |
| 397 | */ |
| 398 | const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah, |
| 399 | unsigned int mode) |
| 400 | { |
| 401 | ATH5K_TRACE(ah->ah_sc); |
| 402 | |
| 403 | if (!test_bit(mode, ah->ah_capabilities.cap_mode)) |
| 404 | return NULL; |
| 405 | |
| 406 | /* Get rate tables */ |
| 407 | switch (mode) { |
| 408 | case MODE_IEEE80211A: |
| 409 | return &ath5k_rt_11a; |
| 410 | case MODE_ATHEROS_TURBO: |
| 411 | return &ath5k_rt_turbo; |
| 412 | case MODE_IEEE80211B: |
| 413 | return &ath5k_rt_11b; |
| 414 | case MODE_IEEE80211G: |
| 415 | return &ath5k_rt_11g; |
| 416 | case MODE_ATHEROS_TURBOG: |
| 417 | return &ath5k_rt_xr; |
| 418 | } |
| 419 | |
| 420 | return NULL; |
| 421 | } |
| 422 | |
| 423 | /* |
| 424 | * Free the ath5k_hw struct |
| 425 | */ |
| 426 | void ath5k_hw_detach(struct ath5k_hw *ah) |
| 427 | { |
| 428 | ATH5K_TRACE(ah->ah_sc); |
| 429 | |
Pavel Roskin | f50e4a8 | 2008-03-12 16:13:31 -0400 | [diff] [blame] | 430 | __set_bit(ATH_STAT_INVALID, ah->ah_sc->status); |
| 431 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 432 | if (ah->ah_rf_banks != NULL) |
| 433 | kfree(ah->ah_rf_banks); |
| 434 | |
| 435 | /* assume interrupts are down */ |
| 436 | kfree(ah); |
| 437 | } |
| 438 | |
| 439 | /****************************\ |
| 440 | Reset function and helpers |
| 441 | \****************************/ |
| 442 | |
| 443 | /** |
| 444 | * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 |
| 445 | * |
| 446 | * @ah: the &struct ath5k_hw |
| 447 | * @channel: the currently set channel upon reset |
| 448 | * |
| 449 | * Write the OFDM timings for the AR5212 upon reset. This is a helper for |
| 450 | * ath5k_hw_reset(). This seems to tune the PLL a specified frequency |
| 451 | * depending on the bandwidth of the channel. |
| 452 | * |
| 453 | */ |
| 454 | static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, |
| 455 | struct ieee80211_channel *channel) |
| 456 | { |
| 457 | /* Get exponent and mantissa and set it */ |
| 458 | u32 coef_scaled, coef_exp, coef_man, |
| 459 | ds_coef_exp, ds_coef_man, clock; |
| 460 | |
| 461 | if (!(ah->ah_version == AR5K_AR5212) || |
| 462 | !(channel->val & CHANNEL_OFDM)) |
| 463 | BUG(); |
| 464 | |
| 465 | /* Seems there are two PLLs, one for baseband sampling and one |
| 466 | * for tuning. Tuning basebands are 40 MHz or 80MHz when in |
| 467 | * turbo. */ |
| 468 | clock = channel->val & CHANNEL_TURBO ? 80 : 40; |
| 469 | coef_scaled = ((5 * (clock << 24)) / 2) / |
| 470 | channel->freq; |
| 471 | |
| 472 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
| 473 | if ((coef_scaled >> coef_exp) & 0x1) |
| 474 | break; |
| 475 | |
| 476 | if (!coef_exp) |
| 477 | return -EINVAL; |
| 478 | |
| 479 | coef_exp = 14 - (coef_exp - 24); |
| 480 | coef_man = coef_scaled + |
| 481 | (1 << (24 - coef_exp - 1)); |
| 482 | ds_coef_man = coef_man >> (24 - coef_exp); |
| 483 | ds_coef_exp = coef_exp - 16; |
| 484 | |
| 485 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, |
| 486 | AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); |
| 487 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, |
| 488 | AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); |
| 489 | |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | /** |
| 494 | * ath5k_hw_write_rate_duration - set rate duration during hw resets |
| 495 | * |
| 496 | * @ah: the &struct ath5k_hw |
| 497 | * @driver_mode: one of enum ieee80211_phymode or our one of our own |
| 498 | * vendor modes |
| 499 | * |
| 500 | * Write the rate duration table for the current mode upon hw reset. This |
| 501 | * is a helper for ath5k_hw_reset(). It seems all this is doing is setting |
| 502 | * an ACK timeout for the hardware for the current mode for each rate. The |
| 503 | * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, |
| 504 | * and 11Mbps) have another register for the short preamble ACK timeout |
| 505 | * calculation. |
| 506 | * |
| 507 | */ |
| 508 | static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, |
| 509 | unsigned int driver_mode) |
| 510 | { |
| 511 | struct ath5k_softc *sc = ah->ah_sc; |
| 512 | const struct ath5k_rate_table *rt; |
| 513 | unsigned int i; |
| 514 | |
| 515 | /* Get rate table for the current operating mode */ |
| 516 | rt = ath5k_hw_get_rate_table(ah, |
| 517 | driver_mode); |
| 518 | |
| 519 | /* Write rate duration table */ |
| 520 | for (i = 0; i < rt->rate_count; i++) { |
| 521 | const struct ath5k_rate *rate, *control_rate; |
| 522 | u32 reg; |
| 523 | u16 tx_time; |
| 524 | |
| 525 | rate = &rt->rates[i]; |
| 526 | control_rate = &rt->rates[rate->control_rate]; |
| 527 | |
| 528 | /* Set ACK timeout */ |
| 529 | reg = AR5K_RATE_DUR(rate->rate_code); |
| 530 | |
| 531 | /* An ACK frame consists of 10 bytes. If you add the FCS, |
| 532 | * which ieee80211_generic_frame_duration() adds, |
| 533 | * its 14 bytes. Note we use the control rate and not the |
| 534 | * actual rate for this rate. See mac80211 tx.c |
| 535 | * ieee80211_duration() for a brief description of |
| 536 | * what rate we should choose to TX ACKs. */ |
| 537 | tx_time = ieee80211_generic_frame_duration(sc->hw, |
Johannes Berg | 32bfd35 | 2007-12-19 01:31:26 +0100 | [diff] [blame] | 538 | sc->vif, 10, control_rate->rate_kbps/100); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 539 | |
| 540 | ath5k_hw_reg_write(ah, tx_time, reg); |
| 541 | |
| 542 | if (!HAS_SHPREAMBLE(i)) |
| 543 | continue; |
| 544 | |
| 545 | /* |
| 546 | * We're not distinguishing short preamble here, |
| 547 | * This is true, all we'll get is a longer value here |
| 548 | * which is not necessarilly bad. We could use |
| 549 | * export ieee80211_frame_duration() but that needs to be |
| 550 | * fixed first to be properly used by mac802111 drivers: |
| 551 | * |
| 552 | * - remove erp stuff and let the routine figure ofdm |
| 553 | * erp rates |
| 554 | * - remove passing argument ieee80211_local as |
| 555 | * drivers don't have access to it |
| 556 | * - move drivers using ieee80211_generic_frame_duration() |
| 557 | * to this |
| 558 | */ |
| 559 | ath5k_hw_reg_write(ah, tx_time, |
| 560 | reg + (AR5K_SET_SHORT_PREAMBLE << 2)); |
| 561 | } |
| 562 | } |
| 563 | |
| 564 | /* |
| 565 | * Main reset function |
| 566 | */ |
| 567 | int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, |
| 568 | struct ieee80211_channel *channel, bool change_channel) |
| 569 | { |
| 570 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 571 | u32 data, s_seq, s_ant, s_led[3]; |
| 572 | unsigned int i, mode, freq, ee_mode, ant[2], driver_mode = -1; |
| 573 | int ret; |
| 574 | |
| 575 | ATH5K_TRACE(ah->ah_sc); |
| 576 | |
| 577 | s_seq = 0; |
| 578 | s_ant = 0; |
| 579 | ee_mode = 0; |
| 580 | freq = 0; |
| 581 | mode = 0; |
| 582 | |
| 583 | /* |
| 584 | * Save some registers before a reset |
| 585 | */ |
| 586 | /*DCU/Antenna selection not available on 5210*/ |
| 587 | if (ah->ah_version != AR5K_AR5210) { |
| 588 | if (change_channel == true) { |
| 589 | /* Seq number for queue 0 -do this for all queues ? */ |
| 590 | s_seq = ath5k_hw_reg_read(ah, |
| 591 | AR5K_QUEUE_DFS_SEQNUM(0)); |
| 592 | /*Default antenna*/ |
| 593 | s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | /*GPIOs*/ |
| 598 | s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE; |
| 599 | s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); |
| 600 | s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); |
| 601 | |
| 602 | if (change_channel == true && ah->ah_rf_banks != NULL) |
| 603 | ath5k_hw_get_rf_gain(ah); |
| 604 | |
| 605 | |
| 606 | /*Wakeup the device*/ |
| 607 | ret = ath5k_hw_nic_wakeup(ah, channel->val, false); |
| 608 | if (ret) |
| 609 | return ret; |
| 610 | |
| 611 | /* |
| 612 | * Initialize operating mode |
| 613 | */ |
| 614 | ah->ah_op_mode = op_mode; |
| 615 | |
| 616 | /* |
| 617 | * 5111/5112 Settings |
| 618 | * 5210 only comes with RF5110 |
| 619 | */ |
| 620 | if (ah->ah_version != AR5K_AR5210) { |
| 621 | if (ah->ah_radio != AR5K_RF5111 && |
| 622 | ah->ah_radio != AR5K_RF5112 && |
| 623 | ah->ah_radio != AR5K_RF5413) { |
| 624 | ATH5K_ERR(ah->ah_sc, |
| 625 | "invalid phy radio: %u\n", ah->ah_radio); |
| 626 | return -EINVAL; |
| 627 | } |
| 628 | |
| 629 | switch (channel->val & CHANNEL_MODES) { |
| 630 | case CHANNEL_A: |
| 631 | mode = AR5K_INI_VAL_11A; |
| 632 | freq = AR5K_INI_RFGAIN_5GHZ; |
| 633 | ee_mode = AR5K_EEPROM_MODE_11A; |
| 634 | driver_mode = MODE_IEEE80211A; |
| 635 | break; |
| 636 | case CHANNEL_G: |
| 637 | mode = AR5K_INI_VAL_11G; |
| 638 | freq = AR5K_INI_RFGAIN_2GHZ; |
| 639 | ee_mode = AR5K_EEPROM_MODE_11G; |
| 640 | driver_mode = MODE_IEEE80211G; |
| 641 | break; |
| 642 | case CHANNEL_B: |
| 643 | mode = AR5K_INI_VAL_11B; |
| 644 | freq = AR5K_INI_RFGAIN_2GHZ; |
| 645 | ee_mode = AR5K_EEPROM_MODE_11B; |
| 646 | driver_mode = MODE_IEEE80211B; |
| 647 | break; |
| 648 | case CHANNEL_T: |
| 649 | mode = AR5K_INI_VAL_11A_TURBO; |
| 650 | freq = AR5K_INI_RFGAIN_5GHZ; |
| 651 | ee_mode = AR5K_EEPROM_MODE_11A; |
| 652 | driver_mode = MODE_ATHEROS_TURBO; |
| 653 | break; |
| 654 | /*Is this ok on 5211 too ?*/ |
| 655 | case CHANNEL_TG: |
| 656 | mode = AR5K_INI_VAL_11G_TURBO; |
| 657 | freq = AR5K_INI_RFGAIN_2GHZ; |
| 658 | ee_mode = AR5K_EEPROM_MODE_11G; |
| 659 | driver_mode = MODE_ATHEROS_TURBOG; |
| 660 | break; |
| 661 | case CHANNEL_XR: |
| 662 | if (ah->ah_version == AR5K_AR5211) { |
| 663 | ATH5K_ERR(ah->ah_sc, |
| 664 | "XR mode not available on 5211"); |
| 665 | return -EINVAL; |
| 666 | } |
| 667 | mode = AR5K_INI_VAL_XR; |
| 668 | freq = AR5K_INI_RFGAIN_5GHZ; |
| 669 | ee_mode = AR5K_EEPROM_MODE_11A; |
| 670 | driver_mode = MODE_IEEE80211A; |
| 671 | break; |
| 672 | default: |
| 673 | ATH5K_ERR(ah->ah_sc, |
| 674 | "invalid channel: %d\n", channel->freq); |
| 675 | return -EINVAL; |
| 676 | } |
| 677 | |
| 678 | /* PHY access enable */ |
| 679 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); |
| 680 | |
| 681 | } |
| 682 | |
| 683 | ret = ath5k_hw_write_initvals(ah, mode, change_channel); |
| 684 | if (ret) |
| 685 | return ret; |
| 686 | |
| 687 | /* |
| 688 | * 5211/5212 Specific |
| 689 | */ |
| 690 | if (ah->ah_version != AR5K_AR5210) { |
| 691 | /* |
| 692 | * Write initial RF gain settings |
| 693 | * This should work for both 5111/5112 |
| 694 | */ |
| 695 | ret = ath5k_hw_rfgain(ah, freq); |
| 696 | if (ret) |
| 697 | return ret; |
| 698 | |
| 699 | mdelay(1); |
| 700 | |
| 701 | /* |
| 702 | * Write some more initial register settings |
| 703 | */ |
| 704 | if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */ |
| 705 | ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11)); |
| 706 | |
| 707 | if (channel->val == CHANNEL_G) |
| 708 | ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */ |
| 709 | else |
| 710 | ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83)); |
| 711 | |
| 712 | ath5k_hw_reg_write(ah, 0x000001b5, 0xa228); /* 0x000009b5 */ |
| 713 | ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); |
| 714 | ath5k_hw_reg_write(ah, 0x0000000f, 0x8060); |
| 715 | ath5k_hw_reg_write(ah, 0x00000000, 0xa254); |
| 716 | ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL); |
| 717 | } |
| 718 | |
| 719 | /* Fix for first revision of the RF5112 RF chipset */ |
| 720 | if (ah->ah_radio >= AR5K_RF5112 && |
| 721 | ah->ah_radio_5ghz_revision < |
| 722 | AR5K_SREV_RAD_5112A) { |
| 723 | ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, |
| 724 | AR5K_PHY_CCKTXCTL); |
| 725 | if (channel->val & CHANNEL_5GHZ) |
| 726 | data = 0xffb81020; |
| 727 | else |
| 728 | data = 0xffb80d20; |
| 729 | ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); |
| 730 | } |
| 731 | |
| 732 | /* |
| 733 | * Set TX power (FIXME) |
| 734 | */ |
| 735 | ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER); |
| 736 | if (ret) |
| 737 | return ret; |
| 738 | |
Luis R. Rodriguez | 132127e | 2008-01-04 02:21:05 -0500 | [diff] [blame] | 739 | /* Write rate duration table only on AR5212 and if |
| 740 | * virtual interface has already been brought up |
| 741 | * XXX: rethink this after new mode changes to |
| 742 | * mac80211 are integrated */ |
| 743 | if (ah->ah_version == AR5K_AR5212 && |
| 744 | ah->ah_sc->vif != NULL) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 745 | ath5k_hw_write_rate_duration(ah, driver_mode); |
| 746 | |
| 747 | /* |
| 748 | * Write RF registers |
| 749 | * TODO:Does this work on 5211 (5111) ? |
| 750 | */ |
| 751 | ret = ath5k_hw_rfregs(ah, channel, mode); |
| 752 | if (ret) |
| 753 | return ret; |
| 754 | |
| 755 | /* |
| 756 | * Configure additional registers |
| 757 | */ |
| 758 | |
| 759 | /* Write OFDM timings on 5212*/ |
| 760 | if (ah->ah_version == AR5K_AR5212 && |
| 761 | channel->val & CHANNEL_OFDM) { |
| 762 | ret = ath5k_hw_write_ofdm_timings(ah, channel); |
| 763 | if (ret) |
| 764 | return ret; |
| 765 | } |
| 766 | |
| 767 | /*Enable/disable 802.11b mode on 5111 |
| 768 | (enable 2111 frequency converter + CCK)*/ |
| 769 | if (ah->ah_radio == AR5K_RF5111) { |
| 770 | if (driver_mode == MODE_IEEE80211B) |
| 771 | AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, |
| 772 | AR5K_TXCFG_B_MODE); |
| 773 | else |
| 774 | AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, |
| 775 | AR5K_TXCFG_B_MODE); |
| 776 | } |
| 777 | |
| 778 | /* |
| 779 | * Set channel and calibrate the PHY |
| 780 | */ |
| 781 | ret = ath5k_hw_channel(ah, channel); |
| 782 | if (ret) |
| 783 | return ret; |
| 784 | |
| 785 | /* Set antenna mode */ |
| 786 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44), |
| 787 | ah->ah_antenna[ee_mode][0], 0xfffffc06); |
| 788 | |
| 789 | /* |
| 790 | * In case a fixed antenna was set as default |
| 791 | * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE |
| 792 | * registers. |
| 793 | */ |
| 794 | if (s_ant != 0){ |
| 795 | if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */ |
| 796 | ant[0] = ant[1] = AR5K_ANT_FIXED_A; |
| 797 | else /* 2 - Aux */ |
| 798 | ant[0] = ant[1] = AR5K_ANT_FIXED_B; |
| 799 | } else { |
| 800 | ant[0] = AR5K_ANT_FIXED_A; |
| 801 | ant[1] = AR5K_ANT_FIXED_B; |
| 802 | } |
| 803 | |
| 804 | ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]], |
| 805 | AR5K_PHY_ANT_SWITCH_TABLE_0); |
| 806 | ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]], |
| 807 | AR5K_PHY_ANT_SWITCH_TABLE_1); |
| 808 | |
| 809 | /* Commit values from EEPROM */ |
| 810 | if (ah->ah_radio == AR5K_RF5111) |
| 811 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, |
| 812 | AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip); |
| 813 | |
| 814 | ath5k_hw_reg_write(ah, |
| 815 | AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), |
| 816 | AR5K_PHY(0x5a)); |
| 817 | |
| 818 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11), |
| 819 | (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, |
| 820 | 0xffffc07f); |
| 821 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12), |
| 822 | (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, |
| 823 | 0xfffc0fff); |
| 824 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14), |
| 825 | (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | |
| 826 | ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), |
| 827 | 0xffff0000); |
| 828 | |
| 829 | ath5k_hw_reg_write(ah, |
| 830 | (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | |
| 831 | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | |
| 832 | (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | |
| 833 | (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); |
| 834 | |
| 835 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a), |
| 836 | ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); |
| 837 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19), |
| 838 | (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); |
| 839 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01); |
| 840 | |
| 841 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, |
| 842 | AR5K_PHY_IQ_CORR_ENABLE | |
| 843 | (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | |
| 844 | ee->ee_q_cal[ee_mode]); |
| 845 | |
| 846 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) |
| 847 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, |
| 848 | AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, |
| 849 | ee->ee_margin_tx_rx[ee_mode]); |
| 850 | |
| 851 | } else { |
| 852 | mdelay(1); |
| 853 | /* Disable phy and wait */ |
| 854 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); |
| 855 | mdelay(1); |
| 856 | } |
| 857 | |
| 858 | /* |
| 859 | * Restore saved values |
| 860 | */ |
| 861 | /*DCU/Antenna selection not available on 5210*/ |
| 862 | if (ah->ah_version != AR5K_AR5210) { |
| 863 | ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0)); |
| 864 | ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA); |
| 865 | } |
| 866 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]); |
| 867 | ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); |
| 868 | ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); |
| 869 | |
| 870 | /* |
| 871 | * Misc |
| 872 | */ |
| 873 | /* XXX: add ah->aid once mac80211 gives this to us */ |
| 874 | ath5k_hw_set_associd(ah, ah->ah_bssid, 0); |
| 875 | |
| 876 | ath5k_hw_set_opmode(ah); |
| 877 | /*PISR/SISR Not available on 5210*/ |
| 878 | if (ah->ah_version != AR5K_AR5210) { |
| 879 | ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); |
| 880 | /* If we later allow tuning for this, store into sc structure */ |
| 881 | data = AR5K_TUNE_RSSI_THRES | |
| 882 | AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S; |
| 883 | ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR); |
| 884 | } |
| 885 | |
| 886 | /* |
| 887 | * Set Rx/Tx DMA Configuration |
| 888 | *(passing dma size not available on 5210) |
| 889 | */ |
| 890 | if (ah->ah_version != AR5K_AR5210) { |
| 891 | AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, |
| 892 | AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE); |
| 893 | AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, |
| 894 | AR5K_DMASIZE_512B); |
| 895 | } |
| 896 | |
| 897 | /* |
| 898 | * Enable the PHY and wait until completion |
| 899 | */ |
| 900 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); |
| 901 | |
| 902 | /* |
| 903 | * 5111/5112 Specific |
| 904 | */ |
| 905 | if (ah->ah_version != AR5K_AR5210) { |
| 906 | data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & |
| 907 | AR5K_PHY_RX_DELAY_M; |
| 908 | data = (channel->val & CHANNEL_CCK) ? |
| 909 | ((data << 2) / 22) : (data / 10); |
| 910 | |
| 911 | udelay(100 + data); |
| 912 | } else { |
| 913 | mdelay(1); |
| 914 | } |
| 915 | |
| 916 | /* |
| 917 | * Enable calibration and wait until completion |
| 918 | */ |
| 919 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, |
| 920 | AR5K_PHY_AGCCTL_CAL); |
| 921 | |
| 922 | if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
| 923 | AR5K_PHY_AGCCTL_CAL, 0, false)) { |
| 924 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", |
| 925 | channel->freq); |
| 926 | return -EAGAIN; |
| 927 | } |
| 928 | |
| 929 | ret = ath5k_hw_noise_floor_calibration(ah, channel->freq); |
| 930 | if (ret) |
| 931 | return ret; |
| 932 | |
| 933 | ah->ah_calibration = false; |
| 934 | |
| 935 | /* A and G modes can use QAM modulation which requires enabling |
| 936 | * I and Q calibration. Don't bother in B mode. */ |
| 937 | if (!(driver_mode == MODE_IEEE80211B)) { |
| 938 | ah->ah_calibration = true; |
| 939 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, |
| 940 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); |
| 941 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, |
| 942 | AR5K_PHY_IQ_RUN); |
| 943 | } |
| 944 | |
| 945 | /* |
| 946 | * Reset queues and start beacon timers at the end of the reset routine |
| 947 | */ |
| 948 | for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) { |
| 949 | /*No QCU on 5210*/ |
| 950 | if (ah->ah_version != AR5K_AR5210) |
| 951 | AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i); |
| 952 | |
| 953 | ret = ath5k_hw_reset_tx_queue(ah, i); |
| 954 | if (ret) { |
| 955 | ATH5K_ERR(ah->ah_sc, |
| 956 | "failed to reset TX queue #%d\n", i); |
| 957 | return ret; |
| 958 | } |
| 959 | } |
| 960 | |
| 961 | /* Pre-enable interrupts on 5211/5212*/ |
| 962 | if (ah->ah_version != AR5K_AR5210) |
| 963 | ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX | |
| 964 | AR5K_INT_FATAL); |
| 965 | |
| 966 | /* |
| 967 | * Set RF kill flags if supported by the device (read from the EEPROM) |
| 968 | * Disable gpio_intr for now since it results system hang. |
| 969 | * TODO: Handle this in ath5k_intr |
| 970 | */ |
| 971 | #if 0 |
| 972 | if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) { |
| 973 | ath5k_hw_set_gpio_input(ah, 0); |
| 974 | ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0); |
| 975 | if (ah->ah_gpio[0] == 0) |
| 976 | ath5k_hw_set_gpio_intr(ah, 0, 1); |
| 977 | else |
| 978 | ath5k_hw_set_gpio_intr(ah, 0, 0); |
| 979 | } |
| 980 | #endif |
| 981 | |
| 982 | /* |
| 983 | * Set the 32MHz reference clock on 5212 phy clock sleep register |
| 984 | */ |
| 985 | if (ah->ah_version == AR5K_AR5212) { |
| 986 | ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR); |
| 987 | ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); |
| 988 | ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL); |
| 989 | ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); |
| 990 | ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); |
| 991 | ath5k_hw_reg_write(ah, ah->ah_radio == AR5K_RF5111 ? |
| 992 | AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112, |
| 993 | AR5K_PHY_SPENDING); |
| 994 | } |
| 995 | |
| 996 | /* |
| 997 | * Disable beacons and reset the register |
| 998 | */ |
| 999 | AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | |
| 1000 | AR5K_BEACON_RESET_TSF); |
| 1001 | |
| 1002 | return 0; |
| 1003 | } |
| 1004 | |
| 1005 | /* |
| 1006 | * Reset chipset |
| 1007 | */ |
| 1008 | static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) |
| 1009 | { |
| 1010 | int ret; |
| 1011 | u32 mask = val ? val : ~0U; |
| 1012 | |
| 1013 | ATH5K_TRACE(ah->ah_sc); |
| 1014 | |
| 1015 | /* Read-and-clear RX Descriptor Pointer*/ |
| 1016 | ath5k_hw_reg_read(ah, AR5K_RXDP); |
| 1017 | |
| 1018 | /* |
| 1019 | * Reset the device and wait until success |
| 1020 | */ |
| 1021 | ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); |
| 1022 | |
| 1023 | /* Wait at least 128 PCI clocks */ |
| 1024 | udelay(15); |
| 1025 | |
| 1026 | if (ah->ah_version == AR5K_AR5210) { |
| 1027 | val &= AR5K_RESET_CTL_CHIP; |
| 1028 | mask &= AR5K_RESET_CTL_CHIP; |
| 1029 | } else { |
| 1030 | val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; |
| 1031 | mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; |
| 1032 | } |
| 1033 | |
| 1034 | ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false); |
| 1035 | |
| 1036 | /* |
| 1037 | * Reset configuration register (for hw byte-swap). Note that this |
| 1038 | * is only set for big endian. We do the necessary magic in |
| 1039 | * AR5K_INIT_CFG. |
| 1040 | */ |
| 1041 | if ((val & AR5K_RESET_CTL_PCU) == 0) |
| 1042 | ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); |
| 1043 | |
| 1044 | return ret; |
| 1045 | } |
| 1046 | |
| 1047 | /* |
| 1048 | * Power management functions |
| 1049 | */ |
| 1050 | |
| 1051 | /* |
| 1052 | * Sleep control |
| 1053 | */ |
| 1054 | int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, |
| 1055 | bool set_chip, u16 sleep_duration) |
| 1056 | { |
| 1057 | unsigned int i; |
| 1058 | u32 staid; |
| 1059 | |
| 1060 | ATH5K_TRACE(ah->ah_sc); |
| 1061 | staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); |
| 1062 | |
| 1063 | switch (mode) { |
| 1064 | case AR5K_PM_AUTO: |
| 1065 | staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; |
| 1066 | /* fallthrough */ |
| 1067 | case AR5K_PM_NETWORK_SLEEP: |
| 1068 | if (set_chip == true) |
| 1069 | ath5k_hw_reg_write(ah, |
| 1070 | AR5K_SLEEP_CTL_SLE | sleep_duration, |
| 1071 | AR5K_SLEEP_CTL); |
| 1072 | |
| 1073 | staid |= AR5K_STA_ID1_PWR_SV; |
| 1074 | break; |
| 1075 | |
| 1076 | case AR5K_PM_FULL_SLEEP: |
| 1077 | if (set_chip == true) |
| 1078 | ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, |
| 1079 | AR5K_SLEEP_CTL); |
| 1080 | |
| 1081 | staid |= AR5K_STA_ID1_PWR_SV; |
| 1082 | break; |
| 1083 | |
| 1084 | case AR5K_PM_AWAKE: |
| 1085 | if (set_chip == false) |
| 1086 | goto commit; |
| 1087 | |
| 1088 | ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE, |
| 1089 | AR5K_SLEEP_CTL); |
| 1090 | |
| 1091 | for (i = 5000; i > 0; i--) { |
| 1092 | /* Check if the chip did wake up */ |
| 1093 | if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & |
| 1094 | AR5K_PCICFG_SPWR_DN) == 0) |
| 1095 | break; |
| 1096 | |
| 1097 | /* Wait a bit and retry */ |
| 1098 | udelay(200); |
| 1099 | ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE, |
| 1100 | AR5K_SLEEP_CTL); |
| 1101 | } |
| 1102 | |
| 1103 | /* Fail if the chip didn't wake up */ |
| 1104 | if (i <= 0) |
| 1105 | return -EIO; |
| 1106 | |
| 1107 | staid &= ~AR5K_STA_ID1_PWR_SV; |
| 1108 | break; |
| 1109 | |
| 1110 | default: |
| 1111 | return -EINVAL; |
| 1112 | } |
| 1113 | |
| 1114 | commit: |
| 1115 | ah->ah_power_mode = mode; |
| 1116 | ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1); |
| 1117 | |
| 1118 | return 0; |
| 1119 | } |
| 1120 | |
| 1121 | /***********************\ |
| 1122 | DMA Related Functions |
| 1123 | \***********************/ |
| 1124 | |
| 1125 | /* |
| 1126 | * Receive functions |
| 1127 | */ |
| 1128 | |
| 1129 | /* |
| 1130 | * Start DMA receive |
| 1131 | */ |
| 1132 | void ath5k_hw_start_rx(struct ath5k_hw *ah) |
| 1133 | { |
| 1134 | ATH5K_TRACE(ah->ah_sc); |
| 1135 | ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); |
| 1136 | } |
| 1137 | |
| 1138 | /* |
| 1139 | * Stop DMA receive |
| 1140 | */ |
| 1141 | int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) |
| 1142 | { |
| 1143 | unsigned int i; |
| 1144 | |
| 1145 | ATH5K_TRACE(ah->ah_sc); |
| 1146 | ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); |
| 1147 | |
| 1148 | /* |
| 1149 | * It may take some time to disable the DMA receive unit |
| 1150 | */ |
| 1151 | for (i = 2000; i > 0 && |
| 1152 | (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; |
| 1153 | i--) |
| 1154 | udelay(10); |
| 1155 | |
| 1156 | return i ? 0 : -EBUSY; |
| 1157 | } |
| 1158 | |
| 1159 | /* |
| 1160 | * Get the address of the RX Descriptor |
| 1161 | */ |
| 1162 | u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah) |
| 1163 | { |
| 1164 | return ath5k_hw_reg_read(ah, AR5K_RXDP); |
| 1165 | } |
| 1166 | |
| 1167 | /* |
| 1168 | * Set the address of the RX Descriptor |
| 1169 | */ |
| 1170 | void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr) |
| 1171 | { |
| 1172 | ATH5K_TRACE(ah->ah_sc); |
| 1173 | |
| 1174 | /*TODO:Shouldn't we check if RX is enabled first ?*/ |
| 1175 | ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP); |
| 1176 | } |
| 1177 | |
| 1178 | /* |
| 1179 | * Transmit functions |
| 1180 | */ |
| 1181 | |
| 1182 | /* |
| 1183 | * Start DMA transmit for a specific queue |
| 1184 | * (see also QCU/DCU functions) |
| 1185 | */ |
| 1186 | int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue) |
| 1187 | { |
| 1188 | u32 tx_queue; |
| 1189 | |
| 1190 | ATH5K_TRACE(ah->ah_sc); |
| 1191 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
| 1192 | |
| 1193 | /* Return if queue is declared inactive */ |
| 1194 | if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) |
| 1195 | return -EIO; |
| 1196 | |
| 1197 | if (ah->ah_version == AR5K_AR5210) { |
| 1198 | tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); |
| 1199 | |
| 1200 | /* |
| 1201 | * Set the queue by type on 5210 |
| 1202 | */ |
| 1203 | switch (ah->ah_txq[queue].tqi_type) { |
| 1204 | case AR5K_TX_QUEUE_DATA: |
| 1205 | tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; |
| 1206 | break; |
| 1207 | case AR5K_TX_QUEUE_BEACON: |
| 1208 | tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; |
| 1209 | ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, |
| 1210 | AR5K_BSR); |
| 1211 | break; |
| 1212 | case AR5K_TX_QUEUE_CAB: |
| 1213 | tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; |
| 1214 | ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V | |
| 1215 | AR5K_BCR_BDMAE, AR5K_BSR); |
| 1216 | break; |
| 1217 | default: |
| 1218 | return -EINVAL; |
| 1219 | } |
| 1220 | /* Start queue */ |
| 1221 | ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); |
| 1222 | } else { |
| 1223 | /* Return if queue is disabled */ |
| 1224 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) |
| 1225 | return -EIO; |
| 1226 | |
| 1227 | /* Start queue */ |
| 1228 | AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue); |
| 1229 | } |
| 1230 | |
| 1231 | return 0; |
| 1232 | } |
| 1233 | |
| 1234 | /* |
| 1235 | * Stop DMA transmit for a specific queue |
| 1236 | * (see also QCU/DCU functions) |
| 1237 | */ |
| 1238 | int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) |
| 1239 | { |
| 1240 | unsigned int i = 100; |
| 1241 | u32 tx_queue, pending; |
| 1242 | |
| 1243 | ATH5K_TRACE(ah->ah_sc); |
| 1244 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
| 1245 | |
| 1246 | /* Return if queue is declared inactive */ |
| 1247 | if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) |
| 1248 | return -EIO; |
| 1249 | |
| 1250 | if (ah->ah_version == AR5K_AR5210) { |
| 1251 | tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); |
| 1252 | |
| 1253 | /* |
| 1254 | * Set by queue type |
| 1255 | */ |
| 1256 | switch (ah->ah_txq[queue].tqi_type) { |
| 1257 | case AR5K_TX_QUEUE_DATA: |
| 1258 | tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; |
| 1259 | break; |
| 1260 | case AR5K_TX_QUEUE_BEACON: |
| 1261 | case AR5K_TX_QUEUE_CAB: |
| 1262 | /* XXX Fix me... */ |
| 1263 | tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; |
| 1264 | ath5k_hw_reg_write(ah, 0, AR5K_BSR); |
| 1265 | break; |
| 1266 | default: |
| 1267 | return -EINVAL; |
| 1268 | } |
| 1269 | |
| 1270 | /* Stop queue */ |
| 1271 | ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); |
| 1272 | } else { |
| 1273 | /* |
| 1274 | * Schedule TX disable and wait until queue is empty |
| 1275 | */ |
| 1276 | AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue); |
| 1277 | |
| 1278 | /*Check for pending frames*/ |
| 1279 | do { |
| 1280 | pending = ath5k_hw_reg_read(ah, |
| 1281 | AR5K_QUEUE_STATUS(queue)) & |
| 1282 | AR5K_QCU_STS_FRMPENDCNT; |
| 1283 | udelay(100); |
| 1284 | } while (--i && pending); |
| 1285 | |
| 1286 | /* Clear register */ |
| 1287 | ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); |
| 1288 | } |
| 1289 | |
| 1290 | /* TODO: Check for success else return error */ |
| 1291 | return 0; |
| 1292 | } |
| 1293 | |
| 1294 | /* |
| 1295 | * Get the address of the TX Descriptor for a specific queue |
| 1296 | * (see also QCU/DCU functions) |
| 1297 | */ |
| 1298 | u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue) |
| 1299 | { |
| 1300 | u16 tx_reg; |
| 1301 | |
| 1302 | ATH5K_TRACE(ah->ah_sc); |
| 1303 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
| 1304 | |
| 1305 | /* |
| 1306 | * Get the transmit queue descriptor pointer from the selected queue |
| 1307 | */ |
| 1308 | /*5210 doesn't have QCU*/ |
| 1309 | if (ah->ah_version == AR5K_AR5210) { |
| 1310 | switch (ah->ah_txq[queue].tqi_type) { |
| 1311 | case AR5K_TX_QUEUE_DATA: |
| 1312 | tx_reg = AR5K_NOQCU_TXDP0; |
| 1313 | break; |
| 1314 | case AR5K_TX_QUEUE_BEACON: |
| 1315 | case AR5K_TX_QUEUE_CAB: |
| 1316 | tx_reg = AR5K_NOQCU_TXDP1; |
| 1317 | break; |
| 1318 | default: |
| 1319 | return 0xffffffff; |
| 1320 | } |
| 1321 | } else { |
| 1322 | tx_reg = AR5K_QUEUE_TXDP(queue); |
| 1323 | } |
| 1324 | |
| 1325 | return ath5k_hw_reg_read(ah, tx_reg); |
| 1326 | } |
| 1327 | |
| 1328 | /* |
| 1329 | * Set the address of the TX Descriptor for a specific queue |
| 1330 | * (see also QCU/DCU functions) |
| 1331 | */ |
| 1332 | int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) |
| 1333 | { |
| 1334 | u16 tx_reg; |
| 1335 | |
| 1336 | ATH5K_TRACE(ah->ah_sc); |
| 1337 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
| 1338 | |
| 1339 | /* |
| 1340 | * Set the transmit queue descriptor pointer register by type |
| 1341 | * on 5210 |
| 1342 | */ |
| 1343 | if (ah->ah_version == AR5K_AR5210) { |
| 1344 | switch (ah->ah_txq[queue].tqi_type) { |
| 1345 | case AR5K_TX_QUEUE_DATA: |
| 1346 | tx_reg = AR5K_NOQCU_TXDP0; |
| 1347 | break; |
| 1348 | case AR5K_TX_QUEUE_BEACON: |
| 1349 | case AR5K_TX_QUEUE_CAB: |
| 1350 | tx_reg = AR5K_NOQCU_TXDP1; |
| 1351 | break; |
| 1352 | default: |
| 1353 | return -EINVAL; |
| 1354 | } |
| 1355 | } else { |
| 1356 | /* |
| 1357 | * Set the transmit queue descriptor pointer for |
| 1358 | * the selected queue on QCU for 5211+ |
| 1359 | * (this won't work if the queue is still active) |
| 1360 | */ |
| 1361 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) |
| 1362 | return -EIO; |
| 1363 | |
| 1364 | tx_reg = AR5K_QUEUE_TXDP(queue); |
| 1365 | } |
| 1366 | |
| 1367 | /* Set descriptor pointer */ |
| 1368 | ath5k_hw_reg_write(ah, phys_addr, tx_reg); |
| 1369 | |
| 1370 | return 0; |
| 1371 | } |
| 1372 | |
| 1373 | /* |
| 1374 | * Update tx trigger level |
| 1375 | */ |
| 1376 | int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) |
| 1377 | { |
| 1378 | u32 trigger_level, imr; |
| 1379 | int ret = -EIO; |
| 1380 | |
| 1381 | ATH5K_TRACE(ah->ah_sc); |
| 1382 | |
| 1383 | /* |
| 1384 | * Disable interrupts by setting the mask |
| 1385 | */ |
| 1386 | imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); |
| 1387 | |
| 1388 | /*TODO: Boundary check on trigger_level*/ |
| 1389 | trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), |
| 1390 | AR5K_TXCFG_TXFULL); |
| 1391 | |
| 1392 | if (increase == false) { |
| 1393 | if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) |
| 1394 | goto done; |
| 1395 | } else |
| 1396 | trigger_level += |
| 1397 | ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); |
| 1398 | |
| 1399 | /* |
| 1400 | * Update trigger level on success |
| 1401 | */ |
| 1402 | if (ah->ah_version == AR5K_AR5210) |
| 1403 | ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL); |
| 1404 | else |
| 1405 | AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, |
| 1406 | AR5K_TXCFG_TXFULL, trigger_level); |
| 1407 | |
| 1408 | ret = 0; |
| 1409 | |
| 1410 | done: |
| 1411 | /* |
| 1412 | * Restore interrupt mask |
| 1413 | */ |
| 1414 | ath5k_hw_set_intr(ah, imr); |
| 1415 | |
| 1416 | return ret; |
| 1417 | } |
| 1418 | |
| 1419 | /* |
| 1420 | * Interrupt handling |
| 1421 | */ |
| 1422 | |
| 1423 | /* |
| 1424 | * Check if we have pending interrupts |
| 1425 | */ |
| 1426 | bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah) |
| 1427 | { |
| 1428 | ATH5K_TRACE(ah->ah_sc); |
| 1429 | return ath5k_hw_reg_read(ah, AR5K_INTPEND); |
| 1430 | } |
| 1431 | |
| 1432 | /* |
| 1433 | * Get interrupt mask (ISR) |
| 1434 | */ |
| 1435 | int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) |
| 1436 | { |
| 1437 | u32 data; |
| 1438 | |
| 1439 | ATH5K_TRACE(ah->ah_sc); |
| 1440 | |
| 1441 | /* |
| 1442 | * Read interrupt status from the Interrupt Status register |
| 1443 | * on 5210 |
| 1444 | */ |
| 1445 | if (ah->ah_version == AR5K_AR5210) { |
| 1446 | data = ath5k_hw_reg_read(ah, AR5K_ISR); |
| 1447 | if (unlikely(data == AR5K_INT_NOCARD)) { |
| 1448 | *interrupt_mask = data; |
| 1449 | return -ENODEV; |
| 1450 | } |
| 1451 | } else { |
| 1452 | /* |
| 1453 | * Read interrupt status from the Read-And-Clear shadow register |
| 1454 | * Note: PISR/SISR Not available on 5210 |
| 1455 | */ |
| 1456 | data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR); |
| 1457 | } |
| 1458 | |
| 1459 | /* |
| 1460 | * Get abstract interrupt mask (driver-compatible) |
| 1461 | */ |
| 1462 | *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr; |
| 1463 | |
| 1464 | if (unlikely(data == AR5K_INT_NOCARD)) |
| 1465 | return -ENODEV; |
| 1466 | |
| 1467 | if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR)) |
| 1468 | *interrupt_mask |= AR5K_INT_RX; |
| 1469 | |
| 1470 | if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR |
| 1471 | | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL)) |
| 1472 | *interrupt_mask |= AR5K_INT_TX; |
| 1473 | |
| 1474 | if (ah->ah_version != AR5K_AR5210) { |
| 1475 | /*HIU = Host Interface Unit (PCI etc)*/ |
| 1476 | if (unlikely(data & (AR5K_ISR_HIUERR))) |
| 1477 | *interrupt_mask |= AR5K_INT_FATAL; |
| 1478 | |
| 1479 | /*Beacon Not Ready*/ |
| 1480 | if (unlikely(data & (AR5K_ISR_BNR))) |
| 1481 | *interrupt_mask |= AR5K_INT_BNR; |
| 1482 | } |
| 1483 | |
| 1484 | /* |
| 1485 | * XXX: BMISS interrupts may occur after association. |
| 1486 | * I found this on 5210 code but it needs testing. If this is |
| 1487 | * true we should disable them before assoc and re-enable them |
| 1488 | * after a successfull assoc + some jiffies. |
| 1489 | */ |
| 1490 | #if 0 |
| 1491 | interrupt_mask &= ~AR5K_INT_BMISS; |
| 1492 | #endif |
| 1493 | |
| 1494 | /* |
| 1495 | * In case we didn't handle anything, |
| 1496 | * print the register value. |
| 1497 | */ |
| 1498 | if (unlikely(*interrupt_mask == 0 && net_ratelimit())) |
| 1499 | ATH5K_PRINTF("0x%08x\n", data); |
| 1500 | |
| 1501 | return 0; |
| 1502 | } |
| 1503 | |
| 1504 | /* |
| 1505 | * Set interrupt mask |
| 1506 | */ |
| 1507 | enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask) |
| 1508 | { |
| 1509 | enum ath5k_int old_mask, int_mask; |
| 1510 | |
| 1511 | /* |
| 1512 | * Disable card interrupts to prevent any race conditions |
| 1513 | * (they will be re-enabled afterwards). |
| 1514 | */ |
| 1515 | ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); |
| 1516 | |
| 1517 | old_mask = ah->ah_imr; |
| 1518 | |
| 1519 | /* |
| 1520 | * Add additional, chipset-dependent interrupt mask flags |
| 1521 | * and write them to the IMR (interrupt mask register). |
| 1522 | */ |
| 1523 | int_mask = new_mask & AR5K_INT_COMMON; |
| 1524 | |
| 1525 | if (new_mask & AR5K_INT_RX) |
| 1526 | int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN | |
| 1527 | AR5K_IMR_RXDESC; |
| 1528 | |
| 1529 | if (new_mask & AR5K_INT_TX) |
| 1530 | int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC | |
| 1531 | AR5K_IMR_TXURN; |
| 1532 | |
| 1533 | if (ah->ah_version != AR5K_AR5210) { |
| 1534 | if (new_mask & AR5K_INT_FATAL) { |
| 1535 | int_mask |= AR5K_IMR_HIUERR; |
| 1536 | AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT | |
| 1537 | AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR); |
| 1538 | } |
| 1539 | } |
| 1540 | |
| 1541 | ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); |
| 1542 | |
| 1543 | /* Store new interrupt mask */ |
| 1544 | ah->ah_imr = new_mask; |
| 1545 | |
| 1546 | /* ..re-enable interrupts */ |
| 1547 | ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER); |
| 1548 | |
| 1549 | return old_mask; |
| 1550 | } |
| 1551 | |
| 1552 | |
| 1553 | /*************************\ |
| 1554 | EEPROM access functions |
| 1555 | \*************************/ |
| 1556 | |
| 1557 | /* |
| 1558 | * Read from eeprom |
| 1559 | */ |
| 1560 | static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data) |
| 1561 | { |
| 1562 | u32 status, timeout; |
| 1563 | |
| 1564 | ATH5K_TRACE(ah->ah_sc); |
| 1565 | /* |
| 1566 | * Initialize EEPROM access |
| 1567 | */ |
| 1568 | if (ah->ah_version == AR5K_AR5210) { |
| 1569 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); |
| 1570 | (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); |
| 1571 | } else { |
| 1572 | ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); |
| 1573 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, |
| 1574 | AR5K_EEPROM_CMD_READ); |
| 1575 | } |
| 1576 | |
| 1577 | for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { |
| 1578 | status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); |
| 1579 | if (status & AR5K_EEPROM_STAT_RDDONE) { |
| 1580 | if (status & AR5K_EEPROM_STAT_RDERR) |
| 1581 | return -EIO; |
| 1582 | *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & |
| 1583 | 0xffff); |
| 1584 | return 0; |
| 1585 | } |
| 1586 | udelay(15); |
| 1587 | } |
| 1588 | |
| 1589 | return -ETIMEDOUT; |
| 1590 | } |
| 1591 | |
| 1592 | /* |
| 1593 | * Write to eeprom - currently disabled, use at your own risk |
| 1594 | */ |
| 1595 | static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data) |
| 1596 | { |
| 1597 | #if 0 |
| 1598 | u32 status, timeout; |
| 1599 | |
| 1600 | ATH5K_TRACE(ah->ah_sc); |
| 1601 | |
| 1602 | /* |
| 1603 | * Initialize eeprom access |
| 1604 | */ |
| 1605 | |
| 1606 | if (ah->ah_version == AR5K_AR5210) { |
| 1607 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); |
| 1608 | } else { |
| 1609 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, |
| 1610 | AR5K_EEPROM_CMD_RESET); |
| 1611 | } |
| 1612 | |
| 1613 | /* |
| 1614 | * Write data to data register |
| 1615 | */ |
| 1616 | |
| 1617 | if (ah->ah_version == AR5K_AR5210) { |
| 1618 | ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset)); |
| 1619 | } else { |
| 1620 | ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); |
| 1621 | ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA); |
| 1622 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, |
| 1623 | AR5K_EEPROM_CMD_WRITE); |
| 1624 | } |
| 1625 | |
| 1626 | /* |
| 1627 | * Check status |
| 1628 | */ |
| 1629 | |
| 1630 | for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { |
| 1631 | status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); |
| 1632 | if (status & AR5K_EEPROM_STAT_WRDONE) { |
| 1633 | if (status & AR5K_EEPROM_STAT_WRERR) |
| 1634 | return EIO; |
| 1635 | return 0; |
| 1636 | } |
| 1637 | udelay(15); |
| 1638 | } |
| 1639 | #endif |
| 1640 | ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!"); |
| 1641 | return -EIO; |
| 1642 | } |
| 1643 | |
| 1644 | /* |
| 1645 | * Translate binary channel representation in EEPROM to frequency |
| 1646 | */ |
| 1647 | static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode) |
| 1648 | { |
| 1649 | u16 val; |
| 1650 | |
| 1651 | if (bin == AR5K_EEPROM_CHANNEL_DIS) |
| 1652 | return bin; |
| 1653 | |
| 1654 | if (mode == AR5K_EEPROM_MODE_11A) { |
| 1655 | if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2) |
| 1656 | val = (5 * bin) + 4800; |
| 1657 | else |
| 1658 | val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : |
| 1659 | (bin * 10) + 5100; |
| 1660 | } else { |
| 1661 | if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2) |
| 1662 | val = bin + 2300; |
| 1663 | else |
| 1664 | val = bin + 2400; |
| 1665 | } |
| 1666 | |
| 1667 | return val; |
| 1668 | } |
| 1669 | |
| 1670 | /* |
| 1671 | * Read antenna infos from eeprom |
| 1672 | */ |
| 1673 | static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset, |
| 1674 | unsigned int mode) |
| 1675 | { |
| 1676 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 1677 | u32 o = *offset; |
| 1678 | u16 val; |
| 1679 | int ret, i = 0; |
| 1680 | |
| 1681 | AR5K_EEPROM_READ(o++, val); |
| 1682 | ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; |
| 1683 | ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f; |
| 1684 | ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; |
| 1685 | |
| 1686 | AR5K_EEPROM_READ(o++, val); |
| 1687 | ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; |
| 1688 | ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; |
| 1689 | ee->ee_ant_control[mode][i++] = val & 0x3f; |
| 1690 | |
| 1691 | AR5K_EEPROM_READ(o++, val); |
| 1692 | ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; |
| 1693 | ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; |
| 1694 | ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; |
| 1695 | |
| 1696 | AR5K_EEPROM_READ(o++, val); |
| 1697 | ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; |
| 1698 | ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; |
| 1699 | ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; |
| 1700 | ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; |
| 1701 | |
| 1702 | AR5K_EEPROM_READ(o++, val); |
| 1703 | ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; |
| 1704 | ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; |
| 1705 | ee->ee_ant_control[mode][i++] = val & 0x3f; |
| 1706 | |
| 1707 | /* Get antenna modes */ |
| 1708 | ah->ah_antenna[mode][0] = |
| 1709 | (ee->ee_ant_control[mode][0] << 4) | 0x1; |
| 1710 | ah->ah_antenna[mode][AR5K_ANT_FIXED_A] = |
| 1711 | ee->ee_ant_control[mode][1] | |
| 1712 | (ee->ee_ant_control[mode][2] << 6) | |
| 1713 | (ee->ee_ant_control[mode][3] << 12) | |
| 1714 | (ee->ee_ant_control[mode][4] << 18) | |
| 1715 | (ee->ee_ant_control[mode][5] << 24); |
| 1716 | ah->ah_antenna[mode][AR5K_ANT_FIXED_B] = |
| 1717 | ee->ee_ant_control[mode][6] | |
| 1718 | (ee->ee_ant_control[mode][7] << 6) | |
| 1719 | (ee->ee_ant_control[mode][8] << 12) | |
| 1720 | (ee->ee_ant_control[mode][9] << 18) | |
| 1721 | (ee->ee_ant_control[mode][10] << 24); |
| 1722 | |
| 1723 | /* return new offset */ |
| 1724 | *offset = o; |
| 1725 | |
| 1726 | return 0; |
| 1727 | } |
| 1728 | |
| 1729 | /* |
| 1730 | * Read supported modes from eeprom |
| 1731 | */ |
| 1732 | static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, |
| 1733 | unsigned int mode) |
| 1734 | { |
| 1735 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 1736 | u32 o = *offset; |
| 1737 | u16 val; |
| 1738 | int ret; |
| 1739 | |
| 1740 | AR5K_EEPROM_READ(o++, val); |
| 1741 | ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; |
| 1742 | ee->ee_thr_62[mode] = val & 0xff; |
| 1743 | |
| 1744 | if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) |
| 1745 | ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; |
| 1746 | |
| 1747 | AR5K_EEPROM_READ(o++, val); |
| 1748 | ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; |
| 1749 | ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; |
| 1750 | |
| 1751 | AR5K_EEPROM_READ(o++, val); |
| 1752 | ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; |
| 1753 | |
| 1754 | if ((val & 0xff) & 0x80) |
| 1755 | ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); |
| 1756 | else |
| 1757 | ee->ee_noise_floor_thr[mode] = val & 0xff; |
| 1758 | |
| 1759 | if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) |
| 1760 | ee->ee_noise_floor_thr[mode] = |
| 1761 | mode == AR5K_EEPROM_MODE_11A ? -54 : -1; |
| 1762 | |
| 1763 | AR5K_EEPROM_READ(o++, val); |
| 1764 | ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; |
| 1765 | ee->ee_x_gain[mode] = (val >> 1) & 0xf; |
| 1766 | ee->ee_xpd[mode] = val & 0x1; |
| 1767 | |
| 1768 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) |
| 1769 | ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; |
| 1770 | |
| 1771 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { |
| 1772 | AR5K_EEPROM_READ(o++, val); |
| 1773 | ee->ee_false_detect[mode] = (val >> 6) & 0x7f; |
| 1774 | |
| 1775 | if (mode == AR5K_EEPROM_MODE_11A) |
| 1776 | ee->ee_xr_power[mode] = val & 0x3f; |
| 1777 | else { |
| 1778 | ee->ee_ob[mode][0] = val & 0x7; |
| 1779 | ee->ee_db[mode][0] = (val >> 3) & 0x7; |
| 1780 | } |
| 1781 | } |
| 1782 | |
| 1783 | if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { |
| 1784 | ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; |
| 1785 | ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; |
| 1786 | } else { |
| 1787 | ee->ee_i_gain[mode] = (val >> 13) & 0x7; |
| 1788 | |
| 1789 | AR5K_EEPROM_READ(o++, val); |
| 1790 | ee->ee_i_gain[mode] |= (val << 3) & 0x38; |
| 1791 | |
| 1792 | if (mode == AR5K_EEPROM_MODE_11G) |
| 1793 | ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; |
| 1794 | } |
| 1795 | |
| 1796 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && |
| 1797 | mode == AR5K_EEPROM_MODE_11A) { |
| 1798 | ee->ee_i_cal[mode] = (val >> 8) & 0x3f; |
| 1799 | ee->ee_q_cal[mode] = (val >> 3) & 0x1f; |
| 1800 | } |
| 1801 | |
| 1802 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 && |
| 1803 | mode == AR5K_EEPROM_MODE_11G) |
| 1804 | ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; |
| 1805 | |
| 1806 | /* return new offset */ |
| 1807 | *offset = o; |
| 1808 | |
| 1809 | return 0; |
| 1810 | } |
| 1811 | |
| 1812 | /* |
| 1813 | * Initialize eeprom & capabilities structs |
| 1814 | */ |
| 1815 | static int ath5k_eeprom_init(struct ath5k_hw *ah) |
| 1816 | { |
| 1817 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 1818 | unsigned int mode, i; |
| 1819 | int ret; |
| 1820 | u32 offset; |
| 1821 | u16 val; |
| 1822 | |
| 1823 | /* Initial TX thermal adjustment values */ |
| 1824 | ee->ee_tx_clip = 4; |
| 1825 | ee->ee_pwd_84 = ee->ee_pwd_90 = 1; |
| 1826 | ee->ee_gain_select = 1; |
| 1827 | |
| 1828 | /* |
| 1829 | * Read values from EEPROM and store them in the capability structure |
| 1830 | */ |
| 1831 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); |
| 1832 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); |
| 1833 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); |
| 1834 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); |
| 1835 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); |
| 1836 | |
| 1837 | /* Return if we have an old EEPROM */ |
| 1838 | if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0) |
| 1839 | return 0; |
| 1840 | |
| 1841 | #ifdef notyet |
| 1842 | /* |
| 1843 | * Validate the checksum of the EEPROM date. There are some |
| 1844 | * devices with invalid EEPROMs. |
| 1845 | */ |
| 1846 | for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { |
| 1847 | AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); |
| 1848 | cksum ^= val; |
| 1849 | } |
| 1850 | if (cksum != AR5K_EEPROM_INFO_CKSUM) { |
| 1851 | ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum); |
| 1852 | return -EIO; |
| 1853 | } |
| 1854 | #endif |
| 1855 | |
| 1856 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version), |
| 1857 | ee_ant_gain); |
| 1858 | |
| 1859 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { |
| 1860 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); |
| 1861 | AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); |
| 1862 | } |
| 1863 | |
| 1864 | if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { |
| 1865 | AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); |
| 1866 | ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; |
| 1867 | ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; |
| 1868 | |
| 1869 | AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); |
| 1870 | ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; |
| 1871 | ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; |
| 1872 | } |
| 1873 | |
| 1874 | /* |
| 1875 | * Get conformance test limit values |
| 1876 | */ |
| 1877 | offset = AR5K_EEPROM_CTL(ah->ah_ee_version); |
| 1878 | ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version); |
| 1879 | |
| 1880 | for (i = 0; i < ee->ee_ctls; i++) { |
| 1881 | AR5K_EEPROM_READ(offset++, val); |
| 1882 | ee->ee_ctl[i] = (val >> 8) & 0xff; |
| 1883 | ee->ee_ctl[i + 1] = val & 0xff; |
| 1884 | } |
| 1885 | |
| 1886 | /* |
| 1887 | * Get values for 802.11a (5GHz) |
| 1888 | */ |
| 1889 | mode = AR5K_EEPROM_MODE_11A; |
| 1890 | |
| 1891 | ee->ee_turbo_max_power[mode] = |
| 1892 | AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); |
| 1893 | |
| 1894 | offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version); |
| 1895 | |
| 1896 | ret = ath5k_eeprom_read_ants(ah, &offset, mode); |
| 1897 | if (ret) |
| 1898 | return ret; |
| 1899 | |
| 1900 | AR5K_EEPROM_READ(offset++, val); |
| 1901 | ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); |
| 1902 | ee->ee_ob[mode][3] = (val >> 5) & 0x7; |
| 1903 | ee->ee_db[mode][3] = (val >> 2) & 0x7; |
| 1904 | ee->ee_ob[mode][2] = (val << 1) & 0x7; |
| 1905 | |
| 1906 | AR5K_EEPROM_READ(offset++, val); |
| 1907 | ee->ee_ob[mode][2] |= (val >> 15) & 0x1; |
| 1908 | ee->ee_db[mode][2] = (val >> 12) & 0x7; |
| 1909 | ee->ee_ob[mode][1] = (val >> 9) & 0x7; |
| 1910 | ee->ee_db[mode][1] = (val >> 6) & 0x7; |
| 1911 | ee->ee_ob[mode][0] = (val >> 3) & 0x7; |
| 1912 | ee->ee_db[mode][0] = val & 0x7; |
| 1913 | |
| 1914 | ret = ath5k_eeprom_read_modes(ah, &offset, mode); |
| 1915 | if (ret) |
| 1916 | return ret; |
| 1917 | |
| 1918 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { |
| 1919 | AR5K_EEPROM_READ(offset++, val); |
| 1920 | ee->ee_margin_tx_rx[mode] = val & 0x3f; |
| 1921 | } |
| 1922 | |
| 1923 | /* |
| 1924 | * Get values for 802.11b (2.4GHz) |
| 1925 | */ |
| 1926 | mode = AR5K_EEPROM_MODE_11B; |
| 1927 | offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version); |
| 1928 | |
| 1929 | ret = ath5k_eeprom_read_ants(ah, &offset, mode); |
| 1930 | if (ret) |
| 1931 | return ret; |
| 1932 | |
| 1933 | AR5K_EEPROM_READ(offset++, val); |
| 1934 | ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); |
| 1935 | ee->ee_ob[mode][1] = (val >> 4) & 0x7; |
| 1936 | ee->ee_db[mode][1] = val & 0x7; |
| 1937 | |
| 1938 | ret = ath5k_eeprom_read_modes(ah, &offset, mode); |
| 1939 | if (ret) |
| 1940 | return ret; |
| 1941 | |
| 1942 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { |
| 1943 | AR5K_EEPROM_READ(offset++, val); |
| 1944 | ee->ee_cal_pier[mode][0] = |
| 1945 | ath5k_eeprom_bin2freq(ah, val & 0xff, mode); |
| 1946 | ee->ee_cal_pier[mode][1] = |
| 1947 | ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode); |
| 1948 | |
| 1949 | AR5K_EEPROM_READ(offset++, val); |
| 1950 | ee->ee_cal_pier[mode][2] = |
| 1951 | ath5k_eeprom_bin2freq(ah, val & 0xff, mode); |
| 1952 | } |
| 1953 | |
| 1954 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) |
| 1955 | ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; |
| 1956 | |
| 1957 | /* |
| 1958 | * Get values for 802.11g (2.4GHz) |
| 1959 | */ |
| 1960 | mode = AR5K_EEPROM_MODE_11G; |
| 1961 | offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version); |
| 1962 | |
| 1963 | ret = ath5k_eeprom_read_ants(ah, &offset, mode); |
| 1964 | if (ret) |
| 1965 | return ret; |
| 1966 | |
| 1967 | AR5K_EEPROM_READ(offset++, val); |
| 1968 | ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); |
| 1969 | ee->ee_ob[mode][1] = (val >> 4) & 0x7; |
| 1970 | ee->ee_db[mode][1] = val & 0x7; |
| 1971 | |
| 1972 | ret = ath5k_eeprom_read_modes(ah, &offset, mode); |
| 1973 | if (ret) |
| 1974 | return ret; |
| 1975 | |
| 1976 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { |
| 1977 | AR5K_EEPROM_READ(offset++, val); |
| 1978 | ee->ee_cal_pier[mode][0] = |
| 1979 | ath5k_eeprom_bin2freq(ah, val & 0xff, mode); |
| 1980 | ee->ee_cal_pier[mode][1] = |
| 1981 | ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode); |
| 1982 | |
| 1983 | AR5K_EEPROM_READ(offset++, val); |
| 1984 | ee->ee_turbo_max_power[mode] = val & 0x7f; |
| 1985 | ee->ee_xr_power[mode] = (val >> 7) & 0x3f; |
| 1986 | |
| 1987 | AR5K_EEPROM_READ(offset++, val); |
| 1988 | ee->ee_cal_pier[mode][2] = |
| 1989 | ath5k_eeprom_bin2freq(ah, val & 0xff, mode); |
| 1990 | |
| 1991 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) |
| 1992 | ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; |
| 1993 | |
| 1994 | AR5K_EEPROM_READ(offset++, val); |
| 1995 | ee->ee_i_cal[mode] = (val >> 8) & 0x3f; |
| 1996 | ee->ee_q_cal[mode] = (val >> 3) & 0x1f; |
| 1997 | |
| 1998 | if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { |
| 1999 | AR5K_EEPROM_READ(offset++, val); |
| 2000 | ee->ee_cck_ofdm_gain_delta = val & 0xff; |
| 2001 | } |
| 2002 | } |
| 2003 | |
| 2004 | /* |
| 2005 | * Read 5GHz EEPROM channels |
| 2006 | */ |
| 2007 | |
| 2008 | return 0; |
| 2009 | } |
| 2010 | |
| 2011 | /* |
| 2012 | * Read the MAC address from eeprom |
| 2013 | */ |
| 2014 | static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) |
| 2015 | { |
| 2016 | u8 mac_d[ETH_ALEN]; |
| 2017 | u32 total, offset; |
| 2018 | u16 data; |
| 2019 | int octet, ret; |
| 2020 | |
| 2021 | memset(mac, 0, ETH_ALEN); |
| 2022 | memset(mac_d, 0, ETH_ALEN); |
| 2023 | |
| 2024 | ret = ath5k_hw_eeprom_read(ah, 0x20, &data); |
| 2025 | if (ret) |
| 2026 | return ret; |
| 2027 | |
| 2028 | for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { |
| 2029 | ret = ath5k_hw_eeprom_read(ah, offset, &data); |
| 2030 | if (ret) |
| 2031 | return ret; |
| 2032 | |
| 2033 | total += data; |
| 2034 | mac_d[octet + 1] = data & 0xff; |
| 2035 | mac_d[octet] = data >> 8; |
| 2036 | octet += 2; |
| 2037 | } |
| 2038 | |
| 2039 | memcpy(mac, mac_d, ETH_ALEN); |
| 2040 | |
| 2041 | if (!total || total == 3 * 0xffff) |
| 2042 | return -EINVAL; |
| 2043 | |
| 2044 | return 0; |
| 2045 | } |
| 2046 | |
| 2047 | /* |
| 2048 | * Read/Write regulatory domain |
| 2049 | */ |
| 2050 | static bool ath5k_eeprom_regulation_domain(struct ath5k_hw *ah, bool write, |
| 2051 | enum ath5k_regdom *regdomain) |
| 2052 | { |
| 2053 | u16 ee_regdomain; |
| 2054 | |
| 2055 | /* Read current value */ |
| 2056 | if (write != true) { |
| 2057 | ee_regdomain = ah->ah_capabilities.cap_eeprom.ee_regdomain; |
| 2058 | *regdomain = ath5k_regdom_to_ieee(ee_regdomain); |
| 2059 | return true; |
| 2060 | } |
| 2061 | |
| 2062 | ee_regdomain = ath5k_regdom_from_ieee(*regdomain); |
| 2063 | |
| 2064 | /* Try to write a new value */ |
| 2065 | if (ah->ah_capabilities.cap_eeprom.ee_protect & |
| 2066 | AR5K_EEPROM_PROTECT_WR_128_191) |
| 2067 | return false; |
| 2068 | if (ath5k_hw_eeprom_write(ah, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0) |
| 2069 | return false; |
| 2070 | |
| 2071 | ah->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; |
| 2072 | |
| 2073 | return true; |
| 2074 | } |
| 2075 | |
| 2076 | /* |
| 2077 | * Use the above to write a new regulatory domain |
| 2078 | */ |
| 2079 | int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain) |
| 2080 | { |
| 2081 | enum ath5k_regdom ieee_regdomain; |
| 2082 | |
| 2083 | ieee_regdomain = ath5k_regdom_to_ieee(regdomain); |
| 2084 | |
| 2085 | if (ath5k_eeprom_regulation_domain(ah, true, &ieee_regdomain) == true) |
| 2086 | return 0; |
| 2087 | |
| 2088 | return -EIO; |
| 2089 | } |
| 2090 | |
| 2091 | /* |
| 2092 | * Fill the capabilities struct |
| 2093 | */ |
| 2094 | static int ath5k_hw_get_capabilities(struct ath5k_hw *ah) |
| 2095 | { |
| 2096 | u16 ee_header; |
| 2097 | |
| 2098 | ATH5K_TRACE(ah->ah_sc); |
| 2099 | /* Capabilities stored in the EEPROM */ |
| 2100 | ee_header = ah->ah_capabilities.cap_eeprom.ee_header; |
| 2101 | |
| 2102 | if (ah->ah_version == AR5K_AR5210) { |
| 2103 | /* |
| 2104 | * Set radio capabilities |
| 2105 | * (The AR5110 only supports the middle 5GHz band) |
| 2106 | */ |
| 2107 | ah->ah_capabilities.cap_range.range_5ghz_min = 5120; |
| 2108 | ah->ah_capabilities.cap_range.range_5ghz_max = 5430; |
| 2109 | ah->ah_capabilities.cap_range.range_2ghz_min = 0; |
| 2110 | ah->ah_capabilities.cap_range.range_2ghz_max = 0; |
| 2111 | |
| 2112 | /* Set supported modes */ |
| 2113 | __set_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode); |
| 2114 | __set_bit(MODE_ATHEROS_TURBO, ah->ah_capabilities.cap_mode); |
| 2115 | } else { |
| 2116 | /* |
| 2117 | * XXX The tranceiver supports frequencies from 4920 to 6100GHz |
| 2118 | * XXX and from 2312 to 2732GHz. There are problems with the |
| 2119 | * XXX current ieee80211 implementation because the IEEE |
| 2120 | * XXX channel mapping does not support negative channel |
| 2121 | * XXX numbers (2312MHz is channel -19). Of course, this |
| 2122 | * XXX doesn't matter because these channels are out of range |
| 2123 | * XXX but some regulation domains like MKK (Japan) will |
| 2124 | * XXX support frequencies somewhere around 4.8GHz. |
| 2125 | */ |
| 2126 | |
| 2127 | /* |
| 2128 | * Set radio capabilities |
| 2129 | */ |
| 2130 | |
| 2131 | if (AR5K_EEPROM_HDR_11A(ee_header)) { |
| 2132 | ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ |
| 2133 | ah->ah_capabilities.cap_range.range_5ghz_max = 6100; |
| 2134 | |
| 2135 | /* Set supported modes */ |
| 2136 | __set_bit(MODE_IEEE80211A, |
| 2137 | ah->ah_capabilities.cap_mode); |
| 2138 | __set_bit(MODE_ATHEROS_TURBO, |
| 2139 | ah->ah_capabilities.cap_mode); |
| 2140 | if (ah->ah_version == AR5K_AR5212) |
| 2141 | __set_bit(MODE_ATHEROS_TURBOG, |
| 2142 | ah->ah_capabilities.cap_mode); |
| 2143 | } |
| 2144 | |
| 2145 | /* Enable 802.11b if a 2GHz capable radio (2111/5112) is |
| 2146 | * connected */ |
| 2147 | if (AR5K_EEPROM_HDR_11B(ee_header) || |
| 2148 | AR5K_EEPROM_HDR_11G(ee_header)) { |
| 2149 | ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ |
| 2150 | ah->ah_capabilities.cap_range.range_2ghz_max = 2732; |
| 2151 | |
| 2152 | if (AR5K_EEPROM_HDR_11B(ee_header)) |
| 2153 | __set_bit(MODE_IEEE80211B, |
| 2154 | ah->ah_capabilities.cap_mode); |
| 2155 | |
| 2156 | if (AR5K_EEPROM_HDR_11G(ee_header)) |
| 2157 | __set_bit(MODE_IEEE80211G, |
| 2158 | ah->ah_capabilities.cap_mode); |
| 2159 | } |
| 2160 | } |
| 2161 | |
| 2162 | /* GPIO */ |
| 2163 | ah->ah_gpio_npins = AR5K_NUM_GPIO; |
| 2164 | |
| 2165 | /* Set number of supported TX queues */ |
| 2166 | if (ah->ah_version == AR5K_AR5210) |
| 2167 | ah->ah_capabilities.cap_queues.q_tx_num = |
| 2168 | AR5K_NUM_TX_QUEUES_NOQCU; |
| 2169 | else |
| 2170 | ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES; |
| 2171 | |
| 2172 | return 0; |
| 2173 | } |
| 2174 | |
| 2175 | /*********************************\ |
| 2176 | Protocol Control Unit Functions |
| 2177 | \*********************************/ |
| 2178 | |
| 2179 | /* |
| 2180 | * Set Operation mode |
| 2181 | */ |
| 2182 | int ath5k_hw_set_opmode(struct ath5k_hw *ah) |
| 2183 | { |
| 2184 | u32 pcu_reg, beacon_reg, low_id, high_id; |
| 2185 | |
| 2186 | pcu_reg = 0; |
| 2187 | beacon_reg = 0; |
| 2188 | |
| 2189 | ATH5K_TRACE(ah->ah_sc); |
| 2190 | |
| 2191 | switch (ah->ah_op_mode) { |
| 2192 | case IEEE80211_IF_TYPE_IBSS: |
| 2193 | pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA | |
| 2194 | (ah->ah_version == AR5K_AR5210 ? |
| 2195 | AR5K_STA_ID1_NO_PSPOLL : 0); |
| 2196 | beacon_reg |= AR5K_BCR_ADHOC; |
| 2197 | break; |
| 2198 | |
| 2199 | case IEEE80211_IF_TYPE_AP: |
| 2200 | pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA | |
| 2201 | (ah->ah_version == AR5K_AR5210 ? |
| 2202 | AR5K_STA_ID1_NO_PSPOLL : 0); |
| 2203 | beacon_reg |= AR5K_BCR_AP; |
| 2204 | break; |
| 2205 | |
| 2206 | case IEEE80211_IF_TYPE_STA: |
| 2207 | pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | |
| 2208 | (ah->ah_version == AR5K_AR5210 ? |
| 2209 | AR5K_STA_ID1_PWR_SV : 0); |
| 2210 | case IEEE80211_IF_TYPE_MNTR: |
| 2211 | pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA | |
| 2212 | (ah->ah_version == AR5K_AR5210 ? |
| 2213 | AR5K_STA_ID1_NO_PSPOLL : 0); |
| 2214 | break; |
| 2215 | |
| 2216 | default: |
| 2217 | return -EINVAL; |
| 2218 | } |
| 2219 | |
| 2220 | /* |
| 2221 | * Set PCU registers |
| 2222 | */ |
| 2223 | low_id = AR5K_LOW_ID(ah->ah_sta_id); |
| 2224 | high_id = AR5K_HIGH_ID(ah->ah_sta_id); |
| 2225 | ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); |
| 2226 | ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); |
| 2227 | |
| 2228 | /* |
| 2229 | * Set Beacon Control Register on 5210 |
| 2230 | */ |
| 2231 | if (ah->ah_version == AR5K_AR5210) |
| 2232 | ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); |
| 2233 | |
| 2234 | return 0; |
| 2235 | } |
| 2236 | |
| 2237 | /* |
| 2238 | * BSSID Functions |
| 2239 | */ |
| 2240 | |
| 2241 | /* |
| 2242 | * Get station id |
| 2243 | */ |
| 2244 | void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac) |
| 2245 | { |
| 2246 | ATH5K_TRACE(ah->ah_sc); |
| 2247 | memcpy(mac, ah->ah_sta_id, ETH_ALEN); |
| 2248 | } |
| 2249 | |
| 2250 | /* |
| 2251 | * Set station id |
| 2252 | */ |
| 2253 | int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) |
| 2254 | { |
| 2255 | u32 low_id, high_id; |
| 2256 | |
| 2257 | ATH5K_TRACE(ah->ah_sc); |
| 2258 | /* Set new station ID */ |
| 2259 | memcpy(ah->ah_sta_id, mac, ETH_ALEN); |
| 2260 | |
| 2261 | low_id = AR5K_LOW_ID(mac); |
| 2262 | high_id = AR5K_HIGH_ID(mac); |
| 2263 | |
| 2264 | ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); |
| 2265 | ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1); |
| 2266 | |
| 2267 | return 0; |
| 2268 | } |
| 2269 | |
| 2270 | /* |
| 2271 | * Set BSSID |
| 2272 | */ |
| 2273 | void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id) |
| 2274 | { |
| 2275 | u32 low_id, high_id; |
| 2276 | u16 tim_offset = 0; |
| 2277 | |
| 2278 | /* |
| 2279 | * Set simple BSSID mask on 5212 |
| 2280 | */ |
| 2281 | if (ah->ah_version == AR5K_AR5212) { |
| 2282 | ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM0); |
| 2283 | ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM1); |
| 2284 | } |
| 2285 | |
| 2286 | /* |
| 2287 | * Set BSSID which triggers the "SME Join" operation |
| 2288 | */ |
| 2289 | low_id = AR5K_LOW_ID(bssid); |
| 2290 | high_id = AR5K_HIGH_ID(bssid); |
| 2291 | ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0); |
| 2292 | ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) << |
| 2293 | AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); |
| 2294 | |
| 2295 | if (assoc_id == 0) { |
| 2296 | ath5k_hw_disable_pspoll(ah); |
| 2297 | return; |
| 2298 | } |
| 2299 | |
| 2300 | AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, |
| 2301 | tim_offset ? tim_offset + 4 : 0); |
| 2302 | |
| 2303 | ath5k_hw_enable_pspoll(ah, NULL, 0); |
| 2304 | } |
| 2305 | /** |
| 2306 | * ath5k_hw_set_bssid_mask - set common bits we should listen to |
| 2307 | * |
| 2308 | * The bssid_mask is a utility used by AR5212 hardware to inform the hardware |
| 2309 | * which bits of the interface's MAC address should be looked at when trying |
| 2310 | * to decide which packets to ACK. In station mode every bit matters. In AP |
| 2311 | * mode with a single BSS every bit matters as well. In AP mode with |
| 2312 | * multiple BSSes not every bit matters. |
| 2313 | * |
| 2314 | * @ah: the &struct ath5k_hw |
| 2315 | * @mask: the bssid_mask, a u8 array of size ETH_ALEN |
| 2316 | * |
| 2317 | * Note that this is a simple filter and *does* not filter out all |
| 2318 | * relevant frames. Some non-relevant frames will get through, probability |
| 2319 | * jocks are welcomed to compute. |
| 2320 | * |
| 2321 | * When handling multiple BSSes (or VAPs) you can get the BSSID mask by |
| 2322 | * computing the set of: |
| 2323 | * |
| 2324 | * ~ ( MAC XOR BSSID ) |
| 2325 | * |
| 2326 | * When you do this you are essentially computing the common bits. Later it |
| 2327 | * is assumed the harware will "and" (&) the BSSID mask with the MAC address |
| 2328 | * to obtain the relevant bits which should match on the destination frame. |
| 2329 | * |
| 2330 | * Simple example: on your card you have have two BSSes you have created with |
| 2331 | * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address. |
| 2332 | * There is another BSSID-03 but you are not part of it. For simplicity's sake, |
| 2333 | * assuming only 4 bits for a mac address and for BSSIDs you can then have: |
| 2334 | * |
| 2335 | * \ |
| 2336 | * MAC: 0001 | |
| 2337 | * BSSID-01: 0100 | --> Belongs to us |
| 2338 | * BSSID-02: 1001 | |
| 2339 | * / |
| 2340 | * ------------------- |
| 2341 | * BSSID-03: 0110 | --> External |
| 2342 | * ------------------- |
| 2343 | * |
| 2344 | * Our bssid_mask would then be: |
| 2345 | * |
| 2346 | * On loop iteration for BSSID-01: |
| 2347 | * ~(0001 ^ 0100) -> ~(0101) |
| 2348 | * -> 1010 |
| 2349 | * bssid_mask = 1010 |
| 2350 | * |
| 2351 | * On loop iteration for BSSID-02: |
| 2352 | * bssid_mask &= ~(0001 ^ 1001) |
| 2353 | * bssid_mask = (1010) & ~(0001 ^ 1001) |
| 2354 | * bssid_mask = (1010) & ~(1001) |
| 2355 | * bssid_mask = (1010) & (0110) |
| 2356 | * bssid_mask = 0010 |
| 2357 | * |
| 2358 | * A bssid_mask of 0010 means "only pay attention to the second least |
| 2359 | * significant bit". This is because its the only bit common |
| 2360 | * amongst the MAC and all BSSIDs we support. To findout what the real |
| 2361 | * common bit is we can simply "&" the bssid_mask now with any BSSID we have |
| 2362 | * or our MAC address (we assume the hardware uses the MAC address). |
| 2363 | * |
| 2364 | * Now, suppose there's an incoming frame for BSSID-03: |
| 2365 | * |
| 2366 | * IFRAME-01: 0110 |
| 2367 | * |
| 2368 | * An easy eye-inspeciton of this already should tell you that this frame |
| 2369 | * will not pass our check. This is beacuse the bssid_mask tells the |
| 2370 | * hardware to only look at the second least significant bit and the |
| 2371 | * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB |
| 2372 | * as 1, which does not match 0. |
| 2373 | * |
| 2374 | * So with IFRAME-01 we *assume* the hardware will do: |
| 2375 | * |
| 2376 | * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0; |
| 2377 | * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0; |
| 2378 | * --> allow = (0010) == 0000 ? 1 : 0; |
| 2379 | * --> allow = 0 |
| 2380 | * |
| 2381 | * Lets now test a frame that should work: |
| 2382 | * |
| 2383 | * IFRAME-02: 0001 (we should allow) |
| 2384 | * |
| 2385 | * allow = (0001 & 1010) == 1010 |
| 2386 | * |
| 2387 | * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0; |
| 2388 | * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0; |
| 2389 | * --> allow = (0010) == (0010) |
| 2390 | * --> allow = 1 |
| 2391 | * |
| 2392 | * Other examples: |
| 2393 | * |
| 2394 | * IFRAME-03: 0100 --> allowed |
| 2395 | * IFRAME-04: 1001 --> allowed |
| 2396 | * IFRAME-05: 1101 --> allowed but its not for us!!! |
| 2397 | * |
| 2398 | */ |
| 2399 | int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) |
| 2400 | { |
| 2401 | u32 low_id, high_id; |
| 2402 | ATH5K_TRACE(ah->ah_sc); |
| 2403 | |
| 2404 | if (ah->ah_version == AR5K_AR5212) { |
| 2405 | low_id = AR5K_LOW_ID(mask); |
| 2406 | high_id = AR5K_HIGH_ID(mask); |
| 2407 | |
| 2408 | ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0); |
| 2409 | ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1); |
| 2410 | |
| 2411 | return 0; |
| 2412 | } |
| 2413 | |
| 2414 | return -EIO; |
| 2415 | } |
| 2416 | |
| 2417 | /* |
| 2418 | * Receive start/stop functions |
| 2419 | */ |
| 2420 | |
| 2421 | /* |
| 2422 | * Start receive on PCU |
| 2423 | */ |
| 2424 | void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) |
| 2425 | { |
| 2426 | ATH5K_TRACE(ah->ah_sc); |
| 2427 | AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); |
| 2428 | } |
| 2429 | |
| 2430 | /* |
| 2431 | * Stop receive on PCU |
| 2432 | */ |
| 2433 | void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah) |
| 2434 | { |
| 2435 | ATH5K_TRACE(ah->ah_sc); |
| 2436 | AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); |
| 2437 | } |
| 2438 | |
| 2439 | /* |
| 2440 | * RX Filter functions |
| 2441 | */ |
| 2442 | |
| 2443 | /* |
| 2444 | * Set multicast filter |
| 2445 | */ |
| 2446 | void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) |
| 2447 | { |
| 2448 | ATH5K_TRACE(ah->ah_sc); |
| 2449 | /* Set the multicat filter */ |
| 2450 | ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); |
| 2451 | ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); |
| 2452 | } |
| 2453 | |
| 2454 | /* |
| 2455 | * Set multicast filter by index |
| 2456 | */ |
| 2457 | int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index) |
| 2458 | { |
| 2459 | |
| 2460 | ATH5K_TRACE(ah->ah_sc); |
| 2461 | if (index >= 64) |
| 2462 | return -EINVAL; |
| 2463 | else if (index >= 32) |
| 2464 | AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1, |
| 2465 | (1 << (index - 32))); |
| 2466 | else |
| 2467 | AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); |
| 2468 | |
| 2469 | return 0; |
| 2470 | } |
| 2471 | |
| 2472 | /* |
| 2473 | * Clear Multicast filter by index |
| 2474 | */ |
| 2475 | int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index) |
| 2476 | { |
| 2477 | |
| 2478 | ATH5K_TRACE(ah->ah_sc); |
| 2479 | if (index >= 64) |
| 2480 | return -EINVAL; |
| 2481 | else if (index >= 32) |
| 2482 | AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1, |
| 2483 | (1 << (index - 32))); |
| 2484 | else |
| 2485 | AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); |
| 2486 | |
| 2487 | return 0; |
| 2488 | } |
| 2489 | |
| 2490 | /* |
| 2491 | * Get current rx filter |
| 2492 | */ |
| 2493 | u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) |
| 2494 | { |
| 2495 | u32 data, filter = 0; |
| 2496 | |
| 2497 | ATH5K_TRACE(ah->ah_sc); |
| 2498 | filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); |
| 2499 | |
| 2500 | /*Radar detection for 5212*/ |
| 2501 | if (ah->ah_version == AR5K_AR5212) { |
| 2502 | data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); |
| 2503 | |
| 2504 | if (data & AR5K_PHY_ERR_FIL_RADAR) |
| 2505 | filter |= AR5K_RX_FILTER_RADARERR; |
| 2506 | if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) |
| 2507 | filter |= AR5K_RX_FILTER_PHYERR; |
| 2508 | } |
| 2509 | |
| 2510 | return filter; |
| 2511 | } |
| 2512 | |
| 2513 | /* |
| 2514 | * Set rx filter |
| 2515 | */ |
| 2516 | void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) |
| 2517 | { |
| 2518 | u32 data = 0; |
| 2519 | |
| 2520 | ATH5K_TRACE(ah->ah_sc); |
| 2521 | |
| 2522 | /* Set PHY error filter register on 5212*/ |
| 2523 | if (ah->ah_version == AR5K_AR5212) { |
| 2524 | if (filter & AR5K_RX_FILTER_RADARERR) |
| 2525 | data |= AR5K_PHY_ERR_FIL_RADAR; |
| 2526 | if (filter & AR5K_RX_FILTER_PHYERR) |
| 2527 | data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; |
| 2528 | } |
| 2529 | |
| 2530 | /* |
| 2531 | * The AR5210 uses promiscous mode to detect radar activity |
| 2532 | */ |
| 2533 | if (ah->ah_version == AR5K_AR5210 && |
| 2534 | (filter & AR5K_RX_FILTER_RADARERR)) { |
| 2535 | filter &= ~AR5K_RX_FILTER_RADARERR; |
| 2536 | filter |= AR5K_RX_FILTER_PROM; |
| 2537 | } |
| 2538 | |
| 2539 | /*Zero length DMA*/ |
| 2540 | if (data) |
| 2541 | AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); |
| 2542 | else |
| 2543 | AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); |
| 2544 | |
| 2545 | /*Write RX Filter register*/ |
| 2546 | ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); |
| 2547 | |
| 2548 | /*Write PHY error filter register on 5212*/ |
| 2549 | if (ah->ah_version == AR5K_AR5212) |
| 2550 | ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); |
| 2551 | |
| 2552 | } |
| 2553 | |
| 2554 | /* |
| 2555 | * Beacon related functions |
| 2556 | */ |
| 2557 | |
| 2558 | /* |
| 2559 | * Get a 32bit TSF |
| 2560 | */ |
| 2561 | u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah) |
| 2562 | { |
| 2563 | ATH5K_TRACE(ah->ah_sc); |
| 2564 | return ath5k_hw_reg_read(ah, AR5K_TSF_L32); |
| 2565 | } |
| 2566 | |
| 2567 | /* |
| 2568 | * Get the full 64bit TSF |
| 2569 | */ |
| 2570 | u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) |
| 2571 | { |
| 2572 | u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32); |
| 2573 | ATH5K_TRACE(ah->ah_sc); |
| 2574 | |
| 2575 | return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32); |
| 2576 | } |
| 2577 | |
| 2578 | /* |
| 2579 | * Force a TSF reset |
| 2580 | */ |
| 2581 | void ath5k_hw_reset_tsf(struct ath5k_hw *ah) |
| 2582 | { |
| 2583 | ATH5K_TRACE(ah->ah_sc); |
| 2584 | AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF); |
| 2585 | } |
| 2586 | |
| 2587 | /* |
| 2588 | * Initialize beacon timers |
| 2589 | */ |
| 2590 | void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) |
| 2591 | { |
| 2592 | u32 timer1, timer2, timer3; |
| 2593 | |
| 2594 | ATH5K_TRACE(ah->ah_sc); |
| 2595 | /* |
| 2596 | * Set the additional timers by mode |
| 2597 | */ |
| 2598 | switch (ah->ah_op_mode) { |
| 2599 | case IEEE80211_IF_TYPE_STA: |
| 2600 | if (ah->ah_version == AR5K_AR5210) { |
| 2601 | timer1 = 0xffffffff; |
| 2602 | timer2 = 0xffffffff; |
| 2603 | } else { |
| 2604 | timer1 = 0x0000ffff; |
| 2605 | timer2 = 0x0007ffff; |
| 2606 | } |
| 2607 | break; |
| 2608 | |
| 2609 | default: |
Bruno Randolf | 1008e0f | 2008-01-18 21:51:19 +0900 | [diff] [blame] | 2610 | timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; |
| 2611 | timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 2612 | } |
| 2613 | |
| 2614 | timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1); |
| 2615 | |
| 2616 | /* |
| 2617 | * Set the beacon register and enable all timers. |
| 2618 | * (next beacon, DMA beacon, software beacon, ATIM window time) |
| 2619 | */ |
| 2620 | ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); |
| 2621 | ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); |
| 2622 | ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); |
| 2623 | ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); |
| 2624 | |
| 2625 | ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | |
| 2626 | AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE), |
| 2627 | AR5K_BEACON); |
| 2628 | } |
| 2629 | |
| 2630 | #if 0 |
| 2631 | /* |
| 2632 | * Set beacon timers |
| 2633 | */ |
| 2634 | int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, |
| 2635 | const struct ath5k_beacon_state *state) |
| 2636 | { |
| 2637 | u32 cfp_period, next_cfp, dtim, interval, next_beacon; |
| 2638 | |
| 2639 | /* |
| 2640 | * TODO: should be changed through *state |
| 2641 | * review struct ath5k_beacon_state struct |
| 2642 | * |
| 2643 | * XXX: These are used for cfp period bellow, are they |
| 2644 | * ok ? Is it O.K. for tsf here to be 0 or should we use |
| 2645 | * get_tsf ? |
| 2646 | */ |
| 2647 | u32 dtim_count = 0; /* XXX */ |
| 2648 | u32 cfp_count = 0; /* XXX */ |
| 2649 | u32 tsf = 0; /* XXX */ |
| 2650 | |
| 2651 | ATH5K_TRACE(ah->ah_sc); |
| 2652 | /* Return on an invalid beacon state */ |
| 2653 | if (state->bs_interval < 1) |
| 2654 | return -EINVAL; |
| 2655 | |
| 2656 | interval = state->bs_interval; |
| 2657 | dtim = state->bs_dtim_period; |
| 2658 | |
| 2659 | /* |
| 2660 | * PCF support? |
| 2661 | */ |
| 2662 | if (state->bs_cfp_period > 0) { |
| 2663 | /* |
| 2664 | * Enable PCF mode and set the CFP |
| 2665 | * (Contention Free Period) and timer registers |
| 2666 | */ |
| 2667 | cfp_period = state->bs_cfp_period * state->bs_dtim_period * |
| 2668 | state->bs_interval; |
| 2669 | next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * |
| 2670 | state->bs_interval; |
| 2671 | |
| 2672 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, |
| 2673 | AR5K_STA_ID1_DEFAULT_ANTENNA | |
| 2674 | AR5K_STA_ID1_PCF); |
| 2675 | ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD); |
| 2676 | ath5k_hw_reg_write(ah, state->bs_cfp_max_duration, |
| 2677 | AR5K_CFP_DUR); |
| 2678 | ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period : |
| 2679 | next_cfp)) << 3, AR5K_TIMER2); |
| 2680 | } else { |
| 2681 | /* Disable PCF mode */ |
| 2682 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, |
| 2683 | AR5K_STA_ID1_DEFAULT_ANTENNA | |
| 2684 | AR5K_STA_ID1_PCF); |
| 2685 | } |
| 2686 | |
| 2687 | /* |
| 2688 | * Enable the beacon timer register |
| 2689 | */ |
| 2690 | ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0); |
| 2691 | |
| 2692 | /* |
| 2693 | * Start the beacon timers |
| 2694 | */ |
| 2695 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~ |
| 2696 | (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | |
| 2697 | AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, |
| 2698 | AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, |
| 2699 | AR5K_BEACON_PERIOD), AR5K_BEACON); |
| 2700 | |
| 2701 | /* |
| 2702 | * Write new beacon miss threshold, if it appears to be valid |
| 2703 | * XXX: Figure out right values for min <= bs_bmiss_threshold <= max |
| 2704 | * and return if its not in range. We can test this by reading value and |
| 2705 | * setting value to a largest value and seeing which values register. |
| 2706 | */ |
| 2707 | |
| 2708 | AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, |
| 2709 | state->bs_bmiss_threshold); |
| 2710 | |
| 2711 | /* |
| 2712 | * Set sleep control register |
| 2713 | * XXX: Didn't find this in 5210 code but since this register |
| 2714 | * exists also in ar5k's 5210 headers i leave it as common code. |
| 2715 | */ |
| 2716 | AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, |
| 2717 | (state->bs_sleep_duration - 3) << 3); |
| 2718 | |
| 2719 | /* |
| 2720 | * Set enhanced sleep registers on 5212 |
| 2721 | */ |
| 2722 | if (ah->ah_version == AR5K_AR5212) { |
| 2723 | if (state->bs_sleep_duration > state->bs_interval && |
| 2724 | roundup(state->bs_sleep_duration, interval) == |
| 2725 | state->bs_sleep_duration) |
| 2726 | interval = state->bs_sleep_duration; |
| 2727 | |
| 2728 | if (state->bs_sleep_duration > dtim && (dtim == 0 || |
| 2729 | roundup(state->bs_sleep_duration, dtim) == |
| 2730 | state->bs_sleep_duration)) |
| 2731 | dtim = state->bs_sleep_duration; |
| 2732 | |
| 2733 | if (interval > dtim) |
| 2734 | return -EINVAL; |
| 2735 | |
| 2736 | next_beacon = interval == dtim ? state->bs_next_dtim : |
| 2737 | state->bs_next_beacon; |
| 2738 | |
| 2739 | ath5k_hw_reg_write(ah, |
| 2740 | AR5K_REG_SM((state->bs_next_dtim - 3) << 3, |
| 2741 | AR5K_SLEEP0_NEXT_DTIM) | |
| 2742 | AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | |
| 2743 | AR5K_SLEEP0_ENH_SLEEP_EN | |
| 2744 | AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); |
| 2745 | |
| 2746 | ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3, |
| 2747 | AR5K_SLEEP1_NEXT_TIM) | |
| 2748 | AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); |
| 2749 | |
| 2750 | ath5k_hw_reg_write(ah, |
| 2751 | AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | |
| 2752 | AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); |
| 2753 | } |
| 2754 | |
| 2755 | return 0; |
| 2756 | } |
| 2757 | |
| 2758 | /* |
| 2759 | * Reset beacon timers |
| 2760 | */ |
| 2761 | void ath5k_hw_reset_beacon(struct ath5k_hw *ah) |
| 2762 | { |
| 2763 | ATH5K_TRACE(ah->ah_sc); |
| 2764 | /* |
| 2765 | * Disable beacon timer |
| 2766 | */ |
| 2767 | ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); |
| 2768 | |
| 2769 | /* |
| 2770 | * Disable some beacon register values |
| 2771 | */ |
| 2772 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, |
| 2773 | AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); |
| 2774 | ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON); |
| 2775 | } |
| 2776 | |
| 2777 | /* |
| 2778 | * Wait for beacon queue to finish |
| 2779 | */ |
| 2780 | int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr) |
| 2781 | { |
| 2782 | unsigned int i; |
| 2783 | int ret; |
| 2784 | |
| 2785 | ATH5K_TRACE(ah->ah_sc); |
| 2786 | |
| 2787 | /* 5210 doesn't have QCU*/ |
| 2788 | if (ah->ah_version == AR5K_AR5210) { |
| 2789 | /* |
| 2790 | * Wait for beaconn queue to finish by checking |
| 2791 | * Control Register and Beacon Status Register. |
| 2792 | */ |
| 2793 | for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) { |
| 2794 | if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F) |
| 2795 | || |
| 2796 | !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F)) |
| 2797 | break; |
| 2798 | udelay(10); |
| 2799 | } |
| 2800 | |
| 2801 | /* Timeout... */ |
| 2802 | if (i <= 0) { |
| 2803 | /* |
| 2804 | * Re-schedule the beacon queue |
| 2805 | */ |
| 2806 | ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1); |
| 2807 | ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, |
| 2808 | AR5K_BCR); |
| 2809 | |
| 2810 | return -EIO; |
| 2811 | } |
| 2812 | ret = 0; |
| 2813 | } else { |
| 2814 | /*5211/5212*/ |
| 2815 | ret = ath5k_hw_register_timeout(ah, |
| 2816 | AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), |
| 2817 | AR5K_QCU_STS_FRMPENDCNT, 0, false); |
| 2818 | |
| 2819 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) |
| 2820 | return -EIO; |
| 2821 | } |
| 2822 | |
| 2823 | return ret; |
| 2824 | } |
| 2825 | #endif |
| 2826 | |
| 2827 | /* |
| 2828 | * Update mib counters (statistics) |
| 2829 | */ |
| 2830 | void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, |
| 2831 | struct ath5k_mib_stats *statistics) |
| 2832 | { |
| 2833 | ATH5K_TRACE(ah->ah_sc); |
| 2834 | /* Read-And-Clear */ |
| 2835 | statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); |
| 2836 | statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); |
| 2837 | statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK); |
| 2838 | statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); |
| 2839 | statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); |
| 2840 | |
| 2841 | /* Reset profile count registers on 5212*/ |
| 2842 | if (ah->ah_version == AR5K_AR5212) { |
| 2843 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX); |
| 2844 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX); |
| 2845 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR); |
| 2846 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE); |
| 2847 | } |
| 2848 | } |
| 2849 | |
| 2850 | /** ath5k_hw_set_ack_bitrate - set bitrate for ACKs |
| 2851 | * |
| 2852 | * @ah: the &struct ath5k_hw |
| 2853 | * @high: determines if to use low bit rate or now |
| 2854 | */ |
| 2855 | void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high) |
| 2856 | { |
| 2857 | if (ah->ah_version != AR5K_AR5212) |
| 2858 | return; |
| 2859 | else { |
| 2860 | u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; |
| 2861 | if (high) |
| 2862 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); |
| 2863 | else |
| 2864 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); |
| 2865 | } |
| 2866 | } |
| 2867 | |
| 2868 | |
| 2869 | /* |
| 2870 | * ACK/CTS Timeouts |
| 2871 | */ |
| 2872 | |
| 2873 | /* |
| 2874 | * Set ACK timeout on PCU |
| 2875 | */ |
| 2876 | int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) |
| 2877 | { |
| 2878 | ATH5K_TRACE(ah->ah_sc); |
| 2879 | if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), |
| 2880 | ah->ah_turbo) <= timeout) |
| 2881 | return -EINVAL; |
| 2882 | |
| 2883 | AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, |
| 2884 | ath5k_hw_htoclock(timeout, ah->ah_turbo)); |
| 2885 | |
| 2886 | return 0; |
| 2887 | } |
| 2888 | |
| 2889 | /* |
| 2890 | * Read the ACK timeout from PCU |
| 2891 | */ |
| 2892 | unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah) |
| 2893 | { |
| 2894 | ATH5K_TRACE(ah->ah_sc); |
| 2895 | |
| 2896 | return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, |
| 2897 | AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo); |
| 2898 | } |
| 2899 | |
| 2900 | /* |
| 2901 | * Set CTS timeout on PCU |
| 2902 | */ |
| 2903 | int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) |
| 2904 | { |
| 2905 | ATH5K_TRACE(ah->ah_sc); |
| 2906 | if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), |
| 2907 | ah->ah_turbo) <= timeout) |
| 2908 | return -EINVAL; |
| 2909 | |
| 2910 | AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, |
| 2911 | ath5k_hw_htoclock(timeout, ah->ah_turbo)); |
| 2912 | |
| 2913 | return 0; |
| 2914 | } |
| 2915 | |
| 2916 | /* |
| 2917 | * Read CTS timeout from PCU |
| 2918 | */ |
| 2919 | unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah) |
| 2920 | { |
| 2921 | ATH5K_TRACE(ah->ah_sc); |
| 2922 | return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, |
| 2923 | AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo); |
| 2924 | } |
| 2925 | |
| 2926 | /* |
| 2927 | * Key table (WEP) functions |
| 2928 | */ |
| 2929 | |
| 2930 | int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry) |
| 2931 | { |
| 2932 | unsigned int i; |
| 2933 | |
| 2934 | ATH5K_TRACE(ah->ah_sc); |
| 2935 | AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); |
| 2936 | |
| 2937 | for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) |
| 2938 | ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); |
| 2939 | |
| 2940 | /* Set NULL encryption on non-5210*/ |
| 2941 | if (ah->ah_version != AR5K_AR5210) |
| 2942 | ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, |
| 2943 | AR5K_KEYTABLE_TYPE(entry)); |
| 2944 | |
| 2945 | return 0; |
| 2946 | } |
| 2947 | |
| 2948 | int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry) |
| 2949 | { |
| 2950 | ATH5K_TRACE(ah->ah_sc); |
| 2951 | AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); |
| 2952 | |
| 2953 | /* Check the validation flag at the end of the entry */ |
| 2954 | return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) & |
| 2955 | AR5K_KEYTABLE_VALID; |
| 2956 | } |
| 2957 | |
| 2958 | int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, |
| 2959 | const struct ieee80211_key_conf *key, const u8 *mac) |
| 2960 | { |
| 2961 | unsigned int i; |
| 2962 | __le32 key_v[5] = {}; |
| 2963 | u32 keytype; |
| 2964 | |
| 2965 | ATH5K_TRACE(ah->ah_sc); |
| 2966 | |
| 2967 | /* key->keylen comes in from mac80211 in bytes */ |
| 2968 | |
| 2969 | if (key->keylen > AR5K_KEYTABLE_SIZE / 8) |
| 2970 | return -EOPNOTSUPP; |
| 2971 | |
| 2972 | switch (key->keylen) { |
| 2973 | /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */ |
| 2974 | case 40 / 8: |
| 2975 | memcpy(&key_v[0], key->key, 5); |
| 2976 | keytype = AR5K_KEYTABLE_TYPE_40; |
| 2977 | break; |
| 2978 | |
| 2979 | /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */ |
| 2980 | case 104 / 8: |
| 2981 | memcpy(&key_v[0], &key->key[0], 6); |
| 2982 | memcpy(&key_v[2], &key->key[6], 6); |
| 2983 | memcpy(&key_v[4], &key->key[12], 1); |
| 2984 | keytype = AR5K_KEYTABLE_TYPE_104; |
| 2985 | break; |
| 2986 | /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */ |
| 2987 | case 128 / 8: |
| 2988 | memcpy(&key_v[0], &key->key[0], 6); |
| 2989 | memcpy(&key_v[2], &key->key[6], 6); |
| 2990 | memcpy(&key_v[4], &key->key[12], 4); |
| 2991 | keytype = AR5K_KEYTABLE_TYPE_128; |
| 2992 | break; |
| 2993 | |
| 2994 | default: |
| 2995 | return -EINVAL; /* shouldn't happen */ |
| 2996 | } |
| 2997 | |
| 2998 | for (i = 0; i < ARRAY_SIZE(key_v); i++) |
| 2999 | ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]), |
| 3000 | AR5K_KEYTABLE_OFF(entry, i)); |
| 3001 | |
| 3002 | ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry)); |
| 3003 | |
| 3004 | return ath5k_hw_set_key_lladdr(ah, entry, mac); |
| 3005 | } |
| 3006 | |
| 3007 | int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac) |
| 3008 | { |
| 3009 | u32 low_id, high_id; |
| 3010 | |
| 3011 | ATH5K_TRACE(ah->ah_sc); |
| 3012 | /* Invalid entry (key table overflow) */ |
| 3013 | AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); |
| 3014 | |
| 3015 | /* MAC may be NULL if it's a broadcast key. In this case no need to |
| 3016 | * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */ |
| 3017 | if (unlikely(mac == NULL)) { |
| 3018 | low_id = 0xffffffff; |
| 3019 | high_id = 0xffff | AR5K_KEYTABLE_VALID; |
| 3020 | } else { |
| 3021 | low_id = AR5K_LOW_ID(mac); |
| 3022 | high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID; |
| 3023 | } |
| 3024 | |
| 3025 | ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry)); |
| 3026 | ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry)); |
| 3027 | |
| 3028 | return 0; |
| 3029 | } |
| 3030 | |
| 3031 | |
| 3032 | /********************************************\ |
| 3033 | Queue Control Unit, DFS Control Unit Functions |
| 3034 | \********************************************/ |
| 3035 | |
| 3036 | /* |
| 3037 | * Initialize a transmit queue |
| 3038 | */ |
| 3039 | int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, |
| 3040 | struct ath5k_txq_info *queue_info) |
| 3041 | { |
| 3042 | unsigned int queue; |
| 3043 | int ret; |
| 3044 | |
| 3045 | ATH5K_TRACE(ah->ah_sc); |
| 3046 | |
| 3047 | /* |
| 3048 | * Get queue by type |
| 3049 | */ |
| 3050 | /*5210 only has 2 queues*/ |
| 3051 | if (ah->ah_version == AR5K_AR5210) { |
| 3052 | switch (queue_type) { |
| 3053 | case AR5K_TX_QUEUE_DATA: |
| 3054 | queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; |
| 3055 | break; |
| 3056 | case AR5K_TX_QUEUE_BEACON: |
| 3057 | case AR5K_TX_QUEUE_CAB: |
| 3058 | queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; |
| 3059 | break; |
| 3060 | default: |
| 3061 | return -EINVAL; |
| 3062 | } |
| 3063 | } else { |
| 3064 | switch (queue_type) { |
| 3065 | case AR5K_TX_QUEUE_DATA: |
| 3066 | for (queue = AR5K_TX_QUEUE_ID_DATA_MIN; |
| 3067 | ah->ah_txq[queue].tqi_type != |
| 3068 | AR5K_TX_QUEUE_INACTIVE; queue++) { |
| 3069 | |
| 3070 | if (queue > AR5K_TX_QUEUE_ID_DATA_MAX) |
| 3071 | return -EINVAL; |
| 3072 | } |
| 3073 | break; |
| 3074 | case AR5K_TX_QUEUE_UAPSD: |
| 3075 | queue = AR5K_TX_QUEUE_ID_UAPSD; |
| 3076 | break; |
| 3077 | case AR5K_TX_QUEUE_BEACON: |
| 3078 | queue = AR5K_TX_QUEUE_ID_BEACON; |
| 3079 | break; |
| 3080 | case AR5K_TX_QUEUE_CAB: |
| 3081 | queue = AR5K_TX_QUEUE_ID_CAB; |
| 3082 | break; |
| 3083 | case AR5K_TX_QUEUE_XR_DATA: |
| 3084 | if (ah->ah_version != AR5K_AR5212) |
| 3085 | ATH5K_ERR(ah->ah_sc, |
| 3086 | "XR data queues only supported in" |
| 3087 | " 5212!\n"); |
| 3088 | queue = AR5K_TX_QUEUE_ID_XR_DATA; |
| 3089 | break; |
| 3090 | default: |
| 3091 | return -EINVAL; |
| 3092 | } |
| 3093 | } |
| 3094 | |
| 3095 | /* |
| 3096 | * Setup internal queue structure |
| 3097 | */ |
| 3098 | memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info)); |
| 3099 | ah->ah_txq[queue].tqi_type = queue_type; |
| 3100 | |
| 3101 | if (queue_info != NULL) { |
| 3102 | queue_info->tqi_type = queue_type; |
| 3103 | ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info); |
| 3104 | if (ret) |
| 3105 | return ret; |
| 3106 | } |
| 3107 | /* |
| 3108 | * We use ah_txq_status to hold a temp value for |
| 3109 | * the Secondary interrupt mask registers on 5211+ |
| 3110 | * check out ath5k_hw_reset_tx_queue |
| 3111 | */ |
| 3112 | AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue); |
| 3113 | |
| 3114 | return queue; |
| 3115 | } |
| 3116 | |
| 3117 | /* |
| 3118 | * Setup a transmit queue |
| 3119 | */ |
| 3120 | int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue, |
| 3121 | const struct ath5k_txq_info *queue_info) |
| 3122 | { |
| 3123 | ATH5K_TRACE(ah->ah_sc); |
| 3124 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
| 3125 | |
| 3126 | if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) |
| 3127 | return -EIO; |
| 3128 | |
| 3129 | memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info)); |
| 3130 | |
| 3131 | /*XXX: Is this supported on 5210 ?*/ |
| 3132 | if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && |
| 3133 | ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || |
| 3134 | (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || |
| 3135 | queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) |
| 3136 | ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; |
| 3137 | |
| 3138 | return 0; |
| 3139 | } |
| 3140 | |
| 3141 | /* |
| 3142 | * Get properties for a specific transmit queue |
| 3143 | */ |
| 3144 | int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, |
| 3145 | struct ath5k_txq_info *queue_info) |
| 3146 | { |
| 3147 | ATH5K_TRACE(ah->ah_sc); |
| 3148 | memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info)); |
| 3149 | return 0; |
| 3150 | } |
| 3151 | |
| 3152 | /* |
| 3153 | * Set a transmit queue inactive |
| 3154 | */ |
| 3155 | void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue) |
| 3156 | { |
| 3157 | ATH5K_TRACE(ah->ah_sc); |
| 3158 | if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num)) |
| 3159 | return; |
| 3160 | |
| 3161 | /* This queue will be skipped in further operations */ |
| 3162 | ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; |
| 3163 | /*For SIMR setup*/ |
| 3164 | AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue); |
| 3165 | } |
| 3166 | |
| 3167 | /* |
| 3168 | * Set DFS params for a transmit queue |
| 3169 | */ |
| 3170 | int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) |
| 3171 | { |
| 3172 | u32 cw_min, cw_max, retry_lg, retry_sh; |
| 3173 | struct ath5k_txq_info *tq = &ah->ah_txq[queue]; |
| 3174 | |
| 3175 | ATH5K_TRACE(ah->ah_sc); |
| 3176 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
| 3177 | |
| 3178 | tq = &ah->ah_txq[queue]; |
| 3179 | |
| 3180 | if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) |
| 3181 | return 0; |
| 3182 | |
| 3183 | if (ah->ah_version == AR5K_AR5210) { |
| 3184 | /* Only handle data queues, others will be ignored */ |
| 3185 | if (tq->tqi_type != AR5K_TX_QUEUE_DATA) |
| 3186 | return 0; |
| 3187 | |
| 3188 | /* Set Slot time */ |
| 3189 | ath5k_hw_reg_write(ah, ah->ah_turbo == true ? |
| 3190 | AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, |
| 3191 | AR5K_SLOT_TIME); |
| 3192 | /* Set ACK_CTS timeout */ |
| 3193 | ath5k_hw_reg_write(ah, ah->ah_turbo == true ? |
| 3194 | AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : |
| 3195 | AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); |
| 3196 | /* Set Transmit Latency */ |
| 3197 | ath5k_hw_reg_write(ah, ah->ah_turbo == true ? |
| 3198 | AR5K_INIT_TRANSMIT_LATENCY_TURBO : |
| 3199 | AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); |
| 3200 | /* Set IFS0 */ |
| 3201 | if (ah->ah_turbo == true) |
| 3202 | ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + |
| 3203 | (ah->ah_aifs + tq->tqi_aifs) * |
| 3204 | AR5K_INIT_SLOT_TIME_TURBO) << |
| 3205 | AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, |
| 3206 | AR5K_IFS0); |
| 3207 | else |
| 3208 | ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS + |
| 3209 | (ah->ah_aifs + tq->tqi_aifs) * |
| 3210 | AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) | |
| 3211 | AR5K_INIT_SIFS, AR5K_IFS0); |
| 3212 | |
| 3213 | /* Set IFS1 */ |
| 3214 | ath5k_hw_reg_write(ah, ah->ah_turbo == true ? |
| 3215 | AR5K_INIT_PROTO_TIME_CNTRL_TURBO : |
| 3216 | AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); |
| 3217 | /* Set PHY register 0x9844 (??) */ |
| 3218 | ath5k_hw_reg_write(ah, ah->ah_turbo == true ? |
| 3219 | (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 : |
| 3220 | (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C, |
| 3221 | AR5K_PHY(17)); |
| 3222 | /* Set Frame Control Register */ |
| 3223 | ath5k_hw_reg_write(ah, ah->ah_turbo == true ? |
| 3224 | (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | |
| 3225 | AR5K_PHY_TURBO_SHORT | 0x2020) : |
| 3226 | (AR5K_PHY_FRAME_CTL_INI | 0x1020), |
| 3227 | AR5K_PHY_FRAME_CTL_5210); |
| 3228 | } |
| 3229 | |
| 3230 | /* |
| 3231 | * Calculate cwmin/max by channel mode |
| 3232 | */ |
| 3233 | cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN; |
| 3234 | cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX; |
| 3235 | ah->ah_aifs = AR5K_TUNE_AIFS; |
| 3236 | /*XR is only supported on 5212*/ |
| 3237 | if (IS_CHAN_XR(ah->ah_current_channel) && |
| 3238 | ah->ah_version == AR5K_AR5212) { |
| 3239 | cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR; |
| 3240 | cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR; |
| 3241 | ah->ah_aifs = AR5K_TUNE_AIFS_XR; |
| 3242 | /*B mode is not supported on 5210*/ |
| 3243 | } else if (IS_CHAN_B(ah->ah_current_channel) && |
| 3244 | ah->ah_version != AR5K_AR5210) { |
| 3245 | cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B; |
| 3246 | cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B; |
| 3247 | ah->ah_aifs = AR5K_TUNE_AIFS_11B; |
| 3248 | } |
| 3249 | |
| 3250 | cw_min = 1; |
| 3251 | while (cw_min < ah->ah_cw_min) |
| 3252 | cw_min = (cw_min << 1) | 1; |
| 3253 | |
| 3254 | cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) : |
| 3255 | ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); |
| 3256 | cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) : |
| 3257 | ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); |
| 3258 | |
| 3259 | /* |
| 3260 | * Calculate and set retry limits |
| 3261 | */ |
| 3262 | if (ah->ah_software_retry == true) { |
| 3263 | /* XXX Need to test this */ |
| 3264 | retry_lg = ah->ah_limit_tx_retries; |
| 3265 | retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? |
| 3266 | AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; |
| 3267 | } else { |
| 3268 | retry_lg = AR5K_INIT_LG_RETRY; |
| 3269 | retry_sh = AR5K_INIT_SH_RETRY; |
| 3270 | } |
| 3271 | |
| 3272 | /*No QCU/DCU [5210]*/ |
| 3273 | if (ah->ah_version == AR5K_AR5210) { |
| 3274 | ath5k_hw_reg_write(ah, |
| 3275 | (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) |
| 3276 | | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, |
| 3277 | AR5K_NODCU_RETRY_LMT_SLG_RETRY) |
| 3278 | | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, |
| 3279 | AR5K_NODCU_RETRY_LMT_SSH_RETRY) |
| 3280 | | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) |
| 3281 | | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), |
| 3282 | AR5K_NODCU_RETRY_LMT); |
| 3283 | } else { |
| 3284 | /*QCU/DCU [5211+]*/ |
| 3285 | ath5k_hw_reg_write(ah, |
| 3286 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, |
| 3287 | AR5K_DCU_RETRY_LMT_SLG_RETRY) | |
| 3288 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, |
| 3289 | AR5K_DCU_RETRY_LMT_SSH_RETRY) | |
| 3290 | AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | |
| 3291 | AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), |
| 3292 | AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); |
| 3293 | |
| 3294 | /*===Rest is also for QCU/DCU only [5211+]===*/ |
| 3295 | |
| 3296 | /* |
| 3297 | * Set initial content window (cw_min/cw_max) |
| 3298 | * and arbitrated interframe space (aifs)... |
| 3299 | */ |
| 3300 | ath5k_hw_reg_write(ah, |
| 3301 | AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | |
| 3302 | AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | |
| 3303 | AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs, |
| 3304 | AR5K_DCU_LCL_IFS_AIFS), |
| 3305 | AR5K_QUEUE_DFS_LOCAL_IFS(queue)); |
| 3306 | |
| 3307 | /* |
| 3308 | * Set misc registers |
| 3309 | */ |
| 3310 | ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY, |
| 3311 | AR5K_QUEUE_MISC(queue)); |
| 3312 | |
| 3313 | if (tq->tqi_cbr_period) { |
| 3314 | ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period, |
| 3315 | AR5K_QCU_CBRCFG_INTVAL) | |
| 3316 | AR5K_REG_SM(tq->tqi_cbr_overflow_limit, |
| 3317 | AR5K_QCU_CBRCFG_ORN_THRES), |
| 3318 | AR5K_QUEUE_CBRCFG(queue)); |
| 3319 | AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), |
| 3320 | AR5K_QCU_MISC_FRSHED_CBR); |
| 3321 | if (tq->tqi_cbr_overflow_limit) |
| 3322 | AR5K_REG_ENABLE_BITS(ah, |
| 3323 | AR5K_QUEUE_MISC(queue), |
| 3324 | AR5K_QCU_MISC_CBR_THRES_ENABLE); |
| 3325 | } |
| 3326 | |
| 3327 | if (tq->tqi_ready_time) |
| 3328 | ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time, |
| 3329 | AR5K_QCU_RDYTIMECFG_INTVAL) | |
| 3330 | AR5K_QCU_RDYTIMECFG_ENABLE, |
| 3331 | AR5K_QUEUE_RDYTIMECFG(queue)); |
| 3332 | |
| 3333 | if (tq->tqi_burst_time) { |
| 3334 | ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time, |
| 3335 | AR5K_DCU_CHAN_TIME_DUR) | |
| 3336 | AR5K_DCU_CHAN_TIME_ENABLE, |
| 3337 | AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); |
| 3338 | |
| 3339 | if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) |
| 3340 | AR5K_REG_ENABLE_BITS(ah, |
| 3341 | AR5K_QUEUE_MISC(queue), |
| 3342 | AR5K_QCU_MISC_TXE); |
| 3343 | } |
| 3344 | |
| 3345 | if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) |
| 3346 | ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, |
| 3347 | AR5K_QUEUE_DFS_MISC(queue)); |
| 3348 | |
| 3349 | if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) |
| 3350 | ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG, |
| 3351 | AR5K_QUEUE_DFS_MISC(queue)); |
| 3352 | |
| 3353 | /* |
| 3354 | * Set registers by queue type |
| 3355 | */ |
| 3356 | switch (tq->tqi_type) { |
| 3357 | case AR5K_TX_QUEUE_BEACON: |
| 3358 | AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), |
| 3359 | AR5K_QCU_MISC_FRSHED_DBA_GT | |
| 3360 | AR5K_QCU_MISC_CBREXP_BCN | |
| 3361 | AR5K_QCU_MISC_BCN_ENABLE); |
| 3362 | |
| 3363 | AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), |
| 3364 | (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << |
| 3365 | AR5K_DCU_MISC_ARBLOCK_CTL_S) | |
| 3366 | AR5K_DCU_MISC_POST_FR_BKOFF_DIS | |
| 3367 | AR5K_DCU_MISC_BCN_ENABLE); |
| 3368 | |
| 3369 | ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL - |
| 3370 | (AR5K_TUNE_SW_BEACON_RESP - |
| 3371 | AR5K_TUNE_DMA_BEACON_RESP) - |
| 3372 | AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | |
| 3373 | AR5K_QCU_RDYTIMECFG_ENABLE, |
| 3374 | AR5K_QUEUE_RDYTIMECFG(queue)); |
| 3375 | break; |
| 3376 | |
| 3377 | case AR5K_TX_QUEUE_CAB: |
| 3378 | AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), |
| 3379 | AR5K_QCU_MISC_FRSHED_DBA_GT | |
| 3380 | AR5K_QCU_MISC_CBREXP | |
| 3381 | AR5K_QCU_MISC_CBREXP_BCN); |
| 3382 | |
| 3383 | AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), |
| 3384 | (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << |
| 3385 | AR5K_DCU_MISC_ARBLOCK_CTL_S)); |
| 3386 | break; |
| 3387 | |
| 3388 | case AR5K_TX_QUEUE_UAPSD: |
| 3389 | AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), |
| 3390 | AR5K_QCU_MISC_CBREXP); |
| 3391 | break; |
| 3392 | |
| 3393 | case AR5K_TX_QUEUE_DATA: |
| 3394 | default: |
| 3395 | break; |
| 3396 | } |
| 3397 | |
| 3398 | /* |
| 3399 | * Enable interrupts for this tx queue |
| 3400 | * in the secondary interrupt mask registers |
| 3401 | */ |
| 3402 | if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE) |
| 3403 | AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue); |
| 3404 | |
| 3405 | if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE) |
| 3406 | AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue); |
| 3407 | |
| 3408 | if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE) |
| 3409 | AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue); |
| 3410 | |
| 3411 | if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE) |
| 3412 | AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue); |
| 3413 | |
| 3414 | if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE) |
| 3415 | AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue); |
| 3416 | |
| 3417 | |
| 3418 | /* Update secondary interrupt mask registers */ |
| 3419 | ah->ah_txq_imr_txok &= ah->ah_txq_status; |
| 3420 | ah->ah_txq_imr_txerr &= ah->ah_txq_status; |
| 3421 | ah->ah_txq_imr_txurn &= ah->ah_txq_status; |
| 3422 | ah->ah_txq_imr_txdesc &= ah->ah_txq_status; |
| 3423 | ah->ah_txq_imr_txeol &= ah->ah_txq_status; |
| 3424 | |
| 3425 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok, |
| 3426 | AR5K_SIMR0_QCU_TXOK) | |
| 3427 | AR5K_REG_SM(ah->ah_txq_imr_txdesc, |
| 3428 | AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); |
| 3429 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr, |
| 3430 | AR5K_SIMR1_QCU_TXERR) | |
| 3431 | AR5K_REG_SM(ah->ah_txq_imr_txeol, |
| 3432 | AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1); |
| 3433 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn, |
| 3434 | AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2); |
| 3435 | } |
| 3436 | |
| 3437 | return 0; |
| 3438 | } |
| 3439 | |
| 3440 | /* |
| 3441 | * Get number of pending frames |
| 3442 | * for a specific queue [5211+] |
| 3443 | */ |
| 3444 | u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) { |
| 3445 | ATH5K_TRACE(ah->ah_sc); |
| 3446 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
| 3447 | |
| 3448 | /* Return if queue is declared inactive */ |
| 3449 | if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) |
| 3450 | return false; |
| 3451 | |
| 3452 | /* XXX: How about AR5K_CFG_TXCNT ? */ |
| 3453 | if (ah->ah_version == AR5K_AR5210) |
| 3454 | return false; |
| 3455 | |
| 3456 | return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT; |
| 3457 | } |
| 3458 | |
| 3459 | /* |
| 3460 | * Set slot time |
| 3461 | */ |
| 3462 | int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time) |
| 3463 | { |
| 3464 | ATH5K_TRACE(ah->ah_sc); |
| 3465 | if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) |
| 3466 | return -EINVAL; |
| 3467 | |
| 3468 | if (ah->ah_version == AR5K_AR5210) |
| 3469 | ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time, |
| 3470 | ah->ah_turbo), AR5K_SLOT_TIME); |
| 3471 | else |
| 3472 | ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT); |
| 3473 | |
| 3474 | return 0; |
| 3475 | } |
| 3476 | |
| 3477 | /* |
| 3478 | * Get slot time |
| 3479 | */ |
| 3480 | unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah) |
| 3481 | { |
| 3482 | ATH5K_TRACE(ah->ah_sc); |
| 3483 | if (ah->ah_version == AR5K_AR5210) |
| 3484 | return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah, |
| 3485 | AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo); |
| 3486 | else |
| 3487 | return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff; |
| 3488 | } |
| 3489 | |
| 3490 | |
| 3491 | /******************************\ |
| 3492 | Hardware Descriptor Functions |
| 3493 | \******************************/ |
| 3494 | |
| 3495 | /* |
| 3496 | * TX Descriptor |
| 3497 | */ |
| 3498 | |
| 3499 | /* |
| 3500 | * Initialize the 2-word tx descriptor on 5210/5211 |
| 3501 | */ |
| 3502 | static int |
| 3503 | ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, |
| 3504 | unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, |
| 3505 | unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, |
| 3506 | unsigned int key_index, unsigned int antenna_mode, unsigned int flags, |
| 3507 | unsigned int rtscts_rate, unsigned int rtscts_duration) |
| 3508 | { |
| 3509 | u32 frame_type; |
| 3510 | struct ath5k_hw_2w_tx_desc *tx_desc; |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3511 | unsigned int frame_len; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3512 | |
| 3513 | tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0; |
| 3514 | |
| 3515 | /* |
| 3516 | * Validate input |
| 3517 | * - Zero retries don't make sense. |
| 3518 | * - A zero rate will put the HW into a mode where it continously sends |
| 3519 | * noise on the channel, so it is important to avoid this. |
| 3520 | */ |
| 3521 | if (unlikely(tx_tries0 == 0)) { |
| 3522 | ATH5K_ERR(ah->ah_sc, "zero retries\n"); |
| 3523 | WARN_ON(1); |
| 3524 | return -EINVAL; |
| 3525 | } |
| 3526 | if (unlikely(tx_rate0 == 0)) { |
| 3527 | ATH5K_ERR(ah->ah_sc, "zero rate\n"); |
| 3528 | WARN_ON(1); |
| 3529 | return -EINVAL; |
| 3530 | } |
| 3531 | |
| 3532 | /* Clear status descriptor */ |
| 3533 | memset(desc->ds_hw, 0, sizeof(struct ath5k_hw_tx_status)); |
| 3534 | |
| 3535 | /* Initialize control descriptor */ |
| 3536 | tx_desc->tx_control_0 = 0; |
| 3537 | tx_desc->tx_control_1 = 0; |
| 3538 | |
| 3539 | /* Setup control descriptor */ |
| 3540 | |
| 3541 | /* Verify and set frame length */ |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3542 | |
| 3543 | /* remove padding we might have added before */ |
| 3544 | frame_len = pkt_len - (hdr_len & 3) + FCS_LEN; |
| 3545 | |
| 3546 | if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3547 | return -EINVAL; |
| 3548 | |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3549 | tx_desc->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3550 | |
| 3551 | /* Verify and set buffer length */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3552 | |
| 3553 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ |
| 3554 | if(type == AR5K_PKT_TYPE_BEACON) |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3555 | pkt_len = roundup(pkt_len, 4); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3556 | |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3557 | if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3558 | return -EINVAL; |
| 3559 | |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3560 | tx_desc->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3561 | |
| 3562 | /* |
| 3563 | * Verify and set header length |
| 3564 | * XXX: I only found that on 5210 code, does it work on 5211 ? |
| 3565 | */ |
| 3566 | if (ah->ah_version == AR5K_AR5210) { |
| 3567 | if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN) |
| 3568 | return -EINVAL; |
| 3569 | tx_desc->tx_control_0 |= |
| 3570 | AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN); |
| 3571 | } |
| 3572 | |
| 3573 | /*Diferences between 5210-5211*/ |
| 3574 | if (ah->ah_version == AR5K_AR5210) { |
| 3575 | switch (type) { |
| 3576 | case AR5K_PKT_TYPE_BEACON: |
| 3577 | case AR5K_PKT_TYPE_PROBE_RESP: |
| 3578 | frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; |
| 3579 | case AR5K_PKT_TYPE_PIFS: |
| 3580 | frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; |
| 3581 | default: |
| 3582 | frame_type = type /*<< 2 ?*/; |
| 3583 | } |
| 3584 | |
| 3585 | tx_desc->tx_control_0 |= |
| 3586 | AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) | |
| 3587 | AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); |
| 3588 | } else { |
| 3589 | tx_desc->tx_control_0 |= |
| 3590 | AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | |
| 3591 | AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT); |
| 3592 | tx_desc->tx_control_1 |= |
| 3593 | AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE); |
| 3594 | } |
| 3595 | #define _TX_FLAGS(_c, _flag) \ |
| 3596 | if (flags & AR5K_TXDESC_##_flag) \ |
| 3597 | tx_desc->tx_control_##_c |= \ |
| 3598 | AR5K_2W_TX_DESC_CTL##_c##_##_flag |
| 3599 | |
| 3600 | _TX_FLAGS(0, CLRDMASK); |
| 3601 | _TX_FLAGS(0, VEOL); |
| 3602 | _TX_FLAGS(0, INTREQ); |
| 3603 | _TX_FLAGS(0, RTSENA); |
| 3604 | _TX_FLAGS(1, NOACK); |
| 3605 | |
| 3606 | #undef _TX_FLAGS |
| 3607 | |
| 3608 | /* |
| 3609 | * WEP crap |
| 3610 | */ |
| 3611 | if (key_index != AR5K_TXKEYIX_INVALID) { |
| 3612 | tx_desc->tx_control_0 |= |
| 3613 | AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; |
| 3614 | tx_desc->tx_control_1 |= |
| 3615 | AR5K_REG_SM(key_index, |
| 3616 | AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); |
| 3617 | } |
| 3618 | |
| 3619 | /* |
| 3620 | * RTS/CTS Duration [5210 ?] |
| 3621 | */ |
| 3622 | if ((ah->ah_version == AR5K_AR5210) && |
| 3623 | (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) |
| 3624 | tx_desc->tx_control_1 |= rtscts_duration & |
| 3625 | AR5K_2W_TX_DESC_CTL1_RTS_DURATION; |
| 3626 | |
| 3627 | return 0; |
| 3628 | } |
| 3629 | |
| 3630 | /* |
| 3631 | * Initialize the 4-word tx descriptor on 5212 |
| 3632 | */ |
| 3633 | static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah, |
| 3634 | struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len, |
| 3635 | enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, |
| 3636 | unsigned int tx_tries0, unsigned int key_index, |
| 3637 | unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate, |
| 3638 | unsigned int rtscts_duration) |
| 3639 | { |
| 3640 | struct ath5k_hw_4w_tx_desc *tx_desc; |
| 3641 | struct ath5k_hw_tx_status *tx_status; |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3642 | unsigned int frame_len; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3643 | |
| 3644 | ATH5K_TRACE(ah->ah_sc); |
| 3645 | tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; |
| 3646 | tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2]; |
| 3647 | |
| 3648 | /* |
| 3649 | * Validate input |
| 3650 | * - Zero retries don't make sense. |
| 3651 | * - A zero rate will put the HW into a mode where it continously sends |
| 3652 | * noise on the channel, so it is important to avoid this. |
| 3653 | */ |
| 3654 | if (unlikely(tx_tries0 == 0)) { |
| 3655 | ATH5K_ERR(ah->ah_sc, "zero retries\n"); |
| 3656 | WARN_ON(1); |
| 3657 | return -EINVAL; |
| 3658 | } |
| 3659 | if (unlikely(tx_rate0 == 0)) { |
| 3660 | ATH5K_ERR(ah->ah_sc, "zero rate\n"); |
| 3661 | WARN_ON(1); |
| 3662 | return -EINVAL; |
| 3663 | } |
| 3664 | |
| 3665 | /* Clear status descriptor */ |
| 3666 | memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status)); |
| 3667 | |
| 3668 | /* Initialize control descriptor */ |
| 3669 | tx_desc->tx_control_0 = 0; |
| 3670 | tx_desc->tx_control_1 = 0; |
| 3671 | tx_desc->tx_control_2 = 0; |
| 3672 | tx_desc->tx_control_3 = 0; |
| 3673 | |
| 3674 | /* Setup control descriptor */ |
| 3675 | |
| 3676 | /* Verify and set frame length */ |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3677 | |
| 3678 | /* remove padding we might have added before */ |
| 3679 | frame_len = pkt_len - (hdr_len & 3) + FCS_LEN; |
| 3680 | |
| 3681 | if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3682 | return -EINVAL; |
| 3683 | |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3684 | tx_desc->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3685 | |
| 3686 | /* Verify and set buffer length */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3687 | |
| 3688 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ |
| 3689 | if(type == AR5K_PKT_TYPE_BEACON) |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3690 | pkt_len = roundup(pkt_len, 4); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3691 | |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3692 | if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3693 | return -EINVAL; |
| 3694 | |
Bruno Randolf | 281c56d | 2008-02-05 18:44:55 +0900 | [diff] [blame] | 3695 | tx_desc->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3696 | |
| 3697 | tx_desc->tx_control_0 |= |
| 3698 | AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | |
| 3699 | AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); |
| 3700 | tx_desc->tx_control_1 |= AR5K_REG_SM(type, |
| 3701 | AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); |
| 3702 | tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, |
| 3703 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); |
| 3704 | tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; |
| 3705 | |
| 3706 | #define _TX_FLAGS(_c, _flag) \ |
| 3707 | if (flags & AR5K_TXDESC_##_flag) \ |
| 3708 | tx_desc->tx_control_##_c |= \ |
| 3709 | AR5K_4W_TX_DESC_CTL##_c##_##_flag |
| 3710 | |
| 3711 | _TX_FLAGS(0, CLRDMASK); |
| 3712 | _TX_FLAGS(0, VEOL); |
| 3713 | _TX_FLAGS(0, INTREQ); |
| 3714 | _TX_FLAGS(0, RTSENA); |
| 3715 | _TX_FLAGS(0, CTSENA); |
| 3716 | _TX_FLAGS(1, NOACK); |
| 3717 | |
| 3718 | #undef _TX_FLAGS |
| 3719 | |
| 3720 | /* |
| 3721 | * WEP crap |
| 3722 | */ |
| 3723 | if (key_index != AR5K_TXKEYIX_INVALID) { |
| 3724 | tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; |
| 3725 | tx_desc->tx_control_1 |= AR5K_REG_SM(key_index, |
| 3726 | AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX); |
| 3727 | } |
| 3728 | |
| 3729 | /* |
| 3730 | * RTS/CTS |
| 3731 | */ |
| 3732 | if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { |
| 3733 | if ((flags & AR5K_TXDESC_RTSENA) && |
| 3734 | (flags & AR5K_TXDESC_CTSENA)) |
| 3735 | return -EINVAL; |
| 3736 | tx_desc->tx_control_2 |= rtscts_duration & |
| 3737 | AR5K_4W_TX_DESC_CTL2_RTS_DURATION; |
| 3738 | tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate, |
| 3739 | AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); |
| 3740 | } |
| 3741 | |
| 3742 | return 0; |
| 3743 | } |
| 3744 | |
| 3745 | /* |
| 3746 | * Initialize a 4-word multirate tx descriptor on 5212 |
| 3747 | */ |
Jiri Slaby | b988763 | 2008-02-15 21:58:52 +0100 | [diff] [blame] | 3748 | static int |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3749 | ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, |
| 3750 | unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, |
| 3751 | unsigned int tx_rate3, u_int tx_tries3) |
| 3752 | { |
| 3753 | struct ath5k_hw_4w_tx_desc *tx_desc; |
| 3754 | |
| 3755 | /* |
| 3756 | * Rates can be 0 as long as the retry count is 0 too. |
| 3757 | * A zero rate and nonzero retry count will put the HW into a mode where |
| 3758 | * it continously sends noise on the channel, so it is important to |
| 3759 | * avoid this. |
| 3760 | */ |
| 3761 | if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) || |
| 3762 | (tx_rate2 == 0 && tx_tries2 != 0) || |
| 3763 | (tx_rate3 == 0 && tx_tries3 != 0))) { |
| 3764 | ATH5K_ERR(ah->ah_sc, "zero rate\n"); |
| 3765 | WARN_ON(1); |
| 3766 | return -EINVAL; |
| 3767 | } |
| 3768 | |
| 3769 | if (ah->ah_version == AR5K_AR5212) { |
| 3770 | tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; |
| 3771 | |
| 3772 | #define _XTX_TRIES(_n) \ |
| 3773 | if (tx_tries##_n) { \ |
| 3774 | tx_desc->tx_control_2 |= \ |
| 3775 | AR5K_REG_SM(tx_tries##_n, \ |
| 3776 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \ |
| 3777 | tx_desc->tx_control_3 |= \ |
| 3778 | AR5K_REG_SM(tx_rate##_n, \ |
| 3779 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \ |
| 3780 | } |
| 3781 | |
| 3782 | _XTX_TRIES(1); |
| 3783 | _XTX_TRIES(2); |
| 3784 | _XTX_TRIES(3); |
| 3785 | |
| 3786 | #undef _XTX_TRIES |
| 3787 | |
Jiri Slaby | b988763 | 2008-02-15 21:58:52 +0100 | [diff] [blame] | 3788 | return 1; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3789 | } |
| 3790 | |
Jiri Slaby | b988763 | 2008-02-15 21:58:52 +0100 | [diff] [blame] | 3791 | return 0; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 3792 | } |
| 3793 | |
| 3794 | /* |
| 3795 | * Proccess the tx status descriptor on 5210/5211 |
| 3796 | */ |
| 3797 | static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, |
| 3798 | struct ath5k_desc *desc) |
| 3799 | { |
| 3800 | struct ath5k_hw_tx_status *tx_status; |
| 3801 | struct ath5k_hw_2w_tx_desc *tx_desc; |
| 3802 | |
| 3803 | tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0; |
| 3804 | tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0]; |
| 3805 | |
| 3806 | /* No frame has been send or error */ |
| 3807 | if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) |
| 3808 | return -EINPROGRESS; |
| 3809 | |
| 3810 | /* |
| 3811 | * Get descriptor status |
| 3812 | */ |
| 3813 | desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, |
| 3814 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); |
| 3815 | desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, |
| 3816 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); |
| 3817 | desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, |
| 3818 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); |
| 3819 | /*TODO: desc->ds_us.tx.ts_virtcol + test*/ |
| 3820 | desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, |
| 3821 | AR5K_DESC_TX_STATUS1_SEQ_NUM); |
| 3822 | desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, |
| 3823 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); |
| 3824 | desc->ds_us.tx.ts_antenna = 1; |
| 3825 | desc->ds_us.tx.ts_status = 0; |
| 3826 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0, |
| 3827 | AR5K_2W_TX_DESC_CTL0_XMIT_RATE); |
| 3828 | |
| 3829 | if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ |
| 3830 | if (tx_status->tx_status_0 & |
| 3831 | AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) |
| 3832 | desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; |
| 3833 | |
| 3834 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) |
| 3835 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; |
| 3836 | |
| 3837 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) |
| 3838 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; |
| 3839 | } |
| 3840 | |
| 3841 | return 0; |
| 3842 | } |
| 3843 | |
| 3844 | /* |
| 3845 | * Proccess a tx descriptor on 5212 |
| 3846 | */ |
| 3847 | static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, |
| 3848 | struct ath5k_desc *desc) |
| 3849 | { |
| 3850 | struct ath5k_hw_tx_status *tx_status; |
| 3851 | struct ath5k_hw_4w_tx_desc *tx_desc; |
| 3852 | |
| 3853 | ATH5K_TRACE(ah->ah_sc); |
| 3854 | tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0; |
| 3855 | tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2]; |
| 3856 | |
| 3857 | /* No frame has been send or error */ |
| 3858 | if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) |
| 3859 | return -EINPROGRESS; |
| 3860 | |
| 3861 | /* |
| 3862 | * Get descriptor status |
| 3863 | */ |
| 3864 | desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, |
| 3865 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); |
| 3866 | desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, |
| 3867 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); |
| 3868 | desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0, |
| 3869 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); |
| 3870 | desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, |
| 3871 | AR5K_DESC_TX_STATUS1_SEQ_NUM); |
| 3872 | desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, |
| 3873 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); |
| 3874 | desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & |
| 3875 | AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; |
| 3876 | desc->ds_us.tx.ts_status = 0; |
| 3877 | |
| 3878 | switch (AR5K_REG_MS(tx_status->tx_status_1, |
| 3879 | AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) { |
| 3880 | case 0: |
| 3881 | desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & |
| 3882 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; |
| 3883 | break; |
| 3884 | case 1: |
| 3885 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, |
| 3886 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE1); |
| 3887 | desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, |
| 3888 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1); |
| 3889 | break; |
| 3890 | case 2: |
| 3891 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, |
| 3892 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE2); |
| 3893 | desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, |
| 3894 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2); |
| 3895 | break; |
| 3896 | case 3: |
| 3897 | desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3, |
| 3898 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE3); |
| 3899 | desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2, |
| 3900 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3); |
| 3901 | break; |
| 3902 | } |
| 3903 | |
| 3904 | if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){ |
| 3905 | if (tx_status->tx_status_0 & |
| 3906 | AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) |
| 3907 | desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY; |
| 3908 | |
| 3909 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) |
| 3910 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO; |
| 3911 | |
| 3912 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) |
| 3913 | desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT; |
| 3914 | } |
| 3915 | |
| 3916 | return 0; |
| 3917 | } |
| 3918 | |
| 3919 | /* |
| 3920 | * RX Descriptor |
| 3921 | */ |
| 3922 | |
| 3923 | /* |
| 3924 | * Initialize an rx descriptor |
| 3925 | */ |
| 3926 | int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, |
| 3927 | u32 size, unsigned int flags) |
| 3928 | { |
| 3929 | struct ath5k_rx_desc *rx_desc; |
| 3930 | |
| 3931 | ATH5K_TRACE(ah->ah_sc); |
| 3932 | rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0; |
| 3933 | |
| 3934 | /* |
| 3935 | *Clear ds_hw |
| 3936 | * If we don't clean the status descriptor, |
| 3937 | * while scanning we get too many results, |
| 3938 | * most of them virtual, after some secs |
| 3939 | * of scanning system hangs. M.F. |
| 3940 | */ |
| 3941 | memset(desc->ds_hw, 0, sizeof(desc->ds_hw)); |
| 3942 | |
| 3943 | /*Initialize rx descriptor*/ |
| 3944 | rx_desc->rx_control_0 = 0; |
| 3945 | rx_desc->rx_control_1 = 0; |
| 3946 | |
| 3947 | /* Setup descriptor */ |
| 3948 | rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; |
| 3949 | if (unlikely(rx_desc->rx_control_1 != size)) |
| 3950 | return -EINVAL; |
| 3951 | |
| 3952 | if (flags & AR5K_RXDESC_INTREQ) |
| 3953 | rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; |
| 3954 | |
| 3955 | return 0; |
| 3956 | } |
| 3957 | |
| 3958 | /* |
| 3959 | * Proccess the rx status descriptor on 5210/5211 |
| 3960 | */ |
| 3961 | static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *ah, |
| 3962 | struct ath5k_desc *desc) |
| 3963 | { |
| 3964 | struct ath5k_hw_old_rx_status *rx_status; |
| 3965 | |
| 3966 | rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0]; |
| 3967 | |
| 3968 | /* No frame received / not ready */ |
| 3969 | if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE) |
| 3970 | == 0)) |
| 3971 | return -EINPROGRESS; |
| 3972 | |
| 3973 | /* |
| 3974 | * Frame receive status |
| 3975 | */ |
| 3976 | desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & |
| 3977 | AR5K_OLD_RX_DESC_STATUS0_DATA_LEN; |
| 3978 | desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, |
| 3979 | AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL); |
| 3980 | desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, |
| 3981 | AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE); |
| 3982 | desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & |
| 3983 | AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA; |
| 3984 | desc->ds_us.rx.rs_more = rx_status->rx_status_0 & |
| 3985 | AR5K_OLD_RX_DESC_STATUS0_MORE; |
| 3986 | desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, |
| 3987 | AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); |
| 3988 | desc->ds_us.rx.rs_status = 0; |
| 3989 | |
| 3990 | /* |
| 3991 | * Key table status |
| 3992 | */ |
| 3993 | if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID) |
| 3994 | desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, |
| 3995 | AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX); |
| 3996 | else |
| 3997 | desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; |
| 3998 | |
| 3999 | /* |
| 4000 | * Receive/descriptor errors |
| 4001 | */ |
| 4002 | if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK) |
| 4003 | == 0) { |
| 4004 | if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR) |
| 4005 | desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; |
| 4006 | |
| 4007 | if (rx_status->rx_status_1 & |
| 4008 | AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN) |
| 4009 | desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO; |
| 4010 | |
| 4011 | if (rx_status->rx_status_1 & |
| 4012 | AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) { |
| 4013 | desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; |
| 4014 | desc->ds_us.rx.rs_phyerr = |
| 4015 | AR5K_REG_MS(rx_status->rx_status_1, |
| 4016 | AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR); |
| 4017 | } |
| 4018 | |
| 4019 | if (rx_status->rx_status_1 & |
| 4020 | AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) |
| 4021 | desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; |
| 4022 | } |
| 4023 | |
| 4024 | return 0; |
| 4025 | } |
| 4026 | |
| 4027 | /* |
| 4028 | * Proccess the rx status descriptor on 5212 |
| 4029 | */ |
| 4030 | static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *ah, |
| 4031 | struct ath5k_desc *desc) |
| 4032 | { |
| 4033 | struct ath5k_hw_new_rx_status *rx_status; |
| 4034 | struct ath5k_hw_rx_error *rx_err; |
| 4035 | |
| 4036 | ATH5K_TRACE(ah->ah_sc); |
| 4037 | rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0]; |
| 4038 | |
| 4039 | /* Overlay on error */ |
| 4040 | rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0]; |
| 4041 | |
| 4042 | /* No frame received / not ready */ |
| 4043 | if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE) |
| 4044 | == 0)) |
| 4045 | return -EINPROGRESS; |
| 4046 | |
| 4047 | /* |
| 4048 | * Frame receive status |
| 4049 | */ |
| 4050 | desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & |
| 4051 | AR5K_NEW_RX_DESC_STATUS0_DATA_LEN; |
| 4052 | desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, |
| 4053 | AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL); |
| 4054 | desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0, |
| 4055 | AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE); |
| 4056 | desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & |
| 4057 | AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA; |
| 4058 | desc->ds_us.rx.rs_more = rx_status->rx_status_0 & |
| 4059 | AR5K_NEW_RX_DESC_STATUS0_MORE; |
| 4060 | desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, |
| 4061 | AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); |
| 4062 | desc->ds_us.rx.rs_status = 0; |
| 4063 | |
| 4064 | /* |
| 4065 | * Key table status |
| 4066 | */ |
| 4067 | if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID) |
| 4068 | desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, |
| 4069 | AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX); |
| 4070 | else |
| 4071 | desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID; |
| 4072 | |
| 4073 | /* |
| 4074 | * Receive/descriptor errors |
| 4075 | */ |
| 4076 | if ((rx_status->rx_status_1 & |
| 4077 | AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) { |
| 4078 | if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR) |
| 4079 | desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC; |
| 4080 | |
| 4081 | if (rx_status->rx_status_1 & |
| 4082 | AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) { |
| 4083 | desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY; |
| 4084 | desc->ds_us.rx.rs_phyerr = |
| 4085 | AR5K_REG_MS(rx_err->rx_error_1, |
| 4086 | AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE); |
| 4087 | } |
| 4088 | |
| 4089 | if (rx_status->rx_status_1 & |
| 4090 | AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) |
| 4091 | desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT; |
| 4092 | |
| 4093 | if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR) |
| 4094 | desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC; |
| 4095 | } |
| 4096 | |
| 4097 | return 0; |
| 4098 | } |
| 4099 | |
| 4100 | |
| 4101 | /****************\ |
| 4102 | GPIO Functions |
| 4103 | \****************/ |
| 4104 | |
| 4105 | /* |
| 4106 | * Set led state |
| 4107 | */ |
| 4108 | void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state) |
| 4109 | { |
| 4110 | u32 led; |
| 4111 | /*5210 has different led mode handling*/ |
| 4112 | u32 led_5210; |
| 4113 | |
| 4114 | ATH5K_TRACE(ah->ah_sc); |
| 4115 | |
| 4116 | /*Reset led status*/ |
| 4117 | if (ah->ah_version != AR5K_AR5210) |
| 4118 | AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, |
| 4119 | AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED); |
| 4120 | else |
| 4121 | AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED); |
| 4122 | |
| 4123 | /* |
| 4124 | * Some blinking values, define at your wish |
| 4125 | */ |
| 4126 | switch (state) { |
| 4127 | case AR5K_LED_SCAN: |
| 4128 | case AR5K_LED_AUTH: |
| 4129 | led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND; |
| 4130 | led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL; |
| 4131 | break; |
| 4132 | |
| 4133 | case AR5K_LED_INIT: |
| 4134 | led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE; |
| 4135 | led_5210 = AR5K_PCICFG_LED_PEND; |
| 4136 | break; |
| 4137 | |
| 4138 | case AR5K_LED_ASSOC: |
| 4139 | case AR5K_LED_RUN: |
| 4140 | led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC; |
| 4141 | led_5210 = AR5K_PCICFG_LED_ASSOC; |
| 4142 | break; |
| 4143 | |
| 4144 | default: |
| 4145 | led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE; |
| 4146 | led_5210 = AR5K_PCICFG_LED_PEND; |
| 4147 | break; |
| 4148 | } |
| 4149 | |
| 4150 | /*Write new status to the register*/ |
| 4151 | if (ah->ah_version != AR5K_AR5210) |
| 4152 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led); |
| 4153 | else |
| 4154 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210); |
| 4155 | } |
| 4156 | |
| 4157 | /* |
| 4158 | * Set GPIO outputs |
| 4159 | */ |
| 4160 | int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio) |
| 4161 | { |
| 4162 | ATH5K_TRACE(ah->ah_sc); |
| 4163 | if (gpio > AR5K_NUM_GPIO) |
| 4164 | return -EINVAL; |
| 4165 | |
| 4166 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~ |
| 4167 | AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); |
| 4168 | |
| 4169 | return 0; |
| 4170 | } |
| 4171 | |
| 4172 | /* |
| 4173 | * Set GPIO inputs |
| 4174 | */ |
| 4175 | int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio) |
| 4176 | { |
| 4177 | ATH5K_TRACE(ah->ah_sc); |
| 4178 | if (gpio > AR5K_NUM_GPIO) |
| 4179 | return -EINVAL; |
| 4180 | |
| 4181 | ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~ |
| 4182 | AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); |
| 4183 | |
| 4184 | return 0; |
| 4185 | } |
| 4186 | |
| 4187 | /* |
| 4188 | * Get GPIO state |
| 4189 | */ |
| 4190 | u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio) |
| 4191 | { |
| 4192 | ATH5K_TRACE(ah->ah_sc); |
| 4193 | if (gpio > AR5K_NUM_GPIO) |
| 4194 | return 0xffffffff; |
| 4195 | |
| 4196 | /* GPIO input magic */ |
| 4197 | return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) & |
| 4198 | 0x1; |
| 4199 | } |
| 4200 | |
| 4201 | /* |
| 4202 | * Set GPIO state |
| 4203 | */ |
| 4204 | int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val) |
| 4205 | { |
| 4206 | u32 data; |
| 4207 | ATH5K_TRACE(ah->ah_sc); |
| 4208 | |
| 4209 | if (gpio > AR5K_NUM_GPIO) |
| 4210 | return -EINVAL; |
| 4211 | |
| 4212 | /* GPIO output magic */ |
| 4213 | data = ath5k_hw_reg_read(ah, AR5K_GPIODO); |
| 4214 | |
| 4215 | data &= ~(1 << gpio); |
| 4216 | data |= (val & 1) << gpio; |
| 4217 | |
| 4218 | ath5k_hw_reg_write(ah, data, AR5K_GPIODO); |
| 4219 | |
| 4220 | return 0; |
| 4221 | } |
| 4222 | |
| 4223 | /* |
| 4224 | * Initialize the GPIO interrupt (RFKill switch) |
| 4225 | */ |
| 4226 | void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, |
| 4227 | u32 interrupt_level) |
| 4228 | { |
| 4229 | u32 data; |
| 4230 | |
| 4231 | ATH5K_TRACE(ah->ah_sc); |
| 4232 | if (gpio > AR5K_NUM_GPIO) |
| 4233 | return; |
| 4234 | |
| 4235 | /* |
| 4236 | * Set the GPIO interrupt |
| 4237 | */ |
| 4238 | data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & |
| 4239 | ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | |
| 4240 | AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | |
| 4241 | (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); |
| 4242 | |
| 4243 | ath5k_hw_reg_write(ah, interrupt_level ? data : |
| 4244 | (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); |
| 4245 | |
| 4246 | ah->ah_imr |= AR5K_IMR_GPIO; |
| 4247 | |
| 4248 | /* Enable GPIO interrupts */ |
| 4249 | AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO); |
| 4250 | } |
| 4251 | |
| 4252 | |
| 4253 | /*********************************\ |
| 4254 | Regulatory Domain/Channels Setup |
| 4255 | \*********************************/ |
| 4256 | |
| 4257 | u16 ath5k_get_regdomain(struct ath5k_hw *ah) |
| 4258 | { |
| 4259 | u16 regdomain; |
| 4260 | enum ath5k_regdom ieee_regdomain; |
| 4261 | #ifdef COUNTRYCODE |
| 4262 | u16 code; |
| 4263 | #endif |
| 4264 | |
| 4265 | ath5k_eeprom_regulation_domain(ah, false, &ieee_regdomain); |
| 4266 | ah->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; |
| 4267 | |
| 4268 | #ifdef COUNTRYCODE |
| 4269 | /* |
| 4270 | * Get the regulation domain by country code. This will ignore |
| 4271 | * the settings found in the EEPROM. |
| 4272 | */ |
| 4273 | code = ieee80211_name2countrycode(COUNTRYCODE); |
| 4274 | ieee_regdomain = ieee80211_countrycode2regdomain(code); |
| 4275 | #endif |
| 4276 | |
| 4277 | regdomain = ath5k_regdom_from_ieee(ieee_regdomain); |
| 4278 | ah->ah_capabilities.cap_regdomain.reg_current = regdomain; |
| 4279 | |
| 4280 | return regdomain; |
| 4281 | } |
| 4282 | |
| 4283 | |
| 4284 | /****************\ |
| 4285 | Misc functions |
| 4286 | \****************/ |
| 4287 | |
| 4288 | int ath5k_hw_get_capability(struct ath5k_hw *ah, |
| 4289 | enum ath5k_capability_type cap_type, |
| 4290 | u32 capability, u32 *result) |
| 4291 | { |
| 4292 | ATH5K_TRACE(ah->ah_sc); |
| 4293 | |
| 4294 | switch (cap_type) { |
| 4295 | case AR5K_CAP_NUM_TXQUEUES: |
| 4296 | if (result) { |
| 4297 | if (ah->ah_version == AR5K_AR5210) |
| 4298 | *result = AR5K_NUM_TX_QUEUES_NOQCU; |
| 4299 | else |
| 4300 | *result = AR5K_NUM_TX_QUEUES; |
| 4301 | goto yes; |
| 4302 | } |
| 4303 | case AR5K_CAP_VEOL: |
| 4304 | goto yes; |
| 4305 | case AR5K_CAP_COMPRESSION: |
| 4306 | if (ah->ah_version == AR5K_AR5212) |
| 4307 | goto yes; |
| 4308 | else |
| 4309 | goto no; |
| 4310 | case AR5K_CAP_BURST: |
| 4311 | goto yes; |
| 4312 | case AR5K_CAP_TPC: |
| 4313 | goto yes; |
| 4314 | case AR5K_CAP_BSSIDMASK: |
| 4315 | if (ah->ah_version == AR5K_AR5212) |
| 4316 | goto yes; |
| 4317 | else |
| 4318 | goto no; |
| 4319 | case AR5K_CAP_XR: |
| 4320 | if (ah->ah_version == AR5K_AR5212) |
| 4321 | goto yes; |
| 4322 | else |
| 4323 | goto no; |
| 4324 | default: |
| 4325 | goto no; |
| 4326 | } |
| 4327 | |
| 4328 | no: |
| 4329 | return -EINVAL; |
| 4330 | yes: |
| 4331 | return 0; |
| 4332 | } |
| 4333 | |
| 4334 | static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, |
| 4335 | u16 assoc_id) |
| 4336 | { |
| 4337 | ATH5K_TRACE(ah->ah_sc); |
| 4338 | |
| 4339 | if (ah->ah_version == AR5K_AR5210) { |
| 4340 | AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, |
| 4341 | AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); |
| 4342 | return 0; |
| 4343 | } |
| 4344 | |
| 4345 | return -EIO; |
| 4346 | } |
| 4347 | |
| 4348 | static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah) |
| 4349 | { |
| 4350 | ATH5K_TRACE(ah->ah_sc); |
| 4351 | |
| 4352 | if (ah->ah_version == AR5K_AR5210) { |
| 4353 | AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, |
| 4354 | AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA); |
| 4355 | return 0; |
| 4356 | } |
| 4357 | |
| 4358 | return -EIO; |
| 4359 | } |