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gerrit-public.fairphone.software / kernel / msm-4.9 / d5b1521a94659167e77616368fe6e7c9b3aa1733 / . / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
blob: 0ab4cb6dc09b47f3367484e257c77c35c0beb996 [file] [log] [blame]
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame^]1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/kernel.h>
22#include <linux/sh_pfc.h>
23#include <mach/r8a7740.h>
24#include <mach/irqs.h>
25
26#define CPU_ALL_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
28 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
29 PORT_10(fn, pfx##20, sfx), \
30 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
31
32enum {
33 PINMUX_RESERVED = 0,
34
35 /* PORT0_DATA -> PORT211_DATA */
36 PINMUX_DATA_BEGIN,
37 PORT_ALL(DATA),
38 PINMUX_DATA_END,
39
40 /* PORT0_IN -> PORT211_IN */
41 PINMUX_INPUT_BEGIN,
42 PORT_ALL(IN),
43 PINMUX_INPUT_END,
44
45 /* PORT0_IN_PU -> PORT211_IN_PU */
46 PINMUX_INPUT_PULLUP_BEGIN,
47 PORT_ALL(IN_PU),
48 PINMUX_INPUT_PULLUP_END,
49
50 /* PORT0_IN_PD -> PORT211_IN_PD */
51 PINMUX_INPUT_PULLDOWN_BEGIN,
52 PORT_ALL(IN_PD),
53 PINMUX_INPUT_PULLDOWN_END,
54
55 /* PORT0_OUT -> PORT211_OUT */
56 PINMUX_OUTPUT_BEGIN,
57 PORT_ALL(OUT),
58 PINMUX_OUTPUT_END,
59
60 PINMUX_FUNCTION_BEGIN,
61 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
62 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
63 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
64 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
65 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
66 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
67 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
68 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
69 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
70 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
71
72 MSEL1CR_31_0, MSEL1CR_31_1,
73 MSEL1CR_30_0, MSEL1CR_30_1,
74 MSEL1CR_29_0, MSEL1CR_29_1,
75 MSEL1CR_28_0, MSEL1CR_28_1,
76 MSEL1CR_27_0, MSEL1CR_27_1,
77 MSEL1CR_26_0, MSEL1CR_26_1,
78 MSEL1CR_16_0, MSEL1CR_16_1,
79 MSEL1CR_15_0, MSEL1CR_15_1,
80 MSEL1CR_14_0, MSEL1CR_14_1,
81 MSEL1CR_13_0, MSEL1CR_13_1,
82 MSEL1CR_12_0, MSEL1CR_12_1,
83 MSEL1CR_9_0, MSEL1CR_9_1,
84 MSEL1CR_7_0, MSEL1CR_7_1,
85 MSEL1CR_6_0, MSEL1CR_6_1,
86 MSEL1CR_5_0, MSEL1CR_5_1,
87 MSEL1CR_4_0, MSEL1CR_4_1,
88 MSEL1CR_3_0, MSEL1CR_3_1,
89 MSEL1CR_2_0, MSEL1CR_2_1,
90 MSEL1CR_0_0, MSEL1CR_0_1,
91
92 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
93 MSEL3CR_6_0, MSEL3CR_6_1,
94
95 MSEL4CR_19_0, MSEL4CR_19_1,
96 MSEL4CR_18_0, MSEL4CR_18_1,
97 MSEL4CR_15_0, MSEL4CR_15_1,
98 MSEL4CR_10_0, MSEL4CR_10_1,
99 MSEL4CR_6_0, MSEL4CR_6_1,
100 MSEL4CR_4_0, MSEL4CR_4_1,
101 MSEL4CR_1_0, MSEL4CR_1_1,
102
103 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
104 MSEL5CR_30_0, MSEL5CR_30_1,
105 MSEL5CR_29_0, MSEL5CR_29_1,
106 MSEL5CR_27_0, MSEL5CR_27_1,
107 MSEL5CR_25_0, MSEL5CR_25_1,
108 MSEL5CR_23_0, MSEL5CR_23_1,
109 MSEL5CR_21_0, MSEL5CR_21_1,
110 MSEL5CR_19_0, MSEL5CR_19_1,
111 MSEL5CR_17_0, MSEL5CR_17_1,
112 MSEL5CR_15_0, MSEL5CR_15_1,
113 MSEL5CR_14_0, MSEL5CR_14_1,
114 MSEL5CR_13_0, MSEL5CR_13_1,
115 MSEL5CR_12_0, MSEL5CR_12_1,
116 MSEL5CR_11_0, MSEL5CR_11_1,
117 MSEL5CR_10_0, MSEL5CR_10_1,
118 MSEL5CR_8_0, MSEL5CR_8_1,
119 MSEL5CR_7_0, MSEL5CR_7_1,
120 MSEL5CR_6_0, MSEL5CR_6_1,
121 MSEL5CR_5_0, MSEL5CR_5_1,
122 MSEL5CR_4_0, MSEL5CR_4_1,
123 MSEL5CR_3_0, MSEL5CR_3_1,
124 MSEL5CR_2_0, MSEL5CR_2_1,
125 MSEL5CR_0_0, MSEL5CR_0_1,
126 PINMUX_FUNCTION_END,
127
128 PINMUX_MARK_BEGIN,
129
130 /* IRQ */
131 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
132 IRQ1_MARK,
133 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
134 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
135 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
136 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
137 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
138 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
139 IRQ8_MARK,
140 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
141 IRQ10_MARK,
142 IRQ11_MARK,
143 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
144 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
145 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
146 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
147 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
148 IRQ17_MARK,
149 IRQ18_MARK,
150 IRQ19_MARK,
151 IRQ20_MARK,
152 IRQ21_MARK,
153 IRQ22_MARK,
154 IRQ23_MARK,
155 IRQ24_MARK,
156 IRQ25_MARK,
157 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
158 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
159 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
160 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
161 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
162 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
163
164 /* Function */
165
166 /* DBGT */
167 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
168 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
169 DBGMD21_MARK,
170
171 /* FSI-A */
172 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
173 FSIAISLD_PORT5_MARK,
174 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
175 FSIASPDIF_PORT18_MARK,
176 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
177 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
178 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
179
180 /* FSI-B */
181 FSIBCK_MARK,
182
183 /* FMSI */
184 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
185 FMSISLD_PORT6_MARK,
186 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
187 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
188 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
189
190 /* SCIFA0 */
191 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
192 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
193
194 /* SCIFA1 */
195 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
196 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
197
198 /* SCIFA2 */
199 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
200 SCIFA2_SCK_PORT199_MARK,
201 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
202 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
203
204 /* SCIFA3 */
205 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
206 SCIFA3_SCK_PORT116_MARK,
207 SCIFA3_CTS_PORT117_MARK,
208 SCIFA3_RXD_PORT174_MARK,
209 SCIFA3_TXD_PORT175_MARK,
210
211 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
212 SCIFA3_SCK_PORT158_MARK,
213 SCIFA3_CTS_PORT162_MARK,
214 SCIFA3_RXD_PORT159_MARK,
215 SCIFA3_TXD_PORT160_MARK,
216
217 /* SCIFA4 */
218 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
219 SCIFA4_TXD_PORT13_MARK,
220
221 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
222 SCIFA4_TXD_PORT203_MARK,
223
224 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
225 SCIFA4_TXD_PORT93_MARK,
226
227 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
228 SCIFA4_SCK_PORT205_MARK,
229
230 /* SCIFA5 */
231 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
232 SCIFA5_RXD_PORT10_MARK,
233
234 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
235 SCIFA5_TXD_PORT208_MARK,
236
237 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
238 SCIFA5_RXD_PORT92_MARK,
239
240 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
241 SCIFA5_SCK_PORT206_MARK,
242
243 /* SCIFA6 */
244 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
245
246 /* SCIFA7 */
247 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
248
249 /* SCIFAB */
250 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
251 SCIFB_RXD_PORT191_MARK,
252 SCIFB_TXD_PORT192_MARK,
253 SCIFB_RTS_PORT186_MARK,
254 SCIFB_CTS_PORT187_MARK,
255
256 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
257 SCIFB_RXD_PORT3_MARK,
258 SCIFB_TXD_PORT4_MARK,
259 SCIFB_RTS_PORT172_MARK,
260 SCIFB_CTS_PORT173_MARK,
261
262 /* LCD0 */
263 LCDC0_SELECT_MARK,
264
265 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
266 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
267 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
268 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
269 LCD0_D16_MARK, LCD0_D17_MARK,
270 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
271 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
272 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
273 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
274 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
275
276 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
277 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
278 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
279 LCD0_LCLK_PORT165_MARK,
280
281 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
282 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
283 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
284 LCD0_LCLK_PORT102_MARK,
285
286 /* LCD1 */
287 LCDC1_SELECT_MARK,
288
289 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
290 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
291 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
292 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
293 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
294 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
295 LCD1_DON_MARK, LCD1_VCPWC_MARK,
296 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
297
298 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
299 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
300 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
301 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
302
303 /* RSPI */
304 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
305 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
306 RSPI_MISO_A_MARK,
307
308 /* VIO CKO */
309 VIO_CKO1_MARK, /* needs fixup */
310 VIO_CKO2_MARK,
311 VIO_CKO_1_MARK,
312 VIO_CKO_MARK,
313
314 /* VIO0 */
315 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
316 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
317 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
318 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
319 VIO0_FIELD_MARK,
320
321 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
322 VIO0_D14_PORT25_MARK,
323 VIO0_D15_PORT24_MARK,
324
325 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
326 VIO0_D14_PORT95_MARK,
327 VIO0_D15_PORT96_MARK,
328
329 /* VIO1 */
330 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
331 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
332 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
333
334 /* TPU0 */
335 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
336 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
337 TPU0TO2_PORT202_MARK,
338
339 /* SSP1 0 */
340 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
341 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
342 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
343
344 /* SSP1 1 */
345 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
346 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
347 STP1_IPSYNC_MARK,
348
349 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
350 STP1_IPEN_PORT187_MARK,
351
352 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
353 STP1_IPEN_PORT193_MARK,
354
355 /* SIM */
356 SIM_RST_MARK, SIM_CLK_MARK,
357 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
358 SIM_D_PORT199_MARK,
359
360 /* SDHI0 */
361 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
362 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
363
364 /* SDHI1 */
365 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
366 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
367
368 /* SDHI2 */
369 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
370 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
371
372 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
373 SDHI2_WP_PORT25_MARK,
374
375 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
376 SDHI2_CD_PORT202_MARK,
377
378 /* MSIOF2 */
379 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
380 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
381 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
382 MSIOF2_RSCK_MARK,
383
384 /* KEYSC */
385 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
386 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
387 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
388
389 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
390 KEYIN1_PORT44_MARK,
391 KEYIN2_PORT45_MARK,
392 KEYIN3_PORT46_MARK,
393
394 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
395 KEYIN1_PORT57_MARK,
396 KEYIN2_PORT56_MARK,
397 KEYIN3_PORT55_MARK,
398
399 /* VOU */
400 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
401 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
402 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
403 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
404 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
405
406 /* MEMC */
407 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
408 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
409 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
410 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
411 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
412
413 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
414 MEMC_ADV_MARK,
415 MEMC_WAIT_MARK,
416 MEMC_BUSCLK_MARK,
417
418 MEMC_A1_MARK, /* MSEL4CR_6_1 */
419 MEMC_DREQ0_MARK,
420 MEMC_DREQ1_MARK,
421 MEMC_A0_MARK,
422
423 /* MMC */
424 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
425 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
426 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
427 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
428
429 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
430 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
431 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
432 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
433
434 /* MSIOF0 */
435 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
436 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
437 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
438 MSIOF0_TSYNC_MARK,
439
440 /* MSIOF1 */
441 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
442 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
443
444 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
445 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
446 MSIOF1_TSYNC_PORT120_MARK,
447 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
448
449 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
450 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
451 MSIOF1_RXD_PORT75_MARK,
452 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
453
454 /* GPIO */
455 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
456
457 /* USB0 */
458 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
459
460 /* USB1 */
461 USB1_OCI_MARK, USB1_PPON_MARK,
462
463 /* BBIF1 */
464 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
465 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
466 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
467
468 /* BBIF2 */
469 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
470 BBIF2_RXD2_PORT60_MARK,
471 BBIF2_TSYNC2_PORT6_MARK,
472 BBIF2_TSCK2_PORT59_MARK,
473
474 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
475 BBIF2_TXD2_PORT183_MARK,
476 BBIF2_TSCK2_PORT89_MARK,
477 BBIF2_TSYNC2_PORT184_MARK,
478
479 /* BSC / FLCTL / PCMCIA */
480 CS0_MARK, CS2_MARK, CS4_MARK,
481 CS5B_MARK, CS6A_MARK,
482 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
483 CS5A_PORT19_MARK,
484 IOIS16_MARK, /* ? */
485
486 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
487 A4_FOE_MARK, /* share with FLCTL */
488 A5_FCDE_MARK, /* share with FLCTL */
489 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
490 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
491 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
492 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
493 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
494 A26_MARK,
495
496 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
497 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
498 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
499 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
500 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
501 D15_NAF15_MARK, /* share with FLCTL */
502 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
503 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
504 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
505 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
506
507 WE0_FWE_MARK, /* share with FLCTL */
508 WE1_MARK,
509 WE2_ICIORD_MARK, /* share with PCMCIA */
510 WE3_ICIOWR_MARK, /* share with PCMCIA */
511 CKO_MARK, BS_MARK, RDWR_MARK,
512 RD_FSC_MARK, /* share with FLCTL */
513 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
514 WAIT_PORT90_MARK,
515
516 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
517
518 /* IRDA */
519 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
520
521 /* ATAPI */
522 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
523 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
524 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
525 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
526 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
527 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
528 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
529 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
530
531 /* RMII */
532 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
533 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
534 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
535 RMII_REF50CK_MARK, /* for RMII */
536 RMII_REF125CK_MARK, /* for GMII */
537
538 /* GEther */
539 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
540 ET_ETXD2_MARK, ET_ETXD3_MARK,
541 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
542 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
543 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
544 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
545 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
546 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
547 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
548 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
549
550 /* DMA0 */
551 DREQ0_MARK, DACK0_MARK,
552
553 /* DMA1 */
554 DREQ1_MARK, DACK1_MARK,
555
556 /* SYSC */
557 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
558
559 /* IRREM */
560 IROUT_MARK,
561
562 /* SDENC */
563 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
564
565 /* HDMI */
566 HDMI_HPD_MARK, HDMI_CEC_MARK,
567
568 /* DEBUG */
569 EDEBGREQ_PULLUP_MARK, /* for JTAG */
570 EDEBGREQ_PULLDOWN_MARK,
571
572 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
573 TRACEAUD_FROM_LCDC0_MARK,
574 TRACEAUD_FROM_MEMC_MARK,
575
576 PINMUX_MARK_END,
577};
578
579static pinmux_enum_t pinmux_data[] = {
580 /* specify valid pin states for each pin in GPIO mode */
581
582 /* I/O and Pull U/D */
583 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
584 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
585 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
586 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
587 PORT_DATA_IO(8), PORT_DATA_IO(9),
588
589 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
590 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
591 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
592 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
593 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
594
595 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
596 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
597 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
598 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
599 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
600
601 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
602 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
603 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
604 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
605 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
606
607 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
608 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
609 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
610 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
611 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
612
613 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
614 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
615 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
616 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
617 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
618
619 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
620 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
621 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
622 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
623 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
624
625 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
626 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
627 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
628 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
629 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
630
631 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
632 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
633 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
634 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
635 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
636
637 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
638 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
639 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
640 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
641 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
642
643 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
644 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
645 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
646 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
647 PORT_DATA_IO(108), PORT_DATA_IO(109),
648
649 PORT_DATA_IO(110), PORT_DATA_IO(111),
650 PORT_DATA_IO(112), PORT_DATA_IO(113),
651 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
652 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
653 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
654
655 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
656 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
657 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
658 PORT_DATA_IO(126), PORT_DATA_IO(127),
659 PORT_DATA_IO(128), PORT_DATA_IO(129),
660
661 PORT_DATA_IO(130), PORT_DATA_IO(131),
662 PORT_DATA_IO(132), PORT_DATA_IO(133),
663 PORT_DATA_IO(134), PORT_DATA_IO(135),
664 PORT_DATA_IO(136), PORT_DATA_IO(137),
665 PORT_DATA_IO(138), PORT_DATA_IO(139),
666
667 PORT_DATA_IO(140), PORT_DATA_IO(141),
668 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
669 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
670 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
671 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
672
673 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
674 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
675 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
676 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
677 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
678
679 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
680 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
681 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
682 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
683 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
684
685 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
686 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
687 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
688 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
689 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
690
691 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
692 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
693 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
694 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
695 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
696
697 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
698 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
699 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
700 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
701 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
702
703 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
704 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
705 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
706 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
707 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
708
709 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
710
711 /* Port0 */
712 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
713 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
714 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
715 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
716 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
717 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
718 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
719
720 /* Port1 */
721 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
722 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
723 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
724 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
725 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
726 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
727 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
728
729 /* Port2 */
730 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
731 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
732 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
733 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
734 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
735
736 /* Port3 */
737 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
738 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
739 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
740 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
741
742 /* Port4 */
743 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
744 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
745 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
746 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
747
748 /* Port5 */
749 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
750 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
751 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
752 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
753 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
754
755 /* Port6 */
756 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
757 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
758 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
759 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
760 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
761
762 /* Port7 */
763 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
764
765 /* Port8 */
766 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
767
768 /* Port9 */
769 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
770 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
771
772 /* Port10 */
773 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
774 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
775 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
776
777 /* Port11 */
778 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
779 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
780 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
781
782 /* Port12 */
783 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
784 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
785 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
786 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
787 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
788
789 /* Port13 */
790 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
791 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
792 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
793 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
794
795 /* Port14 */
796 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
797 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
798 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
799 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
800 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
801
802 /* Port15 */
803 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
804 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
805 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
806 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
807 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
808
809 /* Port16 */
810 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
811 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
812
813 /* Port17 */
814 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
815 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
816
817 /* Port18 */
818 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
819 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
820
821 /* Port19 */
822 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
823 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
824 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
825
826 /* Port20 */
827 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
828 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
829 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
830
831 /* Port21 */
832 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
833 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
834 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
835 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
836 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
837 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
838
839 /* Port22 */
840 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
841 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
842 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
843
844 /* Port23 */
845 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
846 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
847 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
848 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
849 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
850 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
851
852 /* Port24 */
853 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
854 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
855 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
856 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
857
858 /* Port25 */
859 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
860 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
861 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
862 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
863
864 /* Port26 */
865 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
866 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
867 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
868
869 /* Port27 - Port39 Function */
870 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
871 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
872 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
873 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
874 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
875 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
876 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
877 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
878 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
879 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
880 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
881 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
882 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
883
884 /* Port38 IRQ */
885 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
886
887 /* Port40 */
888 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
889 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
890 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
891
892 /* Port41 */
893 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
894 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
895 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
896
897 /* Port42 */
898 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
899 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
900 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
901
902 /* Port43 */
903 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
904 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
905 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
906 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
907
908 /* Port44 */
909 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
910 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
911 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
912 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
913
914 /* Port45 */
915 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
916 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
917 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
918 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
919
920 /* Port46 */
921 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
922 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
923 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
924
925 /* Port47 */
926 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
927 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
928 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
929
930 /* Port48 */
931 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
932 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
933 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
934
935 /* Port49 */
936 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
937 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
938 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
939 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
940
941 /* Port50 */
942 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
943 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
944 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
945 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
946
947 /* Port51 */
948 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
949 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
950 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
951
952 /* Port52 */
953 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
954 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
955 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
956
957 /* Port53 */
958 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
959 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
960 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
961
962 /* Port54 */
963 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
964 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
965 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
966
967 /* Port55 */
968 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
969 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
970 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
971 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
972
973 /* Port56 */
974 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
975 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
976 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
977 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
978 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
979
980 /* Port57 */
981 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
982 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
983 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
984 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
985 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
986
987 /* Port58 */
988 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
989 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
990 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
991 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
992 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
993
994 /* Port59 */
995 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
996 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
997 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
998
999 /* Port60 */
1000 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
1001 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
1002 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
1003
1004 /* Port61 */
1005 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
1006 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1007
1008 /* Port62 */
1009 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1010 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1011 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1012 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1013
1014 /* Port63 */
1015 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1016 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1017 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1018
1019 /* Port64 */
1020 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1021 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1022 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1023 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1024
1025 /* Port65 */
1026 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1027 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1028 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1029
1030 /* Port66 */
1031 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1032 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1033 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1034 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1035
1036 /* Port67 - Port73 Function1 */
1037 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1038 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1039 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1040 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1041 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1042 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1043 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1044
1045 /* Port67 - Port73 Function2 */
1046 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1047 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1048 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1049 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1050 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1051 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1052 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1053
1054 /* Port67 - Port73 Function4 */
1055 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1056 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1057 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1058 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1059 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1060 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1061 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1062
1063 /* Port67 - Port73 Function6 */
1064 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1065 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1066 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1067 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1068 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1069 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1070 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1071
1072 /* Port67 - Port71 IRQ */
1073 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1074 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1075 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1076 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1077 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1078
1079 /* Port74 */
1080 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1081 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1082 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1083 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1084 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1085
1086 /* Port75 */
1087 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1088 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1089 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1090 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1091 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1092
1093 /* Port76 - Port80 Function */
1094 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1095 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1096 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1097 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1098 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1099
1100 /* Port81 */
1101 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1102 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1103
1104 /* Port82 - Port88 Function */
1105 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1106 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1107 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1108 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1109 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1110 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1111 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1112
1113 /* Port89 */
1114 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1115 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1116 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1117
1118 /* Port90 */
1119 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1120 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1121 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1122 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1123
1124 /* Port91 */
1125 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1126 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1127 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1128 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1129
1130 /* Port92 */
1131 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1132 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1133 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1134 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1135 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1136
1137 /* Port93 */
1138 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1139 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1140 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1141 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1142 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1143
1144 /* Port94 */
1145 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1146 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1147 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1148 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1149 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1150
1151 /* Port95 */
1152 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1153 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1154
1155 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1156 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1157 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1158 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1159
1160 /* Port96 */
1161 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1162 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1163
1164 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1165 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1166 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1167 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1168
1169 /* Port97 */
1170 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1171 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1172 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1173 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1174 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1175
1176 /* Port98 */
1177 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1178 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1179 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1180 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1181
1182 /* Port99 */
1183 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1184 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1185 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1186 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1187 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1188
1189 /* Port100 */
1190 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1191 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1192 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1193 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1194
1195 /* Port101 */
1196 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1197
1198 /* Port102 */
1199 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1200 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1201
1202 /* Port103 */
1203 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1204 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1205 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1206
1207 /* Port104 */
1208 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1209 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1210 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1211
1212 /* Port105 */
1213 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1214 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1215
1216 /* Port106 */
1217 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1218 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1219
1220 /* Port107 - Port115 Function */
1221 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1222 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1223 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1224 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1225 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1226 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1227 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1228 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1229 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1230
1231 /* Port116 */
1232 PINMUX_DATA(A25_MARK, PORT116_FN1),
1233 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1234 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1235 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1236 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1237
1238 /* Port117 */
1239 PINMUX_DATA(A24_MARK, PORT117_FN1),
1240 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1241 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1242 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1243 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1244
1245 /* Port118 */
1246 PINMUX_DATA(A23_MARK, PORT118_FN1),
1247 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1248 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1249 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1250 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1251
1252 /* Port119 */
1253 PINMUX_DATA(A22_MARK, PORT119_FN1),
1254 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1255 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1256 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1257 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1258
1259 /* Port120 */
1260 PINMUX_DATA(A21_MARK, PORT120_FN1),
1261 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1262 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1263 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1264
1265 /* Port121 */
1266 PINMUX_DATA(A20_MARK, PORT121_FN1),
1267 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1268 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1269 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1270
1271 /* Port122 */
1272 PINMUX_DATA(A19_MARK, PORT122_FN1),
1273 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1274
1275 /* Port123 */
1276 PINMUX_DATA(A18_MARK, PORT123_FN1),
1277 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1278
1279 /* Port124 */
1280 PINMUX_DATA(A17_MARK, PORT124_FN1),
1281 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1282
1283 /* Port125 - Port141 Function */
1284 PINMUX_DATA(A16_MARK, PORT125_FN1),
1285 PINMUX_DATA(A15_MARK, PORT126_FN1),
1286 PINMUX_DATA(A14_MARK, PORT127_FN1),
1287 PINMUX_DATA(A13_MARK, PORT128_FN1),
1288 PINMUX_DATA(A12_MARK, PORT129_FN1),
1289 PINMUX_DATA(A11_MARK, PORT130_FN1),
1290 PINMUX_DATA(A10_MARK, PORT131_FN1),
1291 PINMUX_DATA(A9_MARK, PORT132_FN1),
1292 PINMUX_DATA(A8_MARK, PORT133_FN1),
1293 PINMUX_DATA(A7_MARK, PORT134_FN1),
1294 PINMUX_DATA(A6_MARK, PORT135_FN1),
1295 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1296 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1297 PINMUX_DATA(A3_MARK, PORT138_FN1),
1298 PINMUX_DATA(A2_MARK, PORT139_FN1),
1299 PINMUX_DATA(A1_MARK, PORT140_FN1),
1300 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1301
1302 /* Port142 - Port157 Function1 */
1303 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1304 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1305 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1306 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1307 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1308 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1309 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1310 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1311 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1312 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1313 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1314 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1315 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1316 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1317 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1318 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1319
1320 /* Port142 - Port149 Function3 */
1321 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1322 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1323 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1324 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1325 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1326 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1327 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1328 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1329
1330 /* Port158 */
1331 PINMUX_DATA(D31_MARK, PORT158_FN1),
1332 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1333 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1334 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1335 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1336 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1337
1338 /* Port159 */
1339 PINMUX_DATA(D30_MARK, PORT159_FN1),
1340 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1341 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1342 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1343 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1344
1345 /* Port160 */
1346 PINMUX_DATA(D29_MARK, PORT160_FN1),
1347 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1348 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1349 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1350 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1351
1352 /* Port161 */
1353 PINMUX_DATA(D28_MARK, PORT161_FN1),
1354 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1355 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1356 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1357 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1358 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1359
1360 /* Port162 */
1361 PINMUX_DATA(D27_MARK, PORT162_FN1),
1362 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1363 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1364 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1365 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1366
1367 /* Port163 */
1368 PINMUX_DATA(D26_MARK, PORT163_FN1),
1369 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1370 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1371 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1372 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1373 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1374
1375 /* Port164 */
1376 PINMUX_DATA(D25_MARK, PORT164_FN1),
1377 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1378 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1379 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1380 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1381
1382 /* Port165 */
1383 PINMUX_DATA(D24_MARK, PORT165_FN1),
1384 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1385 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1386 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1387
1388 /* Port166 - Port171 Function1 */
1389 PINMUX_DATA(D21_MARK, PORT166_FN1),
1390 PINMUX_DATA(D20_MARK, PORT167_FN1),
1391 PINMUX_DATA(D19_MARK, PORT168_FN1),
1392 PINMUX_DATA(D18_MARK, PORT169_FN1),
1393 PINMUX_DATA(D17_MARK, PORT170_FN1),
1394 PINMUX_DATA(D16_MARK, PORT171_FN1),
1395
1396 /* Port166 - Port171 Function3 */
1397 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1398 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1399 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1400 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1401 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1402 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1403
1404 /* Port166 - Port171 Function6 */
1405 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1406 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1407 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1408 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1409 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1410 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1411
1412 /* Port167 - Port171 IRQ */
1413 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1414 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1415 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1416 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1417 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1418
1419 /* Port172 */
1420 PINMUX_DATA(D23_MARK, PORT172_FN1),
1421 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1422 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1423 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1424 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1425
1426 /* Port173 */
1427 PINMUX_DATA(D22_MARK, PORT173_FN1),
1428 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1429 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1430 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1431 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1432
1433 /* Port174 */
1434 PINMUX_DATA(A26_MARK, PORT174_FN1),
1435 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1436 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1437 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1438
1439 /* Port175 */
1440 PINMUX_DATA(A0_MARK, PORT175_FN1),
1441 PINMUX_DATA(BS_MARK, PORT175_FN2),
1442 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1443 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1444
1445 /* Port176 */
1446 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1447
1448 /* Port177 */
1449 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1450 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1451 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1452 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1453
1454 /* Port178 */
1455 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1456 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1457 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1458
1459 /* Port179 */
1460 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1461 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1462 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1463
1464 /* Port180 */
1465 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1466 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1467 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1468 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1469 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1470
1471 /* Port181 */
1472 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1473 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1474 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1475
1476 /* Port182 */
1477 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1478 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1479 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1480
1481 /* Port183 */
1482 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1483 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1484 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1485
1486 /* Port184 */
1487 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1488 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1489 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1490
1491 /* Port185 - Port192 Function1 */
1492 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1493 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1494 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1495 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1496 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1497 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1498 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1499
1500 /* Port185 - Port192 Function3 */
1501 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1502 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1503 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1504 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1505 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1506 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1507 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1508 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1509
1510 /* Port185 - Port192 Function6 */
1511 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1512 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1513 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1514 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1515 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1516 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1517 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1518 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1519
1520 /* Port193 */
1521 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1522 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1523 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1524 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1525
1526 /* Port194 */
1527 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1528 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1529 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1530 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1531
1532 /* Port195 */
1533 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1534 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1535 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1536 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1537
1538 /* Port196 */
1539 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1540 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1541 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1542 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1543
1544 /* Port197 */
1545 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1546 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1547 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1548 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1549
1550 /* Port198 */
1551 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1552 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1553 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1554 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1555
1556 /* Port199 */
1557 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1558 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1559 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1560 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1561 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1562 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1563
1564 /* Port200 */
1565 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1566 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1567 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1568 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1569 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1570
1571 /* Port201 */
1572 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1573 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1574
1575 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1576 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1577 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1578 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1579
1580 /* Port202 */
1581 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1582 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1583
1584 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1585 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1586 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1587 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1588 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1589 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1590
1591 /* Port203 - Port208 Function1 */
1592 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1593 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1594 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1595 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1596 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1597 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1598
1599 /* Port203 - Port208 Function3 */
1600 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1601 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1602 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1603 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1604 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1605 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1606
1607 /* Port203 - Port208 Function6 */
1608 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1609 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1610 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1611 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1612 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1613 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1614
1615 /* Port203 - Port208 Function7 */
1616 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1617 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1618 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1619 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1620 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1621 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1622
1623 /* Port209 */
1624 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1625 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1626
1627 /* Port210 */
1628 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1629 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1630
1631 /* Port211 */
1632 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1633 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1634
1635 /* LCDC select */
1636 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1637 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1638
1639 /* SDENC */
1640 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1641 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1642
1643 /* SYSC */
1644 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1645 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1646
1647 /* DEBUG */
1648 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1649 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1650
1651 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1652 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1653 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1654};
1655
1656static struct pinmux_gpio pinmux_gpios[] = {
1657
1658 /* PORT */
1659 GPIO_PORT_ALL(),
1660
1661 /* IRQ */
1662 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1663 GPIO_FN(IRQ1),
1664 GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
1665 GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
1666 GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
1667 GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
1668 GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
1669 GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
1670 GPIO_FN(IRQ8),
1671 GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
1672 GPIO_FN(IRQ10),
1673 GPIO_FN(IRQ11),
1674 GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
1675 GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
1676 GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
1677 GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
1678 GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
1679 GPIO_FN(IRQ17),
1680 GPIO_FN(IRQ18),
1681 GPIO_FN(IRQ19),
1682 GPIO_FN(IRQ20),
1683 GPIO_FN(IRQ21),
1684 GPIO_FN(IRQ22),
1685 GPIO_FN(IRQ23),
1686 GPIO_FN(IRQ24),
1687 GPIO_FN(IRQ25),
1688 GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
1689 GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
1690 GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
1691 GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
1692 GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
1693 GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
1694
1695 /* Function */
1696
1697 /* DBGT */
1698 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
1699 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
1700 GPIO_FN(DBGMD21),
1701
1702 /* FSI-A */
1703 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
1704 GPIO_FN(FSIAISLD_PORT5),
1705 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
1706 GPIO_FN(FSIASPDIF_PORT18),
1707 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
1708 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
1709 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
1710
1711 /* FSI-B */
1712 GPIO_FN(FSIBCK),
1713
1714 /* FMSI */
1715 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
1716 GPIO_FN(FMSISLD_PORT6),
1717 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
1718 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
1719 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
1720 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
1721
1722 /* SCIFA0 */
1723 GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
1724 GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
1725
1726 /* SCIFA1 */
1727 GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
1728 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
1729
1730 /* SCIFA2 */
1731 GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
1732 GPIO_FN(SCIFA2_SCK_PORT199),
1733 GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
1734 GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
1735
1736 /* SCIFA3 */
1737 GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
1738 GPIO_FN(SCIFA3_SCK_PORT116),
1739 GPIO_FN(SCIFA3_CTS_PORT117),
1740 GPIO_FN(SCIFA3_RXD_PORT174),
1741 GPIO_FN(SCIFA3_TXD_PORT175),
1742
1743 GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
1744 GPIO_FN(SCIFA3_SCK_PORT158),
1745 GPIO_FN(SCIFA3_CTS_PORT162),
1746 GPIO_FN(SCIFA3_RXD_PORT159),
1747 GPIO_FN(SCIFA3_TXD_PORT160),
1748
1749 /* SCIFA4 */
1750 GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
1751 GPIO_FN(SCIFA4_TXD_PORT13),
1752
1753 GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
1754 GPIO_FN(SCIFA4_TXD_PORT203),
1755
1756 GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
1757 GPIO_FN(SCIFA4_TXD_PORT93),
1758
1759 GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
1760 GPIO_FN(SCIFA4_SCK_PORT205),
1761
1762 /* SCIFA5 */
1763 GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
1764 GPIO_FN(SCIFA5_RXD_PORT10),
1765
1766 GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
1767 GPIO_FN(SCIFA5_TXD_PORT208),
1768
1769 GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
1770 GPIO_FN(SCIFA5_RXD_PORT92),
1771
1772 GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
1773 GPIO_FN(SCIFA5_SCK_PORT206),
1774
1775 /* SCIFA6 */
1776 GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
1777
1778 /* SCIFA7 */
1779 GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
1780
1781 /* SCIFAB */
1782 GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
1783 GPIO_FN(SCIFB_RXD_PORT191),
1784 GPIO_FN(SCIFB_TXD_PORT192),
1785 GPIO_FN(SCIFB_RTS_PORT186),
1786 GPIO_FN(SCIFB_CTS_PORT187),
1787
1788 GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
1789 GPIO_FN(SCIFB_RXD_PORT3),
1790 GPIO_FN(SCIFB_TXD_PORT4),
1791 GPIO_FN(SCIFB_RTS_PORT172),
1792 GPIO_FN(SCIFB_CTS_PORT173),
1793
1794 /* LCD0 */
1795 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1796 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1797 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1798 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1799 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1800 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1801 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1802 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1803 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1804 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1805 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1806
1807 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1808 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1809 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1810 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1811
1812 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1813 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1814 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1815 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1816
1817 /* LCD1 */
1818 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1819 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1820 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1821 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1822 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1823 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1824 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1825 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1826 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1827 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1828 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1829 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1830
1831 /* RSPI */
1832 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1833 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
1834 GPIO_FN(RSPI_MISO_A),
1835
1836 /* VIO CKO */
1837 GPIO_FN(VIO_CKO1),
1838 GPIO_FN(VIO_CKO2),
1839 GPIO_FN(VIO_CKO_1),
1840 GPIO_FN(VIO_CKO),
1841
1842 /* VIO0 */
1843 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
1844 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
1845 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
1846 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
1847 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
1848 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
1849
1850 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
1851 GPIO_FN(VIO0_D14_PORT25),
1852 GPIO_FN(VIO0_D15_PORT24),
1853
1854 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
1855 GPIO_FN(VIO0_D14_PORT95),
1856 GPIO_FN(VIO0_D15_PORT96),
1857
1858 /* VIO1 */
1859 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
1860 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
1861 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
1862 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
1863
1864 /* TPU0 */
1865 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
1866 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
1867 GPIO_FN(TPU0TO2_PORT202),
1868
1869 /* SSP1 0 */
1870 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
1871 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
1872 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
1873 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
1874
1875 /* SSP1 1 */
1876 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
1877 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
1878 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
1879
1880 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
1881 GPIO_FN(STP1_IPEN_PORT187),
1882
1883 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
1884 GPIO_FN(STP1_IPEN_PORT193),
1885
1886 /* SIM */
1887 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
1888 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1889 GPIO_FN(SIM_D_PORT199),
1890
1891 /* SDHI0 */
1892 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1893 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1894 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1895
1896 /* SDHI1 */
1897 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1898 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1899 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1900
1901 /* SDHI2 */
1902 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1903 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1904
1905 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1906 GPIO_FN(SDHI2_WP_PORT25),
1907
1908 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1909 GPIO_FN(SDHI2_CD_PORT202),
1910
1911 /* MSIOF2 */
1912 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1913 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
1914 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
1915 GPIO_FN(MSIOF2_RSCK),
1916
1917 /* KEYSC */
1918 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
1919 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
1920 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
1921 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
1922 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
1923
1924 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
1925 GPIO_FN(KEYIN1_PORT44),
1926 GPIO_FN(KEYIN2_PORT45),
1927 GPIO_FN(KEYIN3_PORT46),
1928
1929 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
1930 GPIO_FN(KEYIN1_PORT57),
1931 GPIO_FN(KEYIN2_PORT56),
1932 GPIO_FN(KEYIN3_PORT55),
1933
1934 /* VOU */
1935 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
1936 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
1937 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
1938 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
1939 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
1940 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
1941 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
1942
1943 /* MEMC */
1944 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
1945 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
1946 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
1947 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
1948 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
1949 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
1950 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
1951 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
1952 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1953 GPIO_FN(MEMC_A0),
1954
1955 /* MMC */
1956 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1957 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1958 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1959 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1960 GPIO_FN(MMC0_CLK_PORT66),
1961 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1962
1963 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1964 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1965 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1966 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1967 GPIO_FN(MMC1_CLK_PORT103),
1968 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1969
1970 /* MSIOF0 */
1971 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1972 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
1973 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
1974 GPIO_FN(MSIOF0_TSYNC),
1975
1976 /* MSIOF1 */
1977 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
1978 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1979
1980 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
1981 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
1982 GPIO_FN(MSIOF1_TSYNC_PORT120),
1983 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
1984
1985 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
1986 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
1987 GPIO_FN(MSIOF1_RXD_PORT75),
1988 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
1989
1990 /* GPIO */
1991 GPIO_FN(GPO0), GPIO_FN(GPI0),
1992 GPIO_FN(GPO1), GPIO_FN(GPI1),
1993
1994 /* USB0 */
1995 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
1996
1997 /* USB1 */
1998 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
1999
2000 /* BBIF1 */
2001 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
2002 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
2003 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
2004
2005 /* BBIF2 */
2006 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
2007 GPIO_FN(BBIF2_RXD2_PORT60),
2008 GPIO_FN(BBIF2_TSYNC2_PORT6),
2009 GPIO_FN(BBIF2_TSCK2_PORT59),
2010
2011 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
2012 GPIO_FN(BBIF2_TXD2_PORT183),
2013 GPIO_FN(BBIF2_TSCK2_PORT89),
2014 GPIO_FN(BBIF2_TSYNC2_PORT184),
2015
2016 /* BSC / FLCTL / PCMCIA */
2017 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
2018 GPIO_FN(CS5B), GPIO_FN(CS6A),
2019 GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
2020 GPIO_FN(CS5A_PORT19),
2021 GPIO_FN(IOIS16), /* ? */
2022
2023 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
2024 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
2025 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
2026 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
2027 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
2028 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
2029 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
2030 GPIO_FN(A26),
2031
2032 GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
2033 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
2034 GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
2035 GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
2036 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
2037 GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
2038 GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
2039 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
2040 GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
2041 GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
2042 GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
2043 GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
2044
2045 GPIO_FN(WE0_FWE), /* share with FLCTL */
2046 GPIO_FN(WE1),
2047 GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
2048 GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
2049 GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
2050 GPIO_FN(RD_FSC), /* share with FLCTL */
2051 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
2052 GPIO_FN(WAIT_PORT90),
2053
2054 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
2055
2056 /* IRDA */
2057 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
2058
2059 /* ATAPI */
2060 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
2061 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
2062 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
2063 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
2064 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
2065 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
2066 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
2067 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
2068 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
2069 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
2070
2071 /* RMII */
2072 GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
2073 GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
2074 GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
2075 GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
2076
2077 /* GEther */
2078 GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
2079 GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
2080 GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
2081 GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
2082 GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
2083 GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
2084 GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
2085 GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
2086 GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
2087 GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
2088 GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
2089 GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
2090
2091 /* DMA0 */
2092 GPIO_FN(DREQ0), GPIO_FN(DACK0),
2093
2094 /* DMA1 */
2095 GPIO_FN(DREQ1), GPIO_FN(DACK1),
2096
2097 /* SYSC */
2098 GPIO_FN(RESETOUTS),
2099
2100 /* IRREM */
2101 GPIO_FN(IROUT),
2102
2103 /* LCDC */
2104 GPIO_FN(LCDC0_SELECT),
2105 GPIO_FN(LCDC1_SELECT),
2106
2107 /* SDENC */
2108 GPIO_FN(SDENC_CPG),
2109 GPIO_FN(SDENC_DV_CLKI),
2110
2111 /* HDMI */
2112 GPIO_FN(HDMI_HPD),
2113 GPIO_FN(HDMI_CEC),
2114
2115 /* SYSC */
2116 GPIO_FN(RESETP_PULLUP),
2117 GPIO_FN(RESETP_PLAIN),
2118
2119 /* DEBUG */
2120 GPIO_FN(EDEBGREQ_PULLDOWN),
2121 GPIO_FN(EDEBGREQ_PULLUP),
2122
2123 GPIO_FN(TRACEAUD_FROM_VIO),
2124 GPIO_FN(TRACEAUD_FROM_LCDC0),
2125 GPIO_FN(TRACEAUD_FROM_MEMC),
2126};
2127
2128static struct pinmux_cfg_reg pinmux_config_regs[] = {
2129 PORTCR(0, 0xe6050000), /* PORT0CR */
2130 PORTCR(1, 0xe6050001), /* PORT1CR */
2131 PORTCR(2, 0xe6050002), /* PORT2CR */
2132 PORTCR(3, 0xe6050003), /* PORT3CR */
2133 PORTCR(4, 0xe6050004), /* PORT4CR */
2134 PORTCR(5, 0xe6050005), /* PORT5CR */
2135 PORTCR(6, 0xe6050006), /* PORT6CR */
2136 PORTCR(7, 0xe6050007), /* PORT7CR */
2137 PORTCR(8, 0xe6050008), /* PORT8CR */
2138 PORTCR(9, 0xe6050009), /* PORT9CR */
2139 PORTCR(10, 0xe605000a), /* PORT10CR */
2140 PORTCR(11, 0xe605000b), /* PORT11CR */
2141 PORTCR(12, 0xe605000c), /* PORT12CR */
2142 PORTCR(13, 0xe605000d), /* PORT13CR */
2143 PORTCR(14, 0xe605000e), /* PORT14CR */
2144 PORTCR(15, 0xe605000f), /* PORT15CR */
2145 PORTCR(16, 0xe6050010), /* PORT16CR */
2146 PORTCR(17, 0xe6050011), /* PORT17CR */
2147 PORTCR(18, 0xe6050012), /* PORT18CR */
2148 PORTCR(19, 0xe6050013), /* PORT19CR */
2149 PORTCR(20, 0xe6050014), /* PORT20CR */
2150 PORTCR(21, 0xe6050015), /* PORT21CR */
2151 PORTCR(22, 0xe6050016), /* PORT22CR */
2152 PORTCR(23, 0xe6050017), /* PORT23CR */
2153 PORTCR(24, 0xe6050018), /* PORT24CR */
2154 PORTCR(25, 0xe6050019), /* PORT25CR */
2155 PORTCR(26, 0xe605001a), /* PORT26CR */
2156 PORTCR(27, 0xe605001b), /* PORT27CR */
2157 PORTCR(28, 0xe605001c), /* PORT28CR */
2158 PORTCR(29, 0xe605001d), /* PORT29CR */
2159 PORTCR(30, 0xe605001e), /* PORT30CR */
2160 PORTCR(31, 0xe605001f), /* PORT31CR */
2161 PORTCR(32, 0xe6050020), /* PORT32CR */
2162 PORTCR(33, 0xe6050021), /* PORT33CR */
2163 PORTCR(34, 0xe6050022), /* PORT34CR */
2164 PORTCR(35, 0xe6050023), /* PORT35CR */
2165 PORTCR(36, 0xe6050024), /* PORT36CR */
2166 PORTCR(37, 0xe6050025), /* PORT37CR */
2167 PORTCR(38, 0xe6050026), /* PORT38CR */
2168 PORTCR(39, 0xe6050027), /* PORT39CR */
2169 PORTCR(40, 0xe6050028), /* PORT40CR */
2170 PORTCR(41, 0xe6050029), /* PORT41CR */
2171 PORTCR(42, 0xe605002a), /* PORT42CR */
2172 PORTCR(43, 0xe605002b), /* PORT43CR */
2173 PORTCR(44, 0xe605002c), /* PORT44CR */
2174 PORTCR(45, 0xe605002d), /* PORT45CR */
2175 PORTCR(46, 0xe605002e), /* PORT46CR */
2176 PORTCR(47, 0xe605002f), /* PORT47CR */
2177 PORTCR(48, 0xe6050030), /* PORT48CR */
2178 PORTCR(49, 0xe6050031), /* PORT49CR */
2179 PORTCR(50, 0xe6050032), /* PORT50CR */
2180 PORTCR(51, 0xe6050033), /* PORT51CR */
2181 PORTCR(52, 0xe6050034), /* PORT52CR */
2182 PORTCR(53, 0xe6050035), /* PORT53CR */
2183 PORTCR(54, 0xe6050036), /* PORT54CR */
2184 PORTCR(55, 0xe6050037), /* PORT55CR */
2185 PORTCR(56, 0xe6050038), /* PORT56CR */
2186 PORTCR(57, 0xe6050039), /* PORT57CR */
2187 PORTCR(58, 0xe605003a), /* PORT58CR */
2188 PORTCR(59, 0xe605003b), /* PORT59CR */
2189 PORTCR(60, 0xe605003c), /* PORT60CR */
2190 PORTCR(61, 0xe605003d), /* PORT61CR */
2191 PORTCR(62, 0xe605003e), /* PORT62CR */
2192 PORTCR(63, 0xe605003f), /* PORT63CR */
2193 PORTCR(64, 0xe6050040), /* PORT64CR */
2194 PORTCR(65, 0xe6050041), /* PORT65CR */
2195 PORTCR(66, 0xe6050042), /* PORT66CR */
2196 PORTCR(67, 0xe6050043), /* PORT67CR */
2197 PORTCR(68, 0xe6050044), /* PORT68CR */
2198 PORTCR(69, 0xe6050045), /* PORT69CR */
2199 PORTCR(70, 0xe6050046), /* PORT70CR */
2200 PORTCR(71, 0xe6050047), /* PORT71CR */
2201 PORTCR(72, 0xe6050048), /* PORT72CR */
2202 PORTCR(73, 0xe6050049), /* PORT73CR */
2203 PORTCR(74, 0xe605004a), /* PORT74CR */
2204 PORTCR(75, 0xe605004b), /* PORT75CR */
2205 PORTCR(76, 0xe605004c), /* PORT76CR */
2206 PORTCR(77, 0xe605004d), /* PORT77CR */
2207 PORTCR(78, 0xe605004e), /* PORT78CR */
2208 PORTCR(79, 0xe605004f), /* PORT79CR */
2209 PORTCR(80, 0xe6050050), /* PORT80CR */
2210 PORTCR(81, 0xe6050051), /* PORT81CR */
2211 PORTCR(82, 0xe6050052), /* PORT82CR */
2212 PORTCR(83, 0xe6050053), /* PORT83CR */
2213
2214 PORTCR(84, 0xe6051054), /* PORT84CR */
2215 PORTCR(85, 0xe6051055), /* PORT85CR */
2216 PORTCR(86, 0xe6051056), /* PORT86CR */
2217 PORTCR(87, 0xe6051057), /* PORT87CR */
2218 PORTCR(88, 0xe6051058), /* PORT88CR */
2219 PORTCR(89, 0xe6051059), /* PORT89CR */
2220 PORTCR(90, 0xe605105a), /* PORT90CR */
2221 PORTCR(91, 0xe605105b), /* PORT91CR */
2222 PORTCR(92, 0xe605105c), /* PORT92CR */
2223 PORTCR(93, 0xe605105d), /* PORT93CR */
2224 PORTCR(94, 0xe605105e), /* PORT94CR */
2225 PORTCR(95, 0xe605105f), /* PORT95CR */
2226 PORTCR(96, 0xe6051060), /* PORT96CR */
2227 PORTCR(97, 0xe6051061), /* PORT97CR */
2228 PORTCR(98, 0xe6051062), /* PORT98CR */
2229 PORTCR(99, 0xe6051063), /* PORT99CR */
2230 PORTCR(100, 0xe6051064), /* PORT100CR */
2231 PORTCR(101, 0xe6051065), /* PORT101CR */
2232 PORTCR(102, 0xe6051066), /* PORT102CR */
2233 PORTCR(103, 0xe6051067), /* PORT103CR */
2234 PORTCR(104, 0xe6051068), /* PORT104CR */
2235 PORTCR(105, 0xe6051069), /* PORT105CR */
2236 PORTCR(106, 0xe605106a), /* PORT106CR */
2237 PORTCR(107, 0xe605106b), /* PORT107CR */
2238 PORTCR(108, 0xe605106c), /* PORT108CR */
2239 PORTCR(109, 0xe605106d), /* PORT109CR */
2240 PORTCR(110, 0xe605106e), /* PORT110CR */
2241 PORTCR(111, 0xe605106f), /* PORT111CR */
2242 PORTCR(112, 0xe6051070), /* PORT112CR */
2243 PORTCR(113, 0xe6051071), /* PORT113CR */
2244 PORTCR(114, 0xe6051072), /* PORT114CR */
2245
2246 PORTCR(115, 0xe6052073), /* PORT115CR */
2247 PORTCR(116, 0xe6052074), /* PORT116CR */
2248 PORTCR(117, 0xe6052075), /* PORT117CR */
2249 PORTCR(118, 0xe6052076), /* PORT118CR */
2250 PORTCR(119, 0xe6052077), /* PORT119CR */
2251 PORTCR(120, 0xe6052078), /* PORT120CR */
2252 PORTCR(121, 0xe6052079), /* PORT121CR */
2253 PORTCR(122, 0xe605207a), /* PORT122CR */
2254 PORTCR(123, 0xe605207b), /* PORT123CR */
2255 PORTCR(124, 0xe605207c), /* PORT124CR */
2256 PORTCR(125, 0xe605207d), /* PORT125CR */
2257 PORTCR(126, 0xe605207e), /* PORT126CR */
2258 PORTCR(127, 0xe605207f), /* PORT127CR */
2259 PORTCR(128, 0xe6052080), /* PORT128CR */
2260 PORTCR(129, 0xe6052081), /* PORT129CR */
2261 PORTCR(130, 0xe6052082), /* PORT130CR */
2262 PORTCR(131, 0xe6052083), /* PORT131CR */
2263 PORTCR(132, 0xe6052084), /* PORT132CR */
2264 PORTCR(133, 0xe6052085), /* PORT133CR */
2265 PORTCR(134, 0xe6052086), /* PORT134CR */
2266 PORTCR(135, 0xe6052087), /* PORT135CR */
2267 PORTCR(136, 0xe6052088), /* PORT136CR */
2268 PORTCR(137, 0xe6052089), /* PORT137CR */
2269 PORTCR(138, 0xe605208a), /* PORT138CR */
2270 PORTCR(139, 0xe605208b), /* PORT139CR */
2271 PORTCR(140, 0xe605208c), /* PORT140CR */
2272 PORTCR(141, 0xe605208d), /* PORT141CR */
2273 PORTCR(142, 0xe605208e), /* PORT142CR */
2274 PORTCR(143, 0xe605208f), /* PORT143CR */
2275 PORTCR(144, 0xe6052090), /* PORT144CR */
2276 PORTCR(145, 0xe6052091), /* PORT145CR */
2277 PORTCR(146, 0xe6052092), /* PORT146CR */
2278 PORTCR(147, 0xe6052093), /* PORT147CR */
2279 PORTCR(148, 0xe6052094), /* PORT148CR */
2280 PORTCR(149, 0xe6052095), /* PORT149CR */
2281 PORTCR(150, 0xe6052096), /* PORT150CR */
2282 PORTCR(151, 0xe6052097), /* PORT151CR */
2283 PORTCR(152, 0xe6052098), /* PORT152CR */
2284 PORTCR(153, 0xe6052099), /* PORT153CR */
2285 PORTCR(154, 0xe605209a), /* PORT154CR */
2286 PORTCR(155, 0xe605209b), /* PORT155CR */
2287 PORTCR(156, 0xe605209c), /* PORT156CR */
2288 PORTCR(157, 0xe605209d), /* PORT157CR */
2289 PORTCR(158, 0xe605209e), /* PORT158CR */
2290 PORTCR(159, 0xe605209f), /* PORT159CR */
2291 PORTCR(160, 0xe60520a0), /* PORT160CR */
2292 PORTCR(161, 0xe60520a1), /* PORT161CR */
2293 PORTCR(162, 0xe60520a2), /* PORT162CR */
2294 PORTCR(163, 0xe60520a3), /* PORT163CR */
2295 PORTCR(164, 0xe60520a4), /* PORT164CR */
2296 PORTCR(165, 0xe60520a5), /* PORT165CR */
2297 PORTCR(166, 0xe60520a6), /* PORT166CR */
2298 PORTCR(167, 0xe60520a7), /* PORT167CR */
2299 PORTCR(168, 0xe60520a8), /* PORT168CR */
2300 PORTCR(169, 0xe60520a9), /* PORT169CR */
2301 PORTCR(170, 0xe60520aa), /* PORT170CR */
2302 PORTCR(171, 0xe60520ab), /* PORT171CR */
2303 PORTCR(172, 0xe60520ac), /* PORT172CR */
2304 PORTCR(173, 0xe60520ad), /* PORT173CR */
2305 PORTCR(174, 0xe60520ae), /* PORT174CR */
2306 PORTCR(175, 0xe60520af), /* PORT175CR */
2307 PORTCR(176, 0xe60520b0), /* PORT176CR */
2308 PORTCR(177, 0xe60520b1), /* PORT177CR */
2309 PORTCR(178, 0xe60520b2), /* PORT178CR */
2310 PORTCR(179, 0xe60520b3), /* PORT179CR */
2311 PORTCR(180, 0xe60520b4), /* PORT180CR */
2312 PORTCR(181, 0xe60520b5), /* PORT181CR */
2313 PORTCR(182, 0xe60520b6), /* PORT182CR */
2314 PORTCR(183, 0xe60520b7), /* PORT183CR */
2315 PORTCR(184, 0xe60520b8), /* PORT184CR */
2316 PORTCR(185, 0xe60520b9), /* PORT185CR */
2317 PORTCR(186, 0xe60520ba), /* PORT186CR */
2318 PORTCR(187, 0xe60520bb), /* PORT187CR */
2319 PORTCR(188, 0xe60520bc), /* PORT188CR */
2320 PORTCR(189, 0xe60520bd), /* PORT189CR */
2321 PORTCR(190, 0xe60520be), /* PORT190CR */
2322 PORTCR(191, 0xe60520bf), /* PORT191CR */
2323 PORTCR(192, 0xe60520c0), /* PORT192CR */
2324 PORTCR(193, 0xe60520c1), /* PORT193CR */
2325 PORTCR(194, 0xe60520c2), /* PORT194CR */
2326 PORTCR(195, 0xe60520c3), /* PORT195CR */
2327 PORTCR(196, 0xe60520c4), /* PORT196CR */
2328 PORTCR(197, 0xe60520c5), /* PORT197CR */
2329 PORTCR(198, 0xe60520c6), /* PORT198CR */
2330 PORTCR(199, 0xe60520c7), /* PORT199CR */
2331 PORTCR(200, 0xe60520c8), /* PORT200CR */
2332 PORTCR(201, 0xe60520c9), /* PORT201CR */
2333 PORTCR(202, 0xe60520ca), /* PORT202CR */
2334 PORTCR(203, 0xe60520cb), /* PORT203CR */
2335 PORTCR(204, 0xe60520cc), /* PORT204CR */
2336 PORTCR(205, 0xe60520cd), /* PORT205CR */
2337 PORTCR(206, 0xe60520ce), /* PORT206CR */
2338 PORTCR(207, 0xe60520cf), /* PORT207CR */
2339 PORTCR(208, 0xe60520d0), /* PORT208CR */
2340 PORTCR(209, 0xe60520d1), /* PORT209CR */
2341
2342 PORTCR(210, 0xe60530d2), /* PORT210CR */
2343 PORTCR(211, 0xe60530d3), /* PORT211CR */
2344
2345 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2346 MSEL1CR_31_0, MSEL1CR_31_1,
2347 MSEL1CR_30_0, MSEL1CR_30_1,
2348 MSEL1CR_29_0, MSEL1CR_29_1,
2349 MSEL1CR_28_0, MSEL1CR_28_1,
2350 MSEL1CR_27_0, MSEL1CR_27_1,
2351 MSEL1CR_26_0, MSEL1CR_26_1,
2352 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2353 0, 0, 0, 0, 0, 0, 0, 0,
2354 MSEL1CR_16_0, MSEL1CR_16_1,
2355 MSEL1CR_15_0, MSEL1CR_15_1,
2356 MSEL1CR_14_0, MSEL1CR_14_1,
2357 MSEL1CR_13_0, MSEL1CR_13_1,
2358 MSEL1CR_12_0, MSEL1CR_12_1,
2359 0, 0, 0, 0,
2360 MSEL1CR_9_0, MSEL1CR_9_1,
2361 0, 0,
2362 MSEL1CR_7_0, MSEL1CR_7_1,
2363 MSEL1CR_6_0, MSEL1CR_6_1,
2364 MSEL1CR_5_0, MSEL1CR_5_1,
2365 MSEL1CR_4_0, MSEL1CR_4_1,
2366 MSEL1CR_3_0, MSEL1CR_3_1,
2367 MSEL1CR_2_0, MSEL1CR_2_1,
2368 0, 0,
2369 MSEL1CR_0_0, MSEL1CR_0_1,
2370 }
2371 },
2372 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2373 0, 0, 0, 0, 0, 0, 0, 0,
2374 0, 0, 0, 0, 0, 0, 0, 0,
2375 0, 0, 0, 0, 0, 0, 0, 0,
2376 0, 0, 0, 0, 0, 0, 0, 0,
2377 MSEL3CR_15_0, MSEL3CR_15_1,
2378 0, 0, 0, 0, 0, 0, 0, 0,
2379 0, 0, 0, 0, 0, 0, 0, 0,
2380 MSEL3CR_6_0, MSEL3CR_6_1,
2381 0, 0, 0, 0, 0, 0, 0, 0,
2382 0, 0, 0, 0,
2383 }
2384 },
2385 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2386 0, 0, 0, 0, 0, 0, 0, 0,
2387 0, 0, 0, 0, 0, 0, 0, 0,
2388 0, 0, 0, 0, 0, 0, 0, 0,
2389 MSEL4CR_19_0, MSEL4CR_19_1,
2390 MSEL4CR_18_0, MSEL4CR_18_1,
2391 0, 0, 0, 0,
2392 MSEL4CR_15_0, MSEL4CR_15_1,
2393 0, 0, 0, 0, 0, 0, 0, 0,
2394 MSEL4CR_10_0, MSEL4CR_10_1,
2395 0, 0, 0, 0, 0, 0,
2396 MSEL4CR_6_0, MSEL4CR_6_1,
2397 0, 0,
2398 MSEL4CR_4_0, MSEL4CR_4_1,
2399 0, 0, 0, 0,
2400 MSEL4CR_1_0, MSEL4CR_1_1,
2401 0, 0,
2402 }
2403 },
2404 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
2405 MSEL5CR_31_0, MSEL5CR_31_1,
2406 MSEL5CR_30_0, MSEL5CR_30_1,
2407 MSEL5CR_29_0, MSEL5CR_29_1,
2408 0, 0,
2409 MSEL5CR_27_0, MSEL5CR_27_1,
2410 0, 0,
2411 MSEL5CR_25_0, MSEL5CR_25_1,
2412 0, 0,
2413 MSEL5CR_23_0, MSEL5CR_23_1,
2414 0, 0,
2415 MSEL5CR_21_0, MSEL5CR_21_1,
2416 0, 0,
2417 MSEL5CR_19_0, MSEL5CR_19_1,
2418 0, 0,
2419 MSEL5CR_17_0, MSEL5CR_17_1,
2420 0, 0,
2421 MSEL5CR_15_0, MSEL5CR_15_1,
2422 MSEL5CR_14_0, MSEL5CR_14_1,
2423 MSEL5CR_13_0, MSEL5CR_13_1,
2424 MSEL5CR_12_0, MSEL5CR_12_1,
2425 MSEL5CR_11_0, MSEL5CR_11_1,
2426 MSEL5CR_10_0, MSEL5CR_10_1,
2427 0, 0,
2428 MSEL5CR_8_0, MSEL5CR_8_1,
2429 MSEL5CR_7_0, MSEL5CR_7_1,
2430 MSEL5CR_6_0, MSEL5CR_6_1,
2431 MSEL5CR_5_0, MSEL5CR_5_1,
2432 MSEL5CR_4_0, MSEL5CR_4_1,
2433 MSEL5CR_3_0, MSEL5CR_3_1,
2434 MSEL5CR_2_0, MSEL5CR_2_1,
2435 0, 0,
2436 MSEL5CR_0_0, MSEL5CR_0_1,
2437 }
2438 },
2439 { },
2440};
2441
2442static struct pinmux_data_reg pinmux_data_regs[] = {
2443 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2444 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2445 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2446 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2447 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2448 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2449 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2450 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2451 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
2452 },
2453 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
2454 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2455 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2456 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2457 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2458 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
2459 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2460 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2461 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
2462 },
2463 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
2464 0, 0, 0, 0,
2465 0, 0, 0, 0,
2466 0, 0, 0, 0,
2467 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2468 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2469 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2470 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2471 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
2472 },
2473 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
2474 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2475 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2476 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2477 0, 0, 0, 0,
2478 0, 0, 0, 0,
2479 0, 0, 0, 0,
2480 0, 0, 0, 0,
2481 0, 0, 0, 0 }
2482 },
2483 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
2484 0, 0, 0, 0,
2485 0, 0, 0, 0,
2486 0, 0, 0, 0,
2487 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2488 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2489 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2490 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2491 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
2492 },
2493 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
2494 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2495 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2496 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2497 PORT115_DATA, 0, 0, 0,
2498 0, 0, 0, 0,
2499 0, 0, 0, 0,
2500 0, 0, 0, 0,
2501 0, 0, 0, 0 }
2502 },
2503 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
2504 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2505 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2506 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2507 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2508 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2509 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2510 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2511 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
2512 },
2513 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
2514 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2515 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2516 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2517 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2518 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2519 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2520 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2521 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
2522 },
2523 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
2524 0, 0, 0, 0,
2525 0, 0, 0, 0,
2526 0, 0, 0, 0,
2527 0, 0, PORT209_DATA, PORT208_DATA,
2528 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2529 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2530 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2531 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
2532 },
2533 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
2534 0, 0, 0, 0,
2535 0, 0, 0, 0,
2536 0, 0, 0, 0,
2537 PORT211_DATA, PORT210_DATA, 0, 0,
2538 0, 0, 0, 0,
2539 0, 0, 0, 0,
2540 0, 0, 0, 0,
2541 0, 0, 0, 0 }
2542 },
2543 { },
2544};
2545
2546static struct pinmux_irq pinmux_irqs[] = {
2547 PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */
2548 PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */
2549 PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */
2550 PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */
2551 PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */
2552 PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */
2553 PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */
2554 PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */
2555 PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */
2556 PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */
2557 PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */
2558 PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */
2559 PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */
2560 PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */
2561 PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */
2562 PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */
2563 PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */
2564 PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */
2565 PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */
2566 PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */
2567 PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */
2568 PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */
2569 PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */
2570 PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */
2571 PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */
2572 PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */
2573 PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */
2574 PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */
2575 PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */
2576 PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */
2577 PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */
2578 PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */
2579};
2580
2581struct sh_pfc_soc_info r8a7740_pinmux_info = {
2582 .name = "r8a7740_pfc",
2583 .reserved_id = PINMUX_RESERVED,
2584 .data = { PINMUX_DATA_BEGIN,
2585 PINMUX_DATA_END },
2586 .input = { PINMUX_INPUT_BEGIN,
2587 PINMUX_INPUT_END },
2588 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
2589 PINMUX_INPUT_PULLUP_END },
2590 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
2591 PINMUX_INPUT_PULLDOWN_END },
2592 .output = { PINMUX_OUTPUT_BEGIN,
2593 PINMUX_OUTPUT_END },
2594 .mark = { PINMUX_MARK_BEGIN,
2595 PINMUX_MARK_END },
2596 .function = { PINMUX_FUNCTION_BEGIN,
2597 PINMUX_FUNCTION_END },
2598
2599 .first_gpio = GPIO_PORT0,
2600 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
2601
2602 .gpios = pinmux_gpios,
2603 .cfg_regs = pinmux_config_regs,
2604 .data_regs = pinmux_data_regs,
2605
2606 .gpio_data = pinmux_data,
2607 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2608
2609 .gpio_irq = pinmux_irqs,
2610 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2611};