David Ertman | e78b80b | 2014-02-04 01:56:06 +0000 | [diff] [blame] | 1 | /* Intel PRO/1000 Linux driver |
Yanir Lubetkin | 529498c | 2015-06-02 17:05:50 +0300 | [diff] [blame] | 2 | * Copyright(c) 1999 - 2015 Intel Corporation. |
David Ertman | e78b80b | 2014-02-04 01:56:06 +0000 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * The full GNU General Public License is included in this distribution in |
| 14 | * the file called "COPYING". |
| 15 | * |
| 16 | * Contact Information: |
| 17 | * Linux NICS <linux.nics@intel.com> |
| 18 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 20 | */ |
Bruce Allan | 93b9f8b | 2013-01-22 08:44:25 +0000 | [diff] [blame] | 21 | |
| 22 | #ifndef _E1000E_PHY_H_ |
| 23 | #define _E1000E_PHY_H_ |
| 24 | |
| 25 | s32 e1000e_check_downshift(struct e1000_hw *hw); |
| 26 | s32 e1000_check_polarity_m88(struct e1000_hw *hw); |
| 27 | s32 e1000_check_polarity_igp(struct e1000_hw *hw); |
| 28 | s32 e1000_check_polarity_ife(struct e1000_hw *hw); |
| 29 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); |
| 30 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); |
| 31 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); |
| 32 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); |
| 33 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); |
| 34 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); |
| 35 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); |
| 36 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); |
| 37 | s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); |
| 38 | s32 e1000e_get_phy_id(struct e1000_hw *hw); |
| 39 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); |
| 40 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); |
| 41 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw); |
| 42 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw); |
| 43 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); |
| 44 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); |
| 45 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); |
| 46 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); |
| 47 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
| 48 | s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); |
| 49 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); |
| 50 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
| 51 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); |
| 52 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
| 53 | s32 e1000e_setup_copper_link(struct e1000_hw *hw); |
| 54 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); |
| 55 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); |
| 56 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); |
| 57 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); |
| 58 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); |
| 59 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
| 60 | u32 usec_interval, bool *success); |
| 61 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); |
| 62 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); |
| 63 | s32 e1000e_determine_phy_address(struct e1000_hw *hw); |
| 64 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); |
| 65 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); |
| 66 | s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); |
| 67 | s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); |
| 68 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); |
| 69 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); |
| 70 | void e1000_power_up_phy_copper(struct e1000_hw *hw); |
| 71 | void e1000_power_down_phy_copper(struct e1000_hw *hw); |
| 72 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); |
| 73 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); |
| 74 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
| 75 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
| 76 | s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
| 77 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); |
| 78 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); |
| 79 | s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); |
| 80 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); |
| 81 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); |
| 82 | s32 e1000_check_polarity_82577(struct e1000_hw *hw); |
| 83 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw); |
| 84 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); |
| 85 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw); |
| 86 | |
| 87 | #define E1000_MAX_PHY_ADDR 8 |
| 88 | |
| 89 | /* IGP01E1000 Specific Registers */ |
| 90 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ |
| 91 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ |
| 92 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ |
| 93 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ |
| 94 | #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ |
| 95 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ |
| 96 | #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ |
| 97 | #define IGP_PAGE_SHIFT 5 |
| 98 | #define PHY_REG_MASK 0x1F |
| 99 | |
| 100 | /* BM/HV Specific Registers */ |
| 101 | #define BM_PORT_CTRL_PAGE 769 |
| 102 | #define BM_WUC_PAGE 800 |
| 103 | #define BM_WUC_ADDRESS_OPCODE 0x11 |
| 104 | #define BM_WUC_DATA_OPCODE 0x12 |
| 105 | #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE |
| 106 | #define BM_WUC_ENABLE_REG 17 |
| 107 | #define BM_WUC_ENABLE_BIT (1 << 2) |
| 108 | #define BM_WUC_HOST_WU_BIT (1 << 4) |
| 109 | #define BM_WUC_ME_WU_BIT (1 << 5) |
| 110 | |
| 111 | #define PHY_UPPER_SHIFT 21 |
| 112 | #define BM_PHY_REG(page, reg) \ |
| 113 | (((reg) & MAX_PHY_REG_ADDRESS) |\ |
| 114 | (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ |
| 115 | (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) |
| 116 | #define BM_PHY_REG_PAGE(offset) \ |
| 117 | ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) |
| 118 | #define BM_PHY_REG_NUM(offset) \ |
| 119 | ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ |
| 120 | (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ |
| 121 | ~MAX_PHY_REG_ADDRESS))) |
| 122 | |
| 123 | #define HV_INTC_FC_PAGE_START 768 |
| 124 | #define I82578_ADDR_REG 29 |
| 125 | #define I82577_ADDR_REG 16 |
| 126 | #define I82577_CFG_REG 22 |
| 127 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
| 128 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ |
| 129 | #define I82577_CTRL_REG 23 |
| 130 | |
| 131 | /* 82577 specific PHY registers */ |
| 132 | #define I82577_PHY_CTRL_2 18 |
| 133 | #define I82577_PHY_LBK_CTRL 19 |
| 134 | #define I82577_PHY_STATUS_2 26 |
| 135 | #define I82577_PHY_DIAG_STATUS 31 |
| 136 | |
| 137 | /* I82577 PHY Status 2 */ |
| 138 | #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 |
| 139 | #define I82577_PHY_STATUS2_MDIX 0x0800 |
| 140 | #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 |
| 141 | #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
| 142 | |
| 143 | /* I82577 PHY Control 2 */ |
| 144 | #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 |
| 145 | #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 |
| 146 | #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 |
| 147 | |
| 148 | /* I82577 PHY Diagnostics Status */ |
| 149 | #define I82577_DSTATUS_CABLE_LENGTH 0x03FC |
| 150 | #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 |
| 151 | |
| 152 | /* BM PHY Copper Specific Control 1 */ |
| 153 | #define BM_CS_CTRL1 16 |
| 154 | |
| 155 | /* BM PHY Copper Specific Status */ |
| 156 | #define BM_CS_STATUS 17 |
| 157 | #define BM_CS_STATUS_LINK_UP 0x0400 |
| 158 | #define BM_CS_STATUS_RESOLVED 0x0800 |
| 159 | #define BM_CS_STATUS_SPEED_MASK 0xC000 |
| 160 | #define BM_CS_STATUS_SPEED_1000 0x8000 |
| 161 | |
| 162 | /* 82577 Mobile Phy Status Register */ |
| 163 | #define HV_M_STATUS 26 |
| 164 | #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 |
| 165 | #define HV_M_STATUS_SPEED_MASK 0x0300 |
| 166 | #define HV_M_STATUS_SPEED_1000 0x0200 |
David Ertman | 77e6114 | 2014-04-22 05:25:53 +0000 | [diff] [blame] | 167 | #define HV_M_STATUS_SPEED_100 0x0100 |
Bruce Allan | 93b9f8b | 2013-01-22 08:44:25 +0000 | [diff] [blame] | 168 | #define HV_M_STATUS_LINK_UP 0x0040 |
| 169 | |
| 170 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
| 171 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
| 172 | |
| 173 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
| 174 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ |
| 175 | |
| 176 | #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
| 177 | |
| 178 | #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ |
| 179 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ |
| 180 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ |
| 181 | |
| 182 | #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
| 183 | |
| 184 | #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
| 185 | #define IGP01E1000_PSSR_MDIX 0x0800 |
| 186 | #define IGP01E1000_PSSR_SPEED_MASK 0xC000 |
| 187 | #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
| 188 | |
| 189 | #define IGP02E1000_PHY_CHANNEL_NUM 4 |
| 190 | #define IGP02E1000_PHY_AGC_A 0x11B1 |
| 191 | #define IGP02E1000_PHY_AGC_B 0x12B1 |
| 192 | #define IGP02E1000_PHY_AGC_C 0x14B1 |
| 193 | #define IGP02E1000_PHY_AGC_D 0x18B1 |
| 194 | |
| 195 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ |
| 196 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F |
| 197 | #define IGP02E1000_AGC_RANGE 15 |
| 198 | |
| 199 | #define E1000_CABLE_LENGTH_UNDEFINED 0xFF |
| 200 | |
| 201 | #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 |
| 202 | #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 |
| 203 | #define E1000_KMRNCTRLSTA_REN 0x00200000 |
| 204 | #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ |
| 205 | #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ |
| 206 | #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ |
| 207 | #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ |
| 208 | #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ |
| 209 | #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ |
| 210 | #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 |
| 211 | #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ |
| 212 | #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ |
| 213 | |
| 214 | #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 |
| 215 | #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ |
| 216 | #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ |
| 217 | #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ |
| 218 | |
| 219 | /* IFE PHY Extended Status Control */ |
| 220 | #define IFE_PESC_POLARITY_REVERSED 0x0100 |
| 221 | |
| 222 | /* IFE PHY Special Control */ |
| 223 | #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 |
| 224 | #define IFE_PSC_FORCE_POLARITY 0x0020 |
| 225 | |
| 226 | /* IFE PHY Special Control and LED Control */ |
| 227 | #define IFE_PSCL_PROBE_MODE 0x0020 |
| 228 | #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ |
| 229 | #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ |
| 230 | |
| 231 | /* IFE PHY MDIX Control */ |
| 232 | #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ |
| 233 | #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ |
| 234 | #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ |
| 235 | |
| 236 | #endif |