blob: bdb3f67068016c4b73770719114558c6f741babe [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-h720x/common.c
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * common stuff for Hynix h720x processors
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/sched.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/mman.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
Russell Kingfced80c2008-09-06 12:10:45 +010020#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22#include <asm/page.h>
23#include <asm/pgtable.h>
24#include <asm/dma.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010025#include <mach/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/irq.h>
27#include <asm/mach/irq.h>
28#include <asm/mach/map.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010029#include <mach/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31#include <asm/mach/dma.h>
32
33#if 0
34#define IRQDBG(args...) printk(args)
35#else
36#define IRQDBG(args...) do {} while(0)
37#endif
38
39void __init arch_dma_init(dma_t *dma)
40{
41}
42
43/*
44 * Return usecs since last timer reload
45 * (timercount * (usecs perjiffie)) / (ticks per jiffie)
46 */
47unsigned long h720x_gettimeoffset(void)
48{
49 return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
50}
51
52/*
53 * mask Global irq's
54 */
55static void mask_global_irq (unsigned int irq )
56{
57 CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
58}
59
60/*
61 * unmask Global irq's
62 */
63static void unmask_global_irq (unsigned int irq )
64{
65 CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
66}
67
68
69/*
70 * ack GPIO irq's
71 * Ack only for edge triggered int's valid
72 */
73static void inline ack_gpio_irq(u32 irq)
74{
75 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
76 u32 bit = IRQ_TO_BIT(irq);
77 if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
78 CPU_REG (reg_base, GPIO_CLR) = bit;
79}
80
81/*
82 * mask GPIO irq's
83 */
84static void inline mask_gpio_irq(u32 irq)
85{
86 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
87 u32 bit = IRQ_TO_BIT(irq);
88 CPU_REG (reg_base, GPIO_MASK) &= ~bit;
89}
90
91/*
92 * unmask GPIO irq's
93 */
94static void inline unmask_gpio_irq(u32 irq)
95{
96 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
97 u32 bit = IRQ_TO_BIT(irq);
98 CPU_REG (reg_base, GPIO_MASK) |= bit;
99}
100
101static void
102h720x_gpio_handler(unsigned int mask, unsigned int irq,
Russell King10dd5ce2006-11-23 11:41:32 +0000103 struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104{
Harvey Harrison8e86f422008-03-04 15:08:02 -0800105 IRQDBG("%s irq: %d\n", __func__, irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 while (mask) {
107 if (mask & 1) {
108 IRQDBG("handling irq %d\n", irq);
Dmitry Baryshkovd8aa0252008-10-09 13:36:24 +0100109 generic_handle_irq(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110 }
111 irq++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 mask >>= 1;
113 }
114}
115
116static void
Russell King10dd5ce2006-11-23 11:41:32 +0000117h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118{
119 unsigned int mask, irq;
120
121 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
122 irq = IRQ_CHAINED_GPIOA(0);
Harvey Harrison8e86f422008-03-04 15:08:02 -0800123 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700124 h720x_gpio_handler(mask, irq, desc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125}
126
127static void
Russell King10dd5ce2006-11-23 11:41:32 +0000128h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129{
130 unsigned int mask, irq;
131 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
132 irq = IRQ_CHAINED_GPIOB(0);
Harvey Harrison8e86f422008-03-04 15:08:02 -0800133 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700134 h720x_gpio_handler(mask, irq, desc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135}
136
137static void
Russell King10dd5ce2006-11-23 11:41:32 +0000138h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139{
140 unsigned int mask, irq;
141
142 mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
143 irq = IRQ_CHAINED_GPIOC(0);
Harvey Harrison8e86f422008-03-04 15:08:02 -0800144 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700145 h720x_gpio_handler(mask, irq, desc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146}
147
148static void
Russell King10dd5ce2006-11-23 11:41:32 +0000149h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150{
151 unsigned int mask, irq;
152
153 mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
154 irq = IRQ_CHAINED_GPIOD(0);
Harvey Harrison8e86f422008-03-04 15:08:02 -0800155 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700156 h720x_gpio_handler(mask, irq, desc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157}
158
159#ifdef CONFIG_CPU_H7202
160static void
Russell King10dd5ce2006-11-23 11:41:32 +0000161h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162{
163 unsigned int mask, irq;
164
165 mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
166 irq = IRQ_CHAINED_GPIOE(0);
Harvey Harrison8e86f422008-03-04 15:08:02 -0800167 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700168 h720x_gpio_handler(mask, irq, desc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169}
170#endif
171
Russell King10dd5ce2006-11-23 11:41:32 +0000172static struct irq_chip h720x_global_chip = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173 .ack = mask_global_irq,
174 .mask = mask_global_irq,
175 .unmask = unmask_global_irq,
176};
177
Russell King10dd5ce2006-11-23 11:41:32 +0000178static struct irq_chip h720x_gpio_chip = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 .ack = ack_gpio_irq,
180 .mask = mask_gpio_irq,
181 .unmask = unmask_gpio_irq,
182};
183
184/*
185 * Initialize IRQ's, mask all, enable multiplexed irq's
186 */
187void __init h720x_init_irq (void)
188{
189 int irq;
190
191 /* Mask global irq's */
192 CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
193
194 /* Mask all multiplexed irq's */
195 CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
196 CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
197 CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
198 CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
199
200 /* Initialize global IRQ's, fast path */
201 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
202 set_irq_chip(irq, &h720x_global_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000203 set_irq_handler(irq, handle_level_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
205 }
206
207 /* Initialize multiplexed IRQ's, slow path */
208 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
209 set_irq_chip(irq, &h720x_gpio_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000210 set_irq_handler(irq, handle_edge_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 set_irq_flags(irq, IRQF_VALID );
212 }
213 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
214 set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
215 set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
216 set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
217
218#ifdef CONFIG_CPU_H7202
219 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
220 set_irq_chip(irq, &h720x_gpio_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000221 set_irq_handler(irq, handle_edge_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 set_irq_flags(irq, IRQF_VALID );
223 }
224 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
225#endif
226
227 /* Enable multiplexed irq's */
228 CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
229}
230
231static struct map_desc h720x_io_desc[] __initdata = {
Deepak Saxena3e9635e2005-10-28 15:19:09 +0100232 {
233 .virtual = IO_VIRT,
234 .pfn = __phys_to_pfn(IO_PHYS),
235 .length = IO_SIZE,
236 .type = MT_DEVICE
237 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238};
239
240/* Initialize io tables */
241void __init h720x_map_io(void)
242{
243 iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
244}