Gregory CLEMENT | 568fc0a | 2013-01-31 15:50:12 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree file for Marvell Armada XP development board |
| 3 | * (DB-MV784MP-GP) |
| 4 | * |
| 5 | * Copyright (C) 2013 Marvell |
| 6 | * |
| 7 | * Lior Amsalem <alior@marvell.com> |
| 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| 9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 10 | * |
| 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. |
| 14 | */ |
| 15 | |
| 16 | /dts-v1/; |
| 17 | /include/ "armada-xp-mv78460.dtsi" |
| 18 | |
| 19 | / { |
| 20 | model = "Marvell Armada XP Development Board DB-MV784MP-GP"; |
| 21 | compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; |
| 22 | |
| 23 | chosen { |
| 24 | bootargs = "console=ttyS0,115200 earlyprintk"; |
| 25 | }; |
| 26 | |
| 27 | memory { |
| 28 | device_type = "memory"; |
Gregory CLEMENT | 568fc0a | 2013-01-31 15:50:12 +0100 | [diff] [blame] | 29 | /* |
Gregory CLEMENT | 7489836 | 2013-04-12 16:29:10 +0200 | [diff] [blame] | 30 | * 8 GB of plug-in RAM modules by default.The amount |
| 31 | * of memory available can be changed by the |
| 32 | * bootloader according the size of the module |
| 33 | * actually plugged. Only 7GB are usable because |
| 34 | * addresses from 0xC0000000 to 0xffffffff are used by |
| 35 | * the internal registers of the SoC. |
Gregory CLEMENT | 568fc0a | 2013-01-31 15:50:12 +0100 | [diff] [blame] | 36 | */ |
Gregory CLEMENT | 7489836 | 2013-04-12 16:29:10 +0200 | [diff] [blame] | 37 | reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, |
| 38 | <0x00000001 0x00000000 0x00000001 0x00000000>; |
Gregory CLEMENT | 568fc0a | 2013-01-31 15:50:12 +0100 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | soc { |
Gregory CLEMENT | 467f54b | 2013-04-12 16:29:09 +0200 | [diff] [blame] | 42 | internal-regs { |
| 43 | serial@12000 { |
| 44 | clock-frequency = <250000000>; |
Thomas Petazzoni | 513a791 | 2013-04-09 23:06:39 +0200 | [diff] [blame] | 45 | status = "okay"; |
| 46 | }; |
Gregory CLEMENT | 467f54b | 2013-04-12 16:29:09 +0200 | [diff] [blame] | 47 | serial@12100 { |
| 48 | clock-frequency = <250000000>; |
Thomas Petazzoni | 513a791 | 2013-04-09 23:06:39 +0200 | [diff] [blame] | 49 | status = "okay"; |
| 50 | }; |
Gregory CLEMENT | 467f54b | 2013-04-12 16:29:09 +0200 | [diff] [blame] | 51 | serial@12200 { |
| 52 | clock-frequency = <250000000>; |
Thomas Petazzoni | 513a791 | 2013-04-09 23:06:39 +0200 | [diff] [blame] | 53 | status = "okay"; |
| 54 | }; |
Gregory CLEMENT | 467f54b | 2013-04-12 16:29:09 +0200 | [diff] [blame] | 55 | serial@12300 { |
| 56 | clock-frequency = <250000000>; |
| 57 | status = "okay"; |
| 58 | }; |
| 59 | |
| 60 | sata@a0000 { |
| 61 | nr-ports = <2>; |
| 62 | status = "okay"; |
| 63 | }; |
| 64 | |
| 65 | mdio { |
| 66 | phy0: ethernet-phy@0 { |
| 67 | reg = <16>; |
| 68 | }; |
| 69 | |
| 70 | phy1: ethernet-phy@1 { |
| 71 | reg = <17>; |
| 72 | }; |
| 73 | |
| 74 | phy2: ethernet-phy@2 { |
| 75 | reg = <18>; |
| 76 | }; |
| 77 | |
| 78 | phy3: ethernet-phy@3 { |
| 79 | reg = <19>; |
| 80 | }; |
| 81 | }; |
| 82 | |
| 83 | ethernet@70000 { |
| 84 | status = "okay"; |
| 85 | phy = <&phy0>; |
| 86 | phy-mode = "rgmii-id"; |
| 87 | }; |
| 88 | ethernet@74000 { |
| 89 | status = "okay"; |
| 90 | phy = <&phy1>; |
| 91 | phy-mode = "rgmii-id"; |
| 92 | }; |
| 93 | ethernet@30000 { |
| 94 | status = "okay"; |
| 95 | phy = <&phy2>; |
| 96 | phy-mode = "rgmii-id"; |
| 97 | }; |
| 98 | ethernet@34000 { |
| 99 | status = "okay"; |
| 100 | phy = <&phy3>; |
| 101 | phy-mode = "rgmii-id"; |
| 102 | }; |
| 103 | |
| 104 | spi0: spi@10600 { |
| 105 | status = "okay"; |
| 106 | |
| 107 | spi-flash@0 { |
| 108 | #address-cells = <1>; |
| 109 | #size-cells = <1>; |
| 110 | compatible = "n25q128a13"; |
| 111 | reg = <0>; /* Chip select 0 */ |
| 112 | spi-max-frequency = <108000000>; |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | devbus-bootcs@10400 { |
| 117 | status = "okay"; |
| 118 | ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ |
| 119 | |
| 120 | /* Device Bus parameters are required */ |
| 121 | |
| 122 | /* Read parameters */ |
| 123 | devbus,bus-width = <8>; |
| 124 | devbus,turn-off-ps = <60000>; |
| 125 | devbus,badr-skew-ps = <0>; |
| 126 | devbus,acc-first-ps = <124000>; |
| 127 | devbus,acc-next-ps = <248000>; |
| 128 | devbus,rd-setup-ps = <0>; |
| 129 | devbus,rd-hold-ps = <0>; |
| 130 | |
| 131 | /* Write parameters */ |
| 132 | devbus,sync-enable = <0>; |
| 133 | devbus,wr-high-ps = <60000>; |
| 134 | devbus,wr-low-ps = <60000>; |
| 135 | devbus,ale-wr-ps = <60000>; |
| 136 | |
| 137 | /* NOR 16 MiB */ |
| 138 | nor@0 { |
| 139 | compatible = "cfi-flash"; |
| 140 | reg = <0 0x1000000>; |
| 141 | bank-width = <2>; |
| 142 | }; |
| 143 | }; |
| 144 | |
| 145 | pcie-controller { |
| 146 | status = "okay"; |
| 147 | |
| 148 | /* |
| 149 | * The 3 slots are physically present as |
| 150 | * standard PCIe slots on the board. |
| 151 | */ |
| 152 | pcie@1,0 { |
| 153 | /* Port 0, Lane 0 */ |
| 154 | status = "okay"; |
| 155 | }; |
| 156 | pcie@9,0 { |
| 157 | /* Port 2, Lane 0 */ |
| 158 | status = "okay"; |
| 159 | }; |
| 160 | pcie@10,0 { |
| 161 | /* Port 3, Lane 0 */ |
| 162 | status = "okay"; |
| 163 | }; |
| 164 | }; |
Thomas Petazzoni | 513a791 | 2013-04-09 23:06:39 +0200 | [diff] [blame] | 165 | }; |
Gregory CLEMENT | 568fc0a | 2013-01-31 15:50:12 +0100 | [diff] [blame] | 166 | }; |
| 167 | }; |