Jiri Pirko | 93c1edb | 2015-07-29 23:33:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * drivers/net/ethernet/mellanox/mlxsw/port.h |
| 3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. |
| 4 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> |
| 5 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> |
| 6 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions are met: |
| 10 | * |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. Neither the names of the copyright holders nor the names of its |
| 17 | * contributors may be used to endorse or promote products derived from |
| 18 | * this software without specific prior written permission. |
| 19 | * |
| 20 | * Alternatively, this software may be distributed under the terms of the |
| 21 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 22 | * Software Foundation. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 34 | * POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | #ifndef _MLXSW_PORT_H |
| 37 | #define _MLXSW_PORT_H |
| 38 | |
| 39 | #include <linux/types.h> |
| 40 | |
| 41 | #define MLXSW_PORT_MAX_MTU 10000 |
| 42 | |
| 43 | #define MLXSW_PORT_DEFAULT_VID 1 |
| 44 | |
Ido Schimmel | 4ec14b7 | 2015-07-29 23:33:48 +0200 | [diff] [blame] | 45 | #define MLXSW_PORT_SWID_DISABLED_PORT 255 |
| 46 | #define MLXSW_PORT_SWID_ALL_SWIDS 254 |
| 47 | #define MLXSW_PORT_SWID_TYPE_ETH 2 |
| 48 | |
| 49 | #define MLXSW_PORT_MID 0xd000 |
| 50 | |
Jiri Pirko | 93c1edb | 2015-07-29 23:33:46 +0200 | [diff] [blame] | 51 | #define MLXSW_PORT_MAX_PHY_PORTS 0x40 |
Ido Schimmel | 1e5ad30 | 2016-02-15 13:19:53 +0100 | [diff] [blame] | 52 | #define MLXSW_PORT_MAX_PORTS (MLXSW_PORT_MAX_PHY_PORTS + 1) |
Jiri Pirko | 93c1edb | 2015-07-29 23:33:46 +0200 | [diff] [blame] | 53 | |
Jiri Pirko | 31557f0 | 2015-07-29 23:33:49 +0200 | [diff] [blame] | 54 | #define MLXSW_PORT_DEVID_BITS_OFFSET 10 |
| 55 | #define MLXSW_PORT_PHY_BITS_OFFSET 4 |
| 56 | #define MLXSW_PORT_PHY_BITS_MASK (MLXSW_PORT_MAX_PHY_PORTS - 1) |
| 57 | |
Jiri Pirko | 93c1edb | 2015-07-29 23:33:46 +0200 | [diff] [blame] | 58 | #define MLXSW_PORT_CPU_PORT 0x0 |
| 59 | |
| 60 | #define MLXSW_PORT_DONT_CARE (MLXSW_PORT_MAX_PORTS) |
| 61 | |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 62 | #define MLXSW_PORT_MODULE_MAX_WIDTH 4 |
| 63 | |
Ido Schimmel | 4ec14b7 | 2015-07-29 23:33:48 +0200 | [diff] [blame] | 64 | enum mlxsw_port_admin_status { |
| 65 | MLXSW_PORT_ADMIN_STATUS_UP = 1, |
| 66 | MLXSW_PORT_ADMIN_STATUS_DOWN = 2, |
| 67 | MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3, |
| 68 | MLXSW_PORT_ADMIN_STATUS_DISABLED = 4, |
| 69 | }; |
| 70 | |
| 71 | enum mlxsw_reg_pude_oper_status { |
| 72 | MLXSW_PORT_OPER_STATUS_UP = 1, |
| 73 | MLXSW_PORT_OPER_STATUS_DOWN = 2, |
| 74 | MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */ |
| 75 | }; |
| 76 | |
Jiri Pirko | 93c1edb | 2015-07-29 23:33:46 +0200 | [diff] [blame] | 77 | #endif /* _MLXSW_PORT_H */ |