Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012-2013 Broadcom Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation version 2. |
| 7 | * |
| 8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 9 | * kind, whether express or implied; without even the implied warranty |
| 10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/bitops.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/gpio.h> |
| 18 | #include <linux/of_device.h> |
| 19 | #include <linux/of_irq.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/irqdomain.h> |
| 22 | #include <linux/irqchip/chained_irq.h> |
| 23 | |
| 24 | #define BCM_GPIO_PASSWD 0x00a5a501 |
| 25 | #define GPIO_PER_BANK 32 |
| 26 | #define GPIO_MAX_BANK_NUM 8 |
| 27 | |
| 28 | #define GPIO_BANK(gpio) ((gpio) >> 5) |
| 29 | #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) |
| 30 | |
Markus Mayer | d762bae | 2014-01-21 16:10:04 -0800 | [diff] [blame^] | 31 | /* There is a GPIO control register for each GPIO */ |
| 32 | #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2)) |
| 33 | |
| 34 | /* The remaining registers are per GPIO bank */ |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 35 | #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) |
| 36 | #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) |
| 37 | #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) |
| 38 | #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) |
| 39 | #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) |
| 40 | #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) |
| 41 | #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 42 | #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) |
| 43 | |
| 44 | #define GPIO_GPPWR_OFFSET 0x00000520 |
| 45 | |
| 46 | #define GPIO_GPCTR0_DBR_SHIFT 5 |
| 47 | #define GPIO_GPCTR0_DBR_MASK 0x000001e0 |
| 48 | |
| 49 | #define GPIO_GPCTR0_ITR_SHIFT 3 |
| 50 | #define GPIO_GPCTR0_ITR_MASK 0x00000018 |
| 51 | #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 |
| 52 | #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 |
| 53 | #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 |
| 54 | |
| 55 | #define GPIO_GPCTR0_IOTR_MASK 0x00000001 |
| 56 | #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 |
| 57 | #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 |
| 58 | |
| 59 | #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100 |
| 60 | |
| 61 | #define LOCK_CODE 0xffffffff |
| 62 | #define UNLOCK_CODE 0x00000000 |
| 63 | |
| 64 | struct bcm_kona_gpio { |
| 65 | void __iomem *reg_base; |
| 66 | int num_bank; |
| 67 | spinlock_t lock; |
| 68 | struct gpio_chip gpio_chip; |
| 69 | struct irq_domain *irq_domain; |
| 70 | struct bcm_kona_gpio_bank *banks; |
| 71 | struct platform_device *pdev; |
| 72 | }; |
| 73 | |
| 74 | struct bcm_kona_gpio_bank { |
| 75 | int id; |
| 76 | int irq; |
| 77 | /* Used in the interrupt handler */ |
| 78 | struct bcm_kona_gpio *kona_gpio; |
| 79 | }; |
| 80 | |
| 81 | static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip) |
| 82 | { |
| 83 | return container_of(chip, struct bcm_kona_gpio, gpio_chip); |
| 84 | } |
| 85 | |
| 86 | static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base, |
| 87 | int bank_id, int lockcode) |
| 88 | { |
| 89 | writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); |
| 90 | writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); |
| 91 | } |
| 92 | |
| 93 | static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id) |
| 94 | { |
| 95 | bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE); |
| 96 | } |
| 97 | |
| 98 | static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base, |
| 99 | int bank_id) |
| 100 | { |
| 101 | bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE); |
| 102 | } |
| 103 | |
| 104 | static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) |
| 105 | { |
| 106 | struct bcm_kona_gpio *kona_gpio; |
| 107 | void __iomem *reg_base; |
| 108 | int bank_id = GPIO_BANK(gpio); |
| 109 | int bit = GPIO_BIT(gpio); |
| 110 | u32 val, reg_offset; |
| 111 | unsigned long flags; |
| 112 | |
| 113 | kona_gpio = to_kona_gpio(chip); |
| 114 | reg_base = kona_gpio->reg_base; |
| 115 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 116 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 117 | |
| 118 | /* determine the GPIO pin direction */ |
| 119 | val = readl(reg_base + GPIO_CONTROL(gpio)); |
| 120 | val &= GPIO_GPCTR0_IOTR_MASK; |
| 121 | |
| 122 | /* this function only applies to output pin */ |
| 123 | if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) |
| 124 | goto out; |
| 125 | |
| 126 | reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); |
| 127 | |
| 128 | val = readl(reg_base + reg_offset); |
| 129 | val |= BIT(bit); |
| 130 | writel(val, reg_base + reg_offset); |
| 131 | |
| 132 | out: |
| 133 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 134 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 135 | } |
| 136 | |
| 137 | static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio) |
| 138 | { |
| 139 | struct bcm_kona_gpio *kona_gpio; |
| 140 | void __iomem *reg_base; |
| 141 | int bank_id = GPIO_BANK(gpio); |
| 142 | int bit = GPIO_BIT(gpio); |
| 143 | u32 val, reg_offset; |
| 144 | unsigned long flags; |
| 145 | |
| 146 | kona_gpio = to_kona_gpio(chip); |
| 147 | reg_base = kona_gpio->reg_base; |
| 148 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 149 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 150 | |
| 151 | /* determine the GPIO pin direction */ |
| 152 | val = readl(reg_base + GPIO_CONTROL(gpio)); |
| 153 | val &= GPIO_GPCTR0_IOTR_MASK; |
| 154 | |
| 155 | /* read the GPIO bank status */ |
| 156 | reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? |
| 157 | GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); |
| 158 | val = readl(reg_base + reg_offset); |
| 159 | |
| 160 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 161 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 162 | |
| 163 | /* return the specified bit status */ |
Markus Mayer | e2f0b00 | 2013-11-21 15:12:46 -0800 | [diff] [blame] | 164 | return !!(val & BIT(bit)); |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
| 168 | { |
| 169 | struct bcm_kona_gpio *kona_gpio; |
| 170 | void __iomem *reg_base; |
| 171 | u32 val; |
| 172 | unsigned long flags; |
| 173 | int bank_id = GPIO_BANK(gpio); |
| 174 | |
| 175 | kona_gpio = to_kona_gpio(chip); |
| 176 | reg_base = kona_gpio->reg_base; |
| 177 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 178 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 179 | |
| 180 | val = readl(reg_base + GPIO_CONTROL(gpio)); |
| 181 | val &= ~GPIO_GPCTR0_IOTR_MASK; |
| 182 | val |= GPIO_GPCTR0_IOTR_CMD_INPUT; |
| 183 | writel(val, reg_base + GPIO_CONTROL(gpio)); |
| 184 | |
| 185 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 186 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 187 | |
| 188 | return 0; |
| 189 | } |
| 190 | |
| 191 | static int bcm_kona_gpio_direction_output(struct gpio_chip *chip, |
| 192 | unsigned gpio, int value) |
| 193 | { |
| 194 | struct bcm_kona_gpio *kona_gpio; |
| 195 | void __iomem *reg_base; |
| 196 | int bank_id = GPIO_BANK(gpio); |
| 197 | int bit = GPIO_BIT(gpio); |
| 198 | u32 val, reg_offset; |
| 199 | unsigned long flags; |
| 200 | |
| 201 | kona_gpio = to_kona_gpio(chip); |
| 202 | reg_base = kona_gpio->reg_base; |
| 203 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 204 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 205 | |
| 206 | val = readl(reg_base + GPIO_CONTROL(gpio)); |
| 207 | val &= ~GPIO_GPCTR0_IOTR_MASK; |
| 208 | val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; |
| 209 | writel(val, reg_base + GPIO_CONTROL(gpio)); |
| 210 | reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); |
| 211 | |
| 212 | val = readl(reg_base + reg_offset); |
| 213 | val |= BIT(bit); |
| 214 | writel(val, reg_base + reg_offset); |
| 215 | |
| 216 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 217 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) |
| 223 | { |
| 224 | struct bcm_kona_gpio *kona_gpio; |
| 225 | |
| 226 | kona_gpio = to_kona_gpio(chip); |
| 227 | if (gpio >= kona_gpio->gpio_chip.ngpio) |
| 228 | return -ENXIO; |
| 229 | return irq_create_mapping(kona_gpio->irq_domain, gpio); |
| 230 | } |
| 231 | |
| 232 | static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio, |
| 233 | unsigned debounce) |
| 234 | { |
| 235 | struct bcm_kona_gpio *kona_gpio; |
| 236 | void __iomem *reg_base; |
| 237 | u32 val, res; |
| 238 | unsigned long flags; |
| 239 | int bank_id = GPIO_BANK(gpio); |
| 240 | |
| 241 | kona_gpio = to_kona_gpio(chip); |
| 242 | reg_base = kona_gpio->reg_base; |
| 243 | /* debounce must be 1-128ms (or 0) */ |
| 244 | if ((debounce > 0 && debounce < 1000) || debounce > 128000) { |
| 245 | dev_err(chip->dev, "Debounce value %u not in range\n", |
| 246 | debounce); |
| 247 | return -EINVAL; |
| 248 | } |
| 249 | |
| 250 | /* calculate debounce bit value */ |
| 251 | if (debounce != 0) { |
| 252 | /* Convert to ms */ |
| 253 | debounce /= 1000; |
| 254 | /* find the MSB */ |
| 255 | res = fls(debounce) - 1; |
| 256 | /* Check if MSB-1 is set (round up or down) */ |
| 257 | if (res > 0 && (debounce & BIT(res - 1))) |
| 258 | res++; |
| 259 | } |
| 260 | |
| 261 | /* spin lock for read-modify-write of the GPIO register */ |
| 262 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 263 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 264 | |
| 265 | val = readl(reg_base + GPIO_CONTROL(gpio)); |
| 266 | val &= ~GPIO_GPCTR0_DBR_MASK; |
| 267 | |
| 268 | if (debounce == 0) { |
| 269 | /* disable debounce */ |
| 270 | val &= ~GPIO_GPCTR0_DB_ENABLE_MASK; |
| 271 | } else { |
| 272 | val |= GPIO_GPCTR0_DB_ENABLE_MASK | |
| 273 | (res << GPIO_GPCTR0_DBR_SHIFT); |
| 274 | } |
| 275 | |
| 276 | writel(val, reg_base + GPIO_CONTROL(gpio)); |
| 277 | |
| 278 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 279 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 280 | |
| 281 | return 0; |
| 282 | } |
| 283 | |
| 284 | static struct gpio_chip template_chip = { |
| 285 | .label = "bcm-kona-gpio", |
Wei Yongjun | afb3690 | 2013-10-29 11:49:20 +0800 | [diff] [blame] | 286 | .owner = THIS_MODULE, |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 287 | .direction_input = bcm_kona_gpio_direction_input, |
| 288 | .get = bcm_kona_gpio_get, |
| 289 | .direction_output = bcm_kona_gpio_direction_output, |
| 290 | .set = bcm_kona_gpio_set, |
| 291 | .set_debounce = bcm_kona_gpio_set_debounce, |
| 292 | .to_irq = bcm_kona_gpio_to_irq, |
| 293 | .base = 0, |
| 294 | }; |
| 295 | |
| 296 | static void bcm_kona_gpio_irq_ack(struct irq_data *d) |
| 297 | { |
| 298 | struct bcm_kona_gpio *kona_gpio; |
| 299 | void __iomem *reg_base; |
| 300 | int gpio = d->hwirq; |
| 301 | int bank_id = GPIO_BANK(gpio); |
| 302 | int bit = GPIO_BIT(gpio); |
| 303 | u32 val; |
| 304 | unsigned long flags; |
| 305 | |
| 306 | kona_gpio = irq_data_get_irq_chip_data(d); |
| 307 | reg_base = kona_gpio->reg_base; |
| 308 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 309 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 310 | |
| 311 | val = readl(reg_base + GPIO_INT_STATUS(bank_id)); |
| 312 | val |= BIT(bit); |
| 313 | writel(val, reg_base + GPIO_INT_STATUS(bank_id)); |
| 314 | |
| 315 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 316 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 317 | } |
| 318 | |
| 319 | static void bcm_kona_gpio_irq_mask(struct irq_data *d) |
| 320 | { |
| 321 | struct bcm_kona_gpio *kona_gpio; |
| 322 | void __iomem *reg_base; |
| 323 | int gpio = d->hwirq; |
| 324 | int bank_id = GPIO_BANK(gpio); |
| 325 | int bit = GPIO_BIT(gpio); |
| 326 | u32 val; |
| 327 | unsigned long flags; |
| 328 | |
| 329 | kona_gpio = irq_data_get_irq_chip_data(d); |
| 330 | reg_base = kona_gpio->reg_base; |
| 331 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 332 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 333 | |
| 334 | val = readl(reg_base + GPIO_INT_MASK(bank_id)); |
| 335 | val |= BIT(bit); |
| 336 | writel(val, reg_base + GPIO_INT_MASK(bank_id)); |
| 337 | |
| 338 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 339 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 340 | } |
| 341 | |
| 342 | static void bcm_kona_gpio_irq_unmask(struct irq_data *d) |
| 343 | { |
| 344 | struct bcm_kona_gpio *kona_gpio; |
| 345 | void __iomem *reg_base; |
| 346 | int gpio = d->hwirq; |
| 347 | int bank_id = GPIO_BANK(gpio); |
| 348 | int bit = GPIO_BIT(gpio); |
| 349 | u32 val; |
| 350 | unsigned long flags; |
| 351 | |
| 352 | kona_gpio = irq_data_get_irq_chip_data(d); |
| 353 | reg_base = kona_gpio->reg_base; |
| 354 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 355 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 356 | |
| 357 | val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); |
| 358 | val |= BIT(bit); |
| 359 | writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); |
| 360 | |
| 361 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 362 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 363 | } |
| 364 | |
| 365 | static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
| 366 | { |
| 367 | struct bcm_kona_gpio *kona_gpio; |
| 368 | void __iomem *reg_base; |
| 369 | int gpio = d->hwirq; |
| 370 | u32 lvl_type; |
| 371 | u32 val; |
| 372 | unsigned long flags; |
| 373 | int bank_id = GPIO_BANK(gpio); |
| 374 | |
| 375 | kona_gpio = irq_data_get_irq_chip_data(d); |
| 376 | reg_base = kona_gpio->reg_base; |
| 377 | switch (type & IRQ_TYPE_SENSE_MASK) { |
| 378 | case IRQ_TYPE_EDGE_RISING: |
| 379 | lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE; |
| 380 | break; |
| 381 | |
| 382 | case IRQ_TYPE_EDGE_FALLING: |
| 383 | lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE; |
| 384 | break; |
| 385 | |
| 386 | case IRQ_TYPE_EDGE_BOTH: |
| 387 | lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE; |
| 388 | break; |
| 389 | |
| 390 | case IRQ_TYPE_LEVEL_HIGH: |
| 391 | case IRQ_TYPE_LEVEL_LOW: |
| 392 | /* BCM GPIO doesn't support level triggering */ |
| 393 | default: |
| 394 | dev_err(kona_gpio->gpio_chip.dev, |
| 395 | "Invalid BCM GPIO irq type 0x%x\n", type); |
| 396 | return -EINVAL; |
| 397 | } |
| 398 | |
| 399 | spin_lock_irqsave(&kona_gpio->lock, flags); |
| 400 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 401 | |
| 402 | val = readl(reg_base + GPIO_CONTROL(gpio)); |
| 403 | val &= ~GPIO_GPCTR0_ITR_MASK; |
| 404 | val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT; |
| 405 | writel(val, reg_base + GPIO_CONTROL(gpio)); |
| 406 | |
| 407 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 408 | spin_unlock_irqrestore(&kona_gpio->lock, flags); |
| 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
| 413 | static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 414 | { |
| 415 | void __iomem *reg_base; |
| 416 | int bit, bank_id; |
| 417 | unsigned long sta; |
| 418 | struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq); |
| 419 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 420 | |
| 421 | chained_irq_enter(chip, desc); |
| 422 | |
| 423 | /* |
| 424 | * For bank interrupts, we can't use chip_data to store the kona_gpio |
| 425 | * pointer, since GIC needs it for its own purposes. Therefore, we get |
| 426 | * our pointer from the bank structure. |
| 427 | */ |
| 428 | reg_base = bank->kona_gpio->reg_base; |
| 429 | bank_id = bank->id; |
| 430 | bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
| 431 | |
| 432 | while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) & |
| 433 | (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) { |
| 434 | for_each_set_bit(bit, &sta, 32) { |
Linus Walleij | d933cc6 | 2013-10-11 19:14:50 +0200 | [diff] [blame] | 435 | int hwirq = GPIO_PER_BANK * bank_id + bit; |
| 436 | int child_irq = |
| 437 | irq_find_mapping(bank->kona_gpio->irq_domain, |
| 438 | hwirq); |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 439 | /* |
| 440 | * Clear interrupt before handler is called so we don't |
| 441 | * miss any interrupt occurred during executing them. |
| 442 | */ |
| 443 | writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) | |
| 444 | BIT(bit), reg_base + GPIO_INT_STATUS(bank_id)); |
| 445 | /* Invoke interrupt handler */ |
Linus Walleij | d933cc6 | 2013-10-11 19:14:50 +0200 | [diff] [blame] | 446 | generic_handle_irq(child_irq); |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 447 | } |
| 448 | } |
| 449 | |
| 450 | bcm_kona_gpio_lock_bank(reg_base, bank_id); |
| 451 | |
| 452 | chained_irq_exit(chip, desc); |
| 453 | } |
| 454 | |
Linus Walleij | db6b3ad | 2013-11-19 14:14:50 +0100 | [diff] [blame] | 455 | static unsigned int bcm_kona_gpio_irq_startup(struct irq_data *d) |
| 456 | { |
| 457 | struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); |
| 458 | |
| 459 | if (gpio_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) |
| 460 | dev_err(kona_gpio->gpio_chip.dev, |
| 461 | "unable to lock HW IRQ %lu for IRQ\n", |
| 462 | d->hwirq); |
| 463 | bcm_kona_gpio_irq_unmask(d); |
| 464 | return 0; |
| 465 | } |
| 466 | |
| 467 | static void bcm_kona_gpio_irq_shutdown(struct irq_data *d) |
| 468 | { |
| 469 | struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); |
| 470 | |
| 471 | bcm_kona_gpio_irq_mask(d); |
| 472 | gpio_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq); |
| 473 | } |
| 474 | |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 475 | static struct irq_chip bcm_gpio_irq_chip = { |
| 476 | .name = "bcm-kona-gpio", |
| 477 | .irq_ack = bcm_kona_gpio_irq_ack, |
| 478 | .irq_mask = bcm_kona_gpio_irq_mask, |
| 479 | .irq_unmask = bcm_kona_gpio_irq_unmask, |
| 480 | .irq_set_type = bcm_kona_gpio_irq_set_type, |
Linus Walleij | db6b3ad | 2013-11-19 14:14:50 +0100 | [diff] [blame] | 481 | .irq_startup = bcm_kona_gpio_irq_startup, |
| 482 | .irq_shutdown = bcm_kona_gpio_irq_shutdown, |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 483 | }; |
| 484 | |
| 485 | static struct __initconst of_device_id bcm_kona_gpio_of_match[] = { |
| 486 | { .compatible = "brcm,kona-gpio" }, |
| 487 | {} |
| 488 | }; |
| 489 | |
| 490 | MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match); |
| 491 | |
| 492 | /* |
| 493 | * This lock class tells lockdep that GPIO irqs are in a different |
| 494 | * category than their parents, so it won't report false recursion. |
| 495 | */ |
| 496 | static struct lock_class_key gpio_lock_class; |
| 497 | |
Linus Walleij | 1dc9427 | 2013-09-20 23:14:18 +0200 | [diff] [blame] | 498 | static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 499 | irq_hw_number_t hwirq) |
| 500 | { |
| 501 | int ret; |
| 502 | |
Linus Walleij | 1dc9427 | 2013-09-20 23:14:18 +0200 | [diff] [blame] | 503 | ret = irq_set_chip_data(irq, d->host_data); |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 504 | if (ret < 0) |
| 505 | return ret; |
Linus Walleij | 1dc9427 | 2013-09-20 23:14:18 +0200 | [diff] [blame] | 506 | irq_set_lockdep_class(irq, &gpio_lock_class); |
| 507 | irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq); |
Linus Walleij | 1dc9427 | 2013-09-20 23:14:18 +0200 | [diff] [blame] | 508 | #ifdef CONFIG_ARM |
| 509 | set_irq_flags(irq, IRQF_VALID); |
| 510 | #else |
| 511 | irq_set_noprobe(irq); |
| 512 | #endif |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
Linus Walleij | d933cc6 | 2013-10-11 19:14:50 +0200 | [diff] [blame] | 517 | static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 518 | { |
Linus Walleij | d933cc6 | 2013-10-11 19:14:50 +0200 | [diff] [blame] | 519 | irq_set_chip_and_handler(irq, NULL, NULL); |
| 520 | irq_set_chip_data(irq, NULL); |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 521 | } |
| 522 | |
| 523 | static struct irq_domain_ops bcm_kona_irq_ops = { |
| 524 | .map = bcm_kona_gpio_irq_map, |
| 525 | .unmap = bcm_kona_gpio_irq_unmap, |
| 526 | .xlate = irq_domain_xlate_twocell, |
| 527 | }; |
| 528 | |
| 529 | static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio) |
| 530 | { |
| 531 | void __iomem *reg_base; |
| 532 | int i; |
| 533 | |
| 534 | reg_base = kona_gpio->reg_base; |
| 535 | /* disable interrupts and clear status */ |
| 536 | for (i = 0; i < kona_gpio->num_bank; i++) { |
| 537 | bcm_kona_gpio_unlock_bank(reg_base, i); |
| 538 | writel(0xffffffff, reg_base + GPIO_INT_MASK(i)); |
| 539 | writel(0xffffffff, reg_base + GPIO_INT_STATUS(i)); |
| 540 | bcm_kona_gpio_lock_bank(reg_base, i); |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | static int bcm_kona_gpio_probe(struct platform_device *pdev) |
| 545 | { |
| 546 | struct device *dev = &pdev->dev; |
| 547 | const struct of_device_id *match; |
| 548 | struct resource *res; |
| 549 | struct bcm_kona_gpio_bank *bank; |
| 550 | struct bcm_kona_gpio *kona_gpio; |
| 551 | struct gpio_chip *chip; |
| 552 | int ret; |
| 553 | int i; |
| 554 | |
| 555 | match = of_match_device(bcm_kona_gpio_of_match, dev); |
| 556 | if (!match) { |
| 557 | dev_err(dev, "Failed to find gpio controller\n"); |
| 558 | return -ENODEV; |
| 559 | } |
| 560 | |
| 561 | kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL); |
| 562 | if (!kona_gpio) |
| 563 | return -ENOMEM; |
| 564 | |
| 565 | kona_gpio->gpio_chip = template_chip; |
| 566 | chip = &kona_gpio->gpio_chip; |
| 567 | kona_gpio->num_bank = of_irq_count(dev->of_node); |
| 568 | if (kona_gpio->num_bank == 0) { |
| 569 | dev_err(dev, "Couldn't determine # GPIO banks\n"); |
| 570 | return -ENOENT; |
| 571 | } |
| 572 | if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) { |
| 573 | dev_err(dev, "Too many GPIO banks configured (max=%d)\n", |
| 574 | GPIO_MAX_BANK_NUM); |
| 575 | return -ENXIO; |
| 576 | } |
| 577 | kona_gpio->banks = devm_kzalloc(dev, |
| 578 | kona_gpio->num_bank * |
| 579 | sizeof(*kona_gpio->banks), GFP_KERNEL); |
| 580 | if (!kona_gpio->banks) |
| 581 | return -ENOMEM; |
| 582 | |
| 583 | kona_gpio->pdev = pdev; |
| 584 | platform_set_drvdata(pdev, kona_gpio); |
| 585 | chip->of_node = dev->of_node; |
| 586 | chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK; |
| 587 | |
| 588 | kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node, |
| 589 | chip->ngpio, |
| 590 | &bcm_kona_irq_ops, |
| 591 | kona_gpio); |
| 592 | if (!kona_gpio->irq_domain) { |
| 593 | dev_err(dev, "Couldn't allocate IRQ domain\n"); |
| 594 | return -ENXIO; |
| 595 | } |
| 596 | |
| 597 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 598 | kona_gpio->reg_base = devm_ioremap_resource(dev, res); |
| 599 | if (IS_ERR(kona_gpio->reg_base)) { |
| 600 | ret = -ENXIO; |
| 601 | goto err_irq_domain; |
| 602 | } |
| 603 | |
| 604 | for (i = 0; i < kona_gpio->num_bank; i++) { |
| 605 | bank = &kona_gpio->banks[i]; |
| 606 | bank->id = i; |
| 607 | bank->irq = platform_get_irq(pdev, i); |
| 608 | bank->kona_gpio = kona_gpio; |
| 609 | if (bank->irq < 0) { |
| 610 | dev_err(dev, "Couldn't get IRQ for bank %d", i); |
| 611 | ret = -ENOENT; |
| 612 | goto err_irq_domain; |
| 613 | } |
| 614 | } |
| 615 | |
Markus Mayer | 23b4faa | 2013-10-18 11:50:03 -0700 | [diff] [blame] | 616 | dev_info(&pdev->dev, "Setting up Kona GPIO\n"); |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 617 | |
| 618 | bcm_kona_gpio_reset(kona_gpio); |
| 619 | |
| 620 | ret = gpiochip_add(chip); |
| 621 | if (ret < 0) { |
| 622 | dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret); |
| 623 | goto err_irq_domain; |
| 624 | } |
| 625 | for (i = 0; i < chip->ngpio; i++) { |
| 626 | int irq = bcm_kona_gpio_to_irq(chip, i); |
| 627 | irq_set_lockdep_class(irq, &gpio_lock_class); |
| 628 | irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, |
| 629 | handle_simple_irq); |
Linus Walleij | 1dc9427 | 2013-09-20 23:14:18 +0200 | [diff] [blame] | 630 | #ifdef CONFIG_ARM |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 631 | set_irq_flags(irq, IRQF_VALID); |
Linus Walleij | 1dc9427 | 2013-09-20 23:14:18 +0200 | [diff] [blame] | 632 | #else |
| 633 | irq_set_noprobe(irq); |
| 634 | #endif |
Markus Mayer | 757651e | 2013-09-10 11:07:01 -0700 | [diff] [blame] | 635 | } |
| 636 | for (i = 0; i < kona_gpio->num_bank; i++) { |
| 637 | bank = &kona_gpio->banks[i]; |
| 638 | irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler); |
| 639 | irq_set_handler_data(bank->irq, bank); |
| 640 | } |
| 641 | |
| 642 | spin_lock_init(&kona_gpio->lock); |
| 643 | |
| 644 | return 0; |
| 645 | |
| 646 | err_irq_domain: |
| 647 | irq_domain_remove(kona_gpio->irq_domain); |
| 648 | |
| 649 | return ret; |
| 650 | } |
| 651 | |
| 652 | static struct platform_driver bcm_kona_gpio_driver = { |
| 653 | .driver = { |
| 654 | .name = "bcm-kona-gpio", |
| 655 | .owner = THIS_MODULE, |
| 656 | .of_match_table = bcm_kona_gpio_of_match, |
| 657 | }, |
| 658 | .probe = bcm_kona_gpio_probe, |
| 659 | }; |
| 660 | |
| 661 | module_platform_driver(bcm_kona_gpio_driver); |
| 662 | |
| 663 | MODULE_AUTHOR("Broadcom"); |
| 664 | MODULE_DESCRIPTION("Broadcom Kona GPIO Driver"); |
| 665 | MODULE_LICENSE("GPL v2"); |