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Auke Kokbc7f75f2007-09-17 12:30:59 -07001/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
Bruce Allanf5e261e2012-01-01 16:00:03 +00004 Copyright(c) 1999 - 2012 Intel Corporation.
Auke Kokbc7f75f2007-09-17 12:30:59 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
Jeff Kirsher86d70e52011-03-25 16:01:01 +000034#include <linux/bitops.h>
Auke Kokbc7f75f2007-09-17 12:30:59 -070035#include <linux/types.h>
36#include <linux/timer.h>
37#include <linux/workqueue.h>
38#include <linux/io.h>
39#include <linux/netdevice.h>
Bruce Alland8014db2009-11-20 23:24:48 +000040#include <linux/pci.h>
Bruce Allan6f461f62010-04-27 03:33:04 +000041#include <linux/pci-aspm.h>
Bruce Allanfe46f582011-01-06 14:29:51 +000042#include <linux/crc32.h>
Jeff Kirsher86d70e52011-03-25 16:01:01 +000043#include <linux/if_vlan.h>
Auke Kokbc7f75f2007-09-17 12:30:59 -070044
45#include "hw.h"
46
47struct e1000_info;
48
Jeff Kirsher44defeb2008-08-04 17:20:41 -070049#define e_dbg(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000050 netdev_dbg(hw->adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070051#define e_err(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000052 netdev_err(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070053#define e_info(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000054 netdev_info(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070055#define e_warn(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000056 netdev_warn(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070057#define e_notice(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000058 netdev_notice(adapter->netdev, format, ## arg)
Auke Kokbc7f75f2007-09-17 12:30:59 -070059
60
Martin Olsson98a17082009-04-22 18:21:29 +020061/* Interrupt modes, as used by the IntMode parameter */
Bruce Allan4662e822008-08-26 18:37:06 -070062#define E1000E_INT_MODE_LEGACY 0
63#define E1000E_INT_MODE_MSI 1
64#define E1000E_INT_MODE_MSIX 2
65
Bruce Allanad680762008-03-28 09:15:03 -070066/* Tx/Rx descriptor defines */
Auke Kokbc7f75f2007-09-17 12:30:59 -070067#define E1000_DEFAULT_TXD 256
68#define E1000_MAX_TXD 4096
Auke Kok7b1be192008-04-23 11:09:19 -070069#define E1000_MIN_TXD 64
Auke Kokbc7f75f2007-09-17 12:30:59 -070070
71#define E1000_DEFAULT_RXD 256
72#define E1000_MAX_RXD 4096
Auke Kok7b1be192008-04-23 11:09:19 -070073#define E1000_MIN_RXD 64
Auke Kokbc7f75f2007-09-17 12:30:59 -070074
Auke Kokde5b3072008-04-23 11:09:08 -070075#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
76#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
77
Auke Kokbc7f75f2007-09-17 12:30:59 -070078/* Early Receive defines */
79#define E1000_ERT_2048 0x100
80
81#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
82
83/* How many Tx Descriptors do we need to call netif_wake_queue ? */
84/* How many Rx Buffers do we bundle into one write to the hardware ? */
85#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
86
87#define AUTO_ALL_MODES 0
88#define E1000_EEPROM_APME 0x0400
89
90#define E1000_MNG_VLAN_NONE (-1)
91
92/* Number of packet split data buffers (not including the header buffer) */
93#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
94
Bruce Allan2adc55c2009-06-02 11:28:58 +000095#define DEFAULT_JUMBO 9234
96
Bruce Allana4f58f52009-06-02 11:29:18 +000097/* BM/HV Specific Registers */
98#define BM_PORT_CTRL_PAGE 769
99
100#define PHY_UPPER_SHIFT 21
101#define BM_PHY_REG(page, reg) \
102 (((reg) & MAX_PHY_REG_ADDRESS) |\
103 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
104 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
105
106/* PHY Wakeup Registers and defines */
Bruce Allan3ebfc7c2011-05-13 07:20:14 +0000107#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
Bruce Allana4f58f52009-06-02 11:29:18 +0000108#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
109#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
110#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
111#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
112#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
113#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
114#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
115#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
116#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
117
118#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
119#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
120#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
121#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
122#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
123#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
124#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
125
Bruce Allan2b6b1682011-05-13 07:20:09 +0000126#define HV_STATS_PAGE 778
127#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
128#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
129#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
130#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
131#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
132#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
133#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
134#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
135#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
136#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
137#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
138#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
139#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
140#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
Bruce Allana4f58f52009-06-02 11:29:18 +0000141
Bruce Allan38eb3942009-11-19 12:34:20 +0000142#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
143
Bruce Allan1d5846b2009-10-29 13:46:05 +0000144/* BM PHY Copper Specific Status */
145#define BM_CS_STATUS 17
146#define BM_CS_STATUS_LINK_UP 0x0400
147#define BM_CS_STATUS_RESOLVED 0x0800
148#define BM_CS_STATUS_SPEED_MASK 0xC000
149#define BM_CS_STATUS_SPEED_1000 0x8000
150
151/* 82577 Mobile Phy Status Register */
152#define HV_M_STATUS 26
153#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
154#define HV_M_STATUS_SPEED_MASK 0x0300
155#define HV_M_STATUS_SPEED_1000 0x0200
156#define HV_M_STATUS_LINK_UP 0x0040
157
Bruce Allanc6e7f512011-07-29 05:53:02 +0000158#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
159#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
160
Rafael J. Wysocki23606cf2010-03-14 14:35:17 +0000161/* Time to wait before putting the device into D3 if there's no link (in ms). */
162#define LINK_TIMEOUT 100
163
Bruce Allanbb9e44d2012-03-21 00:39:12 +0000164/*
165 * Count for polling __E1000_RESET condition every 10-20msec.
166 * Experimentation has shown the reset can take approximately 210msec.
167 */
168#define E1000_CHECK_RESET_COUNT 25
169
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000170#define DEFAULT_RDTR 0
171#define DEFAULT_RADV 8
172#define BURST_RDTR 0x20
173#define BURST_RADV 0x20
174
175/*
176 * in the case of WTHRESH, it appears at least the 82571/2 hardware
177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
178 * WTHRESH=4, and since we want 64 bytes at a time written back, set
179 * it to 5
180 */
181#define E1000_TXDCTL_DMA_BURST_ENABLE \
182 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
183 E1000_TXDCTL_COUNT_DESC | \
184 (5 << 16) | /* wthresh must be +1 more than desired */\
185 (1 << 8) | /* hthresh */ \
186 0x1f) /* pthresh */
187
188#define E1000_RXDCTL_DMA_BURST_ENABLE \
189 (0x01000000 | /* set descriptor granularity */ \
190 (4 << 16) | /* set writeback threshold */ \
191 (4 << 8) | /* set prefetch threshold */ \
192 0x20) /* set hthresh */
193
194#define E1000_TIDV_FPD (1 << 31)
195#define E1000_RDTR_FPD (1 << 31)
196
Auke Kokbc7f75f2007-09-17 12:30:59 -0700197enum e1000_boards {
198 board_82571,
199 board_82572,
200 board_82573,
Bruce Allan4662e822008-08-26 18:37:06 -0700201 board_82574,
Alexander Duyck8c81c9c2009-03-19 01:12:27 +0000202 board_82583,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700203 board_80003es2lan,
204 board_ich8lan,
205 board_ich9lan,
Bruce Allanf4187b52008-08-26 18:36:50 -0700206 board_ich10lan,
Bruce Allana4f58f52009-06-02 11:29:18 +0000207 board_pchlan,
Bruce Alland3738bb2010-06-16 13:27:28 +0000208 board_pch2lan,
Bruce Allan2fbe4522012-04-19 03:21:47 +0000209 board_pch_lpt,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700210};
211
Auke Kokbc7f75f2007-09-17 12:30:59 -0700212struct e1000_ps_page {
213 struct page *page;
214 u64 dma; /* must be u64 - written to hw */
215};
216
217/*
218 * wrappers around a pointer to a socket buffer,
219 * so a DMA handle can be stored along with the buffer
220 */
221struct e1000_buffer {
222 dma_addr_t dma;
223 struct sk_buff *skb;
224 union {
Bruce Allanad680762008-03-28 09:15:03 -0700225 /* Tx */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700226 struct {
227 unsigned long time_stamp;
228 u16 length;
229 u16 next_to_watch;
Tom Herbert9ed318d2010-05-05 14:02:27 +0000230 unsigned int segs;
231 unsigned int bytecount;
Alexander Duyck03b13202009-12-02 16:45:31 +0000232 u16 mapped_as_page;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700233 };
Bruce Allanad680762008-03-28 09:15:03 -0700234 /* Rx */
Alexander Duyck03b13202009-12-02 16:45:31 +0000235 struct {
236 /* arrays of page information for packet split */
237 struct e1000_ps_page *ps_pages;
238 struct page *page;
239 };
Auke Kokbc7f75f2007-09-17 12:30:59 -0700240 };
Auke Kokbc7f75f2007-09-17 12:30:59 -0700241};
242
243struct e1000_ring {
Bruce Allan55aa6982011-12-16 00:45:45 +0000244 struct e1000_adapter *adapter; /* back pointer to adapter */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700245 void *desc; /* pointer to ring memory */
246 dma_addr_t dma; /* phys address of ring */
247 unsigned int size; /* length of ring in bytes */
248 unsigned int count; /* number of desc. in ring */
249
250 u16 next_to_use;
251 u16 next_to_clean;
252
Bruce Allanc5083cf2011-12-16 00:45:40 +0000253 void __iomem *head;
254 void __iomem *tail;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700255
256 /* array of buffer information structs */
257 struct e1000_buffer *buffer_info;
258
Bruce Allan4662e822008-08-26 18:37:06 -0700259 char name[IFNAMSIZ + 5];
260 u32 ims_val;
261 u32 itr_val;
Bruce Allanc5083cf2011-12-16 00:45:40 +0000262 void __iomem *itr_register;
Bruce Allan4662e822008-08-26 18:37:06 -0700263 int set_itr;
264
Auke Kokbc7f75f2007-09-17 12:30:59 -0700265 struct sk_buff *rx_skb_top;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700266};
267
Bruce Allan7c257692008-04-23 11:09:00 -0700268/* PHY register snapshot values */
269struct e1000_phy_regs {
270 u16 bmcr; /* basic mode control register */
271 u16 bmsr; /* basic mode status register */
272 u16 advertise; /* auto-negotiation advertisement */
273 u16 lpa; /* link partner ability register */
274 u16 expansion; /* auto-negotiation expansion reg */
275 u16 ctrl1000; /* 1000BASE-T control register */
276 u16 stat1000; /* 1000BASE-T status register */
277 u16 estatus; /* extended status register */
278};
279
Auke Kokbc7f75f2007-09-17 12:30:59 -0700280/* board specific private data structure */
281struct e1000_adapter {
282 struct timer_list watchdog_timer;
283 struct timer_list phy_info_timer;
284 struct timer_list blink_timer;
285
286 struct work_struct reset_task;
287 struct work_struct watchdog_task;
288
289 const struct e1000_info *ei;
290
Jeff Kirsher86d70e52011-03-25 16:01:01 +0000291 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
Auke Kokbc7f75f2007-09-17 12:30:59 -0700292 u32 bd_number;
293 u32 rx_buffer_len;
294 u16 mng_vlan_id;
295 u16 link_speed;
296 u16 link_duplex;
Bruce Allan84527592008-11-21 17:00:22 -0800297 u16 eeprom_vers;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700298
Auke Kokbc7f75f2007-09-17 12:30:59 -0700299 /* track device up/down/testing state */
300 unsigned long state;
301
302 /* Interrupt Throttle Rate */
303 u32 itr;
304 u32 itr_setting;
305 u16 tx_itr;
306 u16 rx_itr;
307
308 /*
Bruce Allanad680762008-03-28 09:15:03 -0700309 * Tx
Auke Kokbc7f75f2007-09-17 12:30:59 -0700310 */
311 struct e1000_ring *tx_ring /* One per active queue */
312 ____cacheline_aligned_in_smp;
Bruce Alland821a4c2012-08-24 20:38:11 +0000313 u32 tx_fifo_limit;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700314
315 struct napi_struct napi;
316
Auke Kokbc7f75f2007-09-17 12:30:59 -0700317 unsigned int restart_queue;
318 u32 txd_cmd;
319
320 bool detect_tx_hung;
Jeff Kirsher09357b02011-11-18 14:25:00 +0000321 bool tx_hang_recheck;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700322 u8 tx_timeout_factor;
323
324 u32 tx_int_delay;
325 u32 tx_abs_int_delay;
326
327 unsigned int total_tx_bytes;
328 unsigned int total_tx_packets;
329 unsigned int total_rx_bytes;
330 unsigned int total_rx_packets;
331
Bruce Allanad680762008-03-28 09:15:03 -0700332 /* Tx stats */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700333 u64 tpt_old;
334 u64 colc_old;
Bruce Allan7c257692008-04-23 11:09:00 -0700335 u32 gotc;
336 u64 gotc_old;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700337 u32 tx_timeout_count;
338 u32 tx_fifo_head;
339 u32 tx_head_addr;
340 u32 tx_fifo_size;
341 u32 tx_dma_failed;
342
343 /*
Bruce Allanad680762008-03-28 09:15:03 -0700344 * Rx
Auke Kokbc7f75f2007-09-17 12:30:59 -0700345 */
Bruce Allan55aa6982011-12-16 00:45:45 +0000346 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
347 int work_to_do) ____cacheline_aligned_in_smp;
348 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
349 gfp_t gfp);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700350 struct e1000_ring *rx_ring;
351
352 u32 rx_int_delay;
353 u32 rx_abs_int_delay;
354
Bruce Allanad680762008-03-28 09:15:03 -0700355 /* Rx stats */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700356 u64 hw_csum_err;
357 u64 hw_csum_good;
358 u64 rx_hdr_split;
Bruce Allan7c257692008-04-23 11:09:00 -0700359 u32 gorc;
360 u64 gorc_old;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700361 u32 alloc_rx_buff_failed;
362 u32 rx_dma_failed;
363
364 unsigned int rx_ps_pages;
365 u16 rx_ps_bsize0;
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700366 u32 max_frame_size;
367 u32 min_frame_size;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700368
369 /* OS defined structs */
370 struct net_device *netdev;
371 struct pci_dev *pdev;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700372
373 /* structs defined in e1000_hw.h */
374 struct e1000_hw hw;
375
Jeff Kirsher67fd4fc2011-01-07 05:12:09 +0000376 spinlock_t stats64_lock;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700377 struct e1000_hw_stats stats;
378 struct e1000_phy_info phy_info;
379 struct e1000_phy_stats phy_stats;
380
Bruce Allan7c257692008-04-23 11:09:00 -0700381 /* Snapshot of PHY registers */
382 struct e1000_phy_regs phy_regs;
383
Auke Kokbc7f75f2007-09-17 12:30:59 -0700384 struct e1000_ring test_tx_ring;
385 struct e1000_ring test_rx_ring;
386 u32 test_icr;
387
388 u32 msg_enable;
Jeff Kirsher8e86acd2010-08-02 14:27:23 +0000389 unsigned int num_vectors;
Bruce Allan4662e822008-08-26 18:37:06 -0700390 struct msix_entry *msix_entries;
391 int int_mode;
392 u32 eiac_mask;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700393
394 u32 eeprom_wol;
395 u32 wol;
396 u32 pba;
Bruce Allan2adc55c2009-06-02 11:28:58 +0000397 u32 max_hw_frame_size;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700398
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700399 bool fc_autoneg;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700400
Auke Kokbc7f75f2007-09-17 12:30:59 -0700401 unsigned int flags;
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000402 unsigned int flags2;
Jesse Brandeburga8f88ff2008-10-02 16:33:25 -0700403 struct work_struct downshift_task;
404 struct work_struct update_phy_task;
Bruce Allan41cec6f2009-11-20 23:28:56 +0000405 struct work_struct print_hang_task;
Rafael J. Wysocki23606cf2010-03-14 14:35:17 +0000406
407 bool idle_check;
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000408 int phy_hang_count;
Bruce Allan55aa6982011-12-16 00:45:45 +0000409
410 u16 tx_ring_count;
411 u16 rx_ring_count;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700412};
413
414struct e1000_info {
415 enum e1000_mac_type mac;
416 unsigned int flags;
Bruce Allan6f461f62010-04-27 03:33:04 +0000417 unsigned int flags2;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700418 u32 pba;
Bruce Allan2adc55c2009-06-02 11:28:58 +0000419 u32 max_hw_frame_size;
Jeff Kirsher69e3fd82008-04-02 13:48:18 -0700420 s32 (*get_variants)(struct e1000_adapter *);
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +0000421 const struct e1000_mac_operations *mac_ops;
422 const struct e1000_phy_operations *phy_ops;
423 const struct e1000_nvm_operations *nvm_ops;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700424};
425
426/* hardware capability, feature, and workaround flags */
427#define FLAG_HAS_AMT (1 << 0)
428#define FLAG_HAS_FLASH (1 << 1)
429#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
430#define FLAG_HAS_WOL (1 << 3)
Bruce Allan79d4e902011-12-16 00:46:27 +0000431/* reserved bit4 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700432#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
433#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
434#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
Bruce Allan4a770352008-10-01 17:18:35 -0700435#define FLAG_READ_ONLY_NVM (1 << 8)
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700436#define FLAG_IS_ICH (1 << 9)
Bruce Allan4662e822008-08-26 18:37:06 -0700437#define FLAG_HAS_MSIX (1 << 10)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700438#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
439#define FLAG_IS_QUAD_PORT_A (1 << 12)
440#define FLAG_IS_QUAD_PORT (1 << 13)
Bruce Allan6a92f732011-12-16 00:46:12 +0000441/* reserved bit14 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700442#define FLAG_APME_IN_WUC (1 << 15)
443#define FLAG_APME_IN_CTRL3 (1 << 16)
444#define FLAG_APME_CHECK_PORT_B (1 << 17)
445#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
446#define FLAG_NO_WAKE_UCAST (1 << 19)
447#define FLAG_MNG_PT_ENABLED (1 << 20)
448#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
449#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
450#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
451#define FLAG_RX_NEEDS_RESTART (1 << 24)
452#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
453#define FLAG_SMART_POWER_DOWN (1 << 26)
454#define FLAG_MSI_ENABLED (1 << 27)
Bruce Allandc221292011-08-19 03:23:48 +0000455/* reserved (1 << 28) */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700456#define FLAG_TSO_FORCE (1 << 29)
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700457#define FLAG_RX_RESTART_NOW (1 << 30)
Bruce Allanf8d59f72008-08-08 18:36:11 -0700458#define FLAG_MSI_TEST_FAILED (1 << 31)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700459
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000460#define FLAG2_CRC_STRIPPING (1 << 0)
Bruce Allana4f58f52009-06-02 11:29:18 +0000461#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
Jesse Brandeburgb94b5022010-01-19 14:15:59 +0000462#define FLAG2_IS_DISCARDING (1 << 2)
Bruce Allan6f461f62010-04-27 03:33:04 +0000463#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
Bruce Allan8c7bbb92010-06-16 13:26:41 +0000464#define FLAG2_HAS_PHY_STATS (1 << 4)
Bruce Allane52997f2010-06-16 13:27:49 +0000465#define FLAG2_HAS_EEE (1 << 5)
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000466#define FLAG2_DMA_BURST (1 << 6)
Bruce Allan78cd29d2011-03-24 03:09:03 +0000467#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
Bruce Allan828bac82010-09-29 21:39:37 +0000468#define FLAG2_DISABLE_AIM (1 << 8)
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000469#define FLAG2_CHECK_PHY_HANG (1 << 9)
Bruce Allan7f99ae62011-07-22 06:21:35 +0000470#define FLAG2_NO_DISABLE_RX (1 << 10)
Bruce Allanc6e7f512011-07-29 05:53:02 +0000471#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
Ben Greear01840392012-02-11 15:39:25 +0000472#define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000473
Auke Kokbc7f75f2007-09-17 12:30:59 -0700474#define E1000_RX_DESC_PS(R, i) \
475 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
Bruce Allan5f450212011-07-22 06:21:46 +0000476#define E1000_RX_DESC_EXT(R, i) \
477 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
Auke Kokbc7f75f2007-09-17 12:30:59 -0700478#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
Auke Kokbc7f75f2007-09-17 12:30:59 -0700479#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
480#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
481
482enum e1000_state_t {
483 __E1000_TESTING,
484 __E1000_RESETTING,
Bruce Allana90b4122011-10-07 03:50:38 +0000485 __E1000_ACCESS_SHARED_RESOURCE,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700486 __E1000_DOWN
487};
488
489enum latency_range {
490 lowest_latency = 0,
491 low_latency = 1,
492 bulk_latency = 2,
493 latency_invalid = 255
494};
495
496extern char e1000e_driver_name[];
497extern const char e1000e_driver_version[];
498
499extern void e1000e_check_options(struct e1000_adapter *adapter);
500extern void e1000e_set_ethtool_ops(struct net_device *netdev);
501
502extern int e1000e_up(struct e1000_adapter *adapter);
503extern void e1000e_down(struct e1000_adapter *adapter);
504extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
505extern void e1000e_reset(struct e1000_adapter *adapter);
506extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
Bruce Allan55aa6982011-12-16 00:45:45 +0000507extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
508extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
509extern void e1000e_free_rx_resources(struct e1000_ring *ring);
510extern void e1000e_free_tx_resources(struct e1000_ring *ring);
Jeff Kirsher67fd4fc2011-01-07 05:12:09 +0000511extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
512 struct rtnl_link_stats64
513 *stats);
Bruce Allan4662e822008-08-26 18:37:06 -0700514extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
515extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
Bruce Allan31dbe5b2011-01-06 14:29:52 +0000516extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
517extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
Matthew Vick22a4cca2012-07-12 00:02:42 +0000518extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700519
520extern unsigned int copybreak;
521
522extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
523
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +0000524extern const struct e1000_info e1000_82571_info;
525extern const struct e1000_info e1000_82572_info;
526extern const struct e1000_info e1000_82573_info;
527extern const struct e1000_info e1000_82574_info;
528extern const struct e1000_info e1000_82583_info;
529extern const struct e1000_info e1000_ich8_info;
530extern const struct e1000_info e1000_ich9_info;
531extern const struct e1000_info e1000_ich10_info;
532extern const struct e1000_info e1000_pch_info;
533extern const struct e1000_info e1000_pch2_info;
Bruce Allan2fbe4522012-04-19 03:21:47 +0000534extern const struct e1000_info e1000_pch_lpt_info;
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +0000535extern const struct e1000_info e1000_es2_info;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700536
Bruce Allan073287c2010-11-24 06:01:51 +0000537extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
538 u32 pba_num_size);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700539
540extern s32 e1000e_commit_phy(struct e1000_hw *hw);
541
542extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
543
544extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
545extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
546
Bruce Allan4a770352008-10-01 17:18:35 -0700547extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700548extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
549 bool state);
550extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
551extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
Bruce Allan99730e42011-05-13 07:19:48 +0000552extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
553extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
Bruce Allanbb436b22009-11-20 23:24:11 +0000554extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
Bruce Alland3738bb2010-06-16 13:27:28 +0000555extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
556extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700557
558extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
559extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
560extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
Bruce Allana4f58f52009-06-02 11:29:18 +0000561extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700562extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
563extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
564extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
565extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
Bruce Allanf4d2dd42010-01-13 02:05:18 +0000566extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
567extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700568extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
569extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
570extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
571extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
Bruce Alland1964eb2012-02-22 09:02:21 +0000572extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700573extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
574extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
575extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
576extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
Bruce Allan1a46b402012-02-22 09:02:26 +0000577extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
Bruce Allancaaddaf2009-12-01 15:46:43 +0000578extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700579extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
Jeff Kirshere2de3eb2008-03-28 09:15:11 -0700580extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
581 u8 *mc_addr_list,
Bruce Allanab8932f2010-01-13 02:05:38 +0000582 u32 mc_addr_count);
Bruce Allan69e1e012012-04-14 03:28:50 +0000583extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700584extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
585extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
586extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
587extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
Bruce Allan57cde762012-02-22 09:02:58 +0000588extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700589extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
590extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
Bruce Allandbf80dc2011-04-16 00:34:40 +0000591extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
Bruce Allancaaddaf2009-12-01 15:46:43 +0000592extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
Bruce Allan608f8a02010-01-13 02:04:58 +0000593extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700594extern void e1000e_reset_adaptive(struct e1000_hw *hw);
595extern void e1000e_update_adaptive(struct e1000_hw *hw);
596
597extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
598extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
599extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
600extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
601extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
602extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
603extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
Bruce Allan2b6b1682011-05-13 07:20:09 +0000604extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700605extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000606extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
607 u16 *data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700608extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
609extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
610extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000611extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
612 u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700613extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
614extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
615extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
616extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
617extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
618extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
619extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allanf4187b52008-08-26 18:36:50 -0700620extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700621extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700622extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
623extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
624extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan2b6b1682011-05-13 07:20:09 +0000625extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
626 u16 *phy_reg);
627extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
628 u16 *phy_reg);
Bruce Allan4662e822008-08-26 18:37:06 -0700629extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
630extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700631extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
632extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000633extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
634 u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700635extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000636extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
637 u16 *data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700638extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
639 u32 usec_interval, bool *success);
640extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
Bruce Allan17f208d2009-12-01 15:47:22 +0000641extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
642extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
David Graham2d9498f2008-04-23 11:09:14 -0700643extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
644extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700645extern s32 e1000e_check_downshift(struct e1000_hw *hw);
Bruce Allana4f58f52009-06-02 11:29:18 +0000646extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000647extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
648 u16 *data);
Bruce Allan2b6b1682011-05-13 07:20:09 +0000649extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
650 u16 *data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000651extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000652extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
653 u16 data);
Bruce Allan2b6b1682011-05-13 07:20:09 +0000654extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
655 u16 data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000656extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
657extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
658extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
659extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
660extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
661extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700662
Bruce Allan0be84012009-12-02 17:03:18 +0000663extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
664extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
665extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
666extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
667extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000668extern bool e1000_check_phy_82574(struct e1000_hw *hw);
Bruce Allan0be84012009-12-02 17:03:18 +0000669
Auke Kokbc7f75f2007-09-17 12:30:59 -0700670static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
671{
Bruce Allan94d81862009-11-20 23:25:26 +0000672 return hw->phy.ops.reset(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700673}
674
Auke Kokbc7f75f2007-09-17 12:30:59 -0700675static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
676{
Bruce Allan94d81862009-11-20 23:25:26 +0000677 return hw->phy.ops.read_reg(hw, offset, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700678}
679
Bruce Allanf1430d62012-04-14 04:21:52 +0000680static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
681{
682 return hw->phy.ops.read_reg_locked(hw, offset, data);
683}
684
Auke Kokbc7f75f2007-09-17 12:30:59 -0700685static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
686{
Bruce Allan94d81862009-11-20 23:25:26 +0000687 return hw->phy.ops.write_reg(hw, offset, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700688}
689
Bruce Allanf1430d62012-04-14 04:21:52 +0000690static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
691{
692 return hw->phy.ops.write_reg_locked(hw, offset, data);
693}
694
Auke Kokbc7f75f2007-09-17 12:30:59 -0700695static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
696{
697 return hw->phy.ops.get_cable_length(hw);
698}
699
700extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
701extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
702extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
703extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700704extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
705extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
706extern void e1000e_release_nvm(struct e1000_hw *hw);
Bruce Allane85e3632012-02-22 09:03:14 +0000707extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
Bruce Allan608f8a02010-01-13 02:04:58 +0000708extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
709
710static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
711{
712 if (hw->mac.ops.read_mac_addr)
713 return hw->mac.ops.read_mac_addr(hw);
714
715 return e1000_read_mac_addr_generic(hw);
716}
Auke Kokbc7f75f2007-09-17 12:30:59 -0700717
718static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
719{
Bruce Allan94d81862009-11-20 23:25:26 +0000720 return hw->nvm.ops.validate(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700721}
722
723static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
724{
Bruce Allan94d81862009-11-20 23:25:26 +0000725 return hw->nvm.ops.update(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700726}
727
728static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
729{
Bruce Allan94d81862009-11-20 23:25:26 +0000730 return hw->nvm.ops.read(hw, offset, words, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700731}
732
733static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
734{
Bruce Allan94d81862009-11-20 23:25:26 +0000735 return hw->nvm.ops.write(hw, offset, words, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700736}
737
738static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
739{
Bruce Allan94d81862009-11-20 23:25:26 +0000740 return hw->phy.ops.get_info(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700741}
742
Bruce Allan4662e822008-08-26 18:37:06 -0700743extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700744extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
745extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
746
747static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
748{
749 return readl(hw->hw_addr + reg);
750}
751
Bruce Allanbdc125f2012-03-20 03:47:52 +0000752#define er32(reg) __er32(hw, E1000_##reg)
753
754/**
755 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
756 * @hw: pointer to the HW structure
757 *
758 * When updating the MAC CSR registers, the Manageability Engine (ME) could
759 * be accessing the registers at the same time. Normally, this is handled in
760 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
761 * accesses later than it should which could result in the register to have
762 * an incorrect value. Workaround this by checking the FWSM register which
763 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
764 * and try again a number of times.
765 **/
766static inline s32 __ew32_prepare(struct e1000_hw *hw)
767{
768 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
769
770 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
771 udelay(50);
772
773 return i;
774}
775
Auke Kokbc7f75f2007-09-17 12:30:59 -0700776static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
777{
Bruce Allanbdc125f2012-03-20 03:47:52 +0000778 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
779 __ew32_prepare(hw);
780
Auke Kokbc7f75f2007-09-17 12:30:59 -0700781 writel(val, hw->hw_addr + reg);
782}
783
Bruce Allanbdc125f2012-03-20 03:47:52 +0000784#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
785
786#define e1e_flush() er32(STATUS)
787
788#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
789 (__ew32((a), (reg + ((offset) << 2)), (value)))
790
791#define E1000_READ_REG_ARRAY(a, reg, offset) \
792 (readl((a)->hw_addr + reg + ((offset) << 2)))
793
Auke Kokbc7f75f2007-09-17 12:30:59 -0700794#endif /* _E1000_H_ */