blob: c85653f315aad47be0b758863356e95b53c27b60 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15**
16** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17** J5000/J7000/N-class/L-class machines and their successors.
18**
19** FIXME: add DMA hint support programming in both sba and lba modules.
20*/
21
22#include <linux/config.h>
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/spinlock.h>
26#include <linux/slab.h>
27#include <linux/init.h>
28
29#include <linux/mm.h>
30#include <linux/string.h>
31#include <linux/pci.h>
32
33#include <asm/byteorder.h>
34#include <asm/io.h>
35#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
36
37#include <asm/hardware.h> /* for register_parisc_driver() stuff */
38
39#include <linux/proc_fs.h>
40#include <asm/runway.h> /* for proc_runway_root */
41#include <asm/pdc.h> /* for PDC_MODEL_* */
42#include <asm/pdcpat.h> /* for is_pdc_pat() */
43#include <asm/parisc-device.h>
44
45
46/* declared in arch/parisc/kernel/setup.c */
47extern struct proc_dir_entry * proc_mckinley_root;
48
49#define MODULE_NAME "SBA"
50
51#ifdef CONFIG_PROC_FS
52/* depends on proc fs support. But costs CPU performance */
53#undef SBA_COLLECT_STATS
54#endif
55
56/*
57** The number of debug flags is a clue - this code is fragile.
58** Don't even think about messing with it unless you have
59** plenty of 710's to sacrifice to the computer gods. :^)
60*/
61#undef DEBUG_SBA_INIT
62#undef DEBUG_SBA_RUN
63#undef DEBUG_SBA_RUN_SG
64#undef DEBUG_SBA_RESOURCE
65#undef ASSERT_PDIR_SANITY
66#undef DEBUG_LARGE_SG_ENTRIES
67#undef DEBUG_DMB_TRAP
68
69#ifdef DEBUG_SBA_INIT
70#define DBG_INIT(x...) printk(x)
71#else
72#define DBG_INIT(x...)
73#endif
74
75#ifdef DEBUG_SBA_RUN
76#define DBG_RUN(x...) printk(x)
77#else
78#define DBG_RUN(x...)
79#endif
80
81#ifdef DEBUG_SBA_RUN_SG
82#define DBG_RUN_SG(x...) printk(x)
83#else
84#define DBG_RUN_SG(x...)
85#endif
86
87
88#ifdef DEBUG_SBA_RESOURCE
89#define DBG_RES(x...) printk(x)
90#else
91#define DBG_RES(x...)
92#endif
93
Grant Grundler64908ad2005-10-21 22:37:20 -040094#if defined(CONFIG_64BIT)
95/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -070096#define ZX1_SUPPORT
97#endif
98
99#define SBA_INLINE __inline__
100
101
102/*
103** The number of pdir entries to "free" before issueing
104** a read to PCOM register to flush out PCOM writes.
105** Interacts with allocation granularity (ie 4 or 8 entries
106** allocated and free'd/purged at a time might make this
107** less interesting).
108*/
109#define DELAYED_RESOURCE_CNT 16
110
111#define DEFAULT_DMA_HINT_REG 0
112
113#define ASTRO_RUNWAY_PORT 0x582
114#define IKE_MERCED_PORT 0x803
115#define REO_MERCED_PORT 0x804
116#define REOG_MERCED_PORT 0x805
117#define PLUTO_MCKINLEY_PORT 0x880
118
119#define SBA_FUNC_ID 0x0000 /* function id */
120#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
121
122#define IS_ASTRO(id) ((id)->hversion == ASTRO_RUNWAY_PORT)
123#define IS_IKE(id) ((id)->hversion == IKE_MERCED_PORT)
124#define IS_PLUTO(id) ((id)->hversion == PLUTO_MCKINLEY_PORT)
125
126#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
127
128#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
129#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
130/* Ike's IOC's occupy functions 2 and 3 */
131#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
132
133#define IOC_CTRL 0x8 /* IOC_CTRL offset */
134#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
135#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
136#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
137#define IOC_CTRL_RM (1 << 8) /* Real Mode */
138#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
139#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
140#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
141
142#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
143
144#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
145
146
147/*
148** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
149** Firmware programs this stuff. Don't touch it.
150*/
151#define LMMIO_DIRECT0_BASE 0x300
152#define LMMIO_DIRECT0_MASK 0x308
153#define LMMIO_DIRECT0_ROUTE 0x310
154
155#define LMMIO_DIST_BASE 0x360
156#define LMMIO_DIST_MASK 0x368
157#define LMMIO_DIST_ROUTE 0x370
158
159#define IOS_DIST_BASE 0x390
160#define IOS_DIST_MASK 0x398
161#define IOS_DIST_ROUTE 0x3A0
162
163#define IOS_DIRECT_BASE 0x3C0
164#define IOS_DIRECT_MASK 0x3C8
165#define IOS_DIRECT_ROUTE 0x3D0
166
167/*
168** Offsets into I/O TLB (Function 2 and 3 on Ike)
169*/
170#define ROPE0_CTL 0x200 /* "regbus pci0" */
171#define ROPE1_CTL 0x208
172#define ROPE2_CTL 0x210
173#define ROPE3_CTL 0x218
174#define ROPE4_CTL 0x220
175#define ROPE5_CTL 0x228
176#define ROPE6_CTL 0x230
177#define ROPE7_CTL 0x238
178
179#define HF_ENABLE 0x40
180
181
182#define IOC_IBASE 0x300 /* IO TLB */
183#define IOC_IMASK 0x308
184#define IOC_PCOM 0x310
185#define IOC_TCNFG 0x318
186#define IOC_PDIR_BASE 0x320
187
188/* AGP GART driver looks for this */
189#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
190
191
192/*
193** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
194** It's safer (avoid memory corruption) to keep DMA page mappings
195** equivalently sized to VM PAGE_SIZE.
196**
197** We really can't avoid generating a new mapping for each
198** page since the Virtual Coherence Index has to be generated
199** and updated for each page.
200**
201** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
202*/
203#define IOVP_SIZE PAGE_SIZE
204#define IOVP_SHIFT PAGE_SHIFT
205#define IOVP_MASK PAGE_MASK
206
207#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
208#define SBA_PERF_MASK1 0x718
209#define SBA_PERF_MASK2 0x730
210
211
212/*
213** Offsets into PCI Performance Counters (functions 12 and 13)
214** Controlled by PERF registers in function 2 & 3 respectively.
215*/
216#define SBA_PERF_CNT1 0x200
217#define SBA_PERF_CNT2 0x208
218#define SBA_PERF_CNT3 0x210
219
220
221struct ioc {
222 void __iomem *ioc_hpa; /* I/O MMU base address */
223 char *res_map; /* resource map, bit == pdir entry */
224 u64 *pdir_base; /* physical base address */
225 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
226 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
227#ifdef ZX1_SUPPORT
228 unsigned long iovp_mask; /* help convert IOVA to IOVP */
229#endif
230 unsigned long *res_hint; /* next avail IOVP - circular search */
231 spinlock_t res_lock;
232 unsigned int res_bitshift; /* from the LEFT! */
233 unsigned int res_size; /* size of resource map in bytes */
Grant Grundler64908ad2005-10-21 22:37:20 -0400234#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235/* FIXME : DMA HINTs not used */
236 unsigned long hint_mask_pdir; /* bits used for DMA hints */
237 unsigned int hint_shift_pdir;
238#endif
239#if DELAYED_RESOURCE_CNT > 0
240 int saved_cnt;
241 struct sba_dma_pair {
242 dma_addr_t iova;
243 size_t size;
244 } saved[DELAYED_RESOURCE_CNT];
245#endif
246
247#ifdef SBA_COLLECT_STATS
248#define SBA_SEARCH_SAMPLE 0x100
249 unsigned long avg_search[SBA_SEARCH_SAMPLE];
250 unsigned long avg_idx; /* current index into avg_search */
251 unsigned long used_pages;
252 unsigned long msingle_calls;
253 unsigned long msingle_pages;
254 unsigned long msg_calls;
255 unsigned long msg_pages;
256 unsigned long usingle_calls;
257 unsigned long usingle_pages;
258 unsigned long usg_calls;
259 unsigned long usg_pages;
260#endif
261
262 /* STUFF We don't need in performance path */
263 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
264};
265
266struct sba_device {
267 struct sba_device *next; /* list of SBA's in system */
268 struct parisc_device *dev; /* dev found in bus walk */
269 struct parisc_device_id *iodc; /* data about dev from firmware */
270 const char *name;
271 void __iomem *sba_hpa; /* base address */
272 spinlock_t sba_lock;
273 unsigned int flags; /* state/functionality enabled */
274 unsigned int hw_rev; /* HW revision of chip */
275
276 struct resource chip_resv; /* MMIO reserved for chip */
277 struct resource iommu_resv; /* MMIO reserved for iommu */
278
279 unsigned int num_ioc; /* number of on-board IOC's */
280 struct ioc ioc[MAX_IOC];
281};
282
283
284static struct sba_device *sba_list;
285
286static unsigned long ioc_needs_fdc = 0;
287
288/* global count of IOMMUs in the system */
289static unsigned int global_ioc_cnt = 0;
290
291/* PA8700 (Piranha 2.2) bug workaround */
292static unsigned long piranha_bad_128k = 0;
293
294/* Looks nice and keeps the compiler happy */
295#define SBA_DEV(d) ((struct sba_device *) (d))
296
Grant Grundler64908ad2005-10-21 22:37:20 -0400297#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298static int reserve_sba_gart = 1;
299#endif
300
301#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
302
303
304/************************************
305** SBA register read and write support
306**
307** BE WARNED: register writes are posted.
308** (ie follow writes which must reach HW with a read)
309**
310** Superdome (in particular, REO) allows only 64-bit CSR accesses.
311*/
312#define READ_REG32(addr) le32_to_cpu(__raw_readl(addr))
313#define READ_REG64(addr) le64_to_cpu(__raw_readq(addr))
314#define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
315#define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)
316
Grant Grundler64908ad2005-10-21 22:37:20 -0400317#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318#define READ_REG(addr) READ_REG64(addr)
319#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
320#else
321#define READ_REG(addr) READ_REG32(addr)
322#define WRITE_REG(value, addr) WRITE_REG32(value, addr)
323#endif
324
325#ifdef DEBUG_SBA_INIT
326
Grant Grundler64908ad2005-10-21 22:37:20 -0400327/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328
329/**
330 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
331 * @hpa: base address of the sba
332 *
333 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
334 * IO Adapter (aka Bus Converter).
335 */
336static void
337sba_dump_ranges(void __iomem *hpa)
338{
339 DBG_INIT("SBA at 0x%p\n", hpa);
340 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
341 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
342 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
343 DBG_INIT("\n");
344 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
345 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
346 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
347}
348
349/**
350 * sba_dump_tlb - debugging only - print IOMMU operating parameters
351 * @hpa: base address of the IOMMU
352 *
353 * Print the size/location of the IO MMU PDIR.
354 */
355static void sba_dump_tlb(void __iomem *hpa)
356{
357 DBG_INIT("IO TLB at 0x%p\n", hpa);
358 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
359 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
360 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
361 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
362 DBG_INIT("\n");
363}
364#else
365#define sba_dump_ranges(x)
366#define sba_dump_tlb(x)
Grant Grundler64908ad2005-10-21 22:37:20 -0400367#endif /* DEBUG_SBA_INIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368
369
370#ifdef ASSERT_PDIR_SANITY
371
372/**
373 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
374 * @ioc: IO MMU structure which owns the pdir we are interested in.
375 * @msg: text to print ont the output line.
376 * @pide: pdir index.
377 *
378 * Print one entry of the IO MMU PDIR in human readable form.
379 */
380static void
381sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
382{
383 /* start printing from lowest pde in rval */
384 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
385 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
386 uint rcnt;
387
388 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
389 msg,
390 rptr, pide & (BITS_PER_LONG - 1), *rptr);
391
392 rcnt = 0;
393 while (rcnt < BITS_PER_LONG) {
394 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
395 (rcnt == (pide & (BITS_PER_LONG - 1)))
396 ? " -->" : " ",
397 rcnt, ptr, *ptr );
398 rcnt++;
399 ptr++;
400 }
401 printk(KERN_DEBUG "%s", msg);
402}
403
404
405/**
406 * sba_check_pdir - debugging only - consistency checker
407 * @ioc: IO MMU structure which owns the pdir we are interested in.
408 * @msg: text to print ont the output line.
409 *
410 * Verify the resource map and pdir state is consistent
411 */
412static int
413sba_check_pdir(struct ioc *ioc, char *msg)
414{
415 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
416 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
417 u64 *pptr = ioc->pdir_base; /* pdir ptr */
418 uint pide = 0;
419
420 while (rptr < rptr_end) {
421 u32 rval = *rptr;
422 int rcnt = 32; /* number of bits we might check */
423
424 while (rcnt) {
425 /* Get last byte and highest bit from that */
426 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
427 if ((rval ^ pde) & 0x80000000)
428 {
429 /*
430 ** BUMMER! -- res_map != pdir --
431 ** Dump rval and matching pdir entries
432 */
433 sba_dump_pdir_entry(ioc, msg, pide);
434 return(1);
435 }
436 rcnt--;
437 rval <<= 1; /* try the next bit */
438 pptr++;
439 pide++;
440 }
441 rptr++; /* look at next word of res_map */
442 }
443 /* It'd be nice if we always got here :^) */
444 return 0;
445}
446
447
448/**
449 * sba_dump_sg - debugging only - print Scatter-Gather list
450 * @ioc: IO MMU structure which owns the pdir we are interested in.
451 * @startsg: head of the SG list
452 * @nents: number of entries in SG list
453 *
454 * print the SG list so we can verify it's correct by hand.
455 */
456static void
457sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
458{
459 while (nents-- > 0) {
460 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
461 nents,
462 (unsigned long) sg_dma_address(startsg),
463 sg_dma_len(startsg),
464 sg_virt_addr(startsg), startsg->length);
465 startsg++;
466 }
467}
468
469#endif /* ASSERT_PDIR_SANITY */
470
471
472
473
474/**************************************************************
475*
476* I/O Pdir Resource Management
477*
478* Bits set in the resource map are in use.
479* Each bit can represent a number of pages.
480* LSbs represent lower addresses (IOVA's).
481*
482***************************************************************/
483#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
484
485/* Convert from IOVP to IOVA and vice versa. */
486
487#ifdef ZX1_SUPPORT
488/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
489#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
490#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
491#else
492/* only support Astro and ancestors. Saves a few cycles in key places */
493#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
494#define SBA_IOVP(ioc,iova) (iova)
495#endif
496
497#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
498
499#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
500#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
501
502
503/**
504 * sba_search_bitmap - find free space in IO PDIR resource bitmap
505 * @ioc: IO MMU structure which owns the pdir we are interested in.
506 * @bits_wanted: number of entries we need.
507 *
508 * Find consecutive free bits in resource bitmap.
509 * Each bit represents one entry in the IO Pdir.
510 * Cool perf optimization: search for log2(size) bits at a time.
511 */
512static SBA_INLINE unsigned long
513sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
514{
515 unsigned long *res_ptr = ioc->res_hint;
516 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
517 unsigned long pide = ~0UL;
518
519 if (bits_wanted > (BITS_PER_LONG/2)) {
520 /* Search word at a time - no mask needed */
521 for(; res_ptr < res_end; ++res_ptr) {
522 if (*res_ptr == 0) {
523 *res_ptr = RESMAP_MASK(bits_wanted);
524 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
525 pide <<= 3; /* convert to bit address */
526 break;
527 }
528 }
529 /* point to the next word on next pass */
530 res_ptr++;
531 ioc->res_bitshift = 0;
532 } else {
533 /*
534 ** Search the resource bit map on well-aligned values.
535 ** "o" is the alignment.
536 ** We need the alignment to invalidate I/O TLB using
537 ** SBA HW features in the unmap path.
538 */
539 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
540 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
541 unsigned long mask;
542
543 if (bitshiftcnt >= BITS_PER_LONG) {
544 bitshiftcnt = 0;
545 res_ptr++;
546 }
547 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
548
549 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
550 while(res_ptr < res_end)
551 {
552 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
553 WARN_ON(mask == 0);
554 if(((*res_ptr) & mask) == 0) {
555 *res_ptr |= mask; /* mark resources busy! */
556 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
557 pide <<= 3; /* convert to bit address */
558 pide += bitshiftcnt;
559 break;
560 }
561 mask >>= o;
562 bitshiftcnt += o;
563 if (mask == 0) {
564 mask = RESMAP_MASK(bits_wanted);
565 bitshiftcnt=0;
566 res_ptr++;
567 }
568 }
569 /* look in the same word on the next pass */
570 ioc->res_bitshift = bitshiftcnt + bits_wanted;
571 }
572
573 /* wrapped ? */
574 if (res_end <= res_ptr) {
575 ioc->res_hint = (unsigned long *) ioc->res_map;
576 ioc->res_bitshift = 0;
577 } else {
578 ioc->res_hint = res_ptr;
579 }
580 return (pide);
581}
582
583
584/**
585 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
586 * @ioc: IO MMU structure which owns the pdir we are interested in.
587 * @size: number of bytes to create a mapping for
588 *
589 * Given a size, find consecutive unmarked and then mark those bits in the
590 * resource bit map.
591 */
592static int
593sba_alloc_range(struct ioc *ioc, size_t size)
594{
595 unsigned int pages_needed = size >> IOVP_SHIFT;
596#ifdef SBA_COLLECT_STATS
597 unsigned long cr_start = mfctl(16);
598#endif
599 unsigned long pide;
600
601 pide = sba_search_bitmap(ioc, pages_needed);
602 if (pide >= (ioc->res_size << 3)) {
603 pide = sba_search_bitmap(ioc, pages_needed);
604 if (pide >= (ioc->res_size << 3))
605 panic("%s: I/O MMU @ %p is out of mapping resources\n",
606 __FILE__, ioc->ioc_hpa);
607 }
608
609#ifdef ASSERT_PDIR_SANITY
610 /* verify the first enable bit is clear */
611 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
612 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
613 }
614#endif
615
616 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
617 __FUNCTION__, size, pages_needed, pide,
618 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
619 ioc->res_bitshift );
620
621#ifdef SBA_COLLECT_STATS
622 {
623 unsigned long cr_end = mfctl(16);
624 unsigned long tmp = cr_end - cr_start;
625 /* check for roll over */
626 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
627 }
628 ioc->avg_search[ioc->avg_idx++] = cr_start;
629 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
630
631 ioc->used_pages += pages_needed;
632#endif
633
634 return (pide);
635}
636
637
638/**
639 * sba_free_range - unmark bits in IO PDIR resource bitmap
640 * @ioc: IO MMU structure which owns the pdir we are interested in.
641 * @iova: IO virtual address which was previously allocated.
642 * @size: number of bytes to create a mapping for
643 *
644 * clear bits in the ioc's resource map
645 */
646static SBA_INLINE void
647sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
648{
649 unsigned long iovp = SBA_IOVP(ioc, iova);
650 unsigned int pide = PDIR_INDEX(iovp);
651 unsigned int ridx = pide >> 3; /* convert bit to byte address */
652 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
653
654 int bits_not_wanted = size >> IOVP_SHIFT;
655
656 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
657 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
658
659 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
660 __FUNCTION__, (uint) iova, size,
661 bits_not_wanted, m, pide, res_ptr, *res_ptr);
662
663#ifdef SBA_COLLECT_STATS
664 ioc->used_pages -= bits_not_wanted;
665#endif
666
667 *res_ptr &= ~m;
668}
669
670
671/**************************************************************
672*
673* "Dynamic DMA Mapping" support (aka "Coherent I/O")
674*
675***************************************************************/
676
Grant Grundler64908ad2005-10-21 22:37:20 -0400677#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
679#endif
680
681typedef unsigned long space_t;
682#define KERNEL_SPACE 0
683
684/**
685 * sba_io_pdir_entry - fill in one IO PDIR entry
686 * @pdir_ptr: pointer to IO PDIR entry
687 * @sid: process Space ID - currently only support KERNEL_SPACE
688 * @vba: Virtual CPU address of buffer to map
689 * @hint: DMA hint set to use for this mapping
690 *
691 * SBA Mapping Routine
692 *
693 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
694 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
695 * pdir_ptr (arg0).
696 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
697 * for Astro/Ike looks like:
698 *
699 *
700 * 0 19 51 55 63
701 * +-+---------------------+----------------------------------+----+--------+
702 * |V| U | PPN[43:12] | U | VI |
703 * +-+---------------------+----------------------------------+----+--------+
704 *
705 * Pluto is basically identical, supports fewer physical address bits:
706 *
707 * 0 23 51 55 63
708 * +-+------------------------+-------------------------------+----+--------+
709 * |V| U | PPN[39:12] | U | VI |
710 * +-+------------------------+-------------------------------+----+--------+
711 *
712 * V == Valid Bit (Most Significant Bit is bit 0)
713 * U == Unused
714 * PPN == Physical Page Number
715 * VI == Virtual Index (aka Coherent Index)
716 *
717 * LPA instruction output is put into PPN field.
718 * LCI (Load Coherence Index) instruction provides the "VI" bits.
719 *
720 * We pre-swap the bytes since PCX-W is Big Endian and the
721 * IOMMU uses little endian for the pdir.
722 */
723
724void SBA_INLINE
725sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
726 unsigned long hint)
727{
728 u64 pa; /* physical address */
729 register unsigned ci; /* coherent index */
730
731 pa = virt_to_phys(vba);
732 pa &= IOVP_MASK;
733
734 mtsp(sid,1);
735 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
736 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
737
738 pa |= 0x8000000000000000ULL; /* set "valid" bit */
739 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
740
741 /*
742 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
743 * (bit #61, big endian), we have to flush and sync every time
744 * IO-PDIR is changed in Ike/Astro.
745 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400746 if (ioc_needs_fdc)
747 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748}
749
750
751/**
752 * sba_mark_invalid - invalidate one or more IO PDIR entries
753 * @ioc: IO MMU structure which owns the pdir we are interested in.
754 * @iova: IO Virtual Address mapped earlier
755 * @byte_cnt: number of bytes this mapping covers.
756 *
757 * Marking the IO PDIR entry(ies) as Invalid and invalidate
758 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
759 * is to purge stale entries in the IO TLB when unmapping entries.
760 *
761 * The PCOM register supports purging of multiple pages, with a minium
762 * of 1 page and a maximum of 2GB. Hardware requires the address be
763 * aligned to the size of the range being purged. The size of the range
764 * must be a power of 2. The "Cool perf optimization" in the
765 * allocation routine helps keep that true.
766 */
767static SBA_INLINE void
768sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
769{
770 u32 iovp = (u32) SBA_IOVP(ioc,iova);
Grant Grundler64908ad2005-10-21 22:37:20 -0400771 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772
773#ifdef ASSERT_PDIR_SANITY
Grant Grundler64908ad2005-10-21 22:37:20 -0400774 /* Assert first pdir entry is set.
775 **
776 ** Even though this is a big-endian machine, the entries
777 ** in the iopdir are little endian. That's why we look at
778 ** the byte at +7 instead of at +0.
779 */
780 if (0x80 != (((u8 *) pdir_ptr)[7])) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
782 }
783#endif
784
Grant Grundler64908ad2005-10-21 22:37:20 -0400785 if (byte_cnt > IOVP_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 {
Grant Grundler64908ad2005-10-21 22:37:20 -0400787#if 0
788 unsigned long entries_per_cacheline = ioc_needs_fdc ?
789 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
790 - (unsigned long) pdir_ptr;
791 : 262144;
792#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793
Grant Grundler64908ad2005-10-21 22:37:20 -0400794 /* set "size" field for PCOM */
795 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 do {
798 /* clear I/O Pdir entry "valid" bit first */
Grant Grundler64908ad2005-10-21 22:37:20 -0400799 ((u8 *) pdir_ptr)[7] = 0;
800 if (ioc_needs_fdc) {
801 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
802#if 0
803 entries_per_cacheline = L1_CACHE_SHIFT - 3;
804#endif
805 }
806 pdir_ptr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 byte_cnt -= IOVP_SIZE;
Grant Grundler64908ad2005-10-21 22:37:20 -0400808 } while (byte_cnt > IOVP_SIZE);
809 } else
810 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
811
812 /*
813 ** clear I/O PDIR entry "valid" bit.
814 ** We have to R/M/W the cacheline regardless how much of the
815 ** pdir entry that we clobber.
816 ** The rest of the entry would be useful for debugging if we
817 ** could dump core on HPMC.
818 */
819 ((u8 *) pdir_ptr)[7] = 0;
820 if (ioc_needs_fdc)
821 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
823 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
824}
825
826/**
827 * sba_dma_supported - PCI driver can query DMA support
828 * @dev: instance of PCI owned by the driver that's asking
829 * @mask: number of address bits this PCI device can handle
830 *
831 * See Documentation/DMA-mapping.txt
832 */
833static int sba_dma_supported( struct device *dev, u64 mask)
834{
835 struct ioc *ioc;
Grant Grundler64908ad2005-10-21 22:37:20 -0400836
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 if (dev == NULL) {
838 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
839 BUG();
840 return(0);
841 }
842
Grant Grundler64908ad2005-10-21 22:37:20 -0400843 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
844 * then fall back to 32-bit if that fails.
845 * We are just "encouraging" 32-bit DMA masks here since we can
846 * never allow IOMMU bypass unless we add special support for ZX1.
847 */
848 if (mask > ~0U)
849 return 0;
850
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 ioc = GET_IOC(dev);
852
Grant Grundler64908ad2005-10-21 22:37:20 -0400853 /*
854 * check if mask is >= than the current max IO Virt Address
855 * The max IO Virt address will *always* < 30 bits.
856 */
857 return((int)(mask >= (ioc->ibase - 1 +
858 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859}
860
861
862/**
863 * sba_map_single - map one buffer and return IOVA for DMA
864 * @dev: instance of PCI owned by the driver that's asking.
865 * @addr: driver buffer to map.
866 * @size: number of bytes to map in driver buffer.
867 * @direction: R/W or both.
868 *
869 * See Documentation/DMA-mapping.txt
870 */
871static dma_addr_t
872sba_map_single(struct device *dev, void *addr, size_t size,
873 enum dma_data_direction direction)
874{
875 struct ioc *ioc;
876 unsigned long flags;
877 dma_addr_t iovp;
878 dma_addr_t offset;
879 u64 *pdir_start;
880 int pide;
881
882 ioc = GET_IOC(dev);
883
884 /* save offset bits */
885 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
886
887 /* round up to nearest IOVP_SIZE */
888 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
889
890 spin_lock_irqsave(&ioc->res_lock, flags);
891#ifdef ASSERT_PDIR_SANITY
892 sba_check_pdir(ioc,"Check before sba_map_single()");
893#endif
894
895#ifdef SBA_COLLECT_STATS
896 ioc->msingle_calls++;
897 ioc->msingle_pages += size >> IOVP_SHIFT;
898#endif
899 pide = sba_alloc_range(ioc, size);
900 iovp = (dma_addr_t) pide << IOVP_SHIFT;
901
902 DBG_RUN("%s() 0x%p -> 0x%lx\n",
903 __FUNCTION__, addr, (long) iovp | offset);
904
905 pdir_start = &(ioc->pdir_base[pide]);
906
907 while (size > 0) {
908 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
909
910 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
911 pdir_start,
912 (u8) (((u8 *) pdir_start)[7]),
913 (u8) (((u8 *) pdir_start)[6]),
914 (u8) (((u8 *) pdir_start)[5]),
915 (u8) (((u8 *) pdir_start)[4]),
916 (u8) (((u8 *) pdir_start)[3]),
917 (u8) (((u8 *) pdir_start)[2]),
918 (u8) (((u8 *) pdir_start)[1]),
919 (u8) (((u8 *) pdir_start)[0])
920 );
921
922 addr += IOVP_SIZE;
923 size -= IOVP_SIZE;
924 pdir_start++;
925 }
Grant Grundler64908ad2005-10-21 22:37:20 -0400926
927 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
928 if (ioc_needs_fdc)
929 asm volatile("sync" : : );
930
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931#ifdef ASSERT_PDIR_SANITY
932 sba_check_pdir(ioc,"Check after sba_map_single()");
933#endif
934 spin_unlock_irqrestore(&ioc->res_lock, flags);
Grant Grundler64908ad2005-10-21 22:37:20 -0400935
936 /* form complete address */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
938}
939
940
941/**
942 * sba_unmap_single - unmap one IOVA and free resources
943 * @dev: instance of PCI owned by the driver that's asking.
944 * @iova: IOVA of driver buffer previously mapped.
945 * @size: number of bytes mapped in driver buffer.
946 * @direction: R/W or both.
947 *
948 * See Documentation/DMA-mapping.txt
949 */
950static void
951sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
952 enum dma_data_direction direction)
953{
954 struct ioc *ioc;
955#if DELAYED_RESOURCE_CNT > 0
956 struct sba_dma_pair *d;
957#endif
958 unsigned long flags;
959 dma_addr_t offset;
960
961 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
962
963 ioc = GET_IOC(dev);
964 offset = iova & ~IOVP_MASK;
965 iova ^= offset; /* clear offset bits */
966 size += offset;
967 size = ROUNDUP(size, IOVP_SIZE);
968
969 spin_lock_irqsave(&ioc->res_lock, flags);
970
971#ifdef SBA_COLLECT_STATS
972 ioc->usingle_calls++;
973 ioc->usingle_pages += size >> IOVP_SHIFT;
974#endif
975
976 sba_mark_invalid(ioc, iova, size);
977
978#if DELAYED_RESOURCE_CNT > 0
979 /* Delaying when we re-use a IO Pdir entry reduces the number
980 * of MMIO reads needed to flush writes to the PCOM register.
981 */
982 d = &(ioc->saved[ioc->saved_cnt]);
983 d->iova = iova;
984 d->size = size;
985 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
986 int cnt = ioc->saved_cnt;
987 while (cnt--) {
988 sba_free_range(ioc, d->iova, d->size);
989 d--;
990 }
991 ioc->saved_cnt = 0;
Grant Grundler64908ad2005-10-21 22:37:20 -0400992
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
994 }
995#else /* DELAYED_RESOURCE_CNT == 0 */
996 sba_free_range(ioc, iova, size);
Grant Grundler64908ad2005-10-21 22:37:20 -0400997
998 /* If fdc's were issued, force fdc's to be visible now */
999 if (ioc_needs_fdc)
1000 asm volatile("sync" : : );
1001
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1003#endif /* DELAYED_RESOURCE_CNT == 0 */
Grant Grundler64908ad2005-10-21 22:37:20 -04001004
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 spin_unlock_irqrestore(&ioc->res_lock, flags);
1006
1007 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
1008 ** For Astro based systems this isn't a big deal WRT performance.
1009 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
1010 ** we don't need the syncdma. The issue here is I/O MMU cachelines
1011 ** are *not* coherent in all cases. May be hwrev dependent.
1012 ** Need to investigate more.
1013 asm volatile("syncdma");
1014 */
1015}
1016
1017
1018/**
1019 * sba_alloc_consistent - allocate/map shared mem for DMA
1020 * @hwdev: instance of PCI owned by the driver that's asking.
1021 * @size: number of bytes mapped in driver buffer.
1022 * @dma_handle: IOVA of new buffer.
1023 *
1024 * See Documentation/DMA-mapping.txt
1025 */
1026static void *sba_alloc_consistent(struct device *hwdev, size_t size,
Al Viro5c1fb412005-10-21 03:21:28 -04001027 dma_addr_t *dma_handle, gfp_t gfp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028{
1029 void *ret;
1030
1031 if (!hwdev) {
1032 /* only support PCI */
1033 *dma_handle = 0;
1034 return 0;
1035 }
1036
1037 ret = (void *) __get_free_pages(gfp, get_order(size));
1038
1039 if (ret) {
1040 memset(ret, 0, size);
1041 *dma_handle = sba_map_single(hwdev, ret, size, 0);
1042 }
1043
1044 return ret;
1045}
1046
1047
1048/**
1049 * sba_free_consistent - free/unmap shared mem for DMA
1050 * @hwdev: instance of PCI owned by the driver that's asking.
1051 * @size: number of bytes mapped in driver buffer.
1052 * @vaddr: virtual address IOVA of "consistent" buffer.
1053 * @dma_handler: IO virtual address of "consistent" buffer.
1054 *
1055 * See Documentation/DMA-mapping.txt
1056 */
1057static void
1058sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
1059 dma_addr_t dma_handle)
1060{
1061 sba_unmap_single(hwdev, dma_handle, size, 0);
1062 free_pages((unsigned long) vaddr, get_order(size));
1063}
1064
1065
1066/*
1067** Since 0 is a valid pdir_base index value, can't use that
1068** to determine if a value is valid or not. Use a flag to indicate
1069** the SG list entry contains a valid pdir index.
1070*/
1071#define PIDE_FLAG 0x80000000UL
1072
1073#ifdef SBA_COLLECT_STATS
1074#define IOMMU_MAP_STATS
1075#endif
1076#include "iommu-helpers.h"
1077
1078#ifdef DEBUG_LARGE_SG_ENTRIES
1079int dump_run_sg = 0;
1080#endif
1081
1082
1083/**
1084 * sba_map_sg - map Scatter/Gather list
1085 * @dev: instance of PCI owned by the driver that's asking.
1086 * @sglist: array of buffer/length pairs
1087 * @nents: number of entries in list
1088 * @direction: R/W or both.
1089 *
1090 * See Documentation/DMA-mapping.txt
1091 */
1092static int
1093sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
1094 enum dma_data_direction direction)
1095{
1096 struct ioc *ioc;
1097 int coalesced, filled = 0;
1098 unsigned long flags;
1099
1100 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1101
1102 ioc = GET_IOC(dev);
1103
1104 /* Fast path single entry scatterlists. */
1105 if (nents == 1) {
1106 sg_dma_address(sglist) = sba_map_single(dev,
1107 (void *)sg_virt_addr(sglist),
1108 sglist->length, direction);
1109 sg_dma_len(sglist) = sglist->length;
1110 return 1;
1111 }
1112
1113 spin_lock_irqsave(&ioc->res_lock, flags);
1114
1115#ifdef ASSERT_PDIR_SANITY
1116 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1117 {
1118 sba_dump_sg(ioc, sglist, nents);
1119 panic("Check before sba_map_sg()");
1120 }
1121#endif
1122
1123#ifdef SBA_COLLECT_STATS
1124 ioc->msg_calls++;
1125#endif
1126
1127 /*
1128 ** First coalesce the chunks and allocate I/O pdir space
1129 **
1130 ** If this is one DMA stream, we can properly map using the
1131 ** correct virtual address associated with each DMA page.
1132 ** w/o this association, we wouldn't have coherent DMA!
1133 ** Access to the virtual address is what forces a two pass algorithm.
1134 */
1135 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);
1136
1137 /*
1138 ** Program the I/O Pdir
1139 **
1140 ** map the virtual addresses to the I/O Pdir
1141 ** o dma_address will contain the pdir index
1142 ** o dma_len will contain the number of bytes to map
1143 ** o address contains the virtual address.
1144 */
1145 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1146
Grant Grundler64908ad2005-10-21 22:37:20 -04001147 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1148 if (ioc_needs_fdc)
1149 asm volatile("sync" : : );
1150
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151#ifdef ASSERT_PDIR_SANITY
1152 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1153 {
1154 sba_dump_sg(ioc, sglist, nents);
1155 panic("Check after sba_map_sg()\n");
1156 }
1157#endif
1158
1159 spin_unlock_irqrestore(&ioc->res_lock, flags);
1160
1161 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1162
1163 return filled;
1164}
1165
1166
1167/**
1168 * sba_unmap_sg - unmap Scatter/Gather list
1169 * @dev: instance of PCI owned by the driver that's asking.
1170 * @sglist: array of buffer/length pairs
1171 * @nents: number of entries in list
1172 * @direction: R/W or both.
1173 *
1174 * See Documentation/DMA-mapping.txt
1175 */
1176static void
1177sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1178 enum dma_data_direction direction)
1179{
1180 struct ioc *ioc;
1181#ifdef ASSERT_PDIR_SANITY
1182 unsigned long flags;
1183#endif
1184
1185 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1186 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1187
1188 ioc = GET_IOC(dev);
1189
1190#ifdef SBA_COLLECT_STATS
1191 ioc->usg_calls++;
1192#endif
1193
1194#ifdef ASSERT_PDIR_SANITY
1195 spin_lock_irqsave(&ioc->res_lock, flags);
1196 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1197 spin_unlock_irqrestore(&ioc->res_lock, flags);
1198#endif
1199
1200 while (sg_dma_len(sglist) && nents--) {
1201
1202 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1203#ifdef SBA_COLLECT_STATS
1204 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1205 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1206#endif
1207 ++sglist;
1208 }
1209
1210 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1211
1212#ifdef ASSERT_PDIR_SANITY
1213 spin_lock_irqsave(&ioc->res_lock, flags);
1214 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1215 spin_unlock_irqrestore(&ioc->res_lock, flags);
1216#endif
1217
1218}
1219
1220static struct hppa_dma_ops sba_ops = {
1221 .dma_supported = sba_dma_supported,
1222 .alloc_consistent = sba_alloc_consistent,
1223 .alloc_noncoherent = sba_alloc_consistent,
1224 .free_consistent = sba_free_consistent,
1225 .map_single = sba_map_single,
1226 .unmap_single = sba_unmap_single,
1227 .map_sg = sba_map_sg,
1228 .unmap_sg = sba_unmap_sg,
1229 .dma_sync_single_for_cpu = NULL,
1230 .dma_sync_single_for_device = NULL,
1231 .dma_sync_sg_for_cpu = NULL,
1232 .dma_sync_sg_for_device = NULL,
1233};
1234
1235
1236/**************************************************************************
1237**
1238** SBA PAT PDC support
1239**
1240** o call pdc_pat_cell_module()
1241** o store ranges in PCI "resource" structures
1242**
1243**************************************************************************/
1244
1245static void
1246sba_get_pat_resources(struct sba_device *sba_dev)
1247{
1248#if 0
1249/*
1250** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1251** PAT PDC to program the SBA/LBA directed range registers...this
1252** burden may fall on the LBA code since it directly supports the
1253** PCI subsystem. It's not clear yet. - ggg
1254*/
1255PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1256 FIXME : ???
1257PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1258 Tells where the dvi bits are located in the address.
1259PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1260 FIXME : ???
1261#endif
1262}
1263
1264
1265/**************************************************************
1266*
1267* Initialization and claim
1268*
1269***************************************************************/
1270#define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1271#define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1272static void *
1273sba_alloc_pdir(unsigned int pdir_size)
1274{
1275 unsigned long pdir_base;
1276 unsigned long pdir_order = get_order(pdir_size);
1277
1278 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
Grant Grundler64908ad2005-10-21 22:37:20 -04001279 if (NULL == (void *) pdir_base) {
1280 panic("%s() could not allocate I/O Page Table\n",
1281 __FUNCTION__);
1282 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283
1284 /* If this is not PA8700 (PCX-W2)
1285 ** OR newer than ver 2.2
1286 ** OR in a system that doesn't need VINDEX bits from SBA,
1287 **
1288 ** then we aren't exposed to the HW bug.
1289 */
1290 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1291 || (boot_cpu_data.pdc.versions > 0x202)
1292 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1293 return (void *) pdir_base;
1294
1295 /*
1296 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1297 *
1298 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1299 * Ike/Astro can cause silent data corruption. This is only
1300 * a problem if the I/O PDIR is located in memory such that
1301 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1302 *
1303 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1304 * right physical address, we can either avoid (IOPDIR <= 1MB)
1305 * or minimize (2MB IO Pdir) the problem if we restrict the
1306 * IO Pdir to a maximum size of 2MB-128K (1902K).
1307 *
1308 * Because we always allocate 2^N sized IO pdirs, either of the
1309 * "bad" regions will be the last 128K if at all. That's easy
1310 * to test for.
1311 *
1312 */
1313 if (pdir_order <= (19-12)) {
1314 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1315 /* allocate a new one on 512k alignment */
1316 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1317 /* release original */
1318 free_pages(pdir_base, pdir_order);
1319
1320 pdir_base = new_pdir;
1321
1322 /* release excess */
1323 while (pdir_order < (19-12)) {
1324 new_pdir += pdir_size;
1325 free_pages(new_pdir, pdir_order);
1326 pdir_order +=1;
1327 pdir_size <<=1;
1328 }
1329 }
1330 } else {
1331 /*
1332 ** 1MB or 2MB Pdir
1333 ** Needs to be aligned on an "odd" 1MB boundary.
1334 */
1335 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1336
1337 /* release original */
1338 free_pages( pdir_base, pdir_order);
1339
1340 /* release first 1MB */
1341 free_pages(new_pdir, 20-12);
1342
1343 pdir_base = new_pdir + 1024*1024;
1344
1345 if (pdir_order > (20-12)) {
1346 /*
1347 ** 2MB Pdir.
1348 **
1349 ** Flag tells init_bitmap() to mark bad 128k as used
1350 ** and to reduce the size by 128k.
1351 */
1352 piranha_bad_128k = 1;
1353
1354 new_pdir += 3*1024*1024;
1355 /* release last 1MB */
1356 free_pages(new_pdir, 20-12);
1357
1358 /* release unusable 128KB */
1359 free_pages(new_pdir - 128*1024 , 17-12);
1360
1361 pdir_size -= 128*1024;
1362 }
1363 }
1364
1365 memset((void *) pdir_base, 0, pdir_size);
1366 return (void *) pdir_base;
1367}
1368
Matthew Wilcox56583742005-10-21 22:33:38 -04001369static struct device *next_device(struct klist_iter *i)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370{
Matthew Wilcox56583742005-10-21 22:33:38 -04001371 struct klist_node * n = klist_next(i);
1372 return n ? container_of(n, struct device, knode_parent) : NULL;
1373}
1374
1375/* setup Mercury or Elroy IBASE/IMASK registers. */
1376static void
1377setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1378{
1379 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1381 struct device *dev;
Matthew Wilcox56583742005-10-21 22:33:38 -04001382 struct klist_iter i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383
Matthew Wilcox56583742005-10-21 22:33:38 -04001384 klist_iter_init(&sba->dev.klist_children, &i);
1385 while ((dev = next_device(&i))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001386 struct parisc_device *lba = to_parisc_device(dev);
Matthew Wilcox56583742005-10-21 22:33:38 -04001387 int rope_num = (lba->hpa.start >> 13) & 0xf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388 if (rope_num >> 3 == ioc_num)
1389 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1390 }
Matthew Wilcox56583742005-10-21 22:33:38 -04001391 klist_iter_exit(&i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392}
1393
1394static void
1395sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1396{
1397 u32 iova_space_mask;
1398 u32 iova_space_size;
1399 int iov_order, tcnfg;
Grant Grundler64908ad2005-10-21 22:37:20 -04001400#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401 int agp_found = 0;
1402#endif
1403 /*
1404 ** Firmware programs the base and size of a "safe IOVA space"
1405 ** (one that doesn't overlap memory or LMMIO space) in the
1406 ** IBASE and IMASK registers.
1407 */
1408 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1409 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1410
1411 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1412 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1413 iova_space_size /= 2;
1414 }
1415
1416 /*
1417 ** iov_order is always based on a 1GB IOVA space since we want to
1418 ** turn on the other half for AGP GART.
1419 */
1420 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1421 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1422
1423 DBG_INIT("%s() hpa 0x%lx IOV %dMB (%d bits)\n",
1424 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
1425 iov_order + PAGE_SHIFT);
1426
1427 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1428 get_order(ioc->pdir_size));
1429 if (!ioc->pdir_base)
1430 panic("Couldn't allocate I/O Page Table\n");
1431
1432 memset(ioc->pdir_base, 0, ioc->pdir_size);
1433
1434 DBG_INIT("%s() pdir %p size %x\n",
1435 __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
1436
Grant Grundler64908ad2005-10-21 22:37:20 -04001437#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1439 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1440
1441 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1442 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1443#endif
1444
1445 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1446 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1447
1448 /* build IMASK for IOC and Elroy */
1449 iova_space_mask = 0xffffffff;
1450 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1451 ioc->imask = iova_space_mask;
1452#ifdef ZX1_SUPPORT
1453 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1454#endif
1455 sba_dump_tlb(ioc->ioc_hpa);
1456
1457 setup_ibase_imask(sba, ioc, ioc_num);
1458
1459 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1460
Grant Grundler64908ad2005-10-21 22:37:20 -04001461#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 /*
1463 ** Setting the upper bits makes checking for bypass addresses
1464 ** a little faster later on.
1465 */
1466 ioc->imask |= 0xFFFFFFFF00000000UL;
1467#endif
1468
1469 /* Set I/O PDIR Page size to system page size */
1470 switch (PAGE_SHIFT) {
1471 case 12: tcnfg = 0; break; /* 4K */
1472 case 13: tcnfg = 1; break; /* 8K */
1473 case 14: tcnfg = 2; break; /* 16K */
1474 case 16: tcnfg = 3; break; /* 64K */
1475 default:
1476 panic(__FILE__ "Unsupported system page size %d",
1477 1 << PAGE_SHIFT);
1478 break;
1479 }
1480 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1481
1482 /*
1483 ** Program the IOC's ibase and enable IOVA translation
1484 ** Bit zero == enable bit.
1485 */
1486 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1487
1488 /*
1489 ** Clear I/O TLB of any possible entries.
1490 ** (Yes. This is a bit paranoid...but so what)
1491 */
1492 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1493
Grant Grundler64908ad2005-10-21 22:37:20 -04001494#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495 /*
1496 ** If an AGP device is present, only use half of the IOV space
1497 ** for PCI DMA. Unfortunately we can't know ahead of time
1498 ** whether GART support will actually be used, for now we
1499 ** can just key on any AGP device found in the system.
1500 ** We program the next pdir index after we stop w/ a key for
1501 ** the GART code to handshake on.
1502 */
1503 device=NULL;
1504 for (lba = sba->child; lba; lba = lba->sibling) {
1505 if (IS_QUICKSILVER(lba))
1506 break;
1507 }
1508
1509 if (lba) {
1510 DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
1511 ioc->pdir_size /= 2;
1512 ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
1513 } else {
1514 DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
1515 }
1516#endif /* 0 */
1517
1518}
1519
1520static void
1521sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1522{
1523 u32 iova_space_size, iova_space_mask;
1524 unsigned int pdir_size, iov_order;
1525
1526 /*
1527 ** Determine IOVA Space size from memory size.
1528 **
1529 ** Ideally, PCI drivers would register the maximum number
1530 ** of DMA they can have outstanding for each device they
1531 ** own. Next best thing would be to guess how much DMA
1532 ** can be outstanding based on PCI Class/sub-class. Both
1533 ** methods still require some "extra" to support PCI
1534 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1535 **
1536 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1537 ** for DMA hints - ergo only 30 bits max.
1538 */
1539
1540 iova_space_size = (u32) (num_physpages/global_ioc_cnt);
1541
1542 /* limit IOVA space size to 1MB-1GB */
1543 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1544 iova_space_size = 1 << (20 - PAGE_SHIFT);
1545 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001546 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1547 iova_space_size = 1 << (30 - PAGE_SHIFT);
1548 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549
1550 /*
1551 ** iova space must be log2() in size.
1552 ** thus, pdir/res_map will also be log2().
1553 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1554 */
1555 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1556
1557 /* iova_space_size is now bytes, not pages */
1558 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1559
1560 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1561
1562 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1563 __FUNCTION__,
1564 ioc->ioc_hpa,
1565 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1566 iova_space_size>>20,
1567 iov_order + PAGE_SHIFT);
1568
1569 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1570
1571 DBG_INIT("%s() pdir %p size %x\n",
1572 __FUNCTION__, ioc->pdir_base, pdir_size);
1573
Grant Grundler64908ad2005-10-21 22:37:20 -04001574#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575 /* FIXME : DMA HINTs not used */
1576 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1577 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1578
1579 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1580 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1581#endif
1582
1583 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1584
1585 /* build IMASK for IOC and Elroy */
1586 iova_space_mask = 0xffffffff;
1587 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1588
1589 /*
1590 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1591 ** ibase=0, imask=0xFE000000, size=0x2000000.
1592 */
1593 ioc->ibase = 0;
1594 ioc->imask = iova_space_mask; /* save it */
1595#ifdef ZX1_SUPPORT
1596 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1597#endif
1598
1599 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1600 __FUNCTION__, ioc->ibase, ioc->imask);
1601
1602 /*
1603 ** FIXME: Hint registers are programmed with default hint
1604 ** values during boot, so hints should be sane even if we
1605 ** can't reprogram them the way drivers want.
1606 */
1607
1608 setup_ibase_imask(sba, ioc, ioc_num);
1609
1610 /*
1611 ** Program the IOC's ibase and enable IOVA translation
1612 */
1613 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1614 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1615
1616 /* Set I/O PDIR Page size to 4K */
1617 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1618
1619 /*
1620 ** Clear I/O TLB of any possible entries.
1621 ** (Yes. This is a bit paranoid...but so what)
1622 */
1623 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1624
1625 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1626
1627 DBG_INIT("%s() DONE\n", __FUNCTION__);
1628}
1629
1630
1631
1632/**************************************************************************
1633**
1634** SBA initialization code (HW and SW)
1635**
1636** o identify SBA chip itself
1637** o initialize SBA chip modes (HardFail)
1638** o initialize SBA chip modes (HardFail)
1639** o FIXME: initialize DMA hints for reasonable defaults
1640**
1641**************************************************************************/
1642
1643static void __iomem *ioc_remap(struct sba_device *sba_dev, int offset)
1644{
Matthew Wilcox53f01bb2005-10-21 22:36:40 -04001645 return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646}
1647
1648static void sba_hw_init(struct sba_device *sba_dev)
1649{
1650 int i;
1651 int num_ioc;
1652 u64 ioc_ctl;
1653
1654 if (!is_pdc_pat()) {
1655 /* Shutdown the USB controller on Astro-based workstations.
1656 ** Once we reprogram the IOMMU, the next DMA performed by
1657 ** USB will HPMC the box. USB is only enabled if a
1658 ** keyboard is present and found.
1659 **
1660 ** With serial console, j6k v5.0 firmware says:
1661 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1662 **
1663 ** FIXME: Using GFX+USB console at power up but direct
1664 ** linux to serial console is still broken.
1665 ** USB could generate DMA so we must reset USB.
1666 ** The proper sequence would be:
1667 ** o block console output
1668 ** o reset USB device
1669 ** o reprogram serial port
1670 ** o unblock console output
1671 */
1672 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1673 pdc_io_reset_devices();
1674 }
1675
1676 }
1677
1678
1679#if 0
1680printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1681 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1682
1683 /*
1684 ** Need to deal with DMA from LAN.
1685 ** Maybe use page zero boot device as a handle to talk
1686 ** to PDC about which device to shutdown.
1687 **
1688 ** Netbooting, j6k v5.0 firmware says:
1689 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1690 ** ARGH! invalid class.
1691 */
1692 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1693 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1694 pdc_io_reset();
1695 }
1696#endif
1697
1698 if (!IS_PLUTO(sba_dev->iodc)) {
1699 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1700 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1701 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1702 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1703 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1704 /* j6700 v1.6 firmware sets 0x294f */
1705 /* A500 firmware sets 0x4d */
1706
1707 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1708
1709#ifdef DEBUG_SBA_INIT
1710 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1711 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1712#endif
1713 } /* if !PLUTO */
1714
1715 if (IS_ASTRO(sba_dev->iodc)) {
1716 int err;
1717 /* PAT_PDC (L-class) also reports the same goofy base */
1718 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1719 num_ioc = 1;
1720
1721 sba_dev->chip_resv.name = "Astro Intr Ack";
1722 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1723 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1724 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1725 if (err < 0) {
1726 BUG();
1727 }
1728
1729 } else if (IS_PLUTO(sba_dev->iodc)) {
1730 int err;
1731
1732 /* We use a negative value for IOC HPA so it gets
1733 * corrected when we add it with IKE's IOC offset.
1734 * Doesnt look clean, but fewer code.
1735 */
1736 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1737 num_ioc = 1;
1738
1739 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1740 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1741 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1742 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1743 WARN_ON(err < 0);
1744
1745 sba_dev->iommu_resv.name = "IOVA Space";
1746 sba_dev->iommu_resv.start = 0x40000000UL;
1747 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1748 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1749 WARN_ON(err < 0);
1750 } else {
1751 /* IS_IKE (ie N-class, L3000, L1500) */
1752 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1753 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1754 num_ioc = 2;
1755
1756 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1757 }
1758 /* XXX: What about Reo? */
1759
1760 sba_dev->num_ioc = num_ioc;
1761 for (i = 0; i < num_ioc; i++) {
1762 /*
1763 ** Make sure the box crashes if we get any errors on a rope.
1764 */
1765 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE0_CTL);
1766 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE1_CTL);
1767 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE2_CTL);
1768 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE3_CTL);
1769 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE4_CTL);
1770 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE5_CTL);
1771 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE6_CTL);
1772 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1773
1774 /* flush out the writes */
1775 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1776
1777 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1778 i,
1779 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1780 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1781 );
1782 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1783 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1784 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1785 );
1786
1787 if (IS_PLUTO(sba_dev->iodc)) {
1788 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1789 } else {
1790 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1791 }
1792 }
1793}
1794
1795static void
1796sba_common_init(struct sba_device *sba_dev)
1797{
1798 int i;
1799
1800 /* add this one to the head of the list (order doesn't matter)
1801 ** This will be useful for debugging - especially if we get coredumps
1802 */
1803 sba_dev->next = sba_list;
1804 sba_list = sba_dev;
1805
1806 for(i=0; i< sba_dev->num_ioc; i++) {
1807 int res_size;
1808#ifdef DEBUG_DMB_TRAP
1809 extern void iterate_pages(unsigned long , unsigned long ,
1810 void (*)(pte_t * , unsigned long),
1811 unsigned long );
1812 void set_data_memory_break(pte_t * , unsigned long);
1813#endif
1814 /* resource map size dictated by pdir_size */
1815 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1816
1817 /* Second part of PIRANHA BUG */
1818 if (piranha_bad_128k) {
1819 res_size -= (128*1024)/sizeof(u64);
1820 }
1821
1822 res_size >>= 3; /* convert bit count to byte count */
1823 DBG_INIT("%s() res_size 0x%x\n",
1824 __FUNCTION__, res_size);
1825
1826 sba_dev->ioc[i].res_size = res_size;
1827 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1828
1829#ifdef DEBUG_DMB_TRAP
1830 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1831 set_data_memory_break, 0);
1832#endif
1833
1834 if (NULL == sba_dev->ioc[i].res_map)
1835 {
1836 panic("%s:%s() could not allocate resource map\n",
1837 __FILE__, __FUNCTION__ );
1838 }
1839
1840 memset(sba_dev->ioc[i].res_map, 0, res_size);
1841 /* next available IOVP - circular search */
1842 sba_dev->ioc[i].res_hint = (unsigned long *)
1843 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1844
1845#ifdef ASSERT_PDIR_SANITY
1846 /* Mark first bit busy - ie no IOVA 0 */
1847 sba_dev->ioc[i].res_map[0] = 0x80;
1848 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1849#endif
1850
1851 /* Third (and last) part of PIRANHA BUG */
1852 if (piranha_bad_128k) {
1853 /* region from +1408K to +1536 is un-usable. */
1854
1855 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1856 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1857 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1858 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1859
1860 /* mark that part of the io pdir busy */
1861 while (p_start < p_end)
1862 *p_start++ = -1;
1863
1864 }
1865
1866#ifdef DEBUG_DMB_TRAP
1867 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1868 set_data_memory_break, 0);
1869 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1870 set_data_memory_break, 0);
1871#endif
1872
1873 DBG_INIT("%s() %d res_map %x %p\n",
1874 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1875 }
1876
1877 spin_lock_init(&sba_dev->sba_lock);
1878 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1879
1880#ifdef DEBUG_SBA_INIT
1881 /*
1882 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1883 * (bit #61, big endian), we have to flush and sync every time
1884 * IO-PDIR is changed in Ike/Astro.
1885 */
1886 if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) {
1887 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1888 } else {
1889 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1890 }
1891#endif
1892}
1893
1894#ifdef CONFIG_PROC_FS
1895static int sba_proc_info(char *buf, char **start, off_t offset, int len)
1896{
1897 struct sba_device *sba_dev = sba_list;
1898 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1899 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1900 unsigned long i;
1901#ifdef SBA_COLLECT_STATS
1902 unsigned long avg = 0, min, max;
1903#endif
1904
1905 sprintf(buf, "%s rev %d.%d\n",
1906 sba_dev->name,
1907 (sba_dev->hw_rev & 0x7) + 1,
1908 (sba_dev->hw_rev & 0x18) >> 3
1909 );
1910 sprintf(buf, "%sIO PDIR size : %d bytes (%d entries)\n",
1911 buf,
1912 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1913 total_pages);
1914
1915 sprintf(buf, "%sResource bitmap : %d bytes (%d pages)\n",
1916 buf, ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1917
1918 sprintf(buf, "%sLMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1919 buf,
1920 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1921 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1922 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1923 );
1924
1925 for (i=0; i<4; i++)
1926 sprintf(buf, "%sDIR%ld_BASE/MASK/ROUTE %08x %08x %08x\n",
1927 buf, i,
1928 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1929 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1930 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1931 );
1932
1933#ifdef SBA_COLLECT_STATS
1934 sprintf(buf, "%sIO PDIR entries : %ld free %ld used (%d%%)\n", buf,
1935 total_pages - ioc->used_pages, ioc->used_pages,
1936 (int) (ioc->used_pages * 100 / total_pages));
1937
1938 min = max = ioc->avg_search[0];
1939 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1940 avg += ioc->avg_search[i];
1941 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1942 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1943 }
1944 avg /= SBA_SEARCH_SAMPLE;
1945 sprintf(buf, "%s Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1946 buf, min, avg, max);
1947
1948 sprintf(buf, "%spci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1949 buf, ioc->msingle_calls, ioc->msingle_pages,
1950 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1951
1952 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1953 min = ioc->usingle_calls;
1954 max = ioc->usingle_pages - ioc->usg_pages;
1955 sprintf(buf, "%spci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1956 buf, min, max,
1957 (int) ((max * 1000)/min));
1958
1959 sprintf(buf, "%spci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1960 buf, ioc->msg_calls, ioc->msg_pages,
1961 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1962
1963 sprintf(buf, "%spci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1964 buf, ioc->usg_calls, ioc->usg_pages,
1965 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1966#endif
1967
1968 return strlen(buf);
1969}
1970
1971#if 0
1972/* XXX too much output - exceeds 4k limit and needs to be re-written */
1973static int
1974sba_resource_map(char *buf, char **start, off_t offset, int len)
1975{
1976 struct sba_device *sba_dev = sba_list;
1977 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Mutli-IOC suppoer! */
1978 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
1979 int i;
1980
1981 buf[0] = '\0';
1982 for(i = 0; i < (ioc->res_size / sizeof(unsigned int)); ++i, ++res_ptr) {
1983 if ((i & 7) == 0)
1984 strcat(buf,"\n ");
1985 sprintf(buf, "%s %08x", buf, *res_ptr);
1986 }
1987 strcat(buf, "\n");
1988
1989 return strlen(buf);
1990}
1991#endif /* 0 */
1992#endif /* CONFIG_PROC_FS */
1993
1994static struct parisc_device_id sba_tbl[] = {
1995 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1996 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1997 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1998 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1999 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
2000 { 0, }
2001};
2002
2003int sba_driver_callback(struct parisc_device *);
2004
2005static struct parisc_driver sba_driver = {
2006 .name = MODULE_NAME,
2007 .id_table = sba_tbl,
2008 .probe = sba_driver_callback,
2009};
2010
2011/*
2012** Determine if sba should claim this chip (return 0) or not (return 1).
2013** If so, initialize the chip and tell other partners in crime they
2014** have work to do.
2015*/
2016int
2017sba_driver_callback(struct parisc_device *dev)
2018{
2019 struct sba_device *sba_dev;
2020 u32 func_class;
2021 int i;
2022 char *version;
Matthew Wilcox53f01bb2005-10-21 22:36:40 -04002023 void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002024
2025 sba_dump_ranges(sba_addr);
2026
2027 /* Read HW Rev First */
2028 func_class = READ_REG(sba_addr + SBA_FCLASS);
2029
2030 if (IS_ASTRO(&dev->id)) {
2031 unsigned long fclass;
2032 static char astro_rev[]="Astro ?.?";
2033
2034 /* Astro is broken...Read HW Rev First */
2035 fclass = READ_REG(sba_addr);
2036
2037 astro_rev[6] = '1' + (char) (fclass & 0x7);
2038 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
2039 version = astro_rev;
2040
2041 } else if (IS_IKE(&dev->id)) {
2042 static char ike_rev[] = "Ike rev ?";
2043 ike_rev[8] = '0' + (char) (func_class & 0xff);
2044 version = ike_rev;
2045 } else if (IS_PLUTO(&dev->id)) {
2046 static char pluto_rev[]="Pluto ?.?";
2047 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
2048 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
2049 version = pluto_rev;
2050 } else {
2051 static char reo_rev[] = "REO rev ?";
2052 reo_rev[8] = '0' + (char) (func_class & 0xff);
2053 version = reo_rev;
2054 }
2055
2056 if (!global_ioc_cnt) {
2057 global_ioc_cnt = count_parisc_driver(&sba_driver);
2058
2059 /* Astro and Pluto have one IOC per SBA */
2060 if ((!IS_ASTRO(&dev->id)) || (!IS_PLUTO(&dev->id)))
2061 global_ioc_cnt *= 2;
2062 }
2063
2064 printk(KERN_INFO "%s found %s at 0x%lx\n",
Matthew Wilcox53f01bb2005-10-21 22:36:40 -04002065 MODULE_NAME, version, dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002066
2067 sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
2068 if (!sba_dev) {
2069 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
2070 return -ENOMEM;
2071 }
2072
2073 parisc_set_drvdata(dev, sba_dev);
2074 memset(sba_dev, 0, sizeof(struct sba_device));
2075
2076 for(i=0; i<MAX_IOC; i++)
2077 spin_lock_init(&(sba_dev->ioc[i].res_lock));
2078
2079 sba_dev->dev = dev;
2080 sba_dev->hw_rev = func_class;
2081 sba_dev->iodc = &dev->id;
2082 sba_dev->name = dev->name;
2083 sba_dev->sba_hpa = sba_addr;
2084
2085 sba_get_pat_resources(sba_dev);
2086 sba_hw_init(sba_dev);
2087 sba_common_init(sba_dev);
2088
2089 hppa_dma_ops = &sba_ops;
2090
2091#ifdef CONFIG_PROC_FS
2092 if (IS_ASTRO(&dev->id)) {
2093 create_proc_info_entry("Astro", 0, proc_runway_root, sba_proc_info);
2094 } else if (IS_IKE(&dev->id)) {
2095 create_proc_info_entry("Ike", 0, proc_runway_root, sba_proc_info);
2096 } else if (IS_PLUTO(&dev->id)) {
2097 create_proc_info_entry("Pluto", 0, proc_mckinley_root, sba_proc_info);
2098 } else {
2099 create_proc_info_entry("Reo", 0, proc_runway_root, sba_proc_info);
2100 }
2101#if 0
2102 create_proc_info_entry("bitmap", 0, proc_runway_root, sba_resource_map);
2103#endif
2104#endif
2105 parisc_vmerge_boundary = IOVP_SIZE;
2106 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
2107 parisc_has_iommu();
2108 return 0;
2109}
2110
2111/*
2112** One time initialization to let the world know the SBA was found.
2113** This is the only routine which is NOT static.
2114** Must be called exactly once before pci_init().
2115*/
2116void __init sba_init(void)
2117{
2118 register_parisc_driver(&sba_driver);
2119}
2120
2121
2122/**
2123 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2124 * @dev: The parisc device.
2125 *
2126 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2127 * This is cached and used later for PCI DMA Mapping.
2128 */
2129void * sba_get_iommu(struct parisc_device *pci_hba)
2130{
2131 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2132 struct sba_device *sba = sba_dev->dev.driver_data;
2133 char t = sba_dev->id.hw_type;
2134 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2135
2136 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2137
2138 return &(sba->ioc[iocnum]);
2139}
2140
2141
2142/**
2143 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2144 * @pa_dev: The parisc device.
2145 * @r: resource PCI host controller wants start/end fields assigned.
2146 *
2147 * For the given parisc PCI controller, determine if any direct ranges
2148 * are routed down the corresponding rope.
2149 */
2150void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2151{
2152 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2153 struct sba_device *sba = sba_dev->dev.driver_data;
2154 char t = sba_dev->id.hw_type;
2155 int i;
2156 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2157
2158 if ((t!=HPHW_IOA) && (t!=HPHW_BCPORT))
2159 BUG();
2160
2161 r->start = r->end = 0;
2162
2163 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2164 for (i=0; i<4; i++) {
2165 int base, size;
2166 void __iomem *reg = sba->sba_hpa + i*0x18;
2167
2168 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2169 if ((base & 1) == 0)
2170 continue; /* not enabled */
2171
2172 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2173
2174 if ((size & (ROPES_PER_IOC-1)) != rope)
2175 continue; /* directed down different rope */
2176
2177 r->start = (base & ~1UL) | PCI_F_EXTEND;
2178 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2179 r->end = r->start + size;
2180 }
2181}
2182
2183
2184/**
2185 * sba_distributed_lmmio - return portion of distributed LMMIO range
2186 * @pa_dev: The parisc device.
2187 * @r: resource PCI host controller wants start/end fields assigned.
2188 *
2189 * For the given parisc PCI controller, return portion of distributed LMMIO
2190 * range. The distributed LMMIO is always present and it's just a question
2191 * of the base address and size of the range.
2192 */
2193void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2194{
2195 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2196 struct sba_device *sba = sba_dev->dev.driver_data;
2197 char t = sba_dev->id.hw_type;
2198 int base, size;
2199 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2200
2201 if ((t!=HPHW_IOA) && (t!=HPHW_BCPORT))
2202 BUG();
2203
2204 r->start = r->end = 0;
2205
2206 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2207 if ((base & 1) == 0) {
2208 BUG(); /* Gah! Distr Range wasn't enabled! */
2209 return;
2210 }
2211
2212 r->start = (base & ~1UL) | PCI_F_EXTEND;
2213
2214 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2215 r->start += rope * (size + 1); /* adjust base for this rope */
2216 r->end = r->start + size;
2217}