Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Support for a cx23417 mpeg encoder via cx231xx host port. |
| 4 | * |
| 5 | * (c) 2004 Jelle Foks <jelle@foks.us> |
| 6 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> |
| 7 | * (c) 2008 Steven Toth <stoth@linuxtv.org> |
| 8 | * - CX23885/7/8 support |
| 9 | * |
| 10 | * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/), |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | */ |
| 26 | |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/moduleparam.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/fs.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/device.h> |
| 33 | #include <linux/firmware.h> |
Stephen Rothwell | 9439943 | 2010-10-19 18:07:30 +1100 | [diff] [blame] | 34 | #include <linux/vmalloc.h> |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 35 | #include <media/v4l2-common.h> |
| 36 | #include <media/v4l2-ioctl.h> |
| 37 | #include <media/cx2341x.h> |
| 38 | #include <linux/usb.h> |
| 39 | |
| 40 | #include "cx231xx.h" |
| 41 | /*#include "cx23885-ioctl.h"*/ |
| 42 | |
| 43 | #define CX231xx_FIRM_IMAGE_SIZE 376836 |
| 44 | #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" |
| 45 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 46 | /* for polaris ITVC */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 47 | #define ITVC_WRITE_DIR 0x03FDFC00 |
| 48 | #define ITVC_READ_DIR 0x0001FC00 |
| 49 | |
| 50 | #define MCI_MEMORY_DATA_BYTE0 0x00 |
| 51 | #define MCI_MEMORY_DATA_BYTE1 0x08 |
| 52 | #define MCI_MEMORY_DATA_BYTE2 0x10 |
| 53 | #define MCI_MEMORY_DATA_BYTE3 0x18 |
| 54 | |
| 55 | #define MCI_MEMORY_ADDRESS_BYTE2 0x20 |
| 56 | #define MCI_MEMORY_ADDRESS_BYTE1 0x28 |
| 57 | #define MCI_MEMORY_ADDRESS_BYTE0 0x30 |
| 58 | |
| 59 | #define MCI_REGISTER_DATA_BYTE0 0x40 |
| 60 | #define MCI_REGISTER_DATA_BYTE1 0x48 |
| 61 | #define MCI_REGISTER_DATA_BYTE2 0x50 |
| 62 | #define MCI_REGISTER_DATA_BYTE3 0x58 |
| 63 | |
| 64 | #define MCI_REGISTER_ADDRESS_BYTE0 0x60 |
| 65 | #define MCI_REGISTER_ADDRESS_BYTE1 0x68 |
| 66 | |
| 67 | #define MCI_REGISTER_MODE 0x70 |
| 68 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 69 | /* Read and write modes for polaris ITVC */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 70 | #define MCI_MODE_REGISTER_READ 0x000 |
| 71 | #define MCI_MODE_REGISTER_WRITE 0x100 |
| 72 | #define MCI_MODE_MEMORY_READ 0x000 |
| 73 | #define MCI_MODE_MEMORY_WRITE 0x4000 |
| 74 | |
| 75 | static unsigned int mpegbufs = 8; |
| 76 | module_param(mpegbufs, int, 0644); |
| 77 | MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); |
| 78 | static unsigned int mpeglines = 128; |
| 79 | module_param(mpeglines, int, 0644); |
| 80 | MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); |
| 81 | static unsigned int mpeglinesize = 512; |
| 82 | module_param(mpeglinesize, int, 0644); |
| 83 | MODULE_PARM_DESC(mpeglinesize, |
| 84 | "number of bytes in each line of an MPEG buffer, range 512-1024"); |
| 85 | |
| 86 | static unsigned int v4l_debug = 1; |
| 87 | module_param(v4l_debug, int, 0644); |
| 88 | MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); |
| 89 | struct cx231xx_dmaqueue *dma_qq; |
| 90 | #define dprintk(level, fmt, arg...)\ |
| 91 | do { if (v4l_debug >= level) \ |
| 92 | printk(KERN_INFO "%s: " fmt, \ |
| 93 | (dev) ? dev->name : "cx231xx[?]", ## arg); \ |
| 94 | } while (0) |
| 95 | |
| 96 | static struct cx231xx_tvnorm cx231xx_tvnorms[] = { |
| 97 | { |
| 98 | .name = "NTSC-M", |
| 99 | .id = V4L2_STD_NTSC_M, |
| 100 | }, { |
| 101 | .name = "NTSC-JP", |
| 102 | .id = V4L2_STD_NTSC_M_JP, |
| 103 | }, { |
| 104 | .name = "PAL-BG", |
| 105 | .id = V4L2_STD_PAL_BG, |
| 106 | }, { |
| 107 | .name = "PAL-DK", |
| 108 | .id = V4L2_STD_PAL_DK, |
| 109 | }, { |
| 110 | .name = "PAL-I", |
| 111 | .id = V4L2_STD_PAL_I, |
| 112 | }, { |
| 113 | .name = "PAL-M", |
| 114 | .id = V4L2_STD_PAL_M, |
| 115 | }, { |
| 116 | .name = "PAL-N", |
| 117 | .id = V4L2_STD_PAL_N, |
| 118 | }, { |
| 119 | .name = "PAL-Nc", |
| 120 | .id = V4L2_STD_PAL_Nc, |
| 121 | }, { |
| 122 | .name = "PAL-60", |
| 123 | .id = V4L2_STD_PAL_60, |
| 124 | }, { |
| 125 | .name = "SECAM-L", |
| 126 | .id = V4L2_STD_SECAM_L, |
| 127 | }, { |
| 128 | .name = "SECAM-DK", |
| 129 | .id = V4L2_STD_SECAM_DK, |
| 130 | } |
| 131 | }; |
| 132 | |
| 133 | /* ------------------------------------------------------------------ */ |
| 134 | enum cx231xx_capture_type { |
| 135 | CX231xx_MPEG_CAPTURE, |
| 136 | CX231xx_RAW_CAPTURE, |
| 137 | CX231xx_RAW_PASSTHRU_CAPTURE |
| 138 | }; |
| 139 | enum cx231xx_capture_bits { |
| 140 | CX231xx_RAW_BITS_NONE = 0x00, |
| 141 | CX231xx_RAW_BITS_YUV_CAPTURE = 0x01, |
| 142 | CX231xx_RAW_BITS_PCM_CAPTURE = 0x02, |
| 143 | CX231xx_RAW_BITS_VBI_CAPTURE = 0x04, |
| 144 | CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08, |
| 145 | CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10 |
| 146 | }; |
| 147 | enum cx231xx_capture_end { |
| 148 | CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */ |
| 149 | CX231xx_END_NOW, /* stop immediately, no irq */ |
| 150 | }; |
| 151 | enum cx231xx_framerate { |
| 152 | CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */ |
| 153 | CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */ |
| 154 | }; |
| 155 | enum cx231xx_stream_port { |
| 156 | CX231xx_OUTPUT_PORT_MEMORY, |
| 157 | CX231xx_OUTPUT_PORT_STREAMING, |
| 158 | CX231xx_OUTPUT_PORT_SERIAL |
| 159 | }; |
| 160 | enum cx231xx_data_xfer_status { |
| 161 | CX231xx_MORE_BUFFERS_FOLLOW, |
| 162 | CX231xx_LAST_BUFFER, |
| 163 | }; |
| 164 | enum cx231xx_picture_mask { |
| 165 | CX231xx_PICTURE_MASK_NONE, |
| 166 | CX231xx_PICTURE_MASK_I_FRAMES, |
| 167 | CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3, |
| 168 | CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7, |
| 169 | }; |
| 170 | enum cx231xx_vbi_mode_bits { |
| 171 | CX231xx_VBI_BITS_SLICED, |
| 172 | CX231xx_VBI_BITS_RAW, |
| 173 | }; |
| 174 | enum cx231xx_vbi_insertion_bits { |
| 175 | CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, |
| 176 | CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, |
| 177 | CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1, |
| 178 | CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, |
| 179 | CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, |
| 180 | }; |
| 181 | enum cx231xx_dma_unit { |
| 182 | CX231xx_DMA_BYTES, |
| 183 | CX231xx_DMA_FRAMES, |
| 184 | }; |
| 185 | enum cx231xx_dma_transfer_status_bits { |
| 186 | CX231xx_DMA_TRANSFER_BITS_DONE = 0x01, |
| 187 | CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04, |
| 188 | CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10, |
| 189 | }; |
| 190 | enum cx231xx_pause { |
| 191 | CX231xx_PAUSE_ENCODING, |
| 192 | CX231xx_RESUME_ENCODING, |
| 193 | }; |
| 194 | enum cx231xx_copyright { |
| 195 | CX231xx_COPYRIGHT_OFF, |
| 196 | CX231xx_COPYRIGHT_ON, |
| 197 | }; |
| 198 | enum cx231xx_notification_type { |
| 199 | CX231xx_NOTIFICATION_REFRESH, |
| 200 | }; |
| 201 | enum cx231xx_notification_status { |
| 202 | CX231xx_NOTIFICATION_OFF, |
| 203 | CX231xx_NOTIFICATION_ON, |
| 204 | }; |
| 205 | enum cx231xx_notification_mailbox { |
| 206 | CX231xx_NOTIFICATION_NO_MAILBOX = -1, |
| 207 | }; |
| 208 | enum cx231xx_field1_lines { |
| 209 | CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */ |
| 210 | CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */ |
| 211 | CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */ |
| 212 | }; |
| 213 | enum cx231xx_field2_lines { |
| 214 | CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */ |
| 215 | CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */ |
| 216 | CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */ |
| 217 | }; |
| 218 | enum cx231xx_custom_data_type { |
| 219 | CX231xx_CUSTOM_EXTENSION_USR_DATA, |
| 220 | CX231xx_CUSTOM_PRIVATE_PACKET, |
| 221 | }; |
| 222 | enum cx231xx_mute { |
| 223 | CX231xx_UNMUTE, |
| 224 | CX231xx_MUTE, |
| 225 | }; |
| 226 | enum cx231xx_mute_video_mask { |
| 227 | CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00, |
| 228 | CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000, |
| 229 | CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000, |
| 230 | }; |
| 231 | enum cx231xx_mute_video_shift { |
| 232 | CX231xx_MUTE_VIDEO_V_SHIFT = 8, |
| 233 | CX231xx_MUTE_VIDEO_U_SHIFT = 16, |
| 234 | CX231xx_MUTE_VIDEO_Y_SHIFT = 24, |
| 235 | }; |
| 236 | |
| 237 | /* defines below are from ivtv-driver.h */ |
| 238 | #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF |
| 239 | |
| 240 | /* Firmware API commands */ |
| 241 | #define IVTV_API_STD_TIMEOUT 500 |
| 242 | |
| 243 | /* Registers */ |
| 244 | /* IVTV_REG_OFFSET */ |
| 245 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) |
| 246 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) |
| 247 | #define IVTV_REG_SPU (0x9050) |
| 248 | #define IVTV_REG_HW_BLOCKS (0x9054) |
| 249 | #define IVTV_REG_VPU (0x9058) |
| 250 | #define IVTV_REG_APU (0xA064) |
| 251 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 252 | /* |
| 253 | * Bit definitions for MC417_RWD and MC417_OEN registers |
| 254 | * |
| 255 | * bits 31-16 |
| 256 | *+-----------+ |
| 257 | *| Reserved | |
| 258 | *|+-----------+ |
| 259 | *| bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 |
| 260 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ |
| 261 | *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| |
| 262 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ |
| 263 | *| bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 |
| 264 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ |
| 265 | *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| |
| 266 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ |
| 267 | */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 268 | #define MC417_MIWR 0x8000 |
| 269 | #define MC417_MIRD 0x4000 |
| 270 | #define MC417_MICS 0x2000 |
| 271 | #define MC417_MIRDY 0x1000 |
| 272 | #define MC417_MIADDR 0x0F00 |
| 273 | #define MC417_MIDATA 0x00FF |
| 274 | |
| 275 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 276 | /* Bit definitions for MC417_CTL register **** |
| 277 | *bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 |
| 278 | *+--------+-------------+--------+--------------+------------+ |
| 279 | *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| |
| 280 | *+--------+-------------+--------+--------------+------------+ |
| 281 | */ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 282 | #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) |
| 283 | #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) |
| 284 | #define MC417_UART_GPIO_EN 0x00000001 |
| 285 | |
| 286 | /* Values for speed control */ |
| 287 | #define MC417_SPD_CTL_SLOW 0x1 |
| 288 | #define MC417_SPD_CTL_MEDIUM 0x0 |
| 289 | #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */ |
| 290 | |
| 291 | /* Values for GPIO select */ |
| 292 | #define MC417_GPIO_SEL_GPIO3 0x3 |
| 293 | #define MC417_GPIO_SEL_GPIO2 0x2 |
| 294 | #define MC417_GPIO_SEL_GPIO1 0x1 |
| 295 | #define MC417_GPIO_SEL_GPIO0 0x0 |
| 296 | |
| 297 | |
| 298 | #define CX23417_GPIO_MASK 0xFC0003FF |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 299 | static int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 300 | { |
| 301 | int status = 0; |
| 302 | u32 _gpio_direction = 0; |
| 303 | |
| 304 | _gpio_direction = _gpio_direction & CX23417_GPIO_MASK; |
| 305 | _gpio_direction = _gpio_direction|gpio_direction; |
| 306 | status = cx231xx_send_gpio_cmd(dev, _gpio_direction, |
| 307 | (u8 *)&value, 4, 0, 0); |
| 308 | return status; |
| 309 | } |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 310 | static int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 311 | { |
| 312 | int status = 0; |
| 313 | u32 _gpio_direction = 0; |
| 314 | |
| 315 | _gpio_direction = _gpio_direction & CX23417_GPIO_MASK; |
| 316 | _gpio_direction = _gpio_direction|gpio_direction; |
| 317 | |
| 318 | status = cx231xx_send_gpio_cmd(dev, _gpio_direction, |
| 319 | (u8 *)pValue, 4, 0, 1); |
| 320 | return status; |
| 321 | } |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 322 | |
| 323 | static int waitForMciComplete(struct cx231xx *dev) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 324 | { |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 325 | u32 gpio; |
| 326 | u32 gpio_driection = 0; |
| 327 | u8 count = 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 328 | getITVCReg(dev, gpio_driection, &gpio); |
| 329 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 330 | while (!(gpio&0x020000)) { |
| 331 | msleep(10); |
| 332 | |
| 333 | getITVCReg(dev, gpio_driection, &gpio); |
| 334 | |
| 335 | if (count++ > 100) { |
| 336 | dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio); |
| 337 | return -1; |
| 338 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 339 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 340 | return 0; |
| 341 | } |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 342 | |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 343 | static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 344 | { |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 345 | u32 temp; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 346 | int status = 0; |
| 347 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 348 | temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8); |
| 349 | temp = temp<<10; |
| 350 | status = setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 351 | if (status < 0) |
| 352 | return status; |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 353 | temp = temp|((0x05)<<10); |
| 354 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 355 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 356 | /*write data byte 1;*/ |
| 357 | temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00); |
| 358 | temp = temp<<10; |
| 359 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 360 | temp = temp|((0x05)<<10); |
| 361 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 362 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 363 | /*write data byte 2;*/ |
| 364 | temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8); |
| 365 | temp = temp<<10; |
| 366 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 367 | temp = temp|((0x05)<<10); |
| 368 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 369 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 370 | /*write data byte 3;*/ |
| 371 | temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16); |
| 372 | temp = temp<<10; |
| 373 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 374 | temp = temp|((0x05)<<10); |
| 375 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 376 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 377 | /*write address byte 0;*/ |
| 378 | temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8); |
| 379 | temp = temp<<10; |
| 380 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 381 | temp = temp|((0x05)<<10); |
| 382 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 383 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 384 | /*write address byte 1;*/ |
| 385 | temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00); |
| 386 | temp = temp<<10; |
| 387 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 388 | temp = temp|((0x05)<<10); |
| 389 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 390 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 391 | /*Write that the mode is write.*/ |
| 392 | temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE; |
| 393 | temp = temp<<10; |
| 394 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 395 | temp = temp|((0x05)<<10); |
| 396 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 397 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 398 | return waitForMciComplete(dev); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 399 | } |
| 400 | |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 401 | static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 402 | { |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 403 | /*write address byte 0;*/ |
| 404 | u32 temp; |
| 405 | u32 return_value = 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 406 | int ret = 0; |
| 407 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 408 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
| 409 | temp = temp << 10; |
| 410 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 411 | temp = temp | ((0x05) << 10); |
| 412 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 413 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 414 | /*write address byte 1;*/ |
| 415 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00); |
| 416 | temp = temp << 10; |
| 417 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 418 | temp = temp | ((0x05) << 10); |
| 419 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 420 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 421 | /*write that the mode is read;*/ |
| 422 | temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ; |
| 423 | temp = temp << 10; |
| 424 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 425 | temp = temp | ((0x05) << 10); |
| 426 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 427 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 428 | /*wait for the MIRDY line to be asserted , |
| 429 | signalling that the read is done;*/ |
| 430 | ret = waitForMciComplete(dev); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 431 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 432 | /*switch the DATA- GPIO to input mode;*/ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 433 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 434 | /*Read data byte 0;*/ |
| 435 | temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10; |
| 436 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 437 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10); |
| 438 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 439 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
| 440 | return_value |= ((temp & 0x03FC0000) >> 18); |
| 441 | setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 442 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 443 | /* Read data byte 1;*/ |
| 444 | temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10; |
| 445 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 446 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10); |
| 447 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 448 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 449 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 450 | return_value |= ((temp & 0x03FC0000) >> 10); |
| 451 | setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 452 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 453 | /*Read data byte 2;*/ |
| 454 | temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10; |
| 455 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 456 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10); |
| 457 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 458 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
| 459 | return_value |= ((temp & 0x03FC0000) >> 2); |
| 460 | setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 461 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 462 | /*Read data byte 3;*/ |
| 463 | temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10; |
| 464 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 465 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10); |
| 466 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 467 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
| 468 | return_value |= ((temp & 0x03FC0000) << 6); |
| 469 | setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 470 | |
| 471 | *value = return_value; |
| 472 | |
| 473 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 474 | return ret; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 475 | } |
| 476 | |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 477 | static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 478 | { |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 479 | /*write data byte 0;*/ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 480 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 481 | u32 temp; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 482 | int ret = 0; |
| 483 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 484 | temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8); |
| 485 | temp = temp << 10; |
| 486 | ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 487 | if (ret < 0) |
| 488 | return ret; |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 489 | temp = temp | ((0x05) << 10); |
| 490 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 491 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 492 | /*write data byte 1;*/ |
| 493 | temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00); |
| 494 | temp = temp << 10; |
| 495 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 496 | temp = temp | ((0x05) << 10); |
| 497 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 498 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 499 | /*write data byte 2;*/ |
| 500 | temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); |
| 501 | temp = temp<<10; |
| 502 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 503 | temp = temp|((0x05)<<10); |
| 504 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 505 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 506 | /*write data byte 3;*/ |
| 507 | temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); |
| 508 | temp = temp<<10; |
| 509 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 510 | temp = temp|((0x05)<<10); |
| 511 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 512 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 513 | /* write address byte 2;*/ |
| 514 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 515 | ((address & 0x003F0000)>>8); |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 516 | temp = temp<<10; |
| 517 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 518 | temp = temp|((0x05)<<10); |
| 519 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 520 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 521 | /* write address byte 1;*/ |
| 522 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
| 523 | temp = temp<<10; |
| 524 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 525 | temp = temp|((0x05)<<10); |
| 526 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 527 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 528 | /* write address byte 0;*/ |
| 529 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); |
| 530 | temp = temp<<10; |
| 531 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 532 | temp = temp|((0x05)<<10); |
| 533 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 534 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 535 | /*wait for MIRDY line;*/ |
| 536 | waitForMciComplete(dev); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 537 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 538 | return 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 539 | } |
| 540 | |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 541 | static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 542 | { |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 543 | u32 temp = 0; |
| 544 | u32 return_value = 0; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 545 | int ret = 0; |
| 546 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 547 | /*write address byte 2;*/ |
| 548 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 549 | ((address & 0x003F0000)>>8); |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 550 | temp = temp<<10; |
| 551 | ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 552 | if (ret < 0) |
| 553 | return ret; |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 554 | temp = temp|((0x05)<<10); |
| 555 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 556 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 557 | /*write address byte 1*/ |
| 558 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
| 559 | temp = temp<<10; |
| 560 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 561 | temp = temp|((0x05)<<10); |
| 562 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 563 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 564 | /*write address byte 0*/ |
| 565 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8); |
| 566 | temp = temp<<10; |
| 567 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
| 568 | temp = temp|((0x05)<<10); |
| 569 | setITVCReg(dev, ITVC_WRITE_DIR, temp); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 570 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 571 | /*Wait for MIRDY line*/ |
| 572 | ret = waitForMciComplete(dev); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 573 | |
| 574 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 575 | /*Read data byte 3;*/ |
| 576 | temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10; |
| 577 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 578 | temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10); |
| 579 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 580 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
| 581 | return_value |= ((temp&0x03FC0000)<<6); |
| 582 | setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 583 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 584 | /*Read data byte 2;*/ |
| 585 | temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10; |
| 586 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 587 | temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10); |
| 588 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 589 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
| 590 | return_value |= ((temp&0x03FC0000)>>2); |
| 591 | setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 592 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 593 | /* Read data byte 1;*/ |
| 594 | temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10; |
| 595 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 596 | temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10); |
| 597 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 598 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
| 599 | return_value |= ((temp&0x03FC0000)>>10); |
| 600 | setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 601 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 602 | /*Read data byte 0;*/ |
| 603 | temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10; |
| 604 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 605 | temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10); |
| 606 | setITVCReg(dev, ITVC_READ_DIR, temp); |
| 607 | getITVCReg(dev, ITVC_READ_DIR, &temp); |
| 608 | return_value |= ((temp&0x03FC0000)>>18); |
| 609 | setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 610 | |
| 611 | *value = return_value; |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 612 | return ret; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 613 | } |
| 614 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 615 | /* ------------------------------------------------------------------ */ |
| 616 | |
| 617 | /* MPEG encoder API */ |
| 618 | static char *cmd_to_str(int cmd) |
| 619 | { |
| 620 | switch (cmd) { |
| 621 | case CX2341X_ENC_PING_FW: |
| 622 | return "PING_FW"; |
| 623 | case CX2341X_ENC_START_CAPTURE: |
| 624 | return "START_CAPTURE"; |
| 625 | case CX2341X_ENC_STOP_CAPTURE: |
| 626 | return "STOP_CAPTURE"; |
| 627 | case CX2341X_ENC_SET_AUDIO_ID: |
| 628 | return "SET_AUDIO_ID"; |
| 629 | case CX2341X_ENC_SET_VIDEO_ID: |
| 630 | return "SET_VIDEO_ID"; |
| 631 | case CX2341X_ENC_SET_PCR_ID: |
| 632 | return "SET_PCR_PID"; |
| 633 | case CX2341X_ENC_SET_FRAME_RATE: |
| 634 | return "SET_FRAME_RATE"; |
| 635 | case CX2341X_ENC_SET_FRAME_SIZE: |
| 636 | return "SET_FRAME_SIZE"; |
| 637 | case CX2341X_ENC_SET_BIT_RATE: |
| 638 | return "SET_BIT_RATE"; |
| 639 | case CX2341X_ENC_SET_GOP_PROPERTIES: |
| 640 | return "SET_GOP_PROPERTIES"; |
| 641 | case CX2341X_ENC_SET_ASPECT_RATIO: |
| 642 | return "SET_ASPECT_RATIO"; |
| 643 | case CX2341X_ENC_SET_DNR_FILTER_MODE: |
| 644 | return "SET_DNR_FILTER_PROPS"; |
| 645 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: |
| 646 | return "SET_DNR_FILTER_PROPS"; |
| 647 | case CX2341X_ENC_SET_CORING_LEVELS: |
| 648 | return "SET_CORING_LEVELS"; |
| 649 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: |
| 650 | return "SET_SPATIAL_FILTER_TYPE"; |
| 651 | case CX2341X_ENC_SET_VBI_LINE: |
| 652 | return "SET_VBI_LINE"; |
| 653 | case CX2341X_ENC_SET_STREAM_TYPE: |
| 654 | return "SET_STREAM_TYPE"; |
| 655 | case CX2341X_ENC_SET_OUTPUT_PORT: |
| 656 | return "SET_OUTPUT_PORT"; |
| 657 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: |
| 658 | return "SET_AUDIO_PROPERTIES"; |
| 659 | case CX2341X_ENC_HALT_FW: |
| 660 | return "HALT_FW"; |
| 661 | case CX2341X_ENC_GET_VERSION: |
| 662 | return "GET_VERSION"; |
| 663 | case CX2341X_ENC_SET_GOP_CLOSURE: |
| 664 | return "SET_GOP_CLOSURE"; |
| 665 | case CX2341X_ENC_GET_SEQ_END: |
| 666 | return "GET_SEQ_END"; |
| 667 | case CX2341X_ENC_SET_PGM_INDEX_INFO: |
| 668 | return "SET_PGM_INDEX_INFO"; |
| 669 | case CX2341X_ENC_SET_VBI_CONFIG: |
| 670 | return "SET_VBI_CONFIG"; |
| 671 | case CX2341X_ENC_SET_DMA_BLOCK_SIZE: |
| 672 | return "SET_DMA_BLOCK_SIZE"; |
| 673 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10: |
| 674 | return "GET_PREV_DMA_INFO_MB_10"; |
| 675 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9: |
| 676 | return "GET_PREV_DMA_INFO_MB_9"; |
| 677 | case CX2341X_ENC_SCHED_DMA_TO_HOST: |
| 678 | return "SCHED_DMA_TO_HOST"; |
| 679 | case CX2341X_ENC_INITIALIZE_INPUT: |
| 680 | return "INITIALIZE_INPUT"; |
| 681 | case CX2341X_ENC_SET_FRAME_DROP_RATE: |
| 682 | return "SET_FRAME_DROP_RATE"; |
| 683 | case CX2341X_ENC_PAUSE_ENCODER: |
| 684 | return "PAUSE_ENCODER"; |
| 685 | case CX2341X_ENC_REFRESH_INPUT: |
| 686 | return "REFRESH_INPUT"; |
| 687 | case CX2341X_ENC_SET_COPYRIGHT: |
| 688 | return "SET_COPYRIGHT"; |
| 689 | case CX2341X_ENC_SET_EVENT_NOTIFICATION: |
| 690 | return "SET_EVENT_NOTIFICATION"; |
| 691 | case CX2341X_ENC_SET_NUM_VSYNC_LINES: |
| 692 | return "SET_NUM_VSYNC_LINES"; |
| 693 | case CX2341X_ENC_SET_PLACEHOLDER: |
| 694 | return "SET_PLACEHOLDER"; |
| 695 | case CX2341X_ENC_MUTE_VIDEO: |
| 696 | return "MUTE_VIDEO"; |
| 697 | case CX2341X_ENC_MUTE_AUDIO: |
| 698 | return "MUTE_AUDIO"; |
| 699 | case CX2341X_ENC_MISC: |
| 700 | return "MISC"; |
| 701 | default: |
| 702 | return "UNKNOWN"; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | static int cx231xx_mbox_func(void *priv, |
| 707 | u32 command, |
| 708 | int in, |
| 709 | int out, |
| 710 | u32 data[CX2341X_MBOX_MAX_DATA]) |
| 711 | { |
| 712 | struct cx231xx *dev = priv; |
| 713 | unsigned long timeout; |
| 714 | u32 value, flag, retval = 0; |
| 715 | int i; |
| 716 | |
| 717 | dprintk(3, "%s: command(0x%X) = %s\n", __func__, command, |
| 718 | cmd_to_str(command)); |
| 719 | |
| 720 | /* this may not be 100% safe if we can't read any memory location |
| 721 | without side effects */ |
| 722 | mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); |
| 723 | if (value != 0x12345678) { |
| 724 | dprintk(3, |
| 725 | "Firmware and/or mailbox pointer not initialized " |
| 726 | "or corrupted, signature = 0x%x, cmd = %s\n", value, |
| 727 | cmd_to_str(command)); |
| 728 | return -1; |
| 729 | } |
| 730 | |
| 731 | /* This read looks at 32 bits, but flag is only 8 bits. |
| 732 | * Seems we also bail if CMD or TIMEOUT bytes are set??? |
| 733 | */ |
| 734 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); |
| 735 | if (flag) { |
| 736 | dprintk(3, "ERROR: Mailbox appears to be in use " |
| 737 | "(%x), cmd = %s\n", flag, cmd_to_str(command)); |
| 738 | return -1; |
| 739 | } |
| 740 | |
| 741 | flag |= 1; /* tell 'em we're working on it */ |
| 742 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); |
| 743 | |
| 744 | /* write command + args + fill remaining with zeros */ |
| 745 | /* command code */ |
| 746 | mc417_memory_write(dev, dev->cx23417_mailbox + 1, command); |
| 747 | mc417_memory_write(dev, dev->cx23417_mailbox + 3, |
| 748 | IVTV_API_STD_TIMEOUT); /* timeout */ |
| 749 | for (i = 0; i < in; i++) { |
| 750 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]); |
| 751 | dprintk(3, "API Input %d = %d\n", i, data[i]); |
| 752 | } |
| 753 | for (; i < CX2341X_MBOX_MAX_DATA; i++) |
| 754 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0); |
| 755 | |
| 756 | flag |= 3; /* tell 'em we're done writing */ |
| 757 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); |
| 758 | |
| 759 | /* wait for firmware to handle the API command */ |
| 760 | timeout = jiffies + msecs_to_jiffies(10); |
| 761 | for (;;) { |
| 762 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); |
| 763 | if (0 != (flag & 4)) |
| 764 | break; |
| 765 | if (time_after(jiffies, timeout)) { |
| 766 | dprintk(3, "ERROR: API Mailbox timeout\n"); |
| 767 | return -1; |
| 768 | } |
| 769 | udelay(10); |
| 770 | } |
| 771 | |
| 772 | /* read output values */ |
| 773 | for (i = 0; i < out; i++) { |
| 774 | mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i); |
| 775 | dprintk(3, "API Output %d = %d\n", i, data[i]); |
| 776 | } |
| 777 | |
| 778 | mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval); |
| 779 | dprintk(3, "API result = %d\n", retval); |
| 780 | |
| 781 | flag = 0; |
| 782 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); |
| 783 | |
| 784 | return retval; |
| 785 | } |
| 786 | |
| 787 | /* We don't need to call the API often, so using just one |
| 788 | * mailbox will probably suffice |
| 789 | */ |
| 790 | static int cx231xx_api_cmd(struct cx231xx *dev, |
| 791 | u32 command, |
| 792 | u32 inputcnt, |
| 793 | u32 outputcnt, |
| 794 | ...) |
| 795 | { |
| 796 | u32 data[CX2341X_MBOX_MAX_DATA]; |
| 797 | va_list vargs; |
| 798 | int i, err; |
| 799 | |
| 800 | dprintk(3, "%s() cmds = 0x%08x\n", __func__, command); |
| 801 | |
| 802 | va_start(vargs, outputcnt); |
| 803 | for (i = 0; i < inputcnt; i++) |
| 804 | data[i] = va_arg(vargs, int); |
| 805 | |
| 806 | err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data); |
| 807 | for (i = 0; i < outputcnt; i++) { |
| 808 | int *vptr = va_arg(vargs, int *); |
| 809 | *vptr = data[i]; |
| 810 | } |
| 811 | va_end(vargs); |
| 812 | |
| 813 | return err; |
| 814 | } |
| 815 | |
| 816 | static int cx231xx_find_mailbox(struct cx231xx *dev) |
| 817 | { |
| 818 | u32 signature[4] = { |
| 819 | 0x12345678, 0x34567812, 0x56781234, 0x78123456 |
| 820 | }; |
| 821 | int signaturecnt = 0; |
| 822 | u32 value; |
| 823 | int i; |
| 824 | int ret = 0; |
| 825 | |
| 826 | dprintk(2, "%s()\n", __func__); |
| 827 | |
| 828 | for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/ |
| 829 | ret = mc417_memory_read(dev, i, &value); |
| 830 | if (ret < 0) |
| 831 | return ret; |
| 832 | if (value == signature[signaturecnt]) |
| 833 | signaturecnt++; |
| 834 | else |
| 835 | signaturecnt = 0; |
| 836 | if (4 == signaturecnt) { |
| 837 | dprintk(1, "Mailbox signature found at 0x%x\n", i+1); |
| 838 | return i+1; |
| 839 | } |
| 840 | } |
| 841 | dprintk(3, "Mailbox signature values not found!\n"); |
| 842 | return -1; |
| 843 | } |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 844 | |
| 845 | static void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 846 | u32 *p_fw_image) |
| 847 | { |
| 848 | |
| 849 | u32 temp = 0; |
| 850 | int i = 0; |
| 851 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 852 | temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8); |
| 853 | temp = temp<<10; |
| 854 | *p_fw_image = temp; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 855 | p_fw_image++; |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 856 | temp = temp|((0x05)<<10); |
| 857 | *p_fw_image = temp; |
| 858 | p_fw_image++; |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 859 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 860 | /*write data byte 1;*/ |
| 861 | temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00); |
| 862 | temp = temp<<10; |
| 863 | *p_fw_image = temp; |
| 864 | p_fw_image++; |
| 865 | temp = temp|((0x05)<<10); |
| 866 | *p_fw_image = temp; |
| 867 | p_fw_image++; |
| 868 | |
| 869 | /*write data byte 2;*/ |
| 870 | temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); |
| 871 | temp = temp<<10; |
| 872 | *p_fw_image = temp; |
| 873 | p_fw_image++; |
| 874 | temp = temp|((0x05)<<10); |
| 875 | *p_fw_image = temp; |
| 876 | p_fw_image++; |
| 877 | |
| 878 | /*write data byte 3;*/ |
| 879 | temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); |
| 880 | temp = temp<<10; |
| 881 | *p_fw_image = temp; |
| 882 | p_fw_image++; |
| 883 | temp = temp|((0x05)<<10); |
| 884 | *p_fw_image = temp; |
| 885 | p_fw_image++; |
| 886 | |
| 887 | /* write address byte 2;*/ |
| 888 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | |
| 889 | ((address & 0x003F0000)>>8); |
| 890 | temp = temp<<10; |
| 891 | *p_fw_image = temp; |
| 892 | p_fw_image++; |
| 893 | temp = temp|((0x05)<<10); |
| 894 | *p_fw_image = temp; |
| 895 | p_fw_image++; |
| 896 | |
| 897 | /* write address byte 1;*/ |
| 898 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
| 899 | temp = temp<<10; |
| 900 | *p_fw_image = temp; |
| 901 | p_fw_image++; |
| 902 | temp = temp|((0x05)<<10); |
| 903 | *p_fw_image = temp; |
| 904 | p_fw_image++; |
| 905 | |
| 906 | /* write address byte 0;*/ |
| 907 | temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); |
| 908 | temp = temp<<10; |
| 909 | *p_fw_image = temp; |
| 910 | p_fw_image++; |
| 911 | temp = temp|((0x05)<<10); |
| 912 | *p_fw_image = temp; |
| 913 | p_fw_image++; |
| 914 | |
| 915 | for (i = 0; i < 6; i++) { |
| 916 | *p_fw_image = 0xFFFFFFFF; |
| 917 | p_fw_image++; |
| 918 | } |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 919 | } |
| 920 | |
| 921 | |
| 922 | static int cx231xx_load_firmware(struct cx231xx *dev) |
| 923 | { |
| 924 | static const unsigned char magic[8] = { |
| 925 | 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa |
| 926 | }; |
| 927 | const struct firmware *firmware; |
| 928 | int i, retval = 0; |
| 929 | u32 value = 0; |
| 930 | u32 gpio_output = 0; |
| 931 | /*u32 checksum = 0;*/ |
| 932 | /*u32 *dataptr;*/ |
| 933 | u32 transfer_size = 0; |
| 934 | u32 fw_data = 0; |
| 935 | u32 address = 0; |
| 936 | /*u32 current_fw[800];*/ |
| 937 | u32 *p_current_fw, *p_fw; |
| 938 | u32 *p_fw_data; |
| 939 | int frame = 0; |
| 940 | u16 _buffer_size = 4096; |
| 941 | u8 *p_buffer; |
| 942 | |
| 943 | p_current_fw = (u32 *)vmalloc(1884180*4); |
| 944 | p_fw = p_current_fw; |
| 945 | if (p_current_fw == 0) { |
| 946 | dprintk(2, "FAIL!!!\n"); |
| 947 | return -1; |
| 948 | } |
| 949 | |
| 950 | p_buffer = (u8 *)vmalloc(4096); |
| 951 | if (p_buffer == 0) { |
| 952 | dprintk(2, "FAIL!!!\n"); |
| 953 | return -1; |
| 954 | } |
| 955 | |
| 956 | dprintk(2, "%s()\n", __func__); |
| 957 | |
| 958 | /* Save GPIO settings before reset of APU */ |
| 959 | retval |= mc417_memory_read(dev, 0x9020, &gpio_output); |
| 960 | retval |= mc417_memory_read(dev, 0x900C, &value); |
| 961 | |
| 962 | retval = mc417_register_write(dev, |
| 963 | IVTV_REG_VPU, 0xFFFFFFED); |
| 964 | retval |= mc417_register_write(dev, |
| 965 | IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST); |
| 966 | retval |= mc417_register_write(dev, |
| 967 | IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800); |
| 968 | retval |= mc417_register_write(dev, |
| 969 | IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A); |
| 970 | retval |= mc417_register_write(dev, |
| 971 | IVTV_REG_APU, 0); |
| 972 | |
| 973 | if (retval != 0) { |
| 974 | printk(KERN_ERR "%s: Error with mc417_register_write\n", |
| 975 | __func__); |
| 976 | return -1; |
| 977 | } |
| 978 | |
| 979 | retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME, |
| 980 | &dev->udev->dev); |
| 981 | |
| 982 | if (retval != 0) { |
| 983 | printk(KERN_ERR |
| 984 | "ERROR: Hotplug firmware request failed (%s).\n", |
| 985 | CX231xx_FIRM_IMAGE_NAME); |
| 986 | printk(KERN_ERR "Please fix your hotplug setup, the board will " |
| 987 | "not work without firmware loaded!\n"); |
| 988 | return -1; |
| 989 | } |
| 990 | |
| 991 | if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) { |
| 992 | printk(KERN_ERR "ERROR: Firmware size mismatch " |
| 993 | "(have %zd, expected %d)\n", |
| 994 | firmware->size, CX231xx_FIRM_IMAGE_SIZE); |
| 995 | release_firmware(firmware); |
| 996 | return -1; |
| 997 | } |
| 998 | |
| 999 | if (0 != memcmp(firmware->data, magic, 8)) { |
| 1000 | printk(KERN_ERR |
| 1001 | "ERROR: Firmware magic mismatch, wrong file?\n"); |
| 1002 | release_firmware(firmware); |
| 1003 | return -1; |
| 1004 | } |
| 1005 | |
| 1006 | initGPIO(dev); |
| 1007 | |
| 1008 | /* transfer to the chip */ |
| 1009 | dprintk(2, "Loading firmware to GPIO...\n"); |
| 1010 | p_fw_data = (u32 *)firmware->data; |
Mauro Carvalho Chehab | 62c78c9 | 2010-09-25 23:46:08 -0300 | [diff] [blame] | 1011 | dprintk(2, "firmware->size=%zd\n", firmware->size); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1012 | for (transfer_size = 0; transfer_size < firmware->size; |
| 1013 | transfer_size += 4) { |
| 1014 | fw_data = *p_fw_data; |
| 1015 | |
| 1016 | mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw); |
| 1017 | address = address + 1; |
| 1018 | p_current_fw += 20; |
| 1019 | p_fw_data += 1; |
| 1020 | } |
| 1021 | |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 1022 | /*download the firmware by ep5-out*/ |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1023 | |
| 1024 | for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size); |
Mauro Carvalho Chehab | bae94dc | 2010-10-07 03:33:00 -0300 | [diff] [blame] | 1025 | frame++) { |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1026 | for (i = 0; i < _buffer_size; i++) { |
Mauro Carvalho Chehab | bae94dc | 2010-10-07 03:33:00 -0300 | [diff] [blame] | 1027 | *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF); |
| 1028 | i++; |
| 1029 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8); |
| 1030 | i++; |
| 1031 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16); |
| 1032 | i++; |
| 1033 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1034 | } |
| 1035 | cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size); |
| 1036 | } |
| 1037 | |
| 1038 | p_current_fw = p_fw; |
| 1039 | vfree(p_current_fw); |
| 1040 | p_current_fw = NULL; |
| 1041 | uninitGPIO(dev); |
| 1042 | release_firmware(firmware); |
| 1043 | dprintk(1, "Firmware upload successful.\n"); |
| 1044 | |
| 1045 | retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, |
| 1046 | IVTV_CMD_HW_BLOCKS_RST); |
| 1047 | if (retval < 0) { |
| 1048 | printk(KERN_ERR "%s: Error with mc417_register_write\n", |
| 1049 | __func__); |
| 1050 | return retval; |
| 1051 | } |
| 1052 | /* F/W power up disturbs the GPIOs, restore state */ |
| 1053 | retval |= mc417_register_write(dev, 0x9020, gpio_output); |
| 1054 | retval |= mc417_register_write(dev, 0x900C, value); |
| 1055 | |
| 1056 | retval |= mc417_register_read(dev, IVTV_REG_VPU, &value); |
| 1057 | retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); |
| 1058 | |
| 1059 | if (retval < 0) { |
| 1060 | printk(KERN_ERR "%s: Error with mc417_register_write\n", |
| 1061 | __func__); |
| 1062 | return retval; |
| 1063 | } |
| 1064 | return 0; |
| 1065 | } |
| 1066 | |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 1067 | static void cx231xx_417_check_encoder(struct cx231xx *dev) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1068 | { |
| 1069 | u32 status, seq; |
| 1070 | |
| 1071 | status = 0; |
| 1072 | seq = 0; |
| 1073 | cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq); |
| 1074 | dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq); |
| 1075 | } |
| 1076 | |
| 1077 | static void cx231xx_codec_settings(struct cx231xx *dev) |
| 1078 | { |
| 1079 | dprintk(1, "%s()\n", __func__); |
| 1080 | |
| 1081 | /* assign frame size */ |
| 1082 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0, |
| 1083 | dev->ts1.height, dev->ts1.width); |
| 1084 | |
| 1085 | dev->mpeg_params.width = dev->ts1.width; |
| 1086 | dev->mpeg_params.height = dev->ts1.height; |
| 1087 | |
| 1088 | cx2341x_update(dev, cx231xx_mbox_func, NULL, &dev->mpeg_params); |
| 1089 | |
| 1090 | cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1); |
| 1091 | cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1); |
| 1092 | } |
| 1093 | |
| 1094 | static int cx231xx_initialize_codec(struct cx231xx *dev) |
| 1095 | { |
| 1096 | int version; |
| 1097 | int retval; |
| 1098 | u32 i, data[7]; |
| 1099 | u32 val = 0; |
| 1100 | |
| 1101 | dprintk(1, "%s()\n", __func__); |
| 1102 | cx231xx_disable656(dev); |
| 1103 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */ |
| 1104 | if (retval < 0) { |
| 1105 | dprintk(2, "%s() PING OK\n", __func__); |
| 1106 | retval = cx231xx_load_firmware(dev); |
| 1107 | if (retval < 0) { |
| 1108 | printk(KERN_ERR "%s() f/w load failed\n", __func__); |
| 1109 | return retval; |
| 1110 | } |
| 1111 | retval = cx231xx_find_mailbox(dev); |
| 1112 | if (retval < 0) { |
| 1113 | printk(KERN_ERR "%s() mailbox < 0, error\n", |
| 1114 | __func__); |
| 1115 | return -1; |
| 1116 | } |
| 1117 | dev->cx23417_mailbox = retval; |
| 1118 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); |
| 1119 | if (retval < 0) { |
| 1120 | printk(KERN_ERR |
| 1121 | "ERROR: cx23417 firmware ping failed!\n"); |
| 1122 | return -1; |
| 1123 | } |
| 1124 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, |
| 1125 | &version); |
| 1126 | if (retval < 0) { |
| 1127 | printk(KERN_ERR "ERROR: cx23417 firmware get encoder :" |
| 1128 | "version failed!\n"); |
| 1129 | return -1; |
| 1130 | } |
| 1131 | dprintk(1, "cx23417 firmware version is 0x%08x\n", version); |
| 1132 | msleep(200); |
| 1133 | } |
| 1134 | |
| 1135 | for (i = 0; i < 1; i++) { |
| 1136 | retval = mc417_register_read(dev, 0x20f8, &val); |
| 1137 | dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n", |
| 1138 | val); |
| 1139 | if (retval < 0) |
| 1140 | return retval; |
| 1141 | } |
| 1142 | |
| 1143 | cx231xx_enable656(dev); |
| 1144 | /* stop mpeg capture */ |
| 1145 | cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, |
| 1146 | 3, 0, 1, 3, 4); |
| 1147 | |
| 1148 | cx231xx_codec_settings(dev); |
| 1149 | msleep(60); |
| 1150 | |
| 1151 | /* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0, |
| 1152 | CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115); |
| 1153 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0, |
| 1154 | CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1155 | 0, 0); |
| 1156 | */ |
| 1157 | /* Setup to capture VBI */ |
| 1158 | data[0] = 0x0001BD00; |
| 1159 | data[1] = 1; /* frames per interrupt */ |
| 1160 | data[2] = 4; /* total bufs */ |
| 1161 | data[3] = 0x91559155; /* start codes */ |
| 1162 | data[4] = 0x206080C0; /* stop codes */ |
| 1163 | data[5] = 6; /* lines */ |
| 1164 | data[6] = 64; /* BPL */ |
| 1165 | /* |
| 1166 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1], |
| 1167 | data[2], data[3], data[4], data[5], data[6]); |
| 1168 | |
| 1169 | for (i = 2; i <= 24; i++) { |
| 1170 | int valid; |
| 1171 | |
| 1172 | valid = ((i >= 19) && (i <= 21)); |
| 1173 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i, |
| 1174 | valid, 0 , 0, 0); |
| 1175 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, |
| 1176 | i | 0x80000000, valid, 0, 0, 0); |
| 1177 | } |
| 1178 | */ |
| 1179 | /* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE); |
| 1180 | msleep(60); |
| 1181 | */ |
| 1182 | /* initialize the video input */ |
| 1183 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0); |
| 1184 | if (retval < 0) |
| 1185 | return retval; |
| 1186 | msleep(60); |
| 1187 | |
| 1188 | /* Enable VIP style pixel invalidation so we work with scaled mode */ |
| 1189 | mc417_memory_write(dev, 2120, 0x00000080); |
| 1190 | |
| 1191 | /* start capturing to the host interface */ |
| 1192 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0, |
| 1193 | CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE); |
| 1194 | if (retval < 0) |
| 1195 | return retval; |
| 1196 | msleep(10); |
| 1197 | |
| 1198 | for (i = 0; i < 1; i++) { |
| 1199 | mc417_register_read(dev, 0x20f8, &val); |
| 1200 | dprintk(3, "***VIM Capture Lines =%d ***\n", val); |
| 1201 | } |
| 1202 | |
| 1203 | return 0; |
| 1204 | } |
| 1205 | |
| 1206 | /* ------------------------------------------------------------------ */ |
| 1207 | |
| 1208 | static int bb_buf_setup(struct videobuf_queue *q, |
| 1209 | unsigned int *count, unsigned int *size) |
| 1210 | { |
| 1211 | struct cx231xx_fh *fh = q->priv_data; |
| 1212 | |
| 1213 | fh->dev->ts1.ts_packet_size = mpeglinesize; |
| 1214 | fh->dev->ts1.ts_packet_count = mpeglines; |
| 1215 | |
| 1216 | *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; |
| 1217 | *count = mpegbufs; |
| 1218 | |
| 1219 | return 0; |
| 1220 | } |
| 1221 | static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf) |
| 1222 | { |
| 1223 | struct cx231xx_fh *fh = vq->priv_data; |
| 1224 | struct cx231xx *dev = fh->dev; |
| 1225 | unsigned long flags = 0; |
| 1226 | |
| 1227 | if (in_interrupt()) |
| 1228 | BUG(); |
| 1229 | |
| 1230 | spin_lock_irqsave(&dev->video_mode.slock, flags); |
| 1231 | if (dev->USE_ISO) { |
| 1232 | if (dev->video_mode.isoc_ctl.buf == buf) |
| 1233 | dev->video_mode.isoc_ctl.buf = NULL; |
| 1234 | } else { |
| 1235 | if (dev->video_mode.bulk_ctl.buf == buf) |
| 1236 | dev->video_mode.bulk_ctl.buf = NULL; |
| 1237 | } |
| 1238 | spin_unlock_irqrestore(&dev->video_mode.slock, flags); |
| 1239 | videobuf_waiton(vq, &buf->vb, 0, 0); |
| 1240 | videobuf_vmalloc_free(&buf->vb); |
| 1241 | buf->vb.state = VIDEOBUF_NEEDS_INIT; |
| 1242 | } |
| 1243 | |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 1244 | static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1245 | struct cx231xx_dmaqueue *dma_q) |
| 1246 | { |
| 1247 | void *vbuf; |
| 1248 | struct cx231xx_buffer *buf; |
| 1249 | u32 tail_data = 0; |
| 1250 | char *p_data; |
| 1251 | |
| 1252 | if (dma_q->mpeg_buffer_done == 0) { |
| 1253 | if (list_empty(&dma_q->active)) |
| 1254 | return; |
| 1255 | |
| 1256 | buf = list_entry(dma_q->active.next, |
| 1257 | struct cx231xx_buffer, vb.queue); |
| 1258 | dev->video_mode.isoc_ctl.buf = buf; |
| 1259 | dma_q->mpeg_buffer_done = 1; |
| 1260 | } |
| 1261 | /* Fill buffer */ |
| 1262 | buf = dev->video_mode.isoc_ctl.buf; |
| 1263 | vbuf = videobuf_to_vmalloc(&buf->vb); |
| 1264 | |
| 1265 | if ((dma_q->mpeg_buffer_completed+len) < |
| 1266 | mpeglines*mpeglinesize) { |
| 1267 | if (dma_q->add_ps_package_head == |
| 1268 | CX231XX_NEED_ADD_PS_PACKAGE_HEAD) { |
| 1269 | memcpy(vbuf+dma_q->mpeg_buffer_completed, |
| 1270 | dma_q->ps_head, 3); |
| 1271 | dma_q->mpeg_buffer_completed = |
| 1272 | dma_q->mpeg_buffer_completed + 3; |
| 1273 | dma_q->add_ps_package_head = |
| 1274 | CX231XX_NONEED_PS_PACKAGE_HEAD; |
| 1275 | } |
| 1276 | memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len); |
| 1277 | dma_q->mpeg_buffer_completed = |
| 1278 | dma_q->mpeg_buffer_completed + len; |
| 1279 | } else { |
| 1280 | dma_q->mpeg_buffer_done = 0; |
| 1281 | |
| 1282 | tail_data = |
| 1283 | mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed; |
| 1284 | memcpy(vbuf+dma_q->mpeg_buffer_completed, |
| 1285 | data, tail_data); |
| 1286 | |
| 1287 | buf->vb.state = VIDEOBUF_DONE; |
| 1288 | buf->vb.field_count++; |
| 1289 | do_gettimeofday(&buf->vb.ts); |
| 1290 | list_del(&buf->vb.queue); |
| 1291 | wake_up(&buf->vb.done); |
| 1292 | dma_q->mpeg_buffer_completed = 0; |
| 1293 | |
| 1294 | if (len - tail_data > 0) { |
| 1295 | p_data = data + tail_data; |
| 1296 | dma_q->left_data_count = len - tail_data; |
| 1297 | memcpy(dma_q->p_left_data, |
| 1298 | p_data, len - tail_data); |
| 1299 | } |
| 1300 | |
| 1301 | } |
| 1302 | |
| 1303 | return; |
| 1304 | } |
| 1305 | |
Mauro Carvalho Chehab | 82c3cca | 2010-10-07 21:01:31 -0300 | [diff] [blame] | 1306 | static void buffer_filled(char *data, int len, struct urb *urb, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1307 | struct cx231xx_dmaqueue *dma_q) |
| 1308 | { |
| 1309 | void *vbuf; |
| 1310 | struct cx231xx_buffer *buf; |
| 1311 | |
| 1312 | if (list_empty(&dma_q->active)) |
| 1313 | return; |
| 1314 | |
| 1315 | |
| 1316 | buf = list_entry(dma_q->active.next, |
| 1317 | struct cx231xx_buffer, vb.queue); |
| 1318 | |
| 1319 | |
| 1320 | /* Fill buffer */ |
| 1321 | vbuf = videobuf_to_vmalloc(&buf->vb); |
| 1322 | memcpy(vbuf, data, len); |
| 1323 | buf->vb.state = VIDEOBUF_DONE; |
| 1324 | buf->vb.field_count++; |
| 1325 | do_gettimeofday(&buf->vb.ts); |
| 1326 | list_del(&buf->vb.queue); |
| 1327 | wake_up(&buf->vb.done); |
| 1328 | |
| 1329 | return; |
| 1330 | } |
| 1331 | static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb) |
| 1332 | { |
| 1333 | struct cx231xx_dmaqueue *dma_q = urb->context; |
| 1334 | unsigned char *p_buffer; |
| 1335 | u32 buffer_size = 0; |
| 1336 | u32 i = 0; |
| 1337 | |
| 1338 | for (i = 0; i < urb->number_of_packets; i++) { |
| 1339 | if (dma_q->left_data_count > 0) { |
| 1340 | buffer_copy(dev, dma_q->p_left_data, |
| 1341 | dma_q->left_data_count, urb, dma_q); |
| 1342 | dma_q->mpeg_buffer_completed = dma_q->left_data_count; |
| 1343 | dma_q->left_data_count = 0; |
| 1344 | } |
| 1345 | |
| 1346 | p_buffer = urb->transfer_buffer + |
| 1347 | urb->iso_frame_desc[i].offset; |
| 1348 | buffer_size = urb->iso_frame_desc[i].actual_length; |
| 1349 | |
| 1350 | if (buffer_size > 0) |
| 1351 | buffer_copy(dev, p_buffer, buffer_size, urb, dma_q); |
| 1352 | } |
| 1353 | |
| 1354 | return 0; |
| 1355 | } |
| 1356 | static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb) |
| 1357 | { |
| 1358 | |
| 1359 | /*char *outp;*/ |
| 1360 | /*struct cx231xx_buffer *buf;*/ |
| 1361 | struct cx231xx_dmaqueue *dma_q = urb->context; |
| 1362 | unsigned char *p_buffer, *buffer; |
| 1363 | u32 buffer_size = 0; |
| 1364 | |
| 1365 | p_buffer = urb->transfer_buffer; |
| 1366 | buffer_size = urb->actual_length; |
| 1367 | |
| 1368 | buffer = kmalloc(buffer_size, GFP_ATOMIC); |
| 1369 | |
| 1370 | memcpy(buffer, dma_q->ps_head, 3); |
| 1371 | memcpy(buffer+3, p_buffer, buffer_size-3); |
| 1372 | memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3); |
| 1373 | |
| 1374 | p_buffer = buffer; |
| 1375 | buffer_filled(p_buffer, buffer_size, urb, dma_q); |
| 1376 | |
| 1377 | kfree(buffer); |
| 1378 | return 0; |
| 1379 | } |
| 1380 | |
| 1381 | static int bb_buf_prepare(struct videobuf_queue *q, |
| 1382 | struct videobuf_buffer *vb, enum v4l2_field field) |
| 1383 | { |
| 1384 | struct cx231xx_fh *fh = q->priv_data; |
| 1385 | struct cx231xx_buffer *buf = |
| 1386 | container_of(vb, struct cx231xx_buffer, vb); |
| 1387 | struct cx231xx *dev = fh->dev; |
| 1388 | int rc = 0, urb_init = 0; |
| 1389 | int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; |
| 1390 | |
| 1391 | dma_qq = &dev->video_mode.vidq; |
| 1392 | |
| 1393 | if (0 != buf->vb.baddr && buf->vb.bsize < size) |
| 1394 | return -EINVAL; |
| 1395 | buf->vb.width = fh->dev->ts1.ts_packet_size; |
| 1396 | buf->vb.height = fh->dev->ts1.ts_packet_count; |
| 1397 | buf->vb.size = size; |
| 1398 | buf->vb.field = field; |
| 1399 | |
| 1400 | if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { |
| 1401 | rc = videobuf_iolock(q, &buf->vb, NULL); |
| 1402 | if (rc < 0) |
| 1403 | goto fail; |
| 1404 | } |
| 1405 | |
| 1406 | if (dev->USE_ISO) { |
| 1407 | if (!dev->video_mode.isoc_ctl.num_bufs) |
| 1408 | urb_init = 1; |
| 1409 | } else { |
| 1410 | if (!dev->video_mode.bulk_ctl.num_bufs) |
| 1411 | urb_init = 1; |
| 1412 | } |
| 1413 | /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n", |
| 1414 | urb_init, dev->video_mode.max_pkt_size);*/ |
| 1415 | dev->mode_tv = 1; |
| 1416 | |
| 1417 | if (urb_init) { |
| 1418 | rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); |
| 1419 | rc = cx231xx_unmute_audio(dev); |
| 1420 | if (dev->USE_ISO) { |
| 1421 | cx231xx_set_alt_setting(dev, INDEX_TS1, 4); |
| 1422 | rc = cx231xx_init_isoc(dev, mpeglines, |
| 1423 | mpegbufs, |
| 1424 | dev->ts1_mode.max_pkt_size, |
| 1425 | cx231xx_isoc_copy); |
| 1426 | } else { |
| 1427 | cx231xx_set_alt_setting(dev, INDEX_TS1, 0); |
| 1428 | rc = cx231xx_init_bulk(dev, mpeglines, |
| 1429 | mpegbufs, |
| 1430 | dev->ts1_mode.max_pkt_size, |
| 1431 | cx231xx_bulk_copy); |
| 1432 | } |
| 1433 | if (rc < 0) |
| 1434 | goto fail; |
| 1435 | } |
| 1436 | |
| 1437 | buf->vb.state = VIDEOBUF_PREPARED; |
| 1438 | return 0; |
| 1439 | |
| 1440 | fail: |
| 1441 | free_buffer(q, buf); |
| 1442 | return rc; |
| 1443 | } |
| 1444 | |
| 1445 | static void bb_buf_queue(struct videobuf_queue *q, |
| 1446 | struct videobuf_buffer *vb) |
| 1447 | { |
| 1448 | struct cx231xx_fh *fh = q->priv_data; |
| 1449 | |
| 1450 | struct cx231xx_buffer *buf = |
| 1451 | container_of(vb, struct cx231xx_buffer, vb); |
| 1452 | struct cx231xx *dev = fh->dev; |
| 1453 | struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq; |
| 1454 | |
| 1455 | buf->vb.state = VIDEOBUF_QUEUED; |
| 1456 | list_add_tail(&buf->vb.queue, &vidq->active); |
| 1457 | |
| 1458 | } |
| 1459 | |
| 1460 | static void bb_buf_release(struct videobuf_queue *q, |
| 1461 | struct videobuf_buffer *vb) |
| 1462 | { |
| 1463 | struct cx231xx_buffer *buf = |
| 1464 | container_of(vb, struct cx231xx_buffer, vb); |
| 1465 | /*struct cx231xx_fh *fh = q->priv_data;*/ |
| 1466 | /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/ |
| 1467 | |
| 1468 | free_buffer(q, buf); |
| 1469 | } |
| 1470 | |
| 1471 | static struct videobuf_queue_ops cx231xx_qops = { |
| 1472 | .buf_setup = bb_buf_setup, |
| 1473 | .buf_prepare = bb_buf_prepare, |
| 1474 | .buf_queue = bb_buf_queue, |
| 1475 | .buf_release = bb_buf_release, |
| 1476 | }; |
| 1477 | |
| 1478 | /* ------------------------------------------------------------------ */ |
| 1479 | |
| 1480 | static const u32 *ctrl_classes[] = { |
| 1481 | cx2341x_mpeg_ctrls, |
| 1482 | NULL |
| 1483 | }; |
| 1484 | |
| 1485 | static int cx231xx_queryctrl(struct cx231xx *dev, |
| 1486 | struct v4l2_queryctrl *qctrl) |
| 1487 | { |
| 1488 | qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id); |
| 1489 | if (qctrl->id == 0) |
| 1490 | return -EINVAL; |
| 1491 | |
| 1492 | /* MPEG V4L2 controls */ |
| 1493 | if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl)) |
| 1494 | qctrl->flags |= V4L2_CTRL_FLAG_DISABLED; |
| 1495 | |
| 1496 | return 0; |
| 1497 | } |
| 1498 | |
| 1499 | static int cx231xx_querymenu(struct cx231xx *dev, |
| 1500 | struct v4l2_querymenu *qmenu) |
| 1501 | { |
| 1502 | struct v4l2_queryctrl qctrl; |
| 1503 | |
| 1504 | qctrl.id = qmenu->id; |
| 1505 | cx231xx_queryctrl(dev, &qctrl); |
| 1506 | return v4l2_ctrl_query_menu(qmenu, &qctrl, |
| 1507 | cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id)); |
| 1508 | } |
| 1509 | |
| 1510 | static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm) |
| 1511 | { |
| 1512 | struct cx231xx_fh *fh = file->private_data; |
| 1513 | struct cx231xx *dev = fh->dev; |
| 1514 | |
| 1515 | *norm = dev->encodernorm.id; |
| 1516 | return 0; |
| 1517 | } |
| 1518 | static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id) |
| 1519 | { |
| 1520 | struct cx231xx_fh *fh = file->private_data; |
| 1521 | struct cx231xx *dev = fh->dev; |
| 1522 | unsigned int i; |
| 1523 | |
| 1524 | for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++) |
| 1525 | if (*id & cx231xx_tvnorms[i].id) |
| 1526 | break; |
| 1527 | if (i == ARRAY_SIZE(cx231xx_tvnorms)) |
| 1528 | return -EINVAL; |
| 1529 | dev->encodernorm = cx231xx_tvnorms[i]; |
| 1530 | |
| 1531 | if (dev->encodernorm.id & 0xb000) { |
| 1532 | dprintk(3, "encodernorm set to NTSC\n"); |
| 1533 | dev->norm = V4L2_STD_NTSC; |
| 1534 | dev->ts1.height = 480; |
| 1535 | dev->mpeg_params.is_50hz = 0; |
| 1536 | } else { |
| 1537 | dprintk(3, "encodernorm set to PAL\n"); |
| 1538 | dev->norm = V4L2_STD_PAL_B; |
| 1539 | dev->ts1.height = 576; |
| 1540 | dev->mpeg_params.is_50hz = 1; |
| 1541 | } |
| 1542 | call_all(dev, core, s_std, dev->norm); |
| 1543 | /* do mode control overrides */ |
| 1544 | cx231xx_do_mode_ctrl_overrides(dev); |
| 1545 | |
| 1546 | dprintk(3, "exit vidioc_s_std() i=0x%x\n", i); |
| 1547 | return 0; |
| 1548 | } |
| 1549 | static int vidioc_g_audio(struct file *file, void *fh, |
| 1550 | struct v4l2_audio *a) |
| 1551 | { |
| 1552 | struct v4l2_audio *vin = a; |
| 1553 | |
| 1554 | int ret = -EINVAL; |
| 1555 | if (vin->index > 0) |
| 1556 | return ret; |
| 1557 | strncpy(vin->name, "VideoGrabber Audio", 14); |
| 1558 | vin->capability = V4L2_AUDCAP_STEREO; |
| 1559 | return 0; |
| 1560 | } |
| 1561 | static int vidioc_enumaudio(struct file *file, void *fh, |
| 1562 | struct v4l2_audio *a) |
| 1563 | { |
| 1564 | struct v4l2_audio *vin = a; |
| 1565 | |
| 1566 | int ret = -EINVAL; |
| 1567 | |
| 1568 | if (vin->index > 0) |
| 1569 | return ret; |
| 1570 | strncpy(vin->name, "VideoGrabber Audio", 14); |
| 1571 | vin->capability = V4L2_AUDCAP_STEREO; |
| 1572 | |
| 1573 | |
| 1574 | return 0; |
| 1575 | } |
| 1576 | static const char *iname[] = { |
| 1577 | [CX231XX_VMUX_COMPOSITE1] = "Composite1", |
| 1578 | [CX231XX_VMUX_SVIDEO] = "S-Video", |
| 1579 | [CX231XX_VMUX_TELEVISION] = "Television", |
| 1580 | [CX231XX_VMUX_CABLE] = "Cable TV", |
| 1581 | [CX231XX_VMUX_DVB] = "DVB", |
| 1582 | [CX231XX_VMUX_DEBUG] = "for debug only", |
| 1583 | }; |
| 1584 | static int vidioc_enum_input(struct file *file, void *priv, |
| 1585 | struct v4l2_input *i) |
| 1586 | { |
| 1587 | struct cx231xx_fh *fh = file->private_data; |
| 1588 | struct cx231xx *dev = fh->dev; |
| 1589 | struct cx231xx_input *input; |
| 1590 | int n; |
| 1591 | dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i->index); |
| 1592 | |
| 1593 | if (i->index >= 4) |
| 1594 | return -EINVAL; |
| 1595 | |
| 1596 | |
| 1597 | input = &cx231xx_boards[dev->model].input[i->index]; |
| 1598 | |
| 1599 | if (input->type == 0) |
| 1600 | return -EINVAL; |
| 1601 | |
| 1602 | /* FIXME |
| 1603 | * strcpy(i->name, input->name); */ |
| 1604 | |
| 1605 | n = i->index; |
| 1606 | strcpy(i->name, iname[INPUT(n)->type]); |
| 1607 | |
| 1608 | if (input->type == CX231XX_VMUX_TELEVISION || |
| 1609 | input->type == CX231XX_VMUX_CABLE) |
| 1610 | i->type = V4L2_INPUT_TYPE_TUNER; |
| 1611 | else |
| 1612 | i->type = V4L2_INPUT_TYPE_CAMERA; |
| 1613 | |
| 1614 | |
| 1615 | return 0; |
| 1616 | } |
| 1617 | |
| 1618 | static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) |
| 1619 | { |
| 1620 | *i = 0; |
| 1621 | return 0; |
| 1622 | } |
| 1623 | |
| 1624 | static int vidioc_s_input(struct file *file, void *priv, unsigned int i) |
| 1625 | { |
| 1626 | struct cx231xx_fh *fh = file->private_data; |
| 1627 | struct cx231xx *dev = fh->dev; |
| 1628 | |
| 1629 | dprintk(3, "enter vidioc_s_input() i=%d\n", i); |
| 1630 | |
| 1631 | mutex_lock(&dev->lock); |
| 1632 | |
| 1633 | video_mux(dev, i); |
| 1634 | |
| 1635 | mutex_unlock(&dev->lock); |
| 1636 | |
| 1637 | if (i >= 4) |
| 1638 | return -EINVAL; |
| 1639 | dev->input = i; |
| 1640 | dprintk(3, "exit vidioc_s_input()\n"); |
| 1641 | return 0; |
| 1642 | } |
| 1643 | |
| 1644 | static int vidioc_g_tuner(struct file *file, void *priv, |
| 1645 | struct v4l2_tuner *t) |
| 1646 | { |
| 1647 | return 0; |
| 1648 | } |
| 1649 | |
| 1650 | static int vidioc_s_tuner(struct file *file, void *priv, |
| 1651 | struct v4l2_tuner *t) |
| 1652 | { |
| 1653 | return 0; |
| 1654 | } |
| 1655 | |
| 1656 | static int vidioc_g_frequency(struct file *file, void *priv, |
| 1657 | struct v4l2_frequency *f) |
| 1658 | { |
| 1659 | return 0; |
| 1660 | } |
| 1661 | |
| 1662 | static int vidioc_s_frequency(struct file *file, void *priv, |
| 1663 | struct v4l2_frequency *f) |
| 1664 | { |
| 1665 | |
| 1666 | |
| 1667 | return 0; |
| 1668 | } |
| 1669 | |
| 1670 | static int vidioc_s_ctrl(struct file *file, void *priv, |
| 1671 | struct v4l2_control *ctl) |
| 1672 | { |
| 1673 | struct cx231xx_fh *fh = file->private_data; |
| 1674 | struct cx231xx *dev = fh->dev; |
| 1675 | dprintk(3, "enter vidioc_s_ctrl()\n"); |
| 1676 | /* Update the A/V core */ |
| 1677 | call_all(dev, core, s_ctrl, ctl); |
| 1678 | dprintk(3, "exit vidioc_s_ctrl()\n"); |
| 1679 | return 0; |
| 1680 | } |
| 1681 | static struct v4l2_capability pvr_capability = { |
| 1682 | .driver = "cx231xx", |
| 1683 | .card = "VideoGrabber", |
| 1684 | .bus_info = "usb", |
| 1685 | .version = 1, |
| 1686 | .capabilities = (V4L2_CAP_VIDEO_CAPTURE | |
| 1687 | V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_RADIO | |
| 1688 | V4L2_CAP_STREAMING | V4L2_CAP_READWRITE), |
| 1689 | .reserved = {0, 0, 0, 0} |
| 1690 | }; |
| 1691 | static int vidioc_querycap(struct file *file, void *priv, |
| 1692 | struct v4l2_capability *cap) |
| 1693 | { |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | memcpy(cap, &pvr_capability, sizeof(struct v4l2_capability)); |
| 1698 | return 0; |
| 1699 | } |
| 1700 | |
| 1701 | static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, |
| 1702 | struct v4l2_fmtdesc *f) |
| 1703 | { |
| 1704 | |
| 1705 | if (f->index != 0) |
| 1706 | return -EINVAL; |
| 1707 | |
| 1708 | strlcpy(f->description, "MPEG", sizeof(f->description)); |
| 1709 | f->pixelformat = V4L2_PIX_FMT_MPEG; |
| 1710 | |
| 1711 | return 0; |
| 1712 | } |
| 1713 | |
| 1714 | static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
| 1715 | struct v4l2_format *f) |
| 1716 | { |
| 1717 | struct cx231xx_fh *fh = file->private_data; |
| 1718 | struct cx231xx *dev = fh->dev; |
| 1719 | dprintk(3, "enter vidioc_g_fmt_vid_cap()\n"); |
| 1720 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
| 1721 | f->fmt.pix.bytesperline = 0; |
| 1722 | f->fmt.pix.sizeimage = |
| 1723 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; |
| 1724 | f->fmt.pix.colorspace = 0; |
| 1725 | f->fmt.pix.width = dev->ts1.width; |
| 1726 | f->fmt.pix.height = dev->ts1.height; |
| 1727 | f->fmt.pix.field = fh->vidq.field; |
| 1728 | dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n", |
| 1729 | dev->ts1.width, dev->ts1.height, fh->vidq.field); |
| 1730 | dprintk(3, "exit vidioc_g_fmt_vid_cap()\n"); |
| 1731 | return 0; |
| 1732 | } |
| 1733 | |
| 1734 | static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, |
| 1735 | struct v4l2_format *f) |
| 1736 | { |
| 1737 | struct cx231xx_fh *fh = file->private_data; |
| 1738 | struct cx231xx *dev = fh->dev; |
| 1739 | dprintk(3, "enter vidioc_try_fmt_vid_cap()\n"); |
| 1740 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
| 1741 | f->fmt.pix.bytesperline = 0; |
| 1742 | f->fmt.pix.sizeimage = |
| 1743 | dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; |
| 1744 | f->fmt.pix.colorspace = 0; |
| 1745 | dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n", |
| 1746 | dev->ts1.width, dev->ts1.height, fh->vidq.field); |
| 1747 | dprintk(3, "exit vidioc_try_fmt_vid_cap()\n"); |
| 1748 | return 0; |
| 1749 | } |
| 1750 | |
| 1751 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, |
| 1752 | struct v4l2_format *f) |
| 1753 | { |
| 1754 | |
| 1755 | return 0; |
| 1756 | } |
| 1757 | |
| 1758 | static int vidioc_reqbufs(struct file *file, void *priv, |
| 1759 | struct v4l2_requestbuffers *p) |
| 1760 | { |
| 1761 | struct cx231xx_fh *fh = file->private_data; |
| 1762 | |
| 1763 | return videobuf_reqbufs(&fh->vidq, p); |
| 1764 | } |
| 1765 | |
| 1766 | static int vidioc_querybuf(struct file *file, void *priv, |
| 1767 | struct v4l2_buffer *p) |
| 1768 | { |
| 1769 | struct cx231xx_fh *fh = file->private_data; |
| 1770 | |
| 1771 | return videobuf_querybuf(&fh->vidq, p); |
| 1772 | } |
| 1773 | |
| 1774 | static int vidioc_qbuf(struct file *file, void *priv, |
| 1775 | struct v4l2_buffer *p) |
| 1776 | { |
| 1777 | struct cx231xx_fh *fh = file->private_data; |
| 1778 | |
| 1779 | return videobuf_qbuf(&fh->vidq, p); |
| 1780 | } |
| 1781 | |
| 1782 | static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) |
| 1783 | { |
| 1784 | struct cx231xx_fh *fh = priv; |
| 1785 | |
| 1786 | return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK); |
| 1787 | } |
| 1788 | |
| 1789 | |
| 1790 | static int vidioc_streamon(struct file *file, void *priv, |
| 1791 | enum v4l2_buf_type i) |
| 1792 | { |
| 1793 | struct cx231xx_fh *fh = file->private_data; |
| 1794 | |
| 1795 | struct cx231xx *dev = fh->dev; |
| 1796 | int rc = 0; |
| 1797 | dprintk(3, "enter vidioc_streamon()\n"); |
| 1798 | cx231xx_set_alt_setting(dev, INDEX_TS1, 0); |
| 1799 | rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); |
| 1800 | if (dev->USE_ISO) |
| 1801 | rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS, |
| 1802 | CX231XX_NUM_BUFS, |
| 1803 | dev->video_mode.max_pkt_size, |
| 1804 | cx231xx_isoc_copy); |
| 1805 | else { |
| 1806 | rc = cx231xx_init_bulk(dev, 320, |
| 1807 | 5, |
| 1808 | dev->ts1_mode.max_pkt_size, |
| 1809 | cx231xx_bulk_copy); |
| 1810 | } |
| 1811 | dprintk(3, "exit vidioc_streamon()\n"); |
| 1812 | return videobuf_streamon(&fh->vidq); |
| 1813 | } |
| 1814 | |
| 1815 | static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) |
| 1816 | { |
| 1817 | struct cx231xx_fh *fh = file->private_data; |
| 1818 | |
| 1819 | return videobuf_streamoff(&fh->vidq); |
| 1820 | } |
| 1821 | |
| 1822 | static int vidioc_g_ext_ctrls(struct file *file, void *priv, |
| 1823 | struct v4l2_ext_controls *f) |
| 1824 | { |
| 1825 | struct cx231xx_fh *fh = priv; |
| 1826 | struct cx231xx *dev = fh->dev; |
| 1827 | dprintk(3, "enter vidioc_g_ext_ctrls()\n"); |
| 1828 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) |
| 1829 | return -EINVAL; |
| 1830 | dprintk(3, "exit vidioc_g_ext_ctrls()\n"); |
| 1831 | return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS); |
| 1832 | } |
| 1833 | |
| 1834 | static int vidioc_s_ext_ctrls(struct file *file, void *priv, |
| 1835 | struct v4l2_ext_controls *f) |
| 1836 | { |
| 1837 | struct cx231xx_fh *fh = priv; |
| 1838 | struct cx231xx *dev = fh->dev; |
| 1839 | struct cx2341x_mpeg_params p; |
| 1840 | int err; |
| 1841 | dprintk(3, "enter vidioc_s_ext_ctrls()\n"); |
| 1842 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) |
| 1843 | return -EINVAL; |
| 1844 | |
| 1845 | p = dev->mpeg_params; |
| 1846 | err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS); |
| 1847 | if (err == 0) { |
| 1848 | err = cx2341x_update(dev, cx231xx_mbox_func, |
| 1849 | &dev->mpeg_params, &p); |
| 1850 | dev->mpeg_params = p; |
| 1851 | } |
| 1852 | |
| 1853 | return err; |
| 1854 | |
| 1855 | |
| 1856 | return 0; |
| 1857 | } |
| 1858 | |
| 1859 | static int vidioc_try_ext_ctrls(struct file *file, void *priv, |
| 1860 | struct v4l2_ext_controls *f) |
| 1861 | { |
| 1862 | struct cx231xx_fh *fh = priv; |
| 1863 | struct cx231xx *dev = fh->dev; |
| 1864 | struct cx2341x_mpeg_params p; |
| 1865 | int err; |
| 1866 | dprintk(3, "enter vidioc_try_ext_ctrls()\n"); |
| 1867 | if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) |
| 1868 | return -EINVAL; |
| 1869 | |
| 1870 | p = dev->mpeg_params; |
| 1871 | err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS); |
| 1872 | dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err); |
| 1873 | return err; |
| 1874 | } |
| 1875 | |
| 1876 | static int vidioc_log_status(struct file *file, void *priv) |
| 1877 | { |
| 1878 | struct cx231xx_fh *fh = priv; |
| 1879 | struct cx231xx *dev = fh->dev; |
| 1880 | char name[32 + 2]; |
| 1881 | |
| 1882 | snprintf(name, sizeof(name), "%s/2", dev->name); |
| 1883 | dprintk(3, |
| 1884 | "%s/2: ============ START LOG STATUS ============\n", |
| 1885 | dev->name); |
| 1886 | call_all(dev, core, log_status); |
| 1887 | cx2341x_log_status(&dev->mpeg_params, name); |
| 1888 | dprintk(3, |
| 1889 | "%s/2: ============= END LOG STATUS =============\n", |
| 1890 | dev->name); |
| 1891 | return 0; |
| 1892 | } |
| 1893 | |
| 1894 | static int vidioc_querymenu(struct file *file, void *priv, |
| 1895 | struct v4l2_querymenu *a) |
| 1896 | { |
| 1897 | struct cx231xx_fh *fh = priv; |
| 1898 | struct cx231xx *dev = fh->dev; |
| 1899 | dprintk(3, "enter vidioc_querymenu()\n"); |
| 1900 | dprintk(3, "exit vidioc_querymenu()\n"); |
| 1901 | return cx231xx_querymenu(dev, a); |
| 1902 | } |
| 1903 | |
| 1904 | static int vidioc_queryctrl(struct file *file, void *priv, |
| 1905 | struct v4l2_queryctrl *c) |
| 1906 | { |
| 1907 | struct cx231xx_fh *fh = priv; |
| 1908 | struct cx231xx *dev = fh->dev; |
| 1909 | dprintk(3, "enter vidioc_queryctrl()\n"); |
| 1910 | dprintk(3, "exit vidioc_queryctrl()\n"); |
| 1911 | return cx231xx_queryctrl(dev, c); |
| 1912 | } |
| 1913 | |
| 1914 | static int mpeg_open(struct file *file) |
| 1915 | { |
| 1916 | int minor = video_devdata(file)->minor; |
| 1917 | struct cx231xx *h, *dev = NULL; |
| 1918 | /*struct list_head *list;*/ |
| 1919 | struct cx231xx_fh *fh; |
| 1920 | /*u32 value = 0;*/ |
| 1921 | |
| 1922 | dprintk(2, "%s()\n", __func__); |
| 1923 | |
| 1924 | list_for_each_entry(h, &cx231xx_devlist, devlist) { |
| 1925 | if (h->v4l_device->minor == minor) |
| 1926 | dev = h; |
| 1927 | } |
| 1928 | |
Arnd Bergmann | 0edf2e5 | 2010-10-27 09:30:32 -0300 | [diff] [blame] | 1929 | if (dev == NULL) |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1930 | return -ENODEV; |
Arnd Bergmann | 0edf2e5 | 2010-10-27 09:30:32 -0300 | [diff] [blame] | 1931 | |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1932 | mutex_lock(&dev->lock); |
| 1933 | |
| 1934 | /* allocate + initialize per filehandle data */ |
| 1935 | fh = kzalloc(sizeof(*fh), GFP_KERNEL); |
| 1936 | if (NULL == fh) { |
| 1937 | mutex_unlock(&dev->lock); |
| 1938 | return -ENOMEM; |
| 1939 | } |
| 1940 | |
| 1941 | file->private_data = fh; |
| 1942 | fh->dev = dev; |
| 1943 | |
| 1944 | |
| 1945 | videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops, |
| 1946 | NULL, &dev->video_mode.slock, |
| 1947 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED, |
| 1948 | sizeof(struct cx231xx_buffer), fh, NULL); |
| 1949 | /* |
| 1950 | videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops, |
| 1951 | &dev->udev->dev, &dev->ts1.slock, |
| 1952 | V4L2_BUF_TYPE_VIDEO_CAPTURE, |
| 1953 | V4L2_FIELD_INTERLACED, |
| 1954 | sizeof(struct cx231xx_buffer), |
| 1955 | fh, NULL); |
| 1956 | */ |
| 1957 | |
| 1958 | |
| 1959 | cx231xx_set_alt_setting(dev, INDEX_VANC, 1); |
| 1960 | cx231xx_set_gpio_value(dev, 2, 0); |
| 1961 | |
| 1962 | cx231xx_initialize_codec(dev); |
| 1963 | |
| 1964 | mutex_unlock(&dev->lock); |
| 1965 | cx231xx_start_TS1(dev); |
| 1966 | |
| 1967 | return 0; |
| 1968 | } |
| 1969 | |
| 1970 | static int mpeg_release(struct file *file) |
| 1971 | { |
| 1972 | struct cx231xx_fh *fh = file->private_data; |
| 1973 | struct cx231xx *dev = fh->dev; |
| 1974 | |
Devin Heitmueller | dd067a8 | 2010-07-07 19:28:23 -0300 | [diff] [blame] | 1975 | dprintk(3, "mpeg_release()! dev=0x%p\n", dev); |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 1976 | |
| 1977 | if (!dev) { |
| 1978 | dprintk(3, "abort!!!\n"); |
| 1979 | return 0; |
| 1980 | } |
| 1981 | |
| 1982 | mutex_lock(&dev->lock); |
| 1983 | |
| 1984 | cx231xx_stop_TS1(dev); |
| 1985 | |
| 1986 | /* do this before setting alternate! */ |
| 1987 | if (dev->USE_ISO) |
| 1988 | cx231xx_uninit_isoc(dev); |
| 1989 | else |
| 1990 | cx231xx_uninit_bulk(dev); |
| 1991 | cx231xx_set_mode(dev, CX231XX_SUSPEND); |
| 1992 | |
| 1993 | cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, |
| 1994 | CX231xx_END_NOW, CX231xx_MPEG_CAPTURE, |
| 1995 | CX231xx_RAW_BITS_NONE); |
| 1996 | |
| 1997 | /* FIXME: Review this crap */ |
| 1998 | /* Shut device down on last close */ |
| 1999 | if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) { |
| 2000 | if (atomic_dec_return(&dev->v4l_reader_count) == 0) { |
| 2001 | /* stop mpeg capture */ |
| 2002 | |
| 2003 | msleep(500); |
| 2004 | cx231xx_417_check_encoder(dev); |
| 2005 | |
| 2006 | } |
| 2007 | } |
| 2008 | |
| 2009 | if (fh->vidq.streaming) |
| 2010 | videobuf_streamoff(&fh->vidq); |
| 2011 | if (fh->vidq.reading) |
| 2012 | videobuf_read_stop(&fh->vidq); |
| 2013 | |
| 2014 | videobuf_mmap_free(&fh->vidq); |
| 2015 | file->private_data = NULL; |
| 2016 | kfree(fh); |
| 2017 | mutex_unlock(&dev->lock); |
| 2018 | return 0; |
| 2019 | } |
| 2020 | |
| 2021 | static ssize_t mpeg_read(struct file *file, char __user *data, |
| 2022 | size_t count, loff_t *ppos) |
| 2023 | { |
| 2024 | struct cx231xx_fh *fh = file->private_data; |
| 2025 | struct cx231xx *dev = fh->dev; |
| 2026 | |
| 2027 | |
| 2028 | /* Deal w/ A/V decoder * and mpeg encoder sync issues. */ |
| 2029 | /* Start mpeg encoder on first read. */ |
| 2030 | if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) { |
| 2031 | if (atomic_inc_return(&dev->v4l_reader_count) == 1) { |
| 2032 | if (cx231xx_initialize_codec(dev) < 0) |
| 2033 | return -EINVAL; |
| 2034 | } |
| 2035 | } |
| 2036 | |
| 2037 | return videobuf_read_stream(&fh->vidq, data, count, ppos, 0, |
| 2038 | file->f_flags & O_NONBLOCK); |
| 2039 | } |
| 2040 | |
| 2041 | static unsigned int mpeg_poll(struct file *file, |
| 2042 | struct poll_table_struct *wait) |
| 2043 | { |
| 2044 | struct cx231xx_fh *fh = file->private_data; |
| 2045 | /*struct cx231xx *dev = fh->dev;*/ |
| 2046 | |
| 2047 | /*dprintk(2, "%s\n", __func__);*/ |
| 2048 | |
| 2049 | return videobuf_poll_stream(file, &fh->vidq, wait); |
| 2050 | } |
| 2051 | |
| 2052 | static int mpeg_mmap(struct file *file, struct vm_area_struct *vma) |
| 2053 | { |
| 2054 | struct cx231xx_fh *fh = file->private_data; |
| 2055 | struct cx231xx *dev = fh->dev; |
| 2056 | |
| 2057 | dprintk(2, "%s()\n", __func__); |
| 2058 | |
| 2059 | return videobuf_mmap_mapper(&fh->vidq, vma); |
| 2060 | } |
| 2061 | |
| 2062 | static struct v4l2_file_operations mpeg_fops = { |
| 2063 | .owner = THIS_MODULE, |
| 2064 | .open = mpeg_open, |
| 2065 | .release = mpeg_release, |
| 2066 | .read = mpeg_read, |
| 2067 | .poll = mpeg_poll, |
| 2068 | .mmap = mpeg_mmap, |
| 2069 | .ioctl = video_ioctl2, |
| 2070 | }; |
| 2071 | |
| 2072 | static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { |
| 2073 | .vidioc_s_std = vidioc_s_std, |
| 2074 | .vidioc_g_std = vidioc_g_std, |
| 2075 | .vidioc_enum_input = vidioc_enum_input, |
| 2076 | .vidioc_enumaudio = vidioc_enumaudio, |
Mauro Carvalho Chehab | 955e6ed | 2010-10-07 03:23:25 -0300 | [diff] [blame] | 2077 | .vidioc_g_audio = vidioc_g_audio, |
Palash Bandyopadhyay | 64fbf44 | 2010-07-06 18:12:25 -0300 | [diff] [blame] | 2078 | .vidioc_g_input = vidioc_g_input, |
| 2079 | .vidioc_s_input = vidioc_s_input, |
| 2080 | .vidioc_g_tuner = vidioc_g_tuner, |
| 2081 | .vidioc_s_tuner = vidioc_s_tuner, |
| 2082 | .vidioc_g_frequency = vidioc_g_frequency, |
| 2083 | .vidioc_s_frequency = vidioc_s_frequency, |
| 2084 | .vidioc_s_ctrl = vidioc_s_ctrl, |
| 2085 | .vidioc_querycap = vidioc_querycap, |
| 2086 | .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, |
| 2087 | .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, |
| 2088 | .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, |
| 2089 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, |
| 2090 | .vidioc_reqbufs = vidioc_reqbufs, |
| 2091 | .vidioc_querybuf = vidioc_querybuf, |
| 2092 | .vidioc_qbuf = vidioc_qbuf, |
| 2093 | .vidioc_dqbuf = vidioc_dqbuf, |
| 2094 | .vidioc_streamon = vidioc_streamon, |
| 2095 | .vidioc_streamoff = vidioc_streamoff, |
| 2096 | .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls, |
| 2097 | .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls, |
| 2098 | .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls, |
| 2099 | .vidioc_log_status = vidioc_log_status, |
| 2100 | .vidioc_querymenu = vidioc_querymenu, |
| 2101 | .vidioc_queryctrl = vidioc_queryctrl, |
| 2102 | /* .vidioc_g_chip_ident = cx231xx_g_chip_ident,*/ |
| 2103 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 2104 | /* .vidioc_g_register = cx231xx_g_register,*/ |
| 2105 | /* .vidioc_s_register = cx231xx_s_register,*/ |
| 2106 | #endif |
| 2107 | }; |
| 2108 | |
| 2109 | static struct video_device cx231xx_mpeg_template = { |
| 2110 | .name = "cx231xx", |
| 2111 | .fops = &mpeg_fops, |
| 2112 | .ioctl_ops = &mpeg_ioctl_ops, |
| 2113 | .minor = -1, |
| 2114 | .tvnorms = CX231xx_NORMS, |
| 2115 | .current_norm = V4L2_STD_NTSC_M, |
| 2116 | }; |
| 2117 | |
| 2118 | void cx231xx_417_unregister(struct cx231xx *dev) |
| 2119 | { |
| 2120 | dprintk(1, "%s()\n", __func__); |
| 2121 | dprintk(3, "%s()\n", __func__); |
| 2122 | |
| 2123 | if (dev->v4l_device) { |
| 2124 | if (-1 != dev->v4l_device->minor) |
| 2125 | video_unregister_device(dev->v4l_device); |
| 2126 | else |
| 2127 | video_device_release(dev->v4l_device); |
| 2128 | dev->v4l_device = NULL; |
| 2129 | } |
| 2130 | } |
| 2131 | |
| 2132 | static struct video_device *cx231xx_video_dev_alloc( |
| 2133 | struct cx231xx *dev, |
| 2134 | struct usb_device *usbdev, |
| 2135 | struct video_device *template, |
| 2136 | char *type) |
| 2137 | { |
| 2138 | struct video_device *vfd; |
| 2139 | |
| 2140 | dprintk(1, "%s()\n", __func__); |
| 2141 | vfd = video_device_alloc(); |
| 2142 | if (NULL == vfd) |
| 2143 | return NULL; |
| 2144 | *vfd = *template; |
| 2145 | vfd->minor = -1; |
| 2146 | snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, |
| 2147 | type, cx231xx_boards[dev->model].name); |
| 2148 | |
| 2149 | vfd->v4l2_dev = &dev->v4l2_dev; |
| 2150 | vfd->release = video_device_release; |
| 2151 | |
| 2152 | return vfd; |
| 2153 | |
| 2154 | } |
| 2155 | |
| 2156 | int cx231xx_417_register(struct cx231xx *dev) |
| 2157 | { |
| 2158 | /* FIXME: Port1 hardcoded here */ |
| 2159 | int err = -ENODEV; |
| 2160 | struct cx231xx_tsport *tsport = &dev->ts1; |
| 2161 | |
| 2162 | dprintk(1, "%s()\n", __func__); |
| 2163 | |
| 2164 | /* Set default TV standard */ |
| 2165 | dev->encodernorm = cx231xx_tvnorms[0]; |
| 2166 | |
| 2167 | if (dev->encodernorm.id & V4L2_STD_525_60) |
| 2168 | tsport->height = 480; |
| 2169 | else |
| 2170 | tsport->height = 576; |
| 2171 | |
| 2172 | tsport->width = 720; |
| 2173 | cx2341x_fill_defaults(&dev->mpeg_params); |
| 2174 | dev->norm = V4L2_STD_NTSC; |
| 2175 | |
| 2176 | dev->mpeg_params.port = CX2341X_PORT_SERIAL; |
| 2177 | |
| 2178 | /* Allocate and initialize V4L video device */ |
| 2179 | dev->v4l_device = cx231xx_video_dev_alloc(dev, |
| 2180 | dev->udev, &cx231xx_mpeg_template, "mpeg"); |
| 2181 | err = video_register_device(dev->v4l_device, |
| 2182 | VFL_TYPE_GRABBER, -1); |
| 2183 | if (err < 0) { |
| 2184 | dprintk(3, "%s: can't register mpeg device\n", dev->name); |
| 2185 | return err; |
| 2186 | } |
| 2187 | |
| 2188 | dprintk(3, "%s: registered device video%d [mpeg]\n", |
| 2189 | dev->name, dev->v4l_device->num); |
| 2190 | |
| 2191 | return 0; |
| 2192 | } |