| Igor M. Liplianin | e2bc99b | 2009-03-03 11:35:25 -0300 | [diff] [blame] | 1 | /* |
| 2 | * stv0900_reg.h |
| 3 | * |
| 4 | * Driver for ST STV0900 satellite demodulator IC. |
| 5 | * |
| 6 | * Copyright (C) ST Microelectronics. |
| 7 | * Copyright (C) 2009 NetUP Inc. |
| 8 | * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | */ |
| 25 | |
| 26 | #ifndef STV0900_REG_H |
| 27 | #define STV0900_REG_H |
| 28 | |
| 29 | /*MID*/ |
| 30 | #define R0900_MID 0xf100 |
| 31 | #define F0900_MCHIP_IDENT 0xf10000f0 |
| 32 | #define F0900_MRELEASE 0xf100000f |
| 33 | |
| 34 | /*DACR1*/ |
| 35 | #define R0900_DACR1 0xf113 |
| 36 | #define F0900_DAC_MODE 0xf11300e0 |
| 37 | #define F0900_DAC_VALUE1 0xf113000f |
| 38 | |
| 39 | /*DACR2*/ |
| 40 | #define R0900_DACR2 0xf114 |
| 41 | #define F0900_DAC_VALUE0 0xf11400ff |
| 42 | |
| 43 | /*OUTCFG*/ |
| 44 | #define R0900_OUTCFG 0xf11c |
| 45 | #define F0900_INV_DATA6 0xf11c0080 |
| 46 | #define F0900_OUTSERRS1_HZ 0xf11c0040 |
| 47 | #define F0900_OUTSERRS2_HZ 0xf11c0020 |
| 48 | #define F0900_OUTSERRS3_HZ 0xf11c0010 |
| 49 | #define F0900_OUTPARRS3_HZ 0xf11c0008 |
| 50 | #define F0900_OUTHZ3_CONTROL 0xf11c0007 |
| 51 | |
| 52 | /*MODECFG*/ |
| 53 | #define R0900_MODECFG 0xf11d |
| 54 | #define F0900_FECSPY_SEL_2 0xf11d0020 |
| 55 | #define F0900_HWARE_SEL_2 0xf11d0010 |
| 56 | #define F0900_PKTDEL_SEL_2 0xf11d0008 |
| 57 | #define F0900_DISEQC_SEL_2 0xf11d0004 |
| 58 | #define F0900_VIT_SEL_2 0xf11d0002 |
| 59 | #define F0900_DEMOD_SEL_2 0xf11d0001 |
| 60 | |
| 61 | /*IRQSTATUS3*/ |
| 62 | #define R0900_IRQSTATUS3 0xf120 |
| 63 | #define F0900_SPLL_LOCK 0xf1200020 |
| 64 | #define F0900_SSTREAM_LCK_3 0xf1200010 |
| 65 | #define F0900_SSTREAM_LCK_2 0xf1200008 |
| 66 | #define F0900_SSTREAM_LCK_1 0xf1200004 |
| 67 | #define F0900_SDVBS1_PRF_2 0xf1200002 |
| 68 | #define F0900_SDVBS1_PRF_1 0xf1200001 |
| 69 | |
| 70 | /*IRQSTATUS2*/ |
| 71 | #define R0900_IRQSTATUS2 0xf121 |
| 72 | #define F0900_SSPY_ENDSIM_3 0xf1210080 |
| 73 | #define F0900_SSPY_ENDSIM_2 0xf1210040 |
| 74 | #define F0900_SSPY_ENDSIM_1 0xf1210020 |
| 75 | #define F0900_SPKTDEL_ERROR_2 0xf1210010 |
| 76 | #define F0900_SPKTDEL_LOCKB_2 0xf1210008 |
| 77 | #define F0900_SPKTDEL_LOCK_2 0xf1210004 |
| 78 | #define F0900_SPKTDEL_ERROR_1 0xf1210002 |
| 79 | #define F0900_SPKTDEL_LOCKB_1 0xf1210001 |
| 80 | |
| 81 | /*IRQSTATUS1*/ |
| 82 | #define R0900_IRQSTATUS1 0xf122 |
| 83 | #define F0900_SPKTDEL_LOCK_1 0xf1220080 |
| 84 | #define F0900_SEXTPINB2 0xf1220040 |
| 85 | #define F0900_SEXTPIN2 0xf1220020 |
| 86 | #define F0900_SEXTPINB1 0xf1220010 |
| 87 | #define F0900_SEXTPIN1 0xf1220008 |
| 88 | #define F0900_SDEMOD_LOCKB_2 0xf1220004 |
| 89 | #define F0900_SDEMOD_LOCK_2 0xf1220002 |
| 90 | #define F0900_SDEMOD_IRQ_2 0xf1220001 |
| 91 | |
| 92 | /*IRQSTATUS0*/ |
| 93 | #define R0900_IRQSTATUS0 0xf123 |
| 94 | #define F0900_SDEMOD_LOCKB_1 0xf1230080 |
| 95 | #define F0900_SDEMOD_LOCK_1 0xf1230040 |
| 96 | #define F0900_SDEMOD_IRQ_1 0xf1230020 |
| 97 | #define F0900_SBCH_ERRFLAG 0xf1230010 |
| 98 | #define F0900_SDISEQC2RX_IRQ 0xf1230008 |
| 99 | #define F0900_SDISEQC2TX_IRQ 0xf1230004 |
| 100 | #define F0900_SDISEQC1RX_IRQ 0xf1230002 |
| 101 | #define F0900_SDISEQC1TX_IRQ 0xf1230001 |
| 102 | |
| 103 | /*IRQMASK3*/ |
| 104 | #define R0900_IRQMASK3 0xf124 |
| 105 | #define F0900_MPLL_LOCK 0xf1240020 |
| 106 | #define F0900_MSTREAM_LCK_3 0xf1240010 |
| 107 | #define F0900_MSTREAM_LCK_2 0xf1240008 |
| 108 | #define F0900_MSTREAM_LCK_1 0xf1240004 |
| 109 | #define F0900_MDVBS1_PRF_2 0xf1240002 |
| 110 | #define F0900_MDVBS1_PRF_1 0xf1240001 |
| 111 | |
| 112 | /*IRQMASK2*/ |
| 113 | #define R0900_IRQMASK2 0xf125 |
| 114 | #define F0900_MSPY_ENDSIM_3 0xf1250080 |
| 115 | #define F0900_MSPY_ENDSIM_2 0xf1250040 |
| 116 | #define F0900_MSPY_ENDSIM_1 0xf1250020 |
| 117 | #define F0900_MPKTDEL_ERROR_2 0xf1250010 |
| 118 | #define F0900_MPKTDEL_LOCKB_2 0xf1250008 |
| 119 | #define F0900_MPKTDEL_LOCK_2 0xf1250004 |
| 120 | #define F0900_MPKTDEL_ERROR_1 0xf1250002 |
| 121 | #define F0900_MPKTDEL_LOCKB_1 0xf1250001 |
| 122 | |
| 123 | /*IRQMASK1*/ |
| 124 | #define R0900_IRQMASK1 0xf126 |
| 125 | #define F0900_MPKTDEL_LOCK_1 0xf1260080 |
| 126 | #define F0900_MEXTPINB2 0xf1260040 |
| 127 | #define F0900_MEXTPIN2 0xf1260020 |
| 128 | #define F0900_MEXTPINB1 0xf1260010 |
| 129 | #define F0900_MEXTPIN1 0xf1260008 |
| 130 | #define F0900_MDEMOD_LOCKB_2 0xf1260004 |
| 131 | #define F0900_MDEMOD_LOCK_2 0xf1260002 |
| 132 | #define F0900_MDEMOD_IRQ_2 0xf1260001 |
| 133 | |
| 134 | /*IRQMASK0*/ |
| 135 | #define R0900_IRQMASK0 0xf127 |
| 136 | #define F0900_MDEMOD_LOCKB_1 0xf1270080 |
| 137 | #define F0900_MDEMOD_LOCK_1 0xf1270040 |
| 138 | #define F0900_MDEMOD_IRQ_1 0xf1270020 |
| 139 | #define F0900_MBCH_ERRFLAG 0xf1270010 |
| 140 | #define F0900_MDISEQC2RX_IRQ 0xf1270008 |
| 141 | #define F0900_MDISEQC2TX_IRQ 0xf1270004 |
| 142 | #define F0900_MDISEQC1RX_IRQ 0xf1270002 |
| 143 | #define F0900_MDISEQC1TX_IRQ 0xf1270001 |
| 144 | |
| 145 | /*I2CCFG*/ |
| 146 | #define R0900_I2CCFG 0xf129 |
| 147 | #define F0900_I2C2_FASTMODE 0xf1290080 |
| 148 | #define F0900_STATUS_WR2 0xf1290040 |
| 149 | #define F0900_I2C2ADDR_INC 0xf1290030 |
| 150 | #define F0900_I2C_FASTMODE 0xf1290008 |
| 151 | #define F0900_STATUS_WR 0xf1290004 |
| 152 | #define F0900_I2CADDR_INC 0xf1290003 |
| 153 | |
| 154 | /*P1_I2CRPT*/ |
| 155 | #define R0900_P1_I2CRPT 0xf12a |
| 156 | #define F0900_P1_I2CT_ON 0xf12a0080 |
| 157 | #define F0900_P1_ENARPT_LEVEL 0xf12a0070 |
| 158 | #define F0900_P1_SCLT_DELAY 0xf12a0008 |
| 159 | #define F0900_P1_STOP_ENABLE 0xf12a0004 |
| 160 | #define F0900_P1_STOP_SDAT2SDA 0xf12a0002 |
| 161 | |
| 162 | /*P2_I2CRPT*/ |
| 163 | #define R0900_P2_I2CRPT 0xf12b |
| 164 | #define F0900_P2_I2CT_ON 0xf12b0080 |
| 165 | #define F0900_P2_ENARPT_LEVEL 0xf12b0070 |
| 166 | #define F0900_P2_SCLT_DELAY 0xf12b0008 |
| 167 | #define F0900_P2_STOP_ENABLE 0xf12b0004 |
| 168 | #define F0900_P2_STOP_SDAT2SDA 0xf12b0002 |
| 169 | |
| 170 | /*CLKI2CFG*/ |
| 171 | #define R0900_CLKI2CFG 0xf140 |
| 172 | #define F0900_CLKI2_OPD 0xf1400080 |
| 173 | #define F0900_CLKI2_CONFIG 0xf140007e |
| 174 | #define F0900_CLKI2_XOR 0xf1400001 |
| 175 | |
| 176 | /*GPIO1CFG*/ |
| 177 | #define R0900_GPIO1CFG 0xf141 |
| 178 | #define F0900_GPIO1_OPD 0xf1410080 |
| 179 | #define F0900_GPIO1_CONFIG 0xf141007e |
| 180 | #define F0900_GPIO1_XOR 0xf1410001 |
| 181 | |
| 182 | /*GPIO2CFG*/ |
| 183 | #define R0900_GPIO2CFG 0xf142 |
| 184 | #define F0900_GPIO2_OPD 0xf1420080 |
| 185 | #define F0900_GPIO2_CONFIG 0xf142007e |
| 186 | #define F0900_GPIO2_XOR 0xf1420001 |
| 187 | |
| 188 | /*GPIO3CFG*/ |
| 189 | #define R0900_GPIO3CFG 0xf143 |
| 190 | #define F0900_GPIO3_OPD 0xf1430080 |
| 191 | #define F0900_GPIO3_CONFIG 0xf143007e |
| 192 | #define F0900_GPIO3_XOR 0xf1430001 |
| 193 | |
| 194 | /*GPIO4CFG*/ |
| 195 | #define R0900_GPIO4CFG 0xf144 |
| 196 | #define F0900_GPIO4_OPD 0xf1440080 |
| 197 | #define F0900_GPIO4_CONFIG 0xf144007e |
| 198 | #define F0900_GPIO4_XOR 0xf1440001 |
| 199 | |
| 200 | /*GPIO5CFG*/ |
| 201 | #define R0900_GPIO5CFG 0xf145 |
| 202 | #define F0900_GPIO5_OPD 0xf1450080 |
| 203 | #define F0900_GPIO5_CONFIG 0xf145007e |
| 204 | #define F0900_GPIO5_XOR 0xf1450001 |
| 205 | |
| 206 | /*GPIO6CFG*/ |
| 207 | #define R0900_GPIO6CFG 0xf146 |
| 208 | #define F0900_GPIO6_OPD 0xf1460080 |
| 209 | #define F0900_GPIO6_CONFIG 0xf146007e |
| 210 | #define F0900_GPIO6_XOR 0xf1460001 |
| 211 | |
| 212 | /*GPIO7CFG*/ |
| 213 | #define R0900_GPIO7CFG 0xf147 |
| 214 | #define F0900_GPIO7_OPD 0xf1470080 |
| 215 | #define F0900_GPIO7_CONFIG 0xf147007e |
| 216 | #define F0900_GPIO7_XOR 0xf1470001 |
| 217 | |
| 218 | /*GPIO8CFG*/ |
| 219 | #define R0900_GPIO8CFG 0xf148 |
| 220 | #define F0900_GPIO8_OPD 0xf1480080 |
| 221 | #define F0900_GPIO8_CONFIG 0xf148007e |
| 222 | #define F0900_GPIO8_XOR 0xf1480001 |
| 223 | |
| 224 | /*GPIO9CFG*/ |
| 225 | #define R0900_GPIO9CFG 0xf149 |
| 226 | #define F0900_GPIO9_OPD 0xf1490080 |
| 227 | #define F0900_GPIO9_CONFIG 0xf149007e |
| 228 | #define F0900_GPIO9_XOR 0xf1490001 |
| 229 | |
| 230 | /*GPIO10CFG*/ |
| 231 | #define R0900_GPIO10CFG 0xf14a |
| 232 | #define F0900_GPIO10_OPD 0xf14a0080 |
| 233 | #define F0900_GPIO10_CONFIG 0xf14a007e |
| 234 | #define F0900_GPIO10_XOR 0xf14a0001 |
| 235 | |
| 236 | /*GPIO11CFG*/ |
| 237 | #define R0900_GPIO11CFG 0xf14b |
| 238 | #define F0900_GPIO11_OPD 0xf14b0080 |
| 239 | #define F0900_GPIO11_CONFIG 0xf14b007e |
| 240 | #define F0900_GPIO11_XOR 0xf14b0001 |
| 241 | |
| 242 | /*GPIO12CFG*/ |
| 243 | #define R0900_GPIO12CFG 0xf14c |
| 244 | #define F0900_GPIO12_OPD 0xf14c0080 |
| 245 | #define F0900_GPIO12_CONFIG 0xf14c007e |
| 246 | #define F0900_GPIO12_XOR 0xf14c0001 |
| 247 | |
| 248 | /*GPIO13CFG*/ |
| 249 | #define R0900_GPIO13CFG 0xf14d |
| 250 | #define F0900_GPIO13_OPD 0xf14d0080 |
| 251 | #define F0900_GPIO13_CONFIG 0xf14d007e |
| 252 | #define F0900_GPIO13_XOR 0xf14d0001 |
| 253 | |
| 254 | /*CS0CFG*/ |
| 255 | #define R0900_CS0CFG 0xf14e |
| 256 | #define F0900_CS0_OPD 0xf14e0080 |
| 257 | #define F0900_CS0_CONFIG 0xf14e007e |
| 258 | #define F0900_CS0_XOR 0xf14e0001 |
| 259 | |
| 260 | /*CS1CFG*/ |
| 261 | #define R0900_CS1CFG 0xf14f |
| 262 | #define F0900_CS1_OPD 0xf14f0080 |
| 263 | #define F0900_CS1_CONFIG 0xf14f007e |
| 264 | #define F0900_CS1_XOR 0xf14f0001 |
| 265 | |
| 266 | /*STDBYCFG*/ |
| 267 | #define R0900_STDBYCFG 0xf150 |
| 268 | #define F0900_STDBY_OPD 0xf1500080 |
| 269 | #define F0900_STDBY_CONFIG 0xf150007e |
| 270 | #define F0900_STBDY_XOR 0xf1500001 |
| 271 | |
| 272 | /*DIRCLKCFG*/ |
| 273 | #define R0900_DIRCLKCFG 0xf151 |
| 274 | #define F0900_DIRCLK_OPD 0xf1510080 |
| 275 | #define F0900_DIRCLK_CONFIG 0xf151007e |
| 276 | #define F0900_DIRCLK_XOR 0xf1510001 |
| 277 | |
| 278 | /*AGCRF1CFG*/ |
| 279 | #define R0900_AGCRF1CFG 0xf152 |
| 280 | #define F0900_AGCRF1_OPD 0xf1520080 |
| 281 | #define F0900_AGCRF1_CONFIG 0xf152007e |
| 282 | #define F0900_AGCRF1_XOR 0xf1520001 |
| 283 | |
| 284 | /*SDAT1CFG*/ |
| 285 | #define R0900_SDAT1CFG 0xf153 |
| 286 | #define F0900_SDAT1_OPD 0xf1530080 |
| 287 | #define F0900_SDAT1_CONFIG 0xf153007e |
| 288 | #define F0900_SDAT1_XOR 0xf1530001 |
| 289 | |
| 290 | /*SCLT1CFG*/ |
| 291 | #define R0900_SCLT1CFG 0xf154 |
| 292 | #define F0900_SCLT1_OPD 0xf1540080 |
| 293 | #define F0900_SCLT1_CONFIG 0xf154007e |
| 294 | #define F0900_SCLT1_XOR 0xf1540001 |
| 295 | |
| 296 | /*DISEQCO1CFG*/ |
| 297 | #define R0900_DISEQCO1CFG 0xf155 |
| 298 | #define F0900_DISEQCO1_OPD 0xf1550080 |
| 299 | #define F0900_DISEQCO1_CONFIG 0xf155007e |
| 300 | #define F0900_DISEQC1_XOR 0xf1550001 |
| 301 | |
| 302 | /*AGCRF2CFG*/ |
| 303 | #define R0900_AGCRF2CFG 0xf156 |
| 304 | #define F0900_AGCRF2_OPD 0xf1560080 |
| 305 | #define F0900_AGCRF2_CONFIG 0xf156007e |
| 306 | #define F0900_AGCRF2_XOR 0xf1560001 |
| 307 | |
| 308 | /*SDAT2CFG*/ |
| 309 | #define R0900_SDAT2CFG 0xf157 |
| 310 | #define F0900_SDAT2_OPD 0xf1570080 |
| 311 | #define F0900_SDAT2_CONFIG 0xf157007e |
| 312 | #define F0900_SDAT2_XOR 0xf1570001 |
| 313 | |
| 314 | /*SCLT2CFG*/ |
| 315 | #define R0900_SCLT2CFG 0xf158 |
| 316 | #define F0900_SCLT2_OPD 0xf1580080 |
| 317 | #define F0900_SCLT2_CONFIG 0xf158007e |
| 318 | #define F0900_SCLT2_XOR 0xf1580001 |
| 319 | |
| 320 | /*DISEQCO2CFG*/ |
| 321 | #define R0900_DISEQCO2CFG 0xf159 |
| 322 | #define F0900_DISEQCO2_OPD 0xf1590080 |
| 323 | #define F0900_DISEQCO2_CONFIG 0xf159007e |
| 324 | #define F0900_DISEQC2_XOR 0xf1590001 |
| 325 | |
| 326 | /*CLKOUT27CFG*/ |
| 327 | #define R0900_CLKOUT27CFG 0xf15a |
| 328 | #define F0900_CLKOUT27_OPD 0xf15a0080 |
| 329 | #define F0900_CLKOUT27_CONFIG 0xf15a007e |
| 330 | #define F0900_CLKOUT27_XOR 0xf15a0001 |
| 331 | |
| 332 | /*ERROR1CFG*/ |
| 333 | #define R0900_ERROR1CFG 0xf15b |
| 334 | #define F0900_ERROR1_OPD 0xf15b0080 |
| 335 | #define F0900_ERROR1_CONFIG 0xf15b007e |
| 336 | #define F0900_ERROR1_XOR 0xf15b0001 |
| 337 | |
| 338 | /*DPN1CFG*/ |
| 339 | #define R0900_DPN1CFG 0xf15c |
| 340 | #define F0900_DPN1_OPD 0xf15c0080 |
| 341 | #define F0900_DPN1_CONFIG 0xf15c007e |
| 342 | #define F0900_DPN1_XOR 0xf15c0001 |
| 343 | |
| 344 | /*STROUT1CFG*/ |
| 345 | #define R0900_STROUT1CFG 0xf15d |
| 346 | #define F0900_STROUT1_OPD 0xf15d0080 |
| 347 | #define F0900_STROUT1_CONFIG 0xf15d007e |
| 348 | #define F0900_STROUT1_XOR 0xf15d0001 |
| 349 | |
| 350 | /*CLKOUT1CFG*/ |
| 351 | #define R0900_CLKOUT1CFG 0xf15e |
| 352 | #define F0900_CLKOUT1_OPD 0xf15e0080 |
| 353 | #define F0900_CLKOUT1_CONFIG 0xf15e007e |
| 354 | #define F0900_CLKOUT1_XOR 0xf15e0001 |
| 355 | |
| 356 | /*DATA71CFG*/ |
| 357 | #define R0900_DATA71CFG 0xf15f |
| 358 | #define F0900_DATA71_OPD 0xf15f0080 |
| 359 | #define F0900_DATA71_CONFIG 0xf15f007e |
| 360 | #define F0900_DATA71_XOR 0xf15f0001 |
| 361 | |
| 362 | /*ERROR2CFG*/ |
| 363 | #define R0900_ERROR2CFG 0xf160 |
| 364 | #define F0900_ERROR2_OPD 0xf1600080 |
| 365 | #define F0900_ERROR2_CONFIG 0xf160007e |
| 366 | #define F0900_ERROR2_XOR 0xf1600001 |
| 367 | |
| 368 | /*DPN2CFG*/ |
| 369 | #define R0900_DPN2CFG 0xf161 |
| 370 | #define F0900_DPN2_OPD 0xf1610080 |
| 371 | #define F0900_DPN2_CONFIG 0xf161007e |
| 372 | #define F0900_DPN2_XOR 0xf1610001 |
| 373 | |
| 374 | /*STROUT2CFG*/ |
| 375 | #define R0900_STROUT2CFG 0xf162 |
| 376 | #define F0900_STROUT2_OPD 0xf1620080 |
| 377 | #define F0900_STROUT2_CONFIG 0xf162007e |
| 378 | #define F0900_STROUT2_XOR 0xf1620001 |
| 379 | |
| 380 | /*CLKOUT2CFG*/ |
| 381 | #define R0900_CLKOUT2CFG 0xf163 |
| 382 | #define F0900_CLKOUT2_OPD 0xf1630080 |
| 383 | #define F0900_CLKOUT2_CONFIG 0xf163007e |
| 384 | #define F0900_CLKOUT2_XOR 0xf1630001 |
| 385 | |
| 386 | /*DATA72CFG*/ |
| 387 | #define R0900_DATA72CFG 0xf164 |
| 388 | #define F0900_DATA72_OPD 0xf1640080 |
| 389 | #define F0900_DATA72_CONFIG 0xf164007e |
| 390 | #define F0900_DATA72_XOR 0xf1640001 |
| 391 | |
| 392 | /*ERROR3CFG*/ |
| 393 | #define R0900_ERROR3CFG 0xf165 |
| 394 | #define F0900_ERROR3_OPD 0xf1650080 |
| 395 | #define F0900_ERROR3_CONFIG 0xf165007e |
| 396 | #define F0900_ERROR3_XOR 0xf1650001 |
| 397 | |
| 398 | /*DPN3CFG*/ |
| 399 | #define R0900_DPN3CFG 0xf166 |
| 400 | #define F0900_DPN3_OPD 0xf1660080 |
| 401 | #define F0900_DPN3_CONFIG 0xf166007e |
| 402 | #define F0900_DPN3_XOR 0xf1660001 |
| 403 | |
| 404 | /*STROUT3CFG*/ |
| 405 | #define R0900_STROUT3CFG 0xf167 |
| 406 | #define F0900_STROUT3_OPD 0xf1670080 |
| 407 | #define F0900_STROUT3_CONFIG 0xf167007e |
| 408 | #define F0900_STROUT3_XOR 0xf1670001 |
| 409 | |
| 410 | /*CLKOUT3CFG*/ |
| 411 | #define R0900_CLKOUT3CFG 0xf168 |
| 412 | #define F0900_CLKOUT3_OPD 0xf1680080 |
| 413 | #define F0900_CLKOUT3_CONFIG 0xf168007e |
| 414 | #define F0900_CLKOUT3_XOR 0xf1680001 |
| 415 | |
| 416 | /*DATA73CFG*/ |
| 417 | #define R0900_DATA73CFG 0xf169 |
| 418 | #define F0900_DATA73_OPD 0xf1690080 |
| 419 | #define F0900_DATA73_CONFIG 0xf169007e |
| 420 | #define F0900_DATA73_XOR 0xf1690001 |
| 421 | |
| 422 | /*FSKTFC2*/ |
| 423 | #define R0900_FSKTFC2 0xf170 |
| 424 | #define F0900_FSKT_KMOD 0xf17000fc |
| 425 | #define F0900_FSKT_CAR2 0xf1700003 |
| 426 | |
| 427 | /*FSKTFC1*/ |
| 428 | #define R0900_FSKTFC1 0xf171 |
| 429 | #define F0900_FSKT_CAR1 0xf17100ff |
| 430 | |
| 431 | /*FSKTFC0*/ |
| 432 | #define R0900_FSKTFC0 0xf172 |
| 433 | #define F0900_FSKT_CAR0 0xf17200ff |
| 434 | |
| 435 | /*FSKTDELTAF1*/ |
| 436 | #define R0900_FSKTDELTAF1 0xf173 |
| 437 | #define F0900_FSKT_DELTAF1 0xf173000f |
| 438 | |
| 439 | /*FSKTDELTAF0*/ |
| 440 | #define R0900_FSKTDELTAF0 0xf174 |
| 441 | #define F0900_FSKT_DELTAF0 0xf17400ff |
| 442 | |
| 443 | /*FSKTCTRL*/ |
| 444 | #define R0900_FSKTCTRL 0xf175 |
| 445 | #define F0900_FSKT_EN_SGN 0xf1750040 |
| 446 | #define F0900_FSKT_MOD_SGN 0xf1750020 |
| 447 | #define F0900_FSKT_MOD_EN 0xf175001c |
| 448 | #define F0900_FSKT_DACMODE 0xf1750003 |
| 449 | |
| 450 | /*FSKRFC2*/ |
| 451 | #define R0900_FSKRFC2 0xf176 |
| 452 | #define F0900_FSKR_DETSGN 0xf1760040 |
| 453 | #define F0900_FSKR_OUTSGN 0xf1760020 |
| 454 | #define F0900_FSKR_KAGC 0xf176001c |
| 455 | #define F0900_FSKR_CAR2 0xf1760003 |
| 456 | |
| 457 | /*FSKRFC1*/ |
| 458 | #define R0900_FSKRFC1 0xf177 |
| 459 | #define F0900_FSKR_CAR1 0xf17700ff |
| 460 | |
| 461 | /*FSKRFC0*/ |
| 462 | #define R0900_FSKRFC0 0xf178 |
| 463 | #define F0900_FSKR_CAR0 0xf17800ff |
| 464 | |
| 465 | /*FSKRK1*/ |
| 466 | #define R0900_FSKRK1 0xf179 |
| 467 | #define F0900_FSKR_K1_EXP 0xf17900e0 |
| 468 | #define F0900_FSKR_K1_MANT 0xf179001f |
| 469 | |
| 470 | /*FSKRK2*/ |
| 471 | #define R0900_FSKRK2 0xf17a |
| 472 | #define F0900_FSKR_K2_EXP 0xf17a00e0 |
| 473 | #define F0900_FSKR_K2_MANT 0xf17a001f |
| 474 | |
| 475 | /*FSKRAGCR*/ |
| 476 | #define R0900_FSKRAGCR 0xf17b |
| 477 | #define F0900_FSKR_OUTCTL 0xf17b00c0 |
| 478 | #define F0900_FSKR_AGC_REF 0xf17b003f |
| 479 | |
| 480 | /*FSKRAGC*/ |
| 481 | #define R0900_FSKRAGC 0xf17c |
| 482 | #define F0900_FSKR_AGC_ACCU 0xf17c00ff |
| 483 | |
| 484 | /*FSKRALPHA*/ |
| 485 | #define R0900_FSKRALPHA 0xf17d |
| 486 | #define F0900_FSKR_ALPHA_EXP 0xf17d001c |
| 487 | #define F0900_FSKR_ALPHA_M 0xf17d0003 |
| 488 | |
| 489 | /*FSKRPLTH1*/ |
| 490 | #define R0900_FSKRPLTH1 0xf17e |
| 491 | #define F0900_FSKR_BETA 0xf17e00f0 |
| 492 | #define F0900_FSKR_PLL_TRESH1 0xf17e000f |
| 493 | |
| 494 | /*FSKRPLTH0*/ |
| 495 | #define R0900_FSKRPLTH0 0xf17f |
| 496 | #define F0900_FSKR_PLL_TRESH0 0xf17f00ff |
| 497 | |
| 498 | /*FSKRDF1*/ |
| 499 | #define R0900_FSKRDF1 0xf180 |
| 500 | #define F0900_FSKR_OUT 0xf1800080 |
| 501 | #define F0900_FSKR_DELTAF1 0xf180001f |
| 502 | |
| 503 | /*FSKRDF0*/ |
| 504 | #define R0900_FSKRDF0 0xf181 |
| 505 | #define F0900_FSKR_DELTAF0 0xf18100ff |
| 506 | |
| 507 | /*FSKRSTEPP*/ |
| 508 | #define R0900_FSKRSTEPP 0xf182 |
| 509 | #define F0900_FSKR_STEP_PLUS 0xf18200ff |
| 510 | |
| 511 | /*FSKRSTEPM*/ |
| 512 | #define R0900_FSKRSTEPM 0xf183 |
| 513 | #define F0900_FSKR_STEP_MINUS 0xf18300ff |
| 514 | |
| 515 | /*FSKRDET1*/ |
| 516 | #define R0900_FSKRDET1 0xf184 |
| 517 | #define F0900_FSKR_DETECT 0xf1840080 |
| 518 | #define F0900_FSKR_CARDET_ACCU1 0xf184000f |
| 519 | |
| 520 | /*FSKRDET0*/ |
| 521 | #define R0900_FSKRDET0 0xf185 |
| 522 | #define F0900_FSKR_CARDET_ACCU0 0xf18500ff |
| 523 | |
| 524 | /*FSKRDTH1*/ |
| 525 | #define R0900_FSKRDTH1 0xf186 |
| 526 | #define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0 |
| 527 | #define F0900_FSKR_CARDET_THRESH1 0xf186000f |
| 528 | |
| 529 | /*FSKRDTH0*/ |
| 530 | #define R0900_FSKRDTH0 0xf187 |
| 531 | #define F0900_FSKR_CARDET_THRESH0 0xf18700ff |
| 532 | |
| 533 | /*FSKRLOSS*/ |
| 534 | #define R0900_FSKRLOSS 0xf188 |
| 535 | #define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff |
| 536 | |
| 537 | /*P2_DISTXCTL*/ |
| 538 | #define R0900_P2_DISTXCTL 0xf190 |
| 539 | #define F0900_P2_TIM_OFF 0xf1900080 |
| 540 | #define F0900_P2_DISEQC_RESET 0xf1900040 |
| 541 | #define F0900_P2_TIM_CMD 0xf1900030 |
| 542 | #define F0900_P2_DIS_PRECHARGE 0xf1900008 |
| 543 | #define F0900_P2_DISTX_MODE 0xf1900007 |
| 544 | |
| 545 | /*P2_DISRXCTL*/ |
| 546 | #define R0900_P2_DISRXCTL 0xf191 |
| 547 | #define F0900_P2_RECEIVER_ON 0xf1910080 |
| 548 | #define F0900_P2_IGNO_SHORT22K 0xf1910040 |
| 549 | #define F0900_P2_ONECHIP_TRX 0xf1910020 |
| 550 | #define F0900_P2_EXT_ENVELOP 0xf1910010 |
| 551 | #define F0900_P2_PIN_SELECT 0xf191000c |
| 552 | #define F0900_P2_IRQ_RXEND 0xf1910002 |
| 553 | #define F0900_P2_IRQ_4NBYTES 0xf1910001 |
| 554 | |
| 555 | /*P2_DISRX_ST0*/ |
| 556 | #define R0900_P2_DISRX_ST0 0xf194 |
| 557 | #define F0900_P2_RX_END 0xf1940080 |
| 558 | #define F0900_P2_RX_ACTIVE 0xf1940040 |
| 559 | #define F0900_P2_SHORT_22KHZ 0xf1940020 |
| 560 | #define F0900_P2_CONT_TONE 0xf1940010 |
| 561 | #define F0900_P2_FIFO_4BREADY 0xf1940008 |
| 562 | #define F0900_P2_FIFO_EMPTY 0xf1940004 |
| 563 | #define F0900_P2_ABORT_DISRX 0xf1940001 |
| 564 | |
| 565 | /*P2_DISRX_ST1*/ |
| 566 | #define R0900_P2_DISRX_ST1 0xf195 |
| 567 | #define F0900_P2_RX_FAIL 0xf1950080 |
| 568 | #define F0900_P2_FIFO_PARITYFAIL 0xf1950040 |
| 569 | #define F0900_P2_RX_NONBYTE 0xf1950020 |
| 570 | #define F0900_P2_FIFO_OVERFLOW 0xf1950010 |
| 571 | #define F0900_P2_FIFO_BYTENBR 0xf195000f |
| 572 | |
| 573 | /*P2_DISRXDATA*/ |
| 574 | #define R0900_P2_DISRXDATA 0xf196 |
| 575 | #define F0900_P2_DISRX_DATA 0xf19600ff |
| 576 | |
| 577 | /*P2_DISTXDATA*/ |
| 578 | #define R0900_P2_DISTXDATA 0xf197 |
| 579 | #define F0900_P2_DISEQC_FIFO 0xf19700ff |
| 580 | |
| 581 | /*P2_DISTXSTATUS*/ |
| 582 | #define R0900_P2_DISTXSTATUS 0xf198 |
| 583 | #define F0900_P2_TX_FAIL 0xf1980080 |
| 584 | #define F0900_P2_FIFO_FULL 0xf1980040 |
| 585 | #define F0900_P2_TX_IDLE 0xf1980020 |
| 586 | #define F0900_P2_GAP_BURST 0xf1980010 |
| 587 | #define F0900_P2_TXFIFO_BYTES 0xf198000f |
| 588 | |
| 589 | /*P2_F22TX*/ |
| 590 | #define R0900_P2_F22TX 0xf199 |
| 591 | #define F0900_P2_F22_REG 0xf19900ff |
| 592 | |
| 593 | /*P2_F22RX*/ |
| 594 | #define R0900_P2_F22RX 0xf19a |
| 595 | #define F0900_P2_F22RX_REG 0xf19a00ff |
| 596 | |
| 597 | /*P2_ACRPRESC*/ |
| 598 | #define R0900_P2_ACRPRESC 0xf19c |
| 599 | #define F0900_P2_ACR_CODFRDY 0xf19c0008 |
| 600 | #define F0900_P2_ACR_PRESC 0xf19c0007 |
| 601 | |
| 602 | /*P2_ACRDIV*/ |
| 603 | #define R0900_P2_ACRDIV 0xf19d |
| 604 | #define F0900_P2_ACR_DIV 0xf19d00ff |
| 605 | |
| 606 | /*P1_DISTXCTL*/ |
| 607 | #define R0900_P1_DISTXCTL 0xf1a0 |
| 608 | #define F0900_P1_TIM_OFF 0xf1a00080 |
| 609 | #define F0900_P1_DISEQC_RESET 0xf1a00040 |
| 610 | #define F0900_P1_TIM_CMD 0xf1a00030 |
| 611 | #define F0900_P1_DIS_PRECHARGE 0xf1a00008 |
| 612 | #define F0900_P1_DISTX_MODE 0xf1a00007 |
| 613 | |
| 614 | /*P1_DISRXCTL*/ |
| 615 | #define R0900_P1_DISRXCTL 0xf1a1 |
| 616 | #define F0900_P1_RECEIVER_ON 0xf1a10080 |
| 617 | #define F0900_P1_IGNO_SHORT22K 0xf1a10040 |
| 618 | #define F0900_P1_ONECHIP_TRX 0xf1a10020 |
| 619 | #define F0900_P1_EXT_ENVELOP 0xf1a10010 |
| 620 | #define F0900_P1_PIN_SELECT 0xf1a1000c |
| 621 | #define F0900_P1_IRQ_RXEND 0xf1a10002 |
| 622 | #define F0900_P1_IRQ_4NBYTES 0xf1a10001 |
| 623 | |
| 624 | /*P1_DISRX_ST0*/ |
| 625 | #define R0900_P1_DISRX_ST0 0xf1a4 |
| 626 | #define F0900_P1_RX_END 0xf1a40080 |
| 627 | #define F0900_P1_RX_ACTIVE 0xf1a40040 |
| 628 | #define F0900_P1_SHORT_22KHZ 0xf1a40020 |
| 629 | #define F0900_P1_CONT_TONE 0xf1a40010 |
| 630 | #define F0900_P1_FIFO_4BREADY 0xf1a40008 |
| 631 | #define F0900_P1_FIFO_EMPTY 0xf1a40004 |
| 632 | #define F0900_P1_ABORT_DISRX 0xf1a40001 |
| 633 | |
| 634 | /*P1_DISRX_ST1*/ |
| 635 | #define R0900_P1_DISRX_ST1 0xf1a5 |
| 636 | #define F0900_P1_RX_FAIL 0xf1a50080 |
| 637 | #define F0900_P1_FIFO_PARITYFAIL 0xf1a50040 |
| 638 | #define F0900_P1_RX_NONBYTE 0xf1a50020 |
| 639 | #define F0900_P1_FIFO_OVERFLOW 0xf1a50010 |
| 640 | #define F0900_P1_FIFO_BYTENBR 0xf1a5000f |
| 641 | |
| 642 | /*P1_DISRXDATA*/ |
| 643 | #define R0900_P1_DISRXDATA 0xf1a6 |
| 644 | #define F0900_P1_DISRX_DATA 0xf1a600ff |
| 645 | |
| 646 | /*P1_DISTXDATA*/ |
| 647 | #define R0900_P1_DISTXDATA 0xf1a7 |
| 648 | #define F0900_P1_DISEQC_FIFO 0xf1a700ff |
| 649 | |
| 650 | /*P1_DISTXSTATUS*/ |
| 651 | #define R0900_P1_DISTXSTATUS 0xf1a8 |
| 652 | #define F0900_P1_TX_FAIL 0xf1a80080 |
| 653 | #define F0900_P1_FIFO_FULL 0xf1a80040 |
| 654 | #define F0900_P1_TX_IDLE 0xf1a80020 |
| 655 | #define F0900_P1_GAP_BURST 0xf1a80010 |
| 656 | #define F0900_P1_TXFIFO_BYTES 0xf1a8000f |
| 657 | |
| 658 | /*P1_F22TX*/ |
| 659 | #define R0900_P1_F22TX 0xf1a9 |
| 660 | #define F0900_P1_F22_REG 0xf1a900ff |
| 661 | |
| 662 | /*P1_F22RX*/ |
| 663 | #define R0900_P1_F22RX 0xf1aa |
| 664 | #define F0900_P1_F22RX_REG 0xf1aa00ff |
| 665 | |
| 666 | /*P1_ACRPRESC*/ |
| 667 | #define R0900_P1_ACRPRESC 0xf1ac |
| 668 | #define F0900_P1_ACR_CODFRDY 0xf1ac0008 |
| 669 | #define F0900_P1_ACR_PRESC 0xf1ac0007 |
| 670 | |
| 671 | /*P1_ACRDIV*/ |
| 672 | #define R0900_P1_ACRDIV 0xf1ad |
| 673 | #define F0900_P1_ACR_DIV 0xf1ad00ff |
| 674 | |
| 675 | /*NCOARSE*/ |
| 676 | #define R0900_NCOARSE 0xf1b3 |
| 677 | #define F0900_M_DIV 0xf1b300ff |
| 678 | |
| 679 | /*SYNTCTRL*/ |
| 680 | #define R0900_SYNTCTRL 0xf1b6 |
| 681 | #define F0900_STANDBY 0xf1b60080 |
| 682 | #define F0900_BYPASSPLLCORE 0xf1b60040 |
| 683 | #define F0900_SELX1RATIO 0xf1b60020 |
| 684 | #define F0900_I2C_TUD 0xf1b60010 |
| 685 | #define F0900_STOP_PLL 0xf1b60008 |
| 686 | #define F0900_BYPASSPLLFSK 0xf1b60004 |
| 687 | #define F0900_SELOSCI 0xf1b60002 |
| 688 | #define F0900_BYPASSPLLADC 0xf1b60001 |
| 689 | |
| 690 | /*FILTCTRL*/ |
| 691 | #define R0900_FILTCTRL 0xf1b7 |
| 692 | #define F0900_INV_CLK135 0xf1b70080 |
| 693 | #define F0900_PERM_BYPDIS 0xf1b70040 |
| 694 | #define F0900_SEL_FSKCKDIV 0xf1b70004 |
| 695 | #define F0900_INV_CLKFSK 0xf1b70002 |
| 696 | #define F0900_BYPASS_APPLI 0xf1b70001 |
| 697 | |
| 698 | /*PLLSTAT*/ |
| 699 | #define R0900_PLLSTAT 0xf1b8 |
| 700 | #define F0900_ACM_SEL 0xf1b80080 |
| 701 | #define F0900_DTV_SEL 0xf1b80040 |
| 702 | #define F0900_PLLLOCK 0xf1b80001 |
| 703 | |
| 704 | /*STOPCLK1*/ |
| 705 | #define R0900_STOPCLK1 0xf1c2 |
| 706 | #define F0900_STOP_CLKPKDT2 0xf1c20040 |
| 707 | #define F0900_STOP_CLKPKDT1 0xf1c20020 |
| 708 | #define F0900_STOP_CLKFEC 0xf1c20010 |
| 709 | #define F0900_STOP_CLKADCI2 0xf1c20008 |
| 710 | #define F0900_INV_CLKADCI2 0xf1c20004 |
| 711 | #define F0900_STOP_CLKADCI1 0xf1c20002 |
| 712 | #define F0900_INV_CLKADCI1 0xf1c20001 |
| 713 | |
| 714 | /*STOPCLK2*/ |
| 715 | #define R0900_STOPCLK2 0xf1c3 |
| 716 | #define F0900_STOP_CLKSAMP2 0xf1c30010 |
| 717 | #define F0900_STOP_CLKSAMP1 0xf1c30008 |
| 718 | #define F0900_STOP_CLKVIT2 0xf1c30004 |
| 719 | #define F0900_STOP_CLKVIT1 0xf1c30002 |
| 720 | #define F0900_STOP_CLKTS 0xf1c30001 |
| 721 | |
| 722 | /*TSTTNR0*/ |
| 723 | #define R0900_TSTTNR0 0xf1df |
| 724 | #define F0900_SEL_FSK 0xf1df0080 |
| 725 | #define F0900_FSK_PON 0xf1df0004 |
| 726 | #define F0900_FSK_OPENLOOP 0xf1df0002 |
| 727 | |
| 728 | /*TSTTNR1*/ |
| 729 | #define R0900_TSTTNR1 0xf1e0 |
| 730 | #define F0900_BYPASS_ADC1 0xf1e00080 |
| 731 | #define F0900_INVADC1_CKOUT 0xf1e00040 |
| 732 | #define F0900_SELIQSRC1 0xf1e00030 |
| 733 | #define F0900_ADC1_PON 0xf1e00002 |
| 734 | #define F0900_ADC1_INMODE 0xf1e00001 |
| 735 | |
| 736 | /*TSTTNR2*/ |
| 737 | #define R0900_TSTTNR2 0xf1e1 |
| 738 | #define F0900_DISEQC1_PON 0xf1e10020 |
| 739 | #define F0900_DISEQC1_TEST 0xf1e1001f |
| 740 | |
| 741 | /*TSTTNR3*/ |
| 742 | #define R0900_TSTTNR3 0xf1e2 |
| 743 | #define F0900_BYPASS_ADC2 0xf1e20080 |
| 744 | #define F0900_INVADC2_CKOUT 0xf1e20040 |
| 745 | #define F0900_SELIQSRC2 0xf1e20030 |
| 746 | #define F0900_ADC2_PON 0xf1e20002 |
| 747 | #define F0900_ADC2_INMODE 0xf1e20001 |
| 748 | |
| 749 | /*TSTTNR4*/ |
| 750 | #define R0900_TSTTNR4 0xf1e3 |
| 751 | #define F0900_DISEQC2_PON 0xf1e30020 |
| 752 | #define F0900_DISEQC2_TEST 0xf1e3001f |
| 753 | |
| 754 | /*P2_IQCONST*/ |
| 755 | #define R0900_P2_IQCONST 0xf200 |
| 756 | #define F0900_P2_CONSTEL_SELECT 0xf2000060 |
| 757 | #define F0900_P2_IQSYMB_SEL 0xf200001f |
| 758 | |
| 759 | /*P2_NOSCFG*/ |
| 760 | #define R0900_P2_NOSCFG 0xf201 |
| 761 | #define F0900_P2_DUMMYPL_NOSDATA 0xf2010020 |
| 762 | #define F0900_P2_NOSPLH_BETA 0xf2010018 |
| 763 | #define F0900_P2_NOSDATA_BETA 0xf2010007 |
| 764 | |
| 765 | /*P2_ISYMB*/ |
| 766 | #define R0900_P2_ISYMB 0xf202 |
| 767 | #define F0900_P2_I_SYMBOL 0xf20201ff |
| 768 | |
| 769 | /*P2_QSYMB*/ |
| 770 | #define R0900_P2_QSYMB 0xf203 |
| 771 | #define F0900_P2_Q_SYMBOL 0xf20301ff |
| 772 | |
| 773 | /*P2_AGC1CFG*/ |
| 774 | #define R0900_P2_AGC1CFG 0xf204 |
| 775 | #define F0900_P2_DC_FROZEN 0xf2040080 |
| 776 | #define F0900_P2_DC_CORRECT 0xf2040040 |
| 777 | #define F0900_P2_AMM_FROZEN 0xf2040020 |
| 778 | #define F0900_P2_AMM_CORRECT 0xf2040010 |
| 779 | #define F0900_P2_QUAD_FROZEN 0xf2040008 |
| 780 | #define F0900_P2_QUAD_CORRECT 0xf2040004 |
| 781 | #define F0900_P2_DCCOMP_SLOW 0xf2040002 |
| 782 | #define F0900_P2_IQMISM_SLOW 0xf2040001 |
| 783 | |
| 784 | /*P2_AGC1CN*/ |
| 785 | #define R0900_P2_AGC1CN 0xf206 |
| 786 | #define F0900_P2_AGC1_LOCKED 0xf2060080 |
| 787 | #define F0900_P2_AGC1_OVERFLOW 0xf2060040 |
| 788 | #define F0900_P2_AGC1_NOSLOWLK 0xf2060020 |
| 789 | #define F0900_P2_AGC1_MINPOWER 0xf2060010 |
| 790 | #define F0900_P2_AGCOUT_FAST 0xf2060008 |
| 791 | #define F0900_P2_AGCIQ_BETA 0xf2060007 |
| 792 | |
| 793 | /*P2_AGC1REF*/ |
| 794 | #define R0900_P2_AGC1REF 0xf207 |
| 795 | #define F0900_P2_AGCIQ_REF 0xf20700ff |
| 796 | |
| 797 | /*P2_IDCCOMP*/ |
| 798 | #define R0900_P2_IDCCOMP 0xf208 |
| 799 | #define F0900_P2_IAVERAGE_ADJ 0xf20801ff |
| 800 | |
| 801 | /*P2_QDCCOMP*/ |
| 802 | #define R0900_P2_QDCCOMP 0xf209 |
| 803 | #define F0900_P2_QAVERAGE_ADJ 0xf20901ff |
| 804 | |
| 805 | /*P2_POWERI*/ |
| 806 | #define R0900_P2_POWERI 0xf20a |
| 807 | #define F0900_P2_POWER_I 0xf20a00ff |
| 808 | |
| 809 | /*P2_POWERQ*/ |
| 810 | #define R0900_P2_POWERQ 0xf20b |
| 811 | #define F0900_P2_POWER_Q 0xf20b00ff |
| 812 | |
| 813 | /*P2_AGC1AMM*/ |
| 814 | #define R0900_P2_AGC1AMM 0xf20c |
| 815 | #define F0900_P2_AMM_VALUE 0xf20c00ff |
| 816 | |
| 817 | /*P2_AGC1QUAD*/ |
| 818 | #define R0900_P2_AGC1QUAD 0xf20d |
| 819 | #define F0900_P2_QUAD_VALUE 0xf20d01ff |
| 820 | |
| 821 | /*P2_AGCIQIN1*/ |
| 822 | #define R0900_P2_AGCIQIN1 0xf20e |
| 823 | #define F0900_P2_AGCIQ_VALUE1 0xf20e00ff |
| 824 | |
| 825 | /*P2_AGCIQIN0*/ |
| 826 | #define R0900_P2_AGCIQIN0 0xf20f |
| 827 | #define F0900_P2_AGCIQ_VALUE0 0xf20f00ff |
| 828 | |
| 829 | /*P2_DEMOD*/ |
| 830 | #define R0900_P2_DEMOD 0xf210 |
| 831 | #define F0900_P2_DEMOD_STOP 0xf2100040 |
| 832 | #define F0900_P2_SPECINV_CONTROL 0xf2100030 |
| 833 | #define F0900_P2_FORCE_ENASAMP 0xf2100008 |
| 834 | #define F0900_P2_MANUAL_ROLLOFF 0xf2100004 |
| 835 | #define F0900_P2_ROLLOFF_CONTROL 0xf2100003 |
| 836 | |
| 837 | /*P2_DMDMODCOD*/ |
| 838 | #define R0900_P2_DMDMODCOD 0xf211 |
| 839 | #define F0900_P2_MANUAL_MODCOD 0xf2110080 |
| 840 | #define F0900_P2_DEMOD_MODCOD 0xf211007c |
| 841 | #define F0900_P2_DEMOD_TYPE 0xf2110003 |
| 842 | |
| 843 | /*P2_DSTATUS*/ |
| 844 | #define R0900_P2_DSTATUS 0xf212 |
| 845 | #define F0900_P2_CAR_LOCK 0xf2120080 |
| 846 | #define F0900_P2_TMGLOCK_QUALITY 0xf2120060 |
| 847 | #define F0900_P2_SDVBS1_ENABLE 0xf2120010 |
| 848 | #define F0900_P2_LOCK_DEFINITIF 0xf2120008 |
| 849 | #define F0900_P2_TIMING_IS_LOCKED 0xf2120004 |
| 850 | #define F0900_P2_COARSE_TMGLOCK 0xf2120002 |
| 851 | #define F0900_P2_COARSE_CARLOCK 0xf2120001 |
| 852 | |
| 853 | /*P2_DSTATUS2*/ |
| 854 | #define R0900_P2_DSTATUS2 0xf213 |
| 855 | #define F0900_P2_DEMOD_DELOCK 0xf2130080 |
| 856 | #define F0900_P2_DEMOD_TIMEOUT 0xf2130040 |
| 857 | #define F0900_P2_MODCODRQ_SYNCTAG 0xf2130020 |
| 858 | #define F0900_P2_POLYPH_SATEVENT 0xf2130010 |
| 859 | #define F0900_P2_AGC1_NOSIGNALACK 0xf2130008 |
| 860 | #define F0900_P2_AGC2_OVERFLOW 0xf2130004 |
| 861 | #define F0900_P2_CFR_OVERFLOW 0xf2130002 |
| 862 | #define F0900_P2_GAMMA_OVERUNDER 0xf2130001 |
| 863 | |
| 864 | /*P2_DMDCFGMD*/ |
| 865 | #define R0900_P2_DMDCFGMD 0xf214 |
| 866 | #define F0900_P2_DVBS2_ENABLE 0xf2140080 |
| 867 | #define F0900_P2_DVBS1_ENABLE 0xf2140040 |
| 868 | #define F0900_P2_CFR_AUTOSCAN 0xf2140020 |
| 869 | #define F0900_P2_SCAN_ENABLE 0xf2140010 |
| 870 | #define F0900_P2_TUN_AUTOSCAN 0xf2140008 |
| 871 | #define F0900_P2_NOFORCE_RELOCK 0xf2140004 |
| 872 | #define F0900_P2_TUN_RNG 0xf2140003 |
| 873 | |
| 874 | /*P2_DMDCFG2*/ |
| 875 | #define R0900_P2_DMDCFG2 0xf215 |
| 876 | #define F0900_P2_AGC1_WAITLOCK 0xf2150080 |
| 877 | #define F0900_P2_S1S2_SEQUENTIAL 0xf2150040 |
| 878 | #define F0900_P2_OVERFLOW_TIMEOUT 0xf2150020 |
| 879 | #define F0900_P2_SCANFAIL_TIMEOUT 0xf2150010 |
| 880 | #define F0900_P2_DMDTOUT_BACK 0xf2150008 |
| 881 | #define F0900_P2_CARLOCK_S1ENABLE 0xf2150004 |
| 882 | #define F0900_P2_COARSE_LK3MODE 0xf2150002 |
| 883 | #define F0900_P2_COARSE_LK2MODE 0xf2150001 |
| 884 | |
| 885 | /*P2_DMDISTATE*/ |
| 886 | #define R0900_P2_DMDISTATE 0xf216 |
| 887 | #define F0900_P2_I2C_NORESETDMODE 0xf2160080 |
| 888 | #define F0900_P2_FORCE_ETAPED 0xf2160040 |
| 889 | #define F0900_P2_SDMDRST_DIRCLK 0xf2160020 |
| 890 | #define F0900_P2_I2C_DEMOD_MODE 0xf216001f |
| 891 | |
| 892 | /*P2_DMDT0M*/ |
| 893 | #define R0900_P2_DMDT0M 0xf217 |
| 894 | #define F0900_P2_DMDT0_MIN 0xf21700ff |
| 895 | |
| 896 | /*P2_DMDSTATE*/ |
| 897 | #define R0900_P2_DMDSTATE 0xf21b |
| 898 | #define F0900_P2_DEMOD_LOCKED 0xf21b0080 |
| 899 | #define F0900_P2_HEADER_MODE 0xf21b0060 |
| 900 | #define F0900_P2_DEMOD_MODE 0xf21b001f |
| 901 | |
| 902 | /*P2_DMDFLYW*/ |
| 903 | #define R0900_P2_DMDFLYW 0xf21c |
| 904 | #define F0900_P2_I2C_IRQVAL 0xf21c00f0 |
| 905 | #define F0900_P2_FLYWHEEL_CPT 0xf21c000f |
| 906 | |
| 907 | /*P2_DSTATUS3*/ |
| 908 | #define R0900_P2_DSTATUS3 0xf21d |
| 909 | #define F0900_P2_CFR_ZIGZAG 0xf21d0080 |
| 910 | #define F0900_P2_DEMOD_CFGMODE 0xf21d0060 |
| 911 | #define F0900_P2_GAMMA_LOWBAUDRATE 0xf21d0010 |
| 912 | #define F0900_P2_RELOCK_MODE 0xf21d0008 |
| 913 | #define F0900_P2_DEMOD_FAIL 0xf21d0004 |
| 914 | #define F0900_P2_ETAPE1A_DVBXMEM 0xf21d0003 |
| 915 | |
| 916 | /*P2_DMDCFG3*/ |
| 917 | #define R0900_P2_DMDCFG3 0xf21e |
| 918 | #define F0900_P2_DVBS1_TMGWAIT 0xf21e0080 |
| 919 | #define F0900_P2_NO_BWCENTERING 0xf21e0040 |
| 920 | #define F0900_P2_INV_SEQSRCH 0xf21e0020 |
| 921 | #define F0900_P2_DIS_SFRUPLOW_TRK 0xf21e0010 |
| 922 | #define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008 |
| 923 | #define F0900_P2_LOCKTIME_MODE 0xf21e0007 |
| 924 | |
| 925 | /*P2_DMDCFG4*/ |
| 926 | #define R0900_P2_DMDCFG4 0xf21f |
| 927 | #define F0900_P2_TUNER_NRELAUNCH 0xf21f0008 |
| 928 | #define F0900_P2_DIS_CLKENABLE 0xf21f0004 |
| 929 | #define F0900_P2_DIS_HDRDIVLOCK 0xf21f0002 |
| 930 | #define F0900_P2_NO_TNRWBINIT 0xf21f0001 |
| 931 | |
| 932 | /*P2_CORRELMANT*/ |
| 933 | #define R0900_P2_CORRELMANT 0xf220 |
| 934 | #define F0900_P2_CORREL_MANT 0xf22000ff |
| 935 | |
| 936 | /*P2_CORRELABS*/ |
| 937 | #define R0900_P2_CORRELABS 0xf221 |
| 938 | #define F0900_P2_CORREL_ABS 0xf22100ff |
| 939 | |
| 940 | /*P2_CORRELEXP*/ |
| 941 | #define R0900_P2_CORRELEXP 0xf222 |
| 942 | #define F0900_P2_CORREL_ABSEXP 0xf22200f0 |
| 943 | #define F0900_P2_CORREL_EXP 0xf222000f |
| 944 | |
| 945 | /*P2_PLHMODCOD*/ |
| 946 | #define R0900_P2_PLHMODCOD 0xf224 |
| 947 | #define F0900_P2_SPECINV_DEMOD 0xf2240080 |
| 948 | #define F0900_P2_PLH_MODCOD 0xf224007c |
| 949 | #define F0900_P2_PLH_TYPE 0xf2240003 |
| 950 | |
| 951 | /*P2_AGCK32*/ |
| 952 | #define R0900_P2_AGCK32 0xf22b |
| 953 | #define F0900_P2_R3ADJOFF_32APSK 0xf22b0080 |
| 954 | #define F0900_P2_R2ADJOFF_32APSK 0xf22b0040 |
| 955 | #define F0900_P2_R1ADJOFF_32APSK 0xf22b0020 |
| 956 | #define F0900_P2_RADJ_32APSK 0xf22b001f |
| 957 | |
| 958 | /*P2_AGC2O*/ |
| 959 | #define R0900_P2_AGC2O 0xf22c |
| 960 | #define F0900_P2_AGC2REF_ADJUSTING 0xf22c0080 |
| 961 | #define F0900_P2_AGC2_COARSEFAST 0xf22c0040 |
| 962 | #define F0900_P2_AGC2_LKSQRT 0xf22c0020 |
| 963 | #define F0900_P2_AGC2_LKMODE 0xf22c0010 |
| 964 | #define F0900_P2_AGC2_LKEQUA 0xf22c0008 |
| 965 | #define F0900_P2_AGC2_COEF 0xf22c0007 |
| 966 | |
| 967 | /*P2_AGC2REF*/ |
| 968 | #define R0900_P2_AGC2REF 0xf22d |
| 969 | #define F0900_P2_AGC2_REF 0xf22d00ff |
| 970 | |
| 971 | /*P2_AGC1ADJ*/ |
| 972 | #define R0900_P2_AGC1ADJ 0xf22e |
| 973 | #define F0900_P2_AGC1ADJ_MANUAL 0xf22e0080 |
| 974 | #define F0900_P2_AGC1_ADJUSTED 0xf22e017f |
| 975 | |
| 976 | /*P2_AGC2I1*/ |
| 977 | #define R0900_P2_AGC2I1 0xf236 |
| 978 | #define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff |
| 979 | |
| 980 | /*P2_AGC2I0*/ |
| 981 | #define R0900_P2_AGC2I0 0xf237 |
| 982 | #define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff |
| 983 | |
| 984 | /*P2_CARCFG*/ |
| 985 | #define R0900_P2_CARCFG 0xf238 |
| 986 | #define F0900_P2_CFRUPLOW_AUTO 0xf2380080 |
| 987 | #define F0900_P2_CFRUPLOW_TEST 0xf2380040 |
| 988 | #define F0900_P2_EN_CAR2CENTER 0xf2380020 |
| 989 | #define F0900_P2_CARHDR_NODIV8 0xf2380010 |
| 990 | #define F0900_P2_I2C_ROTA 0xf2380008 |
| 991 | #define F0900_P2_ROTAON 0xf2380004 |
| 992 | #define F0900_P2_PH_DET_ALGO 0xf2380003 |
| 993 | |
| 994 | /*P2_ACLC*/ |
| 995 | #define R0900_P2_ACLC 0xf239 |
| 996 | #define F0900_P2_STOP_S2ALPHA 0xf23900c0 |
| 997 | #define F0900_P2_CAR_ALPHA_MANT 0xf2390030 |
| 998 | #define F0900_P2_CAR_ALPHA_EXP 0xf239000f |
| 999 | |
| 1000 | /*P2_BCLC*/ |
| 1001 | #define R0900_P2_BCLC 0xf23a |
| 1002 | #define F0900_P2_STOP_S2BETA 0xf23a00c0 |
| 1003 | #define F0900_P2_CAR_BETA_MANT 0xf23a0030 |
| 1004 | #define F0900_P2_CAR_BETA_EXP 0xf23a000f |
| 1005 | |
| 1006 | /*P2_CARFREQ*/ |
| 1007 | #define R0900_P2_CARFREQ 0xf23d |
| 1008 | #define F0900_P2_KC_COARSE_EXP 0xf23d00f0 |
| 1009 | #define F0900_P2_BETA_FREQ 0xf23d000f |
| 1010 | |
| 1011 | /*P2_CARHDR*/ |
| 1012 | #define R0900_P2_CARHDR 0xf23e |
| 1013 | #define F0900_P2_K_FREQ_HDR 0xf23e00ff |
| 1014 | |
| 1015 | /*P2_LDT*/ |
| 1016 | #define R0900_P2_LDT 0xf23f |
| 1017 | #define F0900_P2_CARLOCK_THRES 0xf23f01ff |
| 1018 | |
| 1019 | /*P2_LDT2*/ |
| 1020 | #define R0900_P2_LDT2 0xf240 |
| 1021 | #define F0900_P2_CARLOCK_THRES2 0xf24001ff |
| 1022 | |
| 1023 | /*P2_CFRICFG*/ |
| 1024 | #define R0900_P2_CFRICFG 0xf241 |
| 1025 | #define F0900_P2_CFRINIT_UNVALRNG 0xf2410080 |
| 1026 | #define F0900_P2_CFRINIT_LUNVALCPT 0xf2410040 |
| 1027 | #define F0900_P2_CFRINIT_ABORTDBL 0xf2410020 |
| 1028 | #define F0900_P2_CFRINIT_ABORTPRED 0xf2410010 |
| 1029 | #define F0900_P2_CFRINIT_UNVALSKIP 0xf2410008 |
| 1030 | #define F0900_P2_CFRINIT_CSTINC 0xf2410004 |
| 1031 | #define F0900_P2_NEG_CFRSTEP 0xf2410001 |
| 1032 | |
| 1033 | /*P2_CFRUP1*/ |
| 1034 | #define R0900_P2_CFRUP1 0xf242 |
| 1035 | #define F0900_P2_CFR_UP1 0xf24201ff |
| 1036 | |
| 1037 | /*P2_CFRUP0*/ |
| 1038 | #define R0900_P2_CFRUP0 0xf243 |
| 1039 | #define F0900_P2_CFR_UP0 0xf24300ff |
| 1040 | |
| 1041 | /*P2_CFRLOW1*/ |
| 1042 | #define R0900_P2_CFRLOW1 0xf246 |
| 1043 | #define F0900_P2_CFR_LOW1 0xf24601ff |
| 1044 | |
| 1045 | /*P2_CFRLOW0*/ |
| 1046 | #define R0900_P2_CFRLOW0 0xf247 |
| 1047 | #define F0900_P2_CFR_LOW0 0xf24700ff |
| 1048 | |
| 1049 | /*P2_CFRINIT1*/ |
| 1050 | #define R0900_P2_CFRINIT1 0xf248 |
| 1051 | #define F0900_P2_CFR_INIT1 0xf24801ff |
| 1052 | |
| 1053 | /*P2_CFRINIT0*/ |
| 1054 | #define R0900_P2_CFRINIT0 0xf249 |
| 1055 | #define F0900_P2_CFR_INIT0 0xf24900ff |
| 1056 | |
| 1057 | /*P2_CFRINC1*/ |
| 1058 | #define R0900_P2_CFRINC1 0xf24a |
| 1059 | #define F0900_P2_MANUAL_CFRINC 0xf24a0080 |
| 1060 | #define F0900_P2_CFR_INC1 0xf24a017f |
| 1061 | |
| 1062 | /*P2_CFRINC0*/ |
| 1063 | #define R0900_P2_CFRINC0 0xf24b |
| 1064 | #define F0900_P2_CFR_INC0 0xf24b00f0 |
| 1065 | |
| 1066 | /*P2_CFR2*/ |
| 1067 | #define R0900_P2_CFR2 0xf24c |
| 1068 | #define F0900_P2_CAR_FREQ2 0xf24c01ff |
| 1069 | |
| 1070 | /*P2_CFR1*/ |
| 1071 | #define R0900_P2_CFR1 0xf24d |
| 1072 | #define F0900_P2_CAR_FREQ1 0xf24d00ff |
| 1073 | |
| 1074 | /*P2_CFR0*/ |
| 1075 | #define R0900_P2_CFR0 0xf24e |
| 1076 | #define F0900_P2_CAR_FREQ0 0xf24e00ff |
| 1077 | |
| 1078 | /*P2_LDI*/ |
| 1079 | #define R0900_P2_LDI 0xf24f |
| 1080 | #define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff |
| 1081 | |
| 1082 | /*P2_TMGCFG*/ |
| 1083 | #define R0900_P2_TMGCFG 0xf250 |
| 1084 | #define F0900_P2_TMGLOCK_BETA 0xf25000c0 |
| 1085 | #define F0900_P2_NOTMG_GROUPDELAY 0xf2500020 |
| 1086 | #define F0900_P2_DO_TIMING_CORR 0xf2500010 |
| 1087 | #define F0900_P2_MANUAL_SCAN 0xf250000c |
| 1088 | #define F0900_P2_TMG_MINFREQ 0xf2500003 |
| 1089 | |
| 1090 | /*P2_RTC*/ |
| 1091 | #define R0900_P2_RTC 0xf251 |
| 1092 | #define F0900_P2_TMGALPHA_EXP 0xf25100f0 |
| 1093 | #define F0900_P2_TMGBETA_EXP 0xf251000f |
| 1094 | |
| 1095 | /*P2_RTCS2*/ |
| 1096 | #define R0900_P2_RTCS2 0xf252 |
| 1097 | #define F0900_P2_TMGALPHAS2_EXP 0xf25200f0 |
| 1098 | #define F0900_P2_TMGBETAS2_EXP 0xf252000f |
| 1099 | |
| 1100 | /*P2_TMGTHRISE*/ |
| 1101 | #define R0900_P2_TMGTHRISE 0xf253 |
| 1102 | #define F0900_P2_TMGLOCK_THRISE 0xf25300ff |
| 1103 | |
| 1104 | /*P2_TMGTHFALL*/ |
| 1105 | #define R0900_P2_TMGTHFALL 0xf254 |
| 1106 | #define F0900_P2_TMGLOCK_THFALL 0xf25400ff |
| 1107 | |
| 1108 | /*P2_SFRUPRATIO*/ |
| 1109 | #define R0900_P2_SFRUPRATIO 0xf255 |
| 1110 | #define F0900_P2_SFR_UPRATIO 0xf25500ff |
| 1111 | |
| 1112 | /*P2_SFRLOWRATIO*/ |
| 1113 | #define R0900_P2_SFRLOWRATIO 0xf256 |
| 1114 | #define F0900_P2_SFR_LOWRATIO 0xf25600ff |
| 1115 | |
| 1116 | /*P2_KREFTMG*/ |
| 1117 | #define R0900_P2_KREFTMG 0xf258 |
| 1118 | #define F0900_P2_KREF_TMG 0xf25800ff |
| 1119 | |
| 1120 | /*P2_SFRSTEP*/ |
| 1121 | #define R0900_P2_SFRSTEP 0xf259 |
| 1122 | #define F0900_P2_SFR_SCANSTEP 0xf25900f0 |
| 1123 | #define F0900_P2_SFR_CENTERSTEP 0xf259000f |
| 1124 | |
| 1125 | /*P2_TMGCFG2*/ |
| 1126 | #define R0900_P2_TMGCFG2 0xf25a |
| 1127 | #define F0900_P2_DIS_AUTOSAMP 0xf25a0008 |
| 1128 | #define F0900_P2_SCANINIT_QUART 0xf25a0004 |
| 1129 | #define F0900_P2_NOTMG_DVBS1DERAT 0xf25a0002 |
| 1130 | #define F0900_P2_SFRRATIO_FINE 0xf25a0001 |
| 1131 | |
| 1132 | /*P2_SFRINIT1*/ |
| 1133 | #define R0900_P2_SFRINIT1 0xf25e |
| 1134 | #define F0900_P2_SFR_INIT1 0xf25e00ff |
| 1135 | |
| 1136 | /*P2_SFRINIT0*/ |
| 1137 | #define R0900_P2_SFRINIT0 0xf25f |
| 1138 | #define F0900_P2_SFR_INIT0 0xf25f00ff |
| 1139 | |
| 1140 | /*P2_SFRUP1*/ |
| 1141 | #define R0900_P2_SFRUP1 0xf260 |
| 1142 | #define F0900_P2_AUTO_GUP 0xf2600080 |
| 1143 | #define F0900_P2_SYMB_FREQ_UP1 0xf260007f |
| 1144 | |
| 1145 | /*P2_SFRUP0*/ |
| 1146 | #define R0900_P2_SFRUP0 0xf261 |
| 1147 | #define F0900_P2_SYMB_FREQ_UP0 0xf26100ff |
| 1148 | |
| 1149 | /*P2_SFRLOW1*/ |
| 1150 | #define R0900_P2_SFRLOW1 0xf262 |
| 1151 | #define F0900_P2_AUTO_GLOW 0xf2620080 |
| 1152 | #define F0900_P2_SYMB_FREQ_LOW1 0xf262007f |
| 1153 | |
| 1154 | /*P2_SFRLOW0*/ |
| 1155 | #define R0900_P2_SFRLOW0 0xf263 |
| 1156 | #define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff |
| 1157 | |
| 1158 | /*P2_SFR3*/ |
| 1159 | #define R0900_P2_SFR3 0xf264 |
| 1160 | #define F0900_P2_SYMB_FREQ3 0xf26400ff |
| 1161 | |
| 1162 | /*P2_SFR2*/ |
| 1163 | #define R0900_P2_SFR2 0xf265 |
| 1164 | #define F0900_P2_SYMB_FREQ2 0xf26500ff |
| 1165 | |
| 1166 | /*P2_SFR1*/ |
| 1167 | #define R0900_P2_SFR1 0xf266 |
| 1168 | #define F0900_P2_SYMB_FREQ1 0xf26600ff |
| 1169 | |
| 1170 | /*P2_SFR0*/ |
| 1171 | #define R0900_P2_SFR0 0xf267 |
| 1172 | #define F0900_P2_SYMB_FREQ0 0xf26700ff |
| 1173 | |
| 1174 | /*P2_TMGREG2*/ |
| 1175 | #define R0900_P2_TMGREG2 0xf268 |
| 1176 | #define F0900_P2_TMGREG2 0xf26800ff |
| 1177 | |
| 1178 | /*P2_TMGREG1*/ |
| 1179 | #define R0900_P2_TMGREG1 0xf269 |
| 1180 | #define F0900_P2_TMGREG1 0xf26900ff |
| 1181 | |
| 1182 | /*P2_TMGREG0*/ |
| 1183 | #define R0900_P2_TMGREG0 0xf26a |
| 1184 | #define F0900_P2_TMGREG0 0xf26a00ff |
| 1185 | |
| 1186 | /*P2_TMGLOCK1*/ |
| 1187 | #define R0900_P2_TMGLOCK1 0xf26b |
| 1188 | #define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff |
| 1189 | |
| 1190 | /*P2_TMGLOCK0*/ |
| 1191 | #define R0900_P2_TMGLOCK0 0xf26c |
| 1192 | #define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff |
| 1193 | |
| 1194 | /*P2_TMGOBS*/ |
| 1195 | #define R0900_P2_TMGOBS 0xf26d |
| 1196 | #define F0900_P2_ROLLOFF_STATUS 0xf26d00c0 |
| 1197 | #define F0900_P2_SCAN_SIGN 0xf26d0030 |
| 1198 | #define F0900_P2_TMG_SCANNING 0xf26d0008 |
| 1199 | #define F0900_P2_CHCENTERING_MODE 0xf26d0004 |
| 1200 | #define F0900_P2_TMG_SCANFAIL 0xf26d0002 |
| 1201 | |
| 1202 | /*P2_EQUALCFG*/ |
| 1203 | #define R0900_P2_EQUALCFG 0xf26f |
| 1204 | #define F0900_P2_NOTMG_NEGALWAIT 0xf26f0080 |
| 1205 | #define F0900_P2_EQUAL_ON 0xf26f0040 |
| 1206 | #define F0900_P2_SEL_EQUALCOR 0xf26f0038 |
| 1207 | #define F0900_P2_MU_EQUALDFE 0xf26f0007 |
| 1208 | |
| 1209 | /*P2_EQUAI1*/ |
| 1210 | #define R0900_P2_EQUAI1 0xf270 |
| 1211 | #define F0900_P2_EQUA_ACCI1 0xf27001ff |
| 1212 | |
| 1213 | /*P2_EQUAQ1*/ |
| 1214 | #define R0900_P2_EQUAQ1 0xf271 |
| 1215 | #define F0900_P2_EQUA_ACCQ1 0xf27101ff |
| 1216 | |
| 1217 | /*P2_EQUAI2*/ |
| 1218 | #define R0900_P2_EQUAI2 0xf272 |
| 1219 | #define F0900_P2_EQUA_ACCI2 0xf27201ff |
| 1220 | |
| 1221 | /*P2_EQUAQ2*/ |
| 1222 | #define R0900_P2_EQUAQ2 0xf273 |
| 1223 | #define F0900_P2_EQUA_ACCQ2 0xf27301ff |
| 1224 | |
| 1225 | /*P2_EQUAI3*/ |
| 1226 | #define R0900_P2_EQUAI3 0xf274 |
| 1227 | #define F0900_P2_EQUA_ACCI3 0xf27401ff |
| 1228 | |
| 1229 | /*P2_EQUAQ3*/ |
| 1230 | #define R0900_P2_EQUAQ3 0xf275 |
| 1231 | #define F0900_P2_EQUA_ACCQ3 0xf27501ff |
| 1232 | |
| 1233 | /*P2_EQUAI4*/ |
| 1234 | #define R0900_P2_EQUAI4 0xf276 |
| 1235 | #define F0900_P2_EQUA_ACCI4 0xf27601ff |
| 1236 | |
| 1237 | /*P2_EQUAQ4*/ |
| 1238 | #define R0900_P2_EQUAQ4 0xf277 |
| 1239 | #define F0900_P2_EQUA_ACCQ4 0xf27701ff |
| 1240 | |
| 1241 | /*P2_EQUAI5*/ |
| 1242 | #define R0900_P2_EQUAI5 0xf278 |
| 1243 | #define F0900_P2_EQUA_ACCI5 0xf27801ff |
| 1244 | |
| 1245 | /*P2_EQUAQ5*/ |
| 1246 | #define R0900_P2_EQUAQ5 0xf279 |
| 1247 | #define F0900_P2_EQUA_ACCQ5 0xf27901ff |
| 1248 | |
| 1249 | /*P2_EQUAI6*/ |
| 1250 | #define R0900_P2_EQUAI6 0xf27a |
| 1251 | #define F0900_P2_EQUA_ACCI6 0xf27a01ff |
| 1252 | |
| 1253 | /*P2_EQUAQ6*/ |
| 1254 | #define R0900_P2_EQUAQ6 0xf27b |
| 1255 | #define F0900_P2_EQUA_ACCQ6 0xf27b01ff |
| 1256 | |
| 1257 | /*P2_EQUAI7*/ |
| 1258 | #define R0900_P2_EQUAI7 0xf27c |
| 1259 | #define F0900_P2_EQUA_ACCI7 0xf27c01ff |
| 1260 | |
| 1261 | /*P2_EQUAQ7*/ |
| 1262 | #define R0900_P2_EQUAQ7 0xf27d |
| 1263 | #define F0900_P2_EQUA_ACCQ7 0xf27d01ff |
| 1264 | |
| 1265 | /*P2_EQUAI8*/ |
| 1266 | #define R0900_P2_EQUAI8 0xf27e |
| 1267 | #define F0900_P2_EQUA_ACCI8 0xf27e01ff |
| 1268 | |
| 1269 | /*P2_EQUAQ8*/ |
| 1270 | #define R0900_P2_EQUAQ8 0xf27f |
| 1271 | #define F0900_P2_EQUA_ACCQ8 0xf27f01ff |
| 1272 | |
| 1273 | /*P2_NNOSDATAT1*/ |
| 1274 | #define R0900_P2_NNOSDATAT1 0xf280 |
| 1275 | #define F0900_P2_NOSDATAT_NORMED1 0xf28000ff |
| 1276 | |
| 1277 | /*P2_NNOSDATAT0*/ |
| 1278 | #define R0900_P2_NNOSDATAT0 0xf281 |
| 1279 | #define F0900_P2_NOSDATAT_NORMED0 0xf28100ff |
| 1280 | |
| 1281 | /*P2_NNOSDATA1*/ |
| 1282 | #define R0900_P2_NNOSDATA1 0xf282 |
| 1283 | #define F0900_P2_NOSDATA_NORMED1 0xf28200ff |
| 1284 | |
| 1285 | /*P2_NNOSDATA0*/ |
| 1286 | #define R0900_P2_NNOSDATA0 0xf283 |
| 1287 | #define F0900_P2_NOSDATA_NORMED0 0xf28300ff |
| 1288 | |
| 1289 | /*P2_NNOSPLHT1*/ |
| 1290 | #define R0900_P2_NNOSPLHT1 0xf284 |
| 1291 | #define F0900_P2_NOSPLHT_NORMED1 0xf28400ff |
| 1292 | |
| 1293 | /*P2_NNOSPLHT0*/ |
| 1294 | #define R0900_P2_NNOSPLHT0 0xf285 |
| 1295 | #define F0900_P2_NOSPLHT_NORMED0 0xf28500ff |
| 1296 | |
| 1297 | /*P2_NNOSPLH1*/ |
| 1298 | #define R0900_P2_NNOSPLH1 0xf286 |
| 1299 | #define F0900_P2_NOSPLH_NORMED1 0xf28600ff |
| 1300 | |
| 1301 | /*P2_NNOSPLH0*/ |
| 1302 | #define R0900_P2_NNOSPLH0 0xf287 |
| 1303 | #define F0900_P2_NOSPLH_NORMED0 0xf28700ff |
| 1304 | |
| 1305 | /*P2_NOSDATAT1*/ |
| 1306 | #define R0900_P2_NOSDATAT1 0xf288 |
| 1307 | #define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff |
| 1308 | |
| 1309 | /*P2_NOSDATAT0*/ |
| 1310 | #define R0900_P2_NOSDATAT0 0xf289 |
| 1311 | #define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff |
| 1312 | |
| 1313 | /*P2_NOSDATA1*/ |
| 1314 | #define R0900_P2_NOSDATA1 0xf28a |
| 1315 | #define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff |
| 1316 | |
| 1317 | /*P2_NOSDATA0*/ |
| 1318 | #define R0900_P2_NOSDATA0 0xf28b |
| 1319 | #define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff |
| 1320 | |
| 1321 | /*P2_NOSPLHT1*/ |
| 1322 | #define R0900_P2_NOSPLHT1 0xf28c |
| 1323 | #define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff |
| 1324 | |
| 1325 | /*P2_NOSPLHT0*/ |
| 1326 | #define R0900_P2_NOSPLHT0 0xf28d |
| 1327 | #define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff |
| 1328 | |
| 1329 | /*P2_NOSPLH1*/ |
| 1330 | #define R0900_P2_NOSPLH1 0xf28e |
| 1331 | #define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff |
| 1332 | |
| 1333 | /*P2_NOSPLH0*/ |
| 1334 | #define R0900_P2_NOSPLH0 0xf28f |
| 1335 | #define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff |
| 1336 | |
| 1337 | /*P2_CAR2CFG*/ |
| 1338 | #define R0900_P2_CAR2CFG 0xf290 |
| 1339 | #define F0900_P2_DESCRAMB_OFF 0xf2900080 |
| 1340 | #define F0900_P2_PN4_SELECT 0xf2900040 |
| 1341 | #define F0900_P2_CFR2_STOPDVBS1 0xf2900020 |
| 1342 | #define F0900_P2_STOP_CFR2UPDATE 0xf2900010 |
| 1343 | #define F0900_P2_STOP_NCO2UPDATE 0xf2900008 |
| 1344 | #define F0900_P2_ROTA2ON 0xf2900004 |
| 1345 | #define F0900_P2_PH_DET_ALGO2 0xf2900003 |
| 1346 | |
| 1347 | /*P2_ACLC2*/ |
| 1348 | #define R0900_P2_ACLC2 0xf291 |
| 1349 | #define F0900_P2_CAR2_PUNCT_ADERAT 0xf2910040 |
| 1350 | #define F0900_P2_CAR2_ALPHA_MANT 0xf2910030 |
| 1351 | #define F0900_P2_CAR2_ALPHA_EXP 0xf291000f |
| 1352 | |
| 1353 | /*P2_BCLC2*/ |
| 1354 | #define R0900_P2_BCLC2 0xf292 |
| 1355 | #define F0900_P2_DVBS2_NIP 0xf2920080 |
| 1356 | #define F0900_P2_CAR2_PUNCT_BDERAT 0xf2920040 |
| 1357 | #define F0900_P2_CAR2_BETA_MANT 0xf2920030 |
| 1358 | #define F0900_P2_CAR2_BETA_EXP 0xf292000f |
| 1359 | |
| 1360 | /*P2_CFR22*/ |
| 1361 | #define R0900_P2_CFR22 0xf293 |
| 1362 | #define F0900_P2_CAR2_FREQ2 0xf29301ff |
| 1363 | |
| 1364 | /*P2_CFR21*/ |
| 1365 | #define R0900_P2_CFR21 0xf294 |
| 1366 | #define F0900_P2_CAR2_FREQ1 0xf29400ff |
| 1367 | |
| 1368 | /*P2_CFR20*/ |
| 1369 | #define R0900_P2_CFR20 0xf295 |
| 1370 | #define F0900_P2_CAR2_FREQ0 0xf29500ff |
| 1371 | |
| 1372 | /*P2_ACLC2S2Q*/ |
| 1373 | #define R0900_P2_ACLC2S2Q 0xf297 |
| 1374 | #define F0900_P2_ENAB_SPSKSYMB 0xf2970080 |
| 1375 | #define F0900_P2_CAR2S2_QADERAT 0xf2970040 |
| 1376 | #define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030 |
| 1377 | #define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f |
| 1378 | |
| 1379 | /*P2_ACLC2S28*/ |
| 1380 | #define R0900_P2_ACLC2S28 0xf298 |
| 1381 | #define F0900_P2_OLDI3Q_MODE 0xf2980080 |
| 1382 | #define F0900_P2_CAR2S2_8ADERAT 0xf2980040 |
| 1383 | #define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030 |
| 1384 | #define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f |
| 1385 | |
| 1386 | /*P2_ACLC2S216A*/ |
| 1387 | #define R0900_P2_ACLC2S216A 0xf299 |
| 1388 | #define F0900_P2_CAR2S2_16ADERAT 0xf2990040 |
| 1389 | #define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030 |
| 1390 | #define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f |
| 1391 | |
| 1392 | /*P2_ACLC2S232A*/ |
| 1393 | #define R0900_P2_ACLC2S232A 0xf29a |
| 1394 | #define F0900_P2_CAR2S2_32ADERAT 0xf29a0040 |
| 1395 | #define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030 |
| 1396 | #define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f |
| 1397 | |
| 1398 | /*P2_BCLC2S2Q*/ |
| 1399 | #define R0900_P2_BCLC2S2Q 0xf29c |
| 1400 | #define F0900_P2_DVBS2S2Q_NIP 0xf29c0080 |
| 1401 | #define F0900_P2_CAR2S2_QBDERAT 0xf29c0040 |
| 1402 | #define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030 |
| 1403 | #define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f |
| 1404 | |
| 1405 | /*P2_BCLC2S28*/ |
| 1406 | #define R0900_P2_BCLC2S28 0xf29d |
| 1407 | #define F0900_P2_DVBS2S28_NIP 0xf29d0080 |
| 1408 | #define F0900_P2_CAR2S2_8BDERAT 0xf29d0040 |
| 1409 | #define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030 |
| 1410 | #define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f |
| 1411 | |
| 1412 | /*P2_BCLC2S216A*/ |
| 1413 | #define R0900_P2_BCLC2S216A 0xf29e |
| 1414 | #define F0900_P2_DVBS2S216A_NIP 0xf29e0080 |
| 1415 | #define F0900_P2_CAR2S2_16BDERAT 0xf29e0040 |
| 1416 | #define F0900_P2_CAR2S2_16A_BETA_M 0xf29e0030 |
| 1417 | #define F0900_P2_CAR2S2_16A_BETA_E 0xf29e000f |
| 1418 | |
| 1419 | /*P2_BCLC2S232A*/ |
| 1420 | #define R0900_P2_BCLC2S232A 0xf29f |
| 1421 | #define F0900_P2_DVBS2S232A_NIP 0xf29f0080 |
| 1422 | #define F0900_P2_CAR2S2_32BDERAT 0xf29f0040 |
| 1423 | #define F0900_P2_CAR2S2_32A_BETA_M 0xf29f0030 |
| 1424 | #define F0900_P2_CAR2S2_32A_BETA_E 0xf29f000f |
| 1425 | |
| 1426 | /*P2_PLROOT2*/ |
| 1427 | #define R0900_P2_PLROOT2 0xf2ac |
| 1428 | #define F0900_P2_SHORTFR_DISABLE 0xf2ac0080 |
| 1429 | #define F0900_P2_LONGFR_DISABLE 0xf2ac0040 |
| 1430 | #define F0900_P2_DUMMYPL_DISABLE 0xf2ac0020 |
| 1431 | #define F0900_P2_SHORTFR_AVOID 0xf2ac0010 |
| 1432 | #define F0900_P2_PLSCRAMB_MODE 0xf2ac000c |
| 1433 | #define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003 |
| 1434 | |
| 1435 | /*P2_PLROOT1*/ |
| 1436 | #define R0900_P2_PLROOT1 0xf2ad |
| 1437 | #define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff |
| 1438 | |
| 1439 | /*P2_PLROOT0*/ |
| 1440 | #define R0900_P2_PLROOT0 0xf2ae |
| 1441 | #define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff |
| 1442 | |
| 1443 | /*P2_MODCODLST0*/ |
| 1444 | #define R0900_P2_MODCODLST0 0xf2b0 |
| 1445 | #define F0900_P2_EN_TOKEN31 0xf2b00080 |
| 1446 | #define F0900_P2_SYNCTAG_SELECT 0xf2b00040 |
| 1447 | #define F0900_P2_MODCODRQ_MODE 0xf2b00030 |
| 1448 | |
| 1449 | /*P2_MODCODLST1*/ |
| 1450 | #define R0900_P2_MODCODLST1 0xf2b1 |
| 1451 | #define F0900_P2_DIS_MODCOD29 0xf2b100f0 |
| 1452 | #define F0900_P2_DIS_32PSK_9_10 0xf2b1000f |
| 1453 | |
| 1454 | /*P2_MODCODLST2*/ |
| 1455 | #define R0900_P2_MODCODLST2 0xf2b2 |
| 1456 | #define F0900_P2_DIS_32PSK_8_9 0xf2b200f0 |
| 1457 | #define F0900_P2_DIS_32PSK_5_6 0xf2b2000f |
| 1458 | |
| 1459 | /*P2_MODCODLST3*/ |
| 1460 | #define R0900_P2_MODCODLST3 0xf2b3 |
| 1461 | #define F0900_P2_DIS_32PSK_4_5 0xf2b300f0 |
| 1462 | #define F0900_P2_DIS_32PSK_3_4 0xf2b3000f |
| 1463 | |
| 1464 | /*P2_MODCODLST4*/ |
| 1465 | #define R0900_P2_MODCODLST4 0xf2b4 |
| 1466 | #define F0900_P2_DIS_16PSK_9_10 0xf2b400f0 |
| 1467 | #define F0900_P2_DIS_16PSK_8_9 0xf2b4000f |
| 1468 | |
| 1469 | /*P2_MODCODLST5*/ |
| 1470 | #define R0900_P2_MODCODLST5 0xf2b5 |
| 1471 | #define F0900_P2_DIS_16PSK_5_6 0xf2b500f0 |
| 1472 | #define F0900_P2_DIS_16PSK_4_5 0xf2b5000f |
| 1473 | |
| 1474 | /*P2_MODCODLST6*/ |
| 1475 | #define R0900_P2_MODCODLST6 0xf2b6 |
| 1476 | #define F0900_P2_DIS_16PSK_3_4 0xf2b600f0 |
| 1477 | #define F0900_P2_DIS_16PSK_2_3 0xf2b6000f |
| 1478 | |
| 1479 | /*P2_MODCODLST7*/ |
| 1480 | #define R0900_P2_MODCODLST7 0xf2b7 |
| 1481 | #define F0900_P2_DIS_8P_9_10 0xf2b700f0 |
| 1482 | #define F0900_P2_DIS_8P_8_9 0xf2b7000f |
| 1483 | |
| 1484 | /*P2_MODCODLST8*/ |
| 1485 | #define R0900_P2_MODCODLST8 0xf2b8 |
| 1486 | #define F0900_P2_DIS_8P_5_6 0xf2b800f0 |
| 1487 | #define F0900_P2_DIS_8P_3_4 0xf2b8000f |
| 1488 | |
| 1489 | /*P2_MODCODLST9*/ |
| 1490 | #define R0900_P2_MODCODLST9 0xf2b9 |
| 1491 | #define F0900_P2_DIS_8P_2_3 0xf2b900f0 |
| 1492 | #define F0900_P2_DIS_8P_3_5 0xf2b9000f |
| 1493 | |
| 1494 | /*P2_MODCODLSTA*/ |
| 1495 | #define R0900_P2_MODCODLSTA 0xf2ba |
| 1496 | #define F0900_P2_DIS_QP_9_10 0xf2ba00f0 |
| 1497 | #define F0900_P2_DIS_QP_8_9 0xf2ba000f |
| 1498 | |
| 1499 | /*P2_MODCODLSTB*/ |
| 1500 | #define R0900_P2_MODCODLSTB 0xf2bb |
| 1501 | #define F0900_P2_DIS_QP_5_6 0xf2bb00f0 |
| 1502 | #define F0900_P2_DIS_QP_4_5 0xf2bb000f |
| 1503 | |
| 1504 | /*P2_MODCODLSTC*/ |
| 1505 | #define R0900_P2_MODCODLSTC 0xf2bc |
| 1506 | #define F0900_P2_DIS_QP_3_4 0xf2bc00f0 |
| 1507 | #define F0900_P2_DIS_QP_2_3 0xf2bc000f |
| 1508 | |
| 1509 | /*P2_MODCODLSTD*/ |
| 1510 | #define R0900_P2_MODCODLSTD 0xf2bd |
| 1511 | #define F0900_P2_DIS_QP_3_5 0xf2bd00f0 |
| 1512 | #define F0900_P2_DIS_QP_1_2 0xf2bd000f |
| 1513 | |
| 1514 | /*P2_MODCODLSTE*/ |
| 1515 | #define R0900_P2_MODCODLSTE 0xf2be |
| 1516 | #define F0900_P2_DIS_QP_2_5 0xf2be00f0 |
| 1517 | #define F0900_P2_DIS_QP_1_3 0xf2be000f |
| 1518 | |
| 1519 | /*P2_MODCODLSTF*/ |
| 1520 | #define R0900_P2_MODCODLSTF 0xf2bf |
| 1521 | #define F0900_P2_DIS_QP_1_4 0xf2bf00f0 |
| 1522 | #define F0900_P2_DDEMOD_SET 0xf2bf0002 |
| 1523 | #define F0900_P2_DDEMOD_MASK 0xf2bf0001 |
| 1524 | |
| 1525 | /*P2_DMDRESCFG*/ |
| 1526 | #define R0900_P2_DMDRESCFG 0xf2c6 |
| 1527 | #define F0900_P2_DMDRES_RESET 0xf2c60080 |
| 1528 | #define F0900_P2_DMDRES_NOISESQR 0xf2c60010 |
| 1529 | #define F0900_P2_DMDRES_STRALL 0xf2c60008 |
| 1530 | #define F0900_P2_DMDRES_NEWONLY 0xf2c60004 |
| 1531 | #define F0900_P2_DMDRES_NOSTORE 0xf2c60002 |
| 1532 | #define F0900_P2_DMDRES_AGC2MEM 0xf2c60001 |
| 1533 | |
| 1534 | /*P2_DMDRESADR*/ |
| 1535 | #define R0900_P2_DMDRESADR 0xf2c7 |
| 1536 | #define F0900_P2_SUSP_PREDCANAL 0xf2c70080 |
| 1537 | #define F0900_P2_DMDRES_VALIDCFR 0xf2c70040 |
| 1538 | #define F0900_P2_DMDRES_MEMFULL 0xf2c70030 |
| 1539 | #define F0900_P2_DMDRES_RESNBR 0xf2c7000f |
| 1540 | |
| 1541 | /*P2_DMDRESDATA7*/ |
| 1542 | #define R0900_P2_DMDRESDATA7 0xf2c8 |
| 1543 | #define F0900_P2_DMDRES_DATA7 0xf2c800ff |
| 1544 | |
| 1545 | /*P2_DMDRESDATA6*/ |
| 1546 | #define R0900_P2_DMDRESDATA6 0xf2c9 |
| 1547 | #define F0900_P2_DMDRES_DATA6 0xf2c900ff |
| 1548 | |
| 1549 | /*P2_DMDRESDATA5*/ |
| 1550 | #define R0900_P2_DMDRESDATA5 0xf2ca |
| 1551 | #define F0900_P2_DMDRES_DATA5 0xf2ca00ff |
| 1552 | |
| 1553 | /*P2_DMDRESDATA4*/ |
| 1554 | #define R0900_P2_DMDRESDATA4 0xf2cb |
| 1555 | #define F0900_P2_DMDRES_DATA4 0xf2cb00ff |
| 1556 | |
| 1557 | /*P2_DMDRESDATA3*/ |
| 1558 | #define R0900_P2_DMDRESDATA3 0xf2cc |
| 1559 | #define F0900_P2_DMDRES_DATA3 0xf2cc00ff |
| 1560 | |
| 1561 | /*P2_DMDRESDATA2*/ |
| 1562 | #define R0900_P2_DMDRESDATA2 0xf2cd |
| 1563 | #define F0900_P2_DMDRES_DATA2 0xf2cd00ff |
| 1564 | |
| 1565 | /*P2_DMDRESDATA1*/ |
| 1566 | #define R0900_P2_DMDRESDATA1 0xf2ce |
| 1567 | #define F0900_P2_DMDRES_DATA1 0xf2ce00ff |
| 1568 | |
| 1569 | /*P2_DMDRESDATA0*/ |
| 1570 | #define R0900_P2_DMDRESDATA0 0xf2cf |
| 1571 | #define F0900_P2_DMDRES_DATA0 0xf2cf00ff |
| 1572 | |
| 1573 | /*P2_FFEI1*/ |
| 1574 | #define R0900_P2_FFEI1 0xf2d0 |
| 1575 | #define F0900_P2_FFE_ACCI1 0xf2d001ff |
| 1576 | |
| 1577 | /*P2_FFEQ1*/ |
| 1578 | #define R0900_P2_FFEQ1 0xf2d1 |
| 1579 | #define F0900_P2_FFE_ACCQ1 0xf2d101ff |
| 1580 | |
| 1581 | /*P2_FFEI2*/ |
| 1582 | #define R0900_P2_FFEI2 0xf2d2 |
| 1583 | #define F0900_P2_FFE_ACCI2 0xf2d201ff |
| 1584 | |
| 1585 | /*P2_FFEQ2*/ |
| 1586 | #define R0900_P2_FFEQ2 0xf2d3 |
| 1587 | #define F0900_P2_FFE_ACCQ2 0xf2d301ff |
| 1588 | |
| 1589 | /*P2_FFEI3*/ |
| 1590 | #define R0900_P2_FFEI3 0xf2d4 |
| 1591 | #define F0900_P2_FFE_ACCI3 0xf2d401ff |
| 1592 | |
| 1593 | /*P2_FFEQ3*/ |
| 1594 | #define R0900_P2_FFEQ3 0xf2d5 |
| 1595 | #define F0900_P2_FFE_ACCQ3 0xf2d501ff |
| 1596 | |
| 1597 | /*P2_FFEI4*/ |
| 1598 | #define R0900_P2_FFEI4 0xf2d6 |
| 1599 | #define F0900_P2_FFE_ACCI4 0xf2d601ff |
| 1600 | |
| 1601 | /*P2_FFEQ4*/ |
| 1602 | #define R0900_P2_FFEQ4 0xf2d7 |
| 1603 | #define F0900_P2_FFE_ACCQ4 0xf2d701ff |
| 1604 | |
| 1605 | /*P2_FFECFG*/ |
| 1606 | #define R0900_P2_FFECFG 0xf2d8 |
| 1607 | #define F0900_P2_EQUALFFE_ON 0xf2d80040 |
| 1608 | #define F0900_P2_EQUAL_USEDSYMB 0xf2d80030 |
| 1609 | #define F0900_P2_MU_EQUALFFE 0xf2d80007 |
| 1610 | |
| 1611 | /*P2_TNRCFG*/ |
| 1612 | #define R0900_P2_TNRCFG 0xf2e0 |
| 1613 | #define F0900_P2_TUN_ACKFAIL 0xf2e00080 |
| 1614 | #define F0900_P2_TUN_TYPE 0xf2e00070 |
| 1615 | #define F0900_P2_TUN_SECSTOP 0xf2e00008 |
| 1616 | #define F0900_P2_TUN_VCOSRCH 0xf2e00004 |
| 1617 | #define F0900_P2_TUN_MADDRESS 0xf2e00003 |
| 1618 | |
| 1619 | /*P2_TNRCFG2*/ |
| 1620 | #define R0900_P2_TNRCFG2 0xf2e1 |
| 1621 | #define F0900_P2_TUN_IQSWAP 0xf2e10080 |
| 1622 | #define F0900_P2_STB6110_STEP2MHZ 0xf2e10040 |
| 1623 | #define F0900_P2_STB6120_DBLI2C 0xf2e10020 |
| 1624 | #define F0900_P2_DIS_FCCK 0xf2e10010 |
| 1625 | #define F0900_P2_DIS_LPEN 0xf2e10008 |
| 1626 | #define F0900_P2_DIS_BWCALC 0xf2e10004 |
| 1627 | #define F0900_P2_SHORT_WAITSTATES 0xf2e10002 |
| 1628 | #define F0900_P2_DIS_2BWAGC1 0xf2e10001 |
| 1629 | |
| 1630 | /*P2_TNRXTAL*/ |
| 1631 | #define R0900_P2_TNRXTAL 0xf2e4 |
| 1632 | #define F0900_P2_TUN_MCLKDECIMAL 0xf2e400e0 |
| 1633 | #define F0900_P2_TUN_XTALFREQ 0xf2e4001f |
| 1634 | |
| 1635 | /*P2_TNRSTEPS*/ |
| 1636 | #define R0900_P2_TNRSTEPS 0xf2e7 |
| 1637 | #define F0900_P2_TUNER_BW1P6 0xf2e70080 |
| 1638 | #define F0900_P2_BWINC_OFFSET 0xf2e70070 |
| 1639 | #define F0900_P2_SOFTSTEP_RNG 0xf2e70008 |
| 1640 | #define F0900_P2_TUN_BWOFFSET 0xf2e70107 |
| 1641 | |
| 1642 | /*P2_TNRGAIN*/ |
| 1643 | #define R0900_P2_TNRGAIN 0xf2e8 |
| 1644 | #define F0900_P2_TUN_KDIVEN 0xf2e800c0 |
| 1645 | #define F0900_P2_STB6X00_OCK 0xf2e80030 |
| 1646 | #define F0900_P2_TUN_GAIN 0xf2e8000f |
| 1647 | |
| 1648 | /*P2_TNRRF1*/ |
| 1649 | #define R0900_P2_TNRRF1 0xf2e9 |
| 1650 | #define F0900_P2_TUN_RFFREQ2 0xf2e900ff |
| 1651 | |
| 1652 | /*P2_TNRRF0*/ |
| 1653 | #define R0900_P2_TNRRF0 0xf2ea |
| 1654 | #define F0900_P2_TUN_RFFREQ1 0xf2ea00ff |
| 1655 | |
| 1656 | /*P2_TNRBW*/ |
| 1657 | #define R0900_P2_TNRBW 0xf2eb |
| 1658 | #define F0900_P2_TUN_RFFREQ0 0xf2eb00c0 |
| 1659 | #define F0900_P2_TUN_BW 0xf2eb003f |
| 1660 | |
| 1661 | /*P2_TNRADJ*/ |
| 1662 | #define R0900_P2_TNRADJ 0xf2ec |
| 1663 | #define F0900_P2_STB61X0_RCLK 0xf2ec0080 |
| 1664 | #define F0900_P2_STB61X0_CALTIME 0xf2ec0040 |
| 1665 | #define F0900_P2_STB6X00_DLB 0xf2ec0038 |
| 1666 | #define F0900_P2_STB6000_FCL 0xf2ec0007 |
| 1667 | |
| 1668 | /*P2_TNRCTL2*/ |
| 1669 | #define R0900_P2_TNRCTL2 0xf2ed |
| 1670 | #define F0900_P2_STB61X0_LCP1_RCCKOFF 0xf2ed0080 |
| 1671 | #define F0900_P2_STB61X0_LCP0 0xf2ed0040 |
| 1672 | #define F0900_P2_STB61X0_XTOUT_RFOUTS 0xf2ed0020 |
| 1673 | #define F0900_P2_STB61X0_XTON_MCKDV 0xf2ed0010 |
| 1674 | #define F0900_P2_STB61X0_CALOFF_DCOFF 0xf2ed0008 |
| 1675 | #define F0900_P2_STB6110_LPT 0xf2ed0004 |
| 1676 | #define F0900_P2_STB6110_RX 0xf2ed0002 |
| 1677 | #define F0900_P2_STB6110_SYN 0xf2ed0001 |
| 1678 | |
| 1679 | /*P2_TNRCFG3*/ |
| 1680 | #define R0900_P2_TNRCFG3 0xf2ee |
| 1681 | #define F0900_P2_STB6120_DISCTRL1 0xf2ee0080 |
| 1682 | #define F0900_P2_STB6120_INVORDER 0xf2ee0040 |
| 1683 | #define F0900_P2_STB6120_ENCTRL6 0xf2ee0020 |
| 1684 | #define F0900_P2_TUN_PLLFREQ 0xf2ee001c |
| 1685 | #define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003 |
| 1686 | |
| 1687 | /*P2_TNRLAUNCH*/ |
| 1688 | #define R0900_P2_TNRLAUNCH 0xf2f0 |
| 1689 | |
| 1690 | /*P2_TNRLD*/ |
| 1691 | #define R0900_P2_TNRLD 0xf2f0 |
| 1692 | #define F0900_P2_TUNLD_VCOING 0xf2f00080 |
| 1693 | #define F0900_P2_TUN_REG1FAIL 0xf2f00040 |
| 1694 | #define F0900_P2_TUN_REG2FAIL 0xf2f00020 |
| 1695 | #define F0900_P2_TUN_REG3FAIL 0xf2f00010 |
| 1696 | #define F0900_P2_TUN_REG4FAIL 0xf2f00008 |
| 1697 | #define F0900_P2_TUN_REG5FAIL 0xf2f00004 |
| 1698 | #define F0900_P2_TUN_BWING 0xf2f00002 |
| 1699 | #define F0900_P2_TUN_LOCKED 0xf2f00001 |
| 1700 | |
| 1701 | /*P2_TNROBSL*/ |
| 1702 | #define R0900_P2_TNROBSL 0xf2f6 |
| 1703 | #define F0900_P2_TUN_I2CABORTED 0xf2f60080 |
| 1704 | #define F0900_P2_TUN_LPEN 0xf2f60040 |
| 1705 | #define F0900_P2_TUN_FCCK 0xf2f60020 |
| 1706 | #define F0900_P2_TUN_I2CLOCKED 0xf2f60010 |
| 1707 | #define F0900_P2_TUN_PROGDONE 0xf2f6000c |
| 1708 | #define F0900_P2_TUN_RFRESTE1 0xf2f60003 |
| 1709 | |
| 1710 | /*P2_TNRRESTE*/ |
| 1711 | #define R0900_P2_TNRRESTE 0xf2f7 |
| 1712 | #define F0900_P2_TUN_RFRESTE0 0xf2f700ff |
| 1713 | |
| 1714 | /*P2_SMAPCOEF7*/ |
| 1715 | #define R0900_P2_SMAPCOEF7 0xf300 |
| 1716 | #define F0900_P2_DIS_QSCALE 0xf3000080 |
| 1717 | #define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f |
| 1718 | |
| 1719 | /*P2_SMAPCOEF6*/ |
| 1720 | #define R0900_P2_SMAPCOEF6 0xf301 |
| 1721 | #define F0900_P2_DIS_NEWSCALE 0xf3010008 |
| 1722 | #define F0900_P2_ADJ_8PSKLLR1 0xf3010004 |
| 1723 | #define F0900_P2_OLD_8PSKLLR1 0xf3010002 |
| 1724 | #define F0900_P2_DIS_AB8PSK 0xf3010001 |
| 1725 | |
| 1726 | /*P2_SMAPCOEF5*/ |
| 1727 | #define R0900_P2_SMAPCOEF5 0xf302 |
| 1728 | #define F0900_P2_DIS_8SCALE 0xf3020080 |
| 1729 | #define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f |
| 1730 | |
| 1731 | /*P2_DMDPLHSTAT*/ |
| 1732 | #define R0900_P2_DMDPLHSTAT 0xf320 |
| 1733 | #define F0900_P2_PLH_STATISTIC 0xf32000ff |
| 1734 | |
| 1735 | /*P2_LOCKTIME3*/ |
| 1736 | #define R0900_P2_LOCKTIME3 0xf322 |
| 1737 | #define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff |
| 1738 | |
| 1739 | /*P2_LOCKTIME2*/ |
| 1740 | #define R0900_P2_LOCKTIME2 0xf323 |
| 1741 | #define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff |
| 1742 | |
| 1743 | /*P2_LOCKTIME1*/ |
| 1744 | #define R0900_P2_LOCKTIME1 0xf324 |
| 1745 | #define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff |
| 1746 | |
| 1747 | /*P2_LOCKTIME0*/ |
| 1748 | #define R0900_P2_LOCKTIME0 0xf325 |
| 1749 | #define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff |
| 1750 | |
| 1751 | /*P2_VITSCALE*/ |
| 1752 | #define R0900_P2_VITSCALE 0xf332 |
| 1753 | #define F0900_P2_NVTH_NOSRANGE 0xf3320080 |
| 1754 | #define F0900_P2_VERROR_MAXMODE 0xf3320040 |
| 1755 | #define F0900_P2_KDIV_MODE 0xf3320030 |
| 1756 | #define F0900_P2_NSLOWSN_LOCKED 0xf3320008 |
| 1757 | #define F0900_P2_DELOCK_PRFLOSS 0xf3320004 |
| 1758 | #define F0900_P2_DIS_RSFLOCK 0xf3320002 |
| 1759 | |
| 1760 | /*P2_FECM*/ |
| 1761 | #define R0900_P2_FECM 0xf333 |
| 1762 | #define F0900_P2_DSS_DVB 0xf3330080 |
| 1763 | #define F0900_P2_DEMOD_BYPASS 0xf3330040 |
| 1764 | #define F0900_P2_CMP_SLOWMODE 0xf3330020 |
| 1765 | #define F0900_P2_DSS_SRCH 0xf3330010 |
| 1766 | #define F0900_P2_DIFF_MODEVIT 0xf3330004 |
| 1767 | #define F0900_P2_SYNCVIT 0xf3330002 |
| 1768 | #define F0900_P2_IQINV 0xf3330001 |
| 1769 | |
| 1770 | /*P2_VTH12*/ |
| 1771 | #define R0900_P2_VTH12 0xf334 |
| 1772 | #define F0900_P2_VTH12 0xf33400ff |
| 1773 | |
| 1774 | /*P2_VTH23*/ |
| 1775 | #define R0900_P2_VTH23 0xf335 |
| 1776 | #define F0900_P2_VTH23 0xf33500ff |
| 1777 | |
| 1778 | /*P2_VTH34*/ |
| 1779 | #define R0900_P2_VTH34 0xf336 |
| 1780 | #define F0900_P2_VTH34 0xf33600ff |
| 1781 | |
| 1782 | /*P2_VTH56*/ |
| 1783 | #define R0900_P2_VTH56 0xf337 |
| 1784 | #define F0900_P2_VTH56 0xf33700ff |
| 1785 | |
| 1786 | /*P2_VTH67*/ |
| 1787 | #define R0900_P2_VTH67 0xf338 |
| 1788 | #define F0900_P2_VTH67 0xf33800ff |
| 1789 | |
| 1790 | /*P2_VTH78*/ |
| 1791 | #define R0900_P2_VTH78 0xf339 |
| 1792 | #define F0900_P2_VTH78 0xf33900ff |
| 1793 | |
| 1794 | /*P2_VITCURPUN*/ |
| 1795 | #define R0900_P2_VITCURPUN 0xf33a |
| 1796 | #define F0900_P2_VIT_MAPPING 0xf33a00e0 |
| 1797 | #define F0900_P2_VIT_CURPUN 0xf33a001f |
| 1798 | |
| 1799 | /*P2_VERROR*/ |
| 1800 | #define R0900_P2_VERROR 0xf33b |
| 1801 | #define F0900_P2_REGERR_VIT 0xf33b00ff |
| 1802 | |
| 1803 | /*P2_PRVIT*/ |
| 1804 | #define R0900_P2_PRVIT 0xf33c |
| 1805 | #define F0900_P2_DIS_VTHLOCK 0xf33c0040 |
| 1806 | #define F0900_P2_E7_8VIT 0xf33c0020 |
| 1807 | #define F0900_P2_E6_7VIT 0xf33c0010 |
| 1808 | #define F0900_P2_E5_6VIT 0xf33c0008 |
| 1809 | #define F0900_P2_E3_4VIT 0xf33c0004 |
| 1810 | #define F0900_P2_E2_3VIT 0xf33c0002 |
| 1811 | #define F0900_P2_E1_2VIT 0xf33c0001 |
| 1812 | |
| 1813 | /*P2_VAVSRVIT*/ |
| 1814 | #define R0900_P2_VAVSRVIT 0xf33d |
| 1815 | #define F0900_P2_AMVIT 0xf33d0080 |
| 1816 | #define F0900_P2_FROZENVIT 0xf33d0040 |
| 1817 | #define F0900_P2_SNVIT 0xf33d0030 |
| 1818 | #define F0900_P2_TOVVIT 0xf33d000c |
| 1819 | #define F0900_P2_HYPVIT 0xf33d0003 |
| 1820 | |
| 1821 | /*P2_VSTATUSVIT*/ |
| 1822 | #define R0900_P2_VSTATUSVIT 0xf33e |
| 1823 | #define F0900_P2_VITERBI_ON 0xf33e0080 |
| 1824 | #define F0900_P2_END_LOOPVIT 0xf33e0040 |
| 1825 | #define F0900_P2_VITERBI_DEPRF 0xf33e0020 |
| 1826 | #define F0900_P2_PRFVIT 0xf33e0010 |
| 1827 | #define F0900_P2_LOCKEDVIT 0xf33e0008 |
| 1828 | #define F0900_P2_VITERBI_DELOCK 0xf33e0004 |
| 1829 | #define F0900_P2_VIT_DEMODSEL 0xf33e0002 |
| 1830 | #define F0900_P2_VITERBI_COMPOUT 0xf33e0001 |
| 1831 | |
| 1832 | /*P2_VTHINUSE*/ |
| 1833 | #define R0900_P2_VTHINUSE 0xf33f |
| 1834 | #define F0900_P2_VIT_INUSE 0xf33f00ff |
| 1835 | |
| 1836 | /*P2_KDIV12*/ |
| 1837 | #define R0900_P2_KDIV12 0xf340 |
| 1838 | #define F0900_P2_KDIV12_MANUAL 0xf3400080 |
| 1839 | #define F0900_P2_K_DIVIDER_12 0xf340007f |
| 1840 | |
| 1841 | /*P2_KDIV23*/ |
| 1842 | #define R0900_P2_KDIV23 0xf341 |
| 1843 | #define F0900_P2_KDIV23_MANUAL 0xf3410080 |
| 1844 | #define F0900_P2_K_DIVIDER_23 0xf341007f |
| 1845 | |
| 1846 | /*P2_KDIV34*/ |
| 1847 | #define R0900_P2_KDIV34 0xf342 |
| 1848 | #define F0900_P2_KDIV34_MANUAL 0xf3420080 |
| 1849 | #define F0900_P2_K_DIVIDER_34 0xf342007f |
| 1850 | |
| 1851 | /*P2_KDIV56*/ |
| 1852 | #define R0900_P2_KDIV56 0xf343 |
| 1853 | #define F0900_P2_KDIV56_MANUAL 0xf3430080 |
| 1854 | #define F0900_P2_K_DIVIDER_56 0xf343007f |
| 1855 | |
| 1856 | /*P2_KDIV67*/ |
| 1857 | #define R0900_P2_KDIV67 0xf344 |
| 1858 | #define F0900_P2_KDIV67_MANUAL 0xf3440080 |
| 1859 | #define F0900_P2_K_DIVIDER_67 0xf344007f |
| 1860 | |
| 1861 | /*P2_KDIV78*/ |
| 1862 | #define R0900_P2_KDIV78 0xf345 |
| 1863 | #define F0900_P2_KDIV78_MANUAL 0xf3450080 |
| 1864 | #define F0900_P2_K_DIVIDER_78 0xf345007f |
| 1865 | |
| 1866 | /*P2_PDELCTRL1*/ |
| 1867 | #define R0900_P2_PDELCTRL1 0xf350 |
| 1868 | #define F0900_P2_INV_MISMASK 0xf3500080 |
| 1869 | #define F0900_P2_FORCE_ACCEPTED 0xf3500040 |
| 1870 | #define F0900_P2_FILTER_EN 0xf3500020 |
| 1871 | #define F0900_P2_FORCE_PKTDELINUSE 0xf3500010 |
| 1872 | #define F0900_P2_HYSTEN 0xf3500008 |
| 1873 | #define F0900_P2_HYSTSWRST 0xf3500004 |
| 1874 | #define F0900_P2_EN_MIS00 0xf3500002 |
| 1875 | #define F0900_P2_ALGOSWRST 0xf3500001 |
| 1876 | |
| 1877 | /*P2_PDELCTRL2*/ |
| 1878 | #define R0900_P2_PDELCTRL2 0xf351 |
| 1879 | #define F0900_P2_FORCE_CONTINUOUS 0xf3510080 |
| 1880 | #define F0900_P2_RESET_UPKO_COUNT 0xf3510040 |
| 1881 | #define F0900_P2_USER_PKTDELIN_NB 0xf3510020 |
| 1882 | #define F0900_P2_FORCE_LOCKED 0xf3510010 |
| 1883 | #define F0900_P2_DATA_UNBBSCRAM 0xf3510008 |
| 1884 | #define F0900_P2_FORCE_LONGPKT 0xf3510004 |
| 1885 | #define F0900_P2_FRAME_MODE 0xf3510002 |
| 1886 | |
| 1887 | /*P2_HYSTTHRESH*/ |
| 1888 | #define R0900_P2_HYSTTHRESH 0xf354 |
| 1889 | #define F0900_P2_UNLCK_THRESH 0xf35400f0 |
| 1890 | #define F0900_P2_DELIN_LCK_THRESH 0xf354000f |
| 1891 | |
| 1892 | /*P2_ISIENTRY*/ |
| 1893 | #define R0900_P2_ISIENTRY 0xf35e |
| 1894 | #define F0900_P2_ISI_ENTRY 0xf35e00ff |
| 1895 | |
| 1896 | /*P2_ISIBITENA*/ |
| 1897 | #define R0900_P2_ISIBITENA 0xf35f |
| 1898 | #define F0900_P2_ISI_BIT_EN 0xf35f00ff |
| 1899 | |
| 1900 | /*P2_MATSTR1*/ |
| 1901 | #define R0900_P2_MATSTR1 0xf360 |
| 1902 | #define F0900_P2_MATYPE_CURRENT1 0xf36000ff |
| 1903 | |
| 1904 | /*P2_MATSTR0*/ |
| 1905 | #define R0900_P2_MATSTR0 0xf361 |
| 1906 | #define F0900_P2_MATYPE_CURRENT0 0xf36100ff |
| 1907 | |
| 1908 | /*P2_UPLSTR1*/ |
| 1909 | #define R0900_P2_UPLSTR1 0xf362 |
| 1910 | #define F0900_P2_UPL_CURRENT1 0xf36200ff |
| 1911 | |
| 1912 | /*P2_UPLSTR0*/ |
| 1913 | #define R0900_P2_UPLSTR0 0xf363 |
| 1914 | #define F0900_P2_UPL_CURRENT0 0xf36300ff |
| 1915 | |
| 1916 | /*P2_DFLSTR1*/ |
| 1917 | #define R0900_P2_DFLSTR1 0xf364 |
| 1918 | #define F0900_P2_DFL_CURRENT1 0xf36400ff |
| 1919 | |
| 1920 | /*P2_DFLSTR0*/ |
| 1921 | #define R0900_P2_DFLSTR0 0xf365 |
| 1922 | #define F0900_P2_DFL_CURRENT0 0xf36500ff |
| 1923 | |
| 1924 | /*P2_SYNCSTR*/ |
| 1925 | #define R0900_P2_SYNCSTR 0xf366 |
| 1926 | #define F0900_P2_SYNC_CURRENT 0xf36600ff |
| 1927 | |
| 1928 | /*P2_SYNCDSTR1*/ |
| 1929 | #define R0900_P2_SYNCDSTR1 0xf367 |
| 1930 | #define F0900_P2_SYNCD_CURRENT1 0xf36700ff |
| 1931 | |
| 1932 | /*P2_SYNCDSTR0*/ |
| 1933 | #define R0900_P2_SYNCDSTR0 0xf368 |
| 1934 | #define F0900_P2_SYNCD_CURRENT0 0xf36800ff |
| 1935 | |
| 1936 | /*P2_PDELSTATUS1*/ |
| 1937 | #define R0900_P2_PDELSTATUS1 0xf369 |
| 1938 | #define F0900_P2_PKTDELIN_DELOCK 0xf3690080 |
| 1939 | #define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040 |
| 1940 | #define F0900_P2_CONTINUOUS_STREAM 0xf3690020 |
| 1941 | #define F0900_P2_UNACCEPTED_STREAM 0xf3690010 |
| 1942 | #define F0900_P2_BCH_ERROR_FLAG 0xf3690008 |
| 1943 | #define F0900_P2_BBHCRCKO 0xf3690004 |
| 1944 | #define F0900_P2_PKTDELIN_LOCK 0xf3690002 |
| 1945 | #define F0900_P2_FIRST_LOCK 0xf3690001 |
| 1946 | |
| 1947 | /*P2_PDELSTATUS2*/ |
| 1948 | #define R0900_P2_PDELSTATUS2 0xf36a |
| 1949 | #define F0900_P2_PKTDEL_DEMODSEL 0xf36a0080 |
| 1950 | #define F0900_P2_FRAME_MODCOD 0xf36a007c |
| 1951 | #define F0900_P2_FRAME_TYPE 0xf36a0003 |
| 1952 | |
| 1953 | /*P2_BBFCRCKO1*/ |
| 1954 | #define R0900_P2_BBFCRCKO1 0xf36b |
| 1955 | #define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff |
| 1956 | |
| 1957 | /*P2_BBFCRCKO0*/ |
| 1958 | #define R0900_P2_BBFCRCKO0 0xf36c |
| 1959 | #define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff |
| 1960 | |
| 1961 | /*P2_UPCRCKO1*/ |
| 1962 | #define R0900_P2_UPCRCKO1 0xf36d |
| 1963 | #define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff |
| 1964 | |
| 1965 | /*P2_UPCRCKO0*/ |
| 1966 | #define R0900_P2_UPCRCKO0 0xf36e |
| 1967 | #define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff |
| 1968 | |
| 1969 | /*P2_TSSTATEM*/ |
| 1970 | #define R0900_P2_TSSTATEM 0xf370 |
| 1971 | #define F0900_P2_TSDIL_ON 0xf3700080 |
| 1972 | #define F0900_P2_TSSKIPRS_ON 0xf3700040 |
| 1973 | #define F0900_P2_TSRS_ON 0xf3700020 |
| 1974 | #define F0900_P2_TSDESCRAMB_ON 0xf3700010 |
| 1975 | #define F0900_P2_TSFRAME_MODE 0xf3700008 |
| 1976 | #define F0900_P2_TS_DISABLE 0xf3700004 |
| 1977 | #define F0900_P2_TSACM_MODE 0xf3700002 |
| 1978 | #define F0900_P2_TSOUT_NOSYNC 0xf3700001 |
| 1979 | |
| 1980 | /*P2_TSCFGH*/ |
| 1981 | #define R0900_P2_TSCFGH 0xf372 |
| 1982 | #define F0900_P2_TSFIFO_DVBCI 0xf3720080 |
| 1983 | #define F0900_P2_TSFIFO_SERIAL 0xf3720040 |
| 1984 | #define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020 |
| 1985 | #define F0900_P2_TSFIFO_DUTY50 0xf3720010 |
| 1986 | #define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008 |
| 1987 | #define F0900_P2_TSFIFO_ERRMODE 0xf3720006 |
| 1988 | #define F0900_P2_RST_HWARE 0xf3720001 |
| 1989 | |
| 1990 | /*P2_TSCFGM*/ |
| 1991 | #define R0900_P2_TSCFGM 0xf373 |
| 1992 | #define F0900_P2_TSFIFO_MANSPEED 0xf37300c0 |
| 1993 | #define F0900_P2_TSFIFO_PERMDATA 0xf3730020 |
| 1994 | #define F0900_P2_TSFIFO_NONEWSGNL 0xf3730010 |
| 1995 | #define F0900_P2_TSFIFO_BITSPEED 0xf3730008 |
| 1996 | #define F0900_P2_NPD_SPECDVBS2 0xf3730004 |
| 1997 | #define F0900_P2_TSFIFO_STOPCKDIS 0xf3730002 |
| 1998 | #define F0900_P2_TSFIFO_INVDATA 0xf3730001 |
| 1999 | |
| 2000 | /*P2_TSCFGL*/ |
| 2001 | #define R0900_P2_TSCFGL 0xf374 |
| 2002 | #define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 |
| 2003 | #define F0900_P2_BCHERROR_MODE 0xf3740030 |
| 2004 | #define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008 |
| 2005 | #define F0900_P2_TSFIFO_EMBINDVB 0xf3740004 |
| 2006 | #define F0900_P2_TSFIFO_DPUNACT 0xf3740002 |
| 2007 | #define F0900_P2_TSFIFO_NPDOFF 0xf3740001 |
| 2008 | |
| 2009 | /*P2_TSINSDELH*/ |
| 2010 | #define R0900_P2_TSINSDELH 0xf376 |
| 2011 | #define F0900_P2_TSDEL_SYNCBYTE 0xf3760080 |
| 2012 | #define F0900_P2_TSDEL_XXHEADER 0xf3760040 |
| 2013 | #define F0900_P2_TSDEL_BBHEADER 0xf3760020 |
| 2014 | #define F0900_P2_TSDEL_DATAFIELD 0xf3760010 |
| 2015 | #define F0900_P2_TSINSDEL_ISCR 0xf3760008 |
| 2016 | #define F0900_P2_TSINSDEL_NPD 0xf3760004 |
| 2017 | #define F0900_P2_TSINSDEL_RSPARITY 0xf3760002 |
| 2018 | #define F0900_P2_TSINSDEL_CRC8 0xf3760001 |
| 2019 | |
| 2020 | /*P2_TSSPEED*/ |
| 2021 | #define R0900_P2_TSSPEED 0xf380 |
| 2022 | #define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff |
| 2023 | |
| 2024 | /*P2_TSSTATUS*/ |
| 2025 | #define R0900_P2_TSSTATUS 0xf381 |
| 2026 | #define F0900_P2_TSFIFO_LINEOK 0xf3810080 |
| 2027 | #define F0900_P2_TSFIFO_ERROR 0xf3810040 |
| 2028 | #define F0900_P2_TSFIFO_DATA7 0xf3810020 |
| 2029 | #define F0900_P2_TSFIFO_NOSYNC 0xf3810010 |
| 2030 | #define F0900_P2_ISCR_INITIALIZED 0xf3810008 |
| 2031 | #define F0900_P2_ISCR_UPDATED 0xf3810004 |
| 2032 | #define F0900_P2_SOFFIFO_UNREGUL 0xf3810002 |
| 2033 | #define F0900_P2_DIL_READY 0xf3810001 |
| 2034 | |
| 2035 | /*P2_TSSTATUS2*/ |
| 2036 | #define R0900_P2_TSSTATUS2 0xf382 |
| 2037 | #define F0900_P2_TSFIFO_DEMODSEL 0xf3820080 |
| 2038 | #define F0900_P2_TSFIFOSPEED_STORE 0xf3820040 |
| 2039 | #define F0900_P2_DILXX_RESET 0xf3820020 |
| 2040 | #define F0900_P2_TSSERIAL_IMPOS 0xf3820010 |
| 2041 | #define F0900_P2_TSFIFO_LINENOK 0xf3820008 |
| 2042 | #define F0900_P2_BITSPEED_EVENT 0xf3820004 |
| 2043 | #define F0900_P2_SCRAMBDETECT 0xf3820002 |
| 2044 | #define F0900_P2_ULDTV67_FALSELOCK 0xf3820001 |
| 2045 | |
| 2046 | /*P2_TSBITRATE1*/ |
| 2047 | #define R0900_P2_TSBITRATE1 0xf383 |
| 2048 | #define F0900_P2_TSFIFO_BITRATE1 0xf38300ff |
| 2049 | |
| 2050 | /*P2_TSBITRATE0*/ |
| 2051 | #define R0900_P2_TSBITRATE0 0xf384 |
| 2052 | #define F0900_P2_TSFIFO_BITRATE0 0xf38400ff |
| 2053 | |
| 2054 | /*P2_ERRCTRL1*/ |
| 2055 | #define R0900_P2_ERRCTRL1 0xf398 |
| 2056 | #define F0900_P2_ERR_SOURCE1 0xf39800f0 |
| 2057 | #define F0900_P2_NUM_EVENT1 0xf3980007 |
| 2058 | |
| 2059 | /*P2_ERRCNT12*/ |
| 2060 | #define R0900_P2_ERRCNT12 0xf399 |
| 2061 | #define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080 |
| 2062 | #define F0900_P2_ERR_CNT12 0xf399007f |
| 2063 | |
| 2064 | /*P2_ERRCNT11*/ |
| 2065 | #define R0900_P2_ERRCNT11 0xf39a |
| 2066 | #define F0900_P2_ERR_CNT11 0xf39a00ff |
| 2067 | |
| 2068 | /*P2_ERRCNT10*/ |
| 2069 | #define R0900_P2_ERRCNT10 0xf39b |
| 2070 | #define F0900_P2_ERR_CNT10 0xf39b00ff |
| 2071 | |
| 2072 | /*P2_ERRCTRL2*/ |
| 2073 | #define R0900_P2_ERRCTRL2 0xf39c |
| 2074 | #define F0900_P2_ERR_SOURCE2 0xf39c00f0 |
| 2075 | #define F0900_P2_NUM_EVENT2 0xf39c0007 |
| 2076 | |
| 2077 | /*P2_ERRCNT22*/ |
| 2078 | #define R0900_P2_ERRCNT22 0xf39d |
| 2079 | #define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080 |
| 2080 | #define F0900_P2_ERR_CNT22 0xf39d007f |
| 2081 | |
| 2082 | /*P2_ERRCNT21*/ |
| 2083 | #define R0900_P2_ERRCNT21 0xf39e |
| 2084 | #define F0900_P2_ERR_CNT21 0xf39e00ff |
| 2085 | |
| 2086 | /*P2_ERRCNT20*/ |
| 2087 | #define R0900_P2_ERRCNT20 0xf39f |
| 2088 | #define F0900_P2_ERR_CNT20 0xf39f00ff |
| 2089 | |
| 2090 | /*P2_FECSPY*/ |
| 2091 | #define R0900_P2_FECSPY 0xf3a0 |
| 2092 | #define F0900_P2_SPY_ENABLE 0xf3a00080 |
| 2093 | #define F0900_P2_NO_SYNCBYTE 0xf3a00040 |
| 2094 | #define F0900_P2_SERIAL_MODE 0xf3a00020 |
| 2095 | #define F0900_P2_UNUSUAL_PACKET 0xf3a00010 |
| 2096 | #define F0900_P2_BER_PACKMODE 0xf3a00008 |
| 2097 | #define F0900_P2_BERMETER_LMODE 0xf3a00002 |
| 2098 | #define F0900_P2_BERMETER_RESET 0xf3a00001 |
| 2099 | |
| 2100 | /*P2_FSPYCFG*/ |
| 2101 | #define R0900_P2_FSPYCFG 0xf3a1 |
| 2102 | #define F0900_P2_FECSPY_INPUT 0xf3a100c0 |
| 2103 | #define F0900_P2_RST_ON_ERROR 0xf3a10020 |
| 2104 | #define F0900_P2_ONE_SHOT 0xf3a10010 |
| 2105 | #define F0900_P2_I2C_MODE 0xf3a1000c |
| 2106 | #define F0900_P2_SPY_HYSTERESIS 0xf3a10003 |
| 2107 | |
| 2108 | /*P2_FSPYDATA*/ |
| 2109 | #define R0900_P2_FSPYDATA 0xf3a2 |
| 2110 | #define F0900_P2_SPY_STUFFING 0xf3a20080 |
| 2111 | #define F0900_P2_NOERROR_PKTJITTER 0xf3a20040 |
| 2112 | #define F0900_P2_SPY_CNULLPKT 0xf3a20020 |
| 2113 | #define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f |
| 2114 | |
| 2115 | /*P2_FSPYOUT*/ |
| 2116 | #define R0900_P2_FSPYOUT 0xf3a3 |
| 2117 | #define F0900_P2_FSPY_DIRECT 0xf3a30080 |
| 2118 | #define F0900_P2_SPY_OUTDATA_BUS 0xf3a30038 |
| 2119 | #define F0900_P2_STUFF_MODE 0xf3a30007 |
| 2120 | |
| 2121 | /*P2_FSTATUS*/ |
| 2122 | #define R0900_P2_FSTATUS 0xf3a4 |
| 2123 | #define F0900_P2_SPY_ENDSIM 0xf3a40080 |
| 2124 | #define F0900_P2_VALID_SIM 0xf3a40040 |
| 2125 | #define F0900_P2_FOUND_SIGNAL 0xf3a40020 |
| 2126 | #define F0900_P2_DSS_SYNCBYTE 0xf3a40010 |
| 2127 | #define F0900_P2_RESULT_STATE 0xf3a4000f |
| 2128 | |
| 2129 | /*P2_FBERCPT4*/ |
| 2130 | #define R0900_P2_FBERCPT4 0xf3a8 |
| 2131 | #define F0900_P2_FBERMETER_CPT4 0xf3a800ff |
| 2132 | |
| 2133 | /*P2_FBERCPT3*/ |
| 2134 | #define R0900_P2_FBERCPT3 0xf3a9 |
| 2135 | #define F0900_P2_FBERMETER_CPT3 0xf3a900ff |
| 2136 | |
| 2137 | /*P2_FBERCPT2*/ |
| 2138 | #define R0900_P2_FBERCPT2 0xf3aa |
| 2139 | #define F0900_P2_FBERMETER_CPT2 0xf3aa00ff |
| 2140 | |
| 2141 | /*P2_FBERCPT1*/ |
| 2142 | #define R0900_P2_FBERCPT1 0xf3ab |
| 2143 | #define F0900_P2_FBERMETER_CPT1 0xf3ab00ff |
| 2144 | |
| 2145 | /*P2_FBERCPT0*/ |
| 2146 | #define R0900_P2_FBERCPT0 0xf3ac |
| 2147 | #define F0900_P2_FBERMETER_CPT0 0xf3ac00ff |
| 2148 | |
| 2149 | /*P2_FBERERR2*/ |
| 2150 | #define R0900_P2_FBERERR2 0xf3ad |
| 2151 | #define F0900_P2_FBERMETER_ERR2 0xf3ad00ff |
| 2152 | |
| 2153 | /*P2_FBERERR1*/ |
| 2154 | #define R0900_P2_FBERERR1 0xf3ae |
| 2155 | #define F0900_P2_FBERMETER_ERR1 0xf3ae00ff |
| 2156 | |
| 2157 | /*P2_FBERERR0*/ |
| 2158 | #define R0900_P2_FBERERR0 0xf3af |
| 2159 | #define F0900_P2_FBERMETER_ERR0 0xf3af00ff |
| 2160 | |
| 2161 | /*P2_FSPYBER*/ |
| 2162 | #define R0900_P2_FSPYBER 0xf3b2 |
| 2163 | #define F0900_P2_FSPYOBS_XORREAD 0xf3b20040 |
| 2164 | #define F0900_P2_FSPYBER_OBSMODE 0xf3b20020 |
| 2165 | #define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010 |
| 2166 | #define F0900_P2_FSPYBER_UNSYNC 0xf3b20008 |
| 2167 | #define F0900_P2_FSPYBER_CTIME 0xf3b20007 |
| 2168 | |
| 2169 | /*P1_IQCONST*/ |
| 2170 | #define R0900_P1_IQCONST 0xf400 |
| 2171 | #define F0900_P1_CONSTEL_SELECT 0xf4000060 |
| 2172 | #define F0900_P1_IQSYMB_SEL 0xf400001f |
| 2173 | |
| 2174 | /*P1_NOSCFG*/ |
| 2175 | #define R0900_P1_NOSCFG 0xf401 |
| 2176 | #define F0900_P1_DUMMYPL_NOSDATA 0xf4010020 |
| 2177 | #define F0900_P1_NOSPLH_BETA 0xf4010018 |
| 2178 | #define F0900_P1_NOSDATA_BETA 0xf4010007 |
| 2179 | |
| 2180 | /*P1_ISYMB*/ |
| 2181 | #define R0900_P1_ISYMB 0xf402 |
| 2182 | #define F0900_P1_I_SYMBOL 0xf40201ff |
| 2183 | |
| 2184 | /*P1_QSYMB*/ |
| 2185 | #define R0900_P1_QSYMB 0xf403 |
| 2186 | #define F0900_P1_Q_SYMBOL 0xf40301ff |
| 2187 | |
| 2188 | /*P1_AGC1CFG*/ |
| 2189 | #define R0900_P1_AGC1CFG 0xf404 |
| 2190 | #define F0900_P1_DC_FROZEN 0xf4040080 |
| 2191 | #define F0900_P1_DC_CORRECT 0xf4040040 |
| 2192 | #define F0900_P1_AMM_FROZEN 0xf4040020 |
| 2193 | #define F0900_P1_AMM_CORRECT 0xf4040010 |
| 2194 | #define F0900_P1_QUAD_FROZEN 0xf4040008 |
| 2195 | #define F0900_P1_QUAD_CORRECT 0xf4040004 |
| 2196 | #define F0900_P1_DCCOMP_SLOW 0xf4040002 |
| 2197 | #define F0900_P1_IQMISM_SLOW 0xf4040001 |
| 2198 | |
| 2199 | /*P1_AGC1CN*/ |
| 2200 | #define R0900_P1_AGC1CN 0xf406 |
| 2201 | #define F0900_P1_AGC1_LOCKED 0xf4060080 |
| 2202 | #define F0900_P1_AGC1_OVERFLOW 0xf4060040 |
| 2203 | #define F0900_P1_AGC1_NOSLOWLK 0xf4060020 |
| 2204 | #define F0900_P1_AGC1_MINPOWER 0xf4060010 |
| 2205 | #define F0900_P1_AGCOUT_FAST 0xf4060008 |
| 2206 | #define F0900_P1_AGCIQ_BETA 0xf4060007 |
| 2207 | |
| 2208 | /*P1_AGC1REF*/ |
| 2209 | #define R0900_P1_AGC1REF 0xf407 |
| 2210 | #define F0900_P1_AGCIQ_REF 0xf40700ff |
| 2211 | |
| 2212 | /*P1_IDCCOMP*/ |
| 2213 | #define R0900_P1_IDCCOMP 0xf408 |
| 2214 | #define F0900_P1_IAVERAGE_ADJ 0xf40801ff |
| 2215 | |
| 2216 | /*P1_QDCCOMP*/ |
| 2217 | #define R0900_P1_QDCCOMP 0xf409 |
| 2218 | #define F0900_P1_QAVERAGE_ADJ 0xf40901ff |
| 2219 | |
| 2220 | /*P1_POWERI*/ |
| 2221 | #define R0900_P1_POWERI 0xf40a |
| 2222 | #define F0900_P1_POWER_I 0xf40a00ff |
| 2223 | |
| 2224 | /*P1_POWERQ*/ |
| 2225 | #define R0900_P1_POWERQ 0xf40b |
| 2226 | #define F0900_P1_POWER_Q 0xf40b00ff |
| 2227 | |
| 2228 | /*P1_AGC1AMM*/ |
| 2229 | #define R0900_P1_AGC1AMM 0xf40c |
| 2230 | #define F0900_P1_AMM_VALUE 0xf40c00ff |
| 2231 | |
| 2232 | /*P1_AGC1QUAD*/ |
| 2233 | #define R0900_P1_AGC1QUAD 0xf40d |
| 2234 | #define F0900_P1_QUAD_VALUE 0xf40d01ff |
| 2235 | |
| 2236 | /*P1_AGCIQIN1*/ |
| 2237 | #define R0900_P1_AGCIQIN1 0xf40e |
| 2238 | #define F0900_P1_AGCIQ_VALUE1 0xf40e00ff |
| 2239 | |
| 2240 | /*P1_AGCIQIN0*/ |
| 2241 | #define R0900_P1_AGCIQIN0 0xf40f |
| 2242 | #define F0900_P1_AGCIQ_VALUE0 0xf40f00ff |
| 2243 | |
| 2244 | /*P1_DEMOD*/ |
| 2245 | #define R0900_P1_DEMOD 0xf410 |
| 2246 | #define F0900_P1_DEMOD_STOP 0xf4100040 |
| 2247 | #define F0900_P1_SPECINV_CONTROL 0xf4100030 |
| 2248 | #define F0900_P1_FORCE_ENASAMP 0xf4100008 |
| 2249 | #define F0900_P1_MANUAL_ROLLOFF 0xf4100004 |
| 2250 | #define F0900_P1_ROLLOFF_CONTROL 0xf4100003 |
| 2251 | |
| 2252 | /*P1_DMDMODCOD*/ |
| 2253 | #define R0900_P1_DMDMODCOD 0xf411 |
| 2254 | #define F0900_P1_MANUAL_MODCOD 0xf4110080 |
| 2255 | #define F0900_P1_DEMOD_MODCOD 0xf411007c |
| 2256 | #define F0900_P1_DEMOD_TYPE 0xf4110003 |
| 2257 | |
| 2258 | /*P1_DSTATUS*/ |
| 2259 | #define R0900_P1_DSTATUS 0xf412 |
| 2260 | #define F0900_P1_CAR_LOCK 0xf4120080 |
| 2261 | #define F0900_P1_TMGLOCK_QUALITY 0xf4120060 |
| 2262 | #define F0900_P1_SDVBS1_ENABLE 0xf4120010 |
| 2263 | #define F0900_P1_LOCK_DEFINITIF 0xf4120008 |
| 2264 | #define F0900_P1_TIMING_IS_LOCKED 0xf4120004 |
| 2265 | #define F0900_P1_COARSE_TMGLOCK 0xf4120002 |
| 2266 | #define F0900_P1_COARSE_CARLOCK 0xf4120001 |
| 2267 | |
| 2268 | /*P1_DSTATUS2*/ |
| 2269 | #define R0900_P1_DSTATUS2 0xf413 |
| 2270 | #define F0900_P1_DEMOD_DELOCK 0xf4130080 |
| 2271 | #define F0900_P1_DEMOD_TIMEOUT 0xf4130040 |
| 2272 | #define F0900_P1_MODCODRQ_SYNCTAG 0xf4130020 |
| 2273 | #define F0900_P1_POLYPH_SATEVENT 0xf4130010 |
| 2274 | #define F0900_P1_AGC1_NOSIGNALACK 0xf4130008 |
| 2275 | #define F0900_P1_AGC2_OVERFLOW 0xf4130004 |
| 2276 | #define F0900_P1_CFR_OVERFLOW 0xf4130002 |
| 2277 | #define F0900_P1_GAMMA_OVERUNDER 0xf4130001 |
| 2278 | |
| 2279 | /*P1_DMDCFGMD*/ |
| 2280 | #define R0900_P1_DMDCFGMD 0xf414 |
| 2281 | #define F0900_P1_DVBS2_ENABLE 0xf4140080 |
| 2282 | #define F0900_P1_DVBS1_ENABLE 0xf4140040 |
| 2283 | #define F0900_P1_CFR_AUTOSCAN 0xf4140020 |
| 2284 | #define F0900_P1_SCAN_ENABLE 0xf4140010 |
| 2285 | #define F0900_P1_TUN_AUTOSCAN 0xf4140008 |
| 2286 | #define F0900_P1_NOFORCE_RELOCK 0xf4140004 |
| 2287 | #define F0900_P1_TUN_RNG 0xf4140003 |
| 2288 | |
| 2289 | /*P1_DMDCFG2*/ |
| 2290 | #define R0900_P1_DMDCFG2 0xf415 |
| 2291 | #define F0900_P1_AGC1_WAITLOCK 0xf4150080 |
| 2292 | #define F0900_P1_S1S2_SEQUENTIAL 0xf4150040 |
| 2293 | #define F0900_P1_OVERFLOW_TIMEOUT 0xf4150020 |
| 2294 | #define F0900_P1_SCANFAIL_TIMEOUT 0xf4150010 |
| 2295 | #define F0900_P1_DMDTOUT_BACK 0xf4150008 |
| 2296 | #define F0900_P1_CARLOCK_S1ENABLE 0xf4150004 |
| 2297 | #define F0900_P1_COARSE_LK3MODE 0xf4150002 |
| 2298 | #define F0900_P1_COARSE_LK2MODE 0xf4150001 |
| 2299 | |
| 2300 | /*P1_DMDISTATE*/ |
| 2301 | #define R0900_P1_DMDISTATE 0xf416 |
| 2302 | #define F0900_P1_I2C_NORESETDMODE 0xf4160080 |
| 2303 | #define F0900_P1_FORCE_ETAPED 0xf4160040 |
| 2304 | #define F0900_P1_SDMDRST_DIRCLK 0xf4160020 |
| 2305 | #define F0900_P1_I2C_DEMOD_MODE 0xf416001f |
| 2306 | |
| 2307 | /*P1_DMDT0M*/ |
| 2308 | #define R0900_P1_DMDT0M 0xf417 |
| 2309 | #define F0900_P1_DMDT0_MIN 0xf41700ff |
| 2310 | |
| 2311 | /*P1_DMDSTATE*/ |
| 2312 | #define R0900_P1_DMDSTATE 0xf41b |
| 2313 | #define F0900_P1_DEMOD_LOCKED 0xf41b0080 |
| 2314 | #define F0900_P1_HEADER_MODE 0xf41b0060 |
| 2315 | #define F0900_P1_DEMOD_MODE 0xf41b001f |
| 2316 | |
| 2317 | /*P1_DMDFLYW*/ |
| 2318 | #define R0900_P1_DMDFLYW 0xf41c |
| 2319 | #define F0900_P1_I2C_IRQVAL 0xf41c00f0 |
| 2320 | #define F0900_P1_FLYWHEEL_CPT 0xf41c000f |
| 2321 | |
| 2322 | /*P1_DSTATUS3*/ |
| 2323 | #define R0900_P1_DSTATUS3 0xf41d |
| 2324 | #define F0900_P1_CFR_ZIGZAG 0xf41d0080 |
| 2325 | #define F0900_P1_DEMOD_CFGMODE 0xf41d0060 |
| 2326 | #define F0900_P1_GAMMA_LOWBAUDRATE 0xf41d0010 |
| 2327 | #define F0900_P1_RELOCK_MODE 0xf41d0008 |
| 2328 | #define F0900_P1_DEMOD_FAIL 0xf41d0004 |
| 2329 | #define F0900_P1_ETAPE1A_DVBXMEM 0xf41d0003 |
| 2330 | |
| 2331 | /*P1_DMDCFG3*/ |
| 2332 | #define R0900_P1_DMDCFG3 0xf41e |
| 2333 | #define F0900_P1_DVBS1_TMGWAIT 0xf41e0080 |
| 2334 | #define F0900_P1_NO_BWCENTERING 0xf41e0040 |
| 2335 | #define F0900_P1_INV_SEQSRCH 0xf41e0020 |
| 2336 | #define F0900_P1_DIS_SFRUPLOW_TRK 0xf41e0010 |
| 2337 | #define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008 |
| 2338 | #define F0900_P1_LOCKTIME_MODE 0xf41e0007 |
| 2339 | |
| 2340 | /*P1_DMDCFG4*/ |
| 2341 | #define R0900_P1_DMDCFG4 0xf41f |
| 2342 | #define F0900_P1_TUNER_NRELAUNCH 0xf41f0008 |
| 2343 | #define F0900_P1_DIS_CLKENABLE 0xf41f0004 |
| 2344 | #define F0900_P1_DIS_HDRDIVLOCK 0xf41f0002 |
| 2345 | #define F0900_P1_NO_TNRWBINIT 0xf41f0001 |
| 2346 | |
| 2347 | /*P1_CORRELMANT*/ |
| 2348 | #define R0900_P1_CORRELMANT 0xf420 |
| 2349 | #define F0900_P1_CORREL_MANT 0xf42000ff |
| 2350 | |
| 2351 | /*P1_CORRELABS*/ |
| 2352 | #define R0900_P1_CORRELABS 0xf421 |
| 2353 | #define F0900_P1_CORREL_ABS 0xf42100ff |
| 2354 | |
| 2355 | /*P1_CORRELEXP*/ |
| 2356 | #define R0900_P1_CORRELEXP 0xf422 |
| 2357 | #define F0900_P1_CORREL_ABSEXP 0xf42200f0 |
| 2358 | #define F0900_P1_CORREL_EXP 0xf422000f |
| 2359 | |
| 2360 | /*P1_PLHMODCOD*/ |
| 2361 | #define R0900_P1_PLHMODCOD 0xf424 |
| 2362 | #define F0900_P1_SPECINV_DEMOD 0xf4240080 |
| 2363 | #define F0900_P1_PLH_MODCOD 0xf424007c |
| 2364 | #define F0900_P1_PLH_TYPE 0xf4240003 |
| 2365 | |
| 2366 | /*P1_AGCK32*/ |
| 2367 | #define R0900_P1_AGCK32 0xf42b |
| 2368 | #define F0900_P1_R3ADJOFF_32APSK 0xf42b0080 |
| 2369 | #define F0900_P1_R2ADJOFF_32APSK 0xf42b0040 |
| 2370 | #define F0900_P1_R1ADJOFF_32APSK 0xf42b0020 |
| 2371 | #define F0900_P1_RADJ_32APSK 0xf42b001f |
| 2372 | |
| 2373 | /*P1_AGC2O*/ |
| 2374 | #define R0900_P1_AGC2O 0xf42c |
| 2375 | #define F0900_P1_AGC2REF_ADJUSTING 0xf42c0080 |
| 2376 | #define F0900_P1_AGC2_COARSEFAST 0xf42c0040 |
| 2377 | #define F0900_P1_AGC2_LKSQRT 0xf42c0020 |
| 2378 | #define F0900_P1_AGC2_LKMODE 0xf42c0010 |
| 2379 | #define F0900_P1_AGC2_LKEQUA 0xf42c0008 |
| 2380 | #define F0900_P1_AGC2_COEF 0xf42c0007 |
| 2381 | |
| 2382 | /*P1_AGC2REF*/ |
| 2383 | #define R0900_P1_AGC2REF 0xf42d |
| 2384 | #define F0900_P1_AGC2_REF 0xf42d00ff |
| 2385 | |
| 2386 | /*P1_AGC1ADJ*/ |
| 2387 | #define R0900_P1_AGC1ADJ 0xf42e |
| 2388 | #define F0900_P1_AGC1ADJ_MANUAL 0xf42e0080 |
| 2389 | #define F0900_P1_AGC1_ADJUSTED 0xf42e017f |
| 2390 | |
| 2391 | /*P1_AGC2I1*/ |
| 2392 | #define R0900_P1_AGC2I1 0xf436 |
| 2393 | #define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff |
| 2394 | |
| 2395 | /*P1_AGC2I0*/ |
| 2396 | #define R0900_P1_AGC2I0 0xf437 |
| 2397 | #define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff |
| 2398 | |
| 2399 | /*P1_CARCFG*/ |
| 2400 | #define R0900_P1_CARCFG 0xf438 |
| 2401 | #define F0900_P1_CFRUPLOW_AUTO 0xf4380080 |
| 2402 | #define F0900_P1_CFRUPLOW_TEST 0xf4380040 |
| 2403 | #define F0900_P1_EN_CAR2CENTER 0xf4380020 |
| 2404 | #define F0900_P1_CARHDR_NODIV8 0xf4380010 |
| 2405 | #define F0900_P1_I2C_ROTA 0xf4380008 |
| 2406 | #define F0900_P1_ROTAON 0xf4380004 |
| 2407 | #define F0900_P1_PH_DET_ALGO 0xf4380003 |
| 2408 | |
| 2409 | /*P1_ACLC*/ |
| 2410 | #define R0900_P1_ACLC 0xf439 |
| 2411 | #define F0900_P1_STOP_S2ALPHA 0xf43900c0 |
| 2412 | #define F0900_P1_CAR_ALPHA_MANT 0xf4390030 |
| 2413 | #define F0900_P1_CAR_ALPHA_EXP 0xf439000f |
| 2414 | |
| 2415 | /*P1_BCLC*/ |
| 2416 | #define R0900_P1_BCLC 0xf43a |
| 2417 | #define F0900_P1_STOP_S2BETA 0xf43a00c0 |
| 2418 | #define F0900_P1_CAR_BETA_MANT 0xf43a0030 |
| 2419 | #define F0900_P1_CAR_BETA_EXP 0xf43a000f |
| 2420 | |
| 2421 | /*P1_CARFREQ*/ |
| 2422 | #define R0900_P1_CARFREQ 0xf43d |
| 2423 | #define F0900_P1_KC_COARSE_EXP 0xf43d00f0 |
| 2424 | #define F0900_P1_BETA_FREQ 0xf43d000f |
| 2425 | |
| 2426 | /*P1_CARHDR*/ |
| 2427 | #define R0900_P1_CARHDR 0xf43e |
| 2428 | #define F0900_P1_K_FREQ_HDR 0xf43e00ff |
| 2429 | |
| 2430 | /*P1_LDT*/ |
| 2431 | #define R0900_P1_LDT 0xf43f |
| 2432 | #define F0900_P1_CARLOCK_THRES 0xf43f01ff |
| 2433 | |
| 2434 | /*P1_LDT2*/ |
| 2435 | #define R0900_P1_LDT2 0xf440 |
| 2436 | #define F0900_P1_CARLOCK_THRES2 0xf44001ff |
| 2437 | |
| 2438 | /*P1_CFRICFG*/ |
| 2439 | #define R0900_P1_CFRICFG 0xf441 |
| 2440 | #define F0900_P1_CFRINIT_UNVALRNG 0xf4410080 |
| 2441 | #define F0900_P1_CFRINIT_LUNVALCPT 0xf4410040 |
| 2442 | #define F0900_P1_CFRINIT_ABORTDBL 0xf4410020 |
| 2443 | #define F0900_P1_CFRINIT_ABORTPRED 0xf4410010 |
| 2444 | #define F0900_P1_CFRINIT_UNVALSKIP 0xf4410008 |
| 2445 | #define F0900_P1_CFRINIT_CSTINC 0xf4410004 |
| 2446 | #define F0900_P1_NEG_CFRSTEP 0xf4410001 |
| 2447 | |
| 2448 | /*P1_CFRUP1*/ |
| 2449 | #define R0900_P1_CFRUP1 0xf442 |
| 2450 | #define F0900_P1_CFR_UP1 0xf44201ff |
| 2451 | |
| 2452 | /*P1_CFRUP0*/ |
| 2453 | #define R0900_P1_CFRUP0 0xf443 |
| 2454 | #define F0900_P1_CFR_UP0 0xf44300ff |
| 2455 | |
| 2456 | /*P1_CFRLOW1*/ |
| 2457 | #define R0900_P1_CFRLOW1 0xf446 |
| 2458 | #define F0900_P1_CFR_LOW1 0xf44601ff |
| 2459 | |
| 2460 | /*P1_CFRLOW0*/ |
| 2461 | #define R0900_P1_CFRLOW0 0xf447 |
| 2462 | #define F0900_P1_CFR_LOW0 0xf44700ff |
| 2463 | |
| 2464 | /*P1_CFRINIT1*/ |
| 2465 | #define R0900_P1_CFRINIT1 0xf448 |
| 2466 | #define F0900_P1_CFR_INIT1 0xf44801ff |
| 2467 | |
| 2468 | /*P1_CFRINIT0*/ |
| 2469 | #define R0900_P1_CFRINIT0 0xf449 |
| 2470 | #define F0900_P1_CFR_INIT0 0xf44900ff |
| 2471 | |
| 2472 | /*P1_CFRINC1*/ |
| 2473 | #define R0900_P1_CFRINC1 0xf44a |
| 2474 | #define F0900_P1_MANUAL_CFRINC 0xf44a0080 |
| 2475 | #define F0900_P1_CFR_INC1 0xf44a017f |
| 2476 | |
| 2477 | /*P1_CFRINC0*/ |
| 2478 | #define R0900_P1_CFRINC0 0xf44b |
| 2479 | #define F0900_P1_CFR_INC0 0xf44b00f0 |
| 2480 | |
| 2481 | /*P1_CFR2*/ |
| 2482 | #define R0900_P1_CFR2 0xf44c |
| 2483 | #define F0900_P1_CAR_FREQ2 0xf44c01ff |
| 2484 | |
| 2485 | /*P1_CFR1*/ |
| 2486 | #define R0900_P1_CFR1 0xf44d |
| 2487 | #define F0900_P1_CAR_FREQ1 0xf44d00ff |
| 2488 | |
| 2489 | /*P1_CFR0*/ |
| 2490 | #define R0900_P1_CFR0 0xf44e |
| 2491 | #define F0900_P1_CAR_FREQ0 0xf44e00ff |
| 2492 | |
| 2493 | /*P1_LDI*/ |
| 2494 | #define R0900_P1_LDI 0xf44f |
| 2495 | #define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff |
| 2496 | |
| 2497 | /*P1_TMGCFG*/ |
| 2498 | #define R0900_P1_TMGCFG 0xf450 |
| 2499 | #define F0900_P1_TMGLOCK_BETA 0xf45000c0 |
| 2500 | #define F0900_P1_NOTMG_GROUPDELAY 0xf4500020 |
| 2501 | #define F0900_P1_DO_TIMING_CORR 0xf4500010 |
| 2502 | #define F0900_P1_MANUAL_SCAN 0xf450000c |
| 2503 | #define F0900_P1_TMG_MINFREQ 0xf4500003 |
| 2504 | |
| 2505 | /*P1_RTC*/ |
| 2506 | #define R0900_P1_RTC 0xf451 |
| 2507 | #define F0900_P1_TMGALPHA_EXP 0xf45100f0 |
| 2508 | #define F0900_P1_TMGBETA_EXP 0xf451000f |
| 2509 | |
| 2510 | /*P1_RTCS2*/ |
| 2511 | #define R0900_P1_RTCS2 0xf452 |
| 2512 | #define F0900_P1_TMGALPHAS2_EXP 0xf45200f0 |
| 2513 | #define F0900_P1_TMGBETAS2_EXP 0xf452000f |
| 2514 | |
| 2515 | /*P1_TMGTHRISE*/ |
| 2516 | #define R0900_P1_TMGTHRISE 0xf453 |
| 2517 | #define F0900_P1_TMGLOCK_THRISE 0xf45300ff |
| 2518 | |
| 2519 | /*P1_TMGTHFALL*/ |
| 2520 | #define R0900_P1_TMGTHFALL 0xf454 |
| 2521 | #define F0900_P1_TMGLOCK_THFALL 0xf45400ff |
| 2522 | |
| 2523 | /*P1_SFRUPRATIO*/ |
| 2524 | #define R0900_P1_SFRUPRATIO 0xf455 |
| 2525 | #define F0900_P1_SFR_UPRATIO 0xf45500ff |
| 2526 | |
| 2527 | /*P1_SFRLOWRATIO*/ |
| 2528 | #define R0900_P1_SFRLOWRATIO 0xf456 |
| 2529 | #define F0900_P1_SFR_LOWRATIO 0xf45600ff |
| 2530 | |
| 2531 | /*P1_KREFTMG*/ |
| 2532 | #define R0900_P1_KREFTMG 0xf458 |
| 2533 | #define F0900_P1_KREF_TMG 0xf45800ff |
| 2534 | |
| 2535 | /*P1_SFRSTEP*/ |
| 2536 | #define R0900_P1_SFRSTEP 0xf459 |
| 2537 | #define F0900_P1_SFR_SCANSTEP 0xf45900f0 |
| 2538 | #define F0900_P1_SFR_CENTERSTEP 0xf459000f |
| 2539 | |
| 2540 | /*P1_TMGCFG2*/ |
| 2541 | #define R0900_P1_TMGCFG2 0xf45a |
| 2542 | #define F0900_P1_DIS_AUTOSAMP 0xf45a0008 |
| 2543 | #define F0900_P1_SCANINIT_QUART 0xf45a0004 |
| 2544 | #define F0900_P1_NOTMG_DVBS1DERAT 0xf45a0002 |
| 2545 | #define F0900_P1_SFRRATIO_FINE 0xf45a0001 |
| 2546 | |
| 2547 | /*P1_SFRINIT1*/ |
| 2548 | #define R0900_P1_SFRINIT1 0xf45e |
| 2549 | #define F0900_P1_SFR_INIT1 0xf45e00ff |
| 2550 | |
| 2551 | /*P1_SFRINIT0*/ |
| 2552 | #define R0900_P1_SFRINIT0 0xf45f |
| 2553 | #define F0900_P1_SFR_INIT0 0xf45f00ff |
| 2554 | |
| 2555 | /*P1_SFRUP1*/ |
| 2556 | #define R0900_P1_SFRUP1 0xf460 |
| 2557 | #define F0900_P1_AUTO_GUP 0xf4600080 |
| 2558 | #define F0900_P1_SYMB_FREQ_UP1 0xf460007f |
| 2559 | |
| 2560 | /*P1_SFRUP0*/ |
| 2561 | #define R0900_P1_SFRUP0 0xf461 |
| 2562 | #define F0900_P1_SYMB_FREQ_UP0 0xf46100ff |
| 2563 | |
| 2564 | /*P1_SFRLOW1*/ |
| 2565 | #define R0900_P1_SFRLOW1 0xf462 |
| 2566 | #define F0900_P1_AUTO_GLOW 0xf4620080 |
| 2567 | #define F0900_P1_SYMB_FREQ_LOW1 0xf462007f |
| 2568 | |
| 2569 | /*P1_SFRLOW0*/ |
| 2570 | #define R0900_P1_SFRLOW0 0xf463 |
| 2571 | #define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff |
| 2572 | |
| 2573 | /*P1_SFR3*/ |
| 2574 | #define R0900_P1_SFR3 0xf464 |
| 2575 | #define F0900_P1_SYMB_FREQ3 0xf46400ff |
| 2576 | |
| 2577 | /*P1_SFR2*/ |
| 2578 | #define R0900_P1_SFR2 0xf465 |
| 2579 | #define F0900_P1_SYMB_FREQ2 0xf46500ff |
| 2580 | |
| 2581 | /*P1_SFR1*/ |
| 2582 | #define R0900_P1_SFR1 0xf466 |
| 2583 | #define F0900_P1_SYMB_FREQ1 0xf46600ff |
| 2584 | |
| 2585 | /*P1_SFR0*/ |
| 2586 | #define R0900_P1_SFR0 0xf467 |
| 2587 | #define F0900_P1_SYMB_FREQ0 0xf46700ff |
| 2588 | |
| 2589 | /*P1_TMGREG2*/ |
| 2590 | #define R0900_P1_TMGREG2 0xf468 |
| 2591 | #define F0900_P1_TMGREG2 0xf46800ff |
| 2592 | |
| 2593 | /*P1_TMGREG1*/ |
| 2594 | #define R0900_P1_TMGREG1 0xf469 |
| 2595 | #define F0900_P1_TMGREG1 0xf46900ff |
| 2596 | |
| 2597 | /*P1_TMGREG0*/ |
| 2598 | #define R0900_P1_TMGREG0 0xf46a |
| 2599 | #define F0900_P1_TMGREG0 0xf46a00ff |
| 2600 | |
| 2601 | /*P1_TMGLOCK1*/ |
| 2602 | #define R0900_P1_TMGLOCK1 0xf46b |
| 2603 | #define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff |
| 2604 | |
| 2605 | /*P1_TMGLOCK0*/ |
| 2606 | #define R0900_P1_TMGLOCK0 0xf46c |
| 2607 | #define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff |
| 2608 | |
| 2609 | /*P1_TMGOBS*/ |
| 2610 | #define R0900_P1_TMGOBS 0xf46d |
| 2611 | #define F0900_P1_ROLLOFF_STATUS 0xf46d00c0 |
| 2612 | #define F0900_P1_SCAN_SIGN 0xf46d0030 |
| 2613 | #define F0900_P1_TMG_SCANNING 0xf46d0008 |
| 2614 | #define F0900_P1_CHCENTERING_MODE 0xf46d0004 |
| 2615 | #define F0900_P1_TMG_SCANFAIL 0xf46d0002 |
| 2616 | |
| 2617 | /*P1_EQUALCFG*/ |
| 2618 | #define R0900_P1_EQUALCFG 0xf46f |
| 2619 | #define F0900_P1_NOTMG_NEGALWAIT 0xf46f0080 |
| 2620 | #define F0900_P1_EQUAL_ON 0xf46f0040 |
| 2621 | #define F0900_P1_SEL_EQUALCOR 0xf46f0038 |
| 2622 | #define F0900_P1_MU_EQUALDFE 0xf46f0007 |
| 2623 | |
| 2624 | /*P1_EQUAI1*/ |
| 2625 | #define R0900_P1_EQUAI1 0xf470 |
| 2626 | #define F0900_P1_EQUA_ACCI1 0xf47001ff |
| 2627 | |
| 2628 | /*P1_EQUAQ1*/ |
| 2629 | #define R0900_P1_EQUAQ1 0xf471 |
| 2630 | #define F0900_P1_EQUA_ACCQ1 0xf47101ff |
| 2631 | |
| 2632 | /*P1_EQUAI2*/ |
| 2633 | #define R0900_P1_EQUAI2 0xf472 |
| 2634 | #define F0900_P1_EQUA_ACCI2 0xf47201ff |
| 2635 | |
| 2636 | /*P1_EQUAQ2*/ |
| 2637 | #define R0900_P1_EQUAQ2 0xf473 |
| 2638 | #define F0900_P1_EQUA_ACCQ2 0xf47301ff |
| 2639 | |
| 2640 | /*P1_EQUAI3*/ |
| 2641 | #define R0900_P1_EQUAI3 0xf474 |
| 2642 | #define F0900_P1_EQUA_ACCI3 0xf47401ff |
| 2643 | |
| 2644 | /*P1_EQUAQ3*/ |
| 2645 | #define R0900_P1_EQUAQ3 0xf475 |
| 2646 | #define F0900_P1_EQUA_ACCQ3 0xf47501ff |
| 2647 | |
| 2648 | /*P1_EQUAI4*/ |
| 2649 | #define R0900_P1_EQUAI4 0xf476 |
| 2650 | #define F0900_P1_EQUA_ACCI4 0xf47601ff |
| 2651 | |
| 2652 | /*P1_EQUAQ4*/ |
| 2653 | #define R0900_P1_EQUAQ4 0xf477 |
| 2654 | #define F0900_P1_EQUA_ACCQ4 0xf47701ff |
| 2655 | |
| 2656 | /*P1_EQUAI5*/ |
| 2657 | #define R0900_P1_EQUAI5 0xf478 |
| 2658 | #define F0900_P1_EQUA_ACCI5 0xf47801ff |
| 2659 | |
| 2660 | /*P1_EQUAQ5*/ |
| 2661 | #define R0900_P1_EQUAQ5 0xf479 |
| 2662 | #define F0900_P1_EQUA_ACCQ5 0xf47901ff |
| 2663 | |
| 2664 | /*P1_EQUAI6*/ |
| 2665 | #define R0900_P1_EQUAI6 0xf47a |
| 2666 | #define F0900_P1_EQUA_ACCI6 0xf47a01ff |
| 2667 | |
| 2668 | /*P1_EQUAQ6*/ |
| 2669 | #define R0900_P1_EQUAQ6 0xf47b |
| 2670 | #define F0900_P1_EQUA_ACCQ6 0xf47b01ff |
| 2671 | |
| 2672 | /*P1_EQUAI7*/ |
| 2673 | #define R0900_P1_EQUAI7 0xf47c |
| 2674 | #define F0900_P1_EQUA_ACCI7 0xf47c01ff |
| 2675 | |
| 2676 | /*P1_EQUAQ7*/ |
| 2677 | #define R0900_P1_EQUAQ7 0xf47d |
| 2678 | #define F0900_P1_EQUA_ACCQ7 0xf47d01ff |
| 2679 | |
| 2680 | /*P1_EQUAI8*/ |
| 2681 | #define R0900_P1_EQUAI8 0xf47e |
| 2682 | #define F0900_P1_EQUA_ACCI8 0xf47e01ff |
| 2683 | |
| 2684 | /*P1_EQUAQ8*/ |
| 2685 | #define R0900_P1_EQUAQ8 0xf47f |
| 2686 | #define F0900_P1_EQUA_ACCQ8 0xf47f01ff |
| 2687 | |
| 2688 | /*P1_NNOSDATAT1*/ |
| 2689 | #define R0900_P1_NNOSDATAT1 0xf480 |
| 2690 | #define F0900_P1_NOSDATAT_NORMED1 0xf48000ff |
| 2691 | |
| 2692 | /*P1_NNOSDATAT0*/ |
| 2693 | #define R0900_P1_NNOSDATAT0 0xf481 |
| 2694 | #define F0900_P1_NOSDATAT_NORMED0 0xf48100ff |
| 2695 | |
| 2696 | /*P1_NNOSDATA1*/ |
| 2697 | #define R0900_P1_NNOSDATA1 0xf482 |
| 2698 | #define F0900_P1_NOSDATA_NORMED1 0xf48200ff |
| 2699 | |
| 2700 | /*P1_NNOSDATA0*/ |
| 2701 | #define R0900_P1_NNOSDATA0 0xf483 |
| 2702 | #define F0900_P1_NOSDATA_NORMED0 0xf48300ff |
| 2703 | |
| 2704 | /*P1_NNOSPLHT1*/ |
| 2705 | #define R0900_P1_NNOSPLHT1 0xf484 |
| 2706 | #define F0900_P1_NOSPLHT_NORMED1 0xf48400ff |
| 2707 | |
| 2708 | /*P1_NNOSPLHT0*/ |
| 2709 | #define R0900_P1_NNOSPLHT0 0xf485 |
| 2710 | #define F0900_P1_NOSPLHT_NORMED0 0xf48500ff |
| 2711 | |
| 2712 | /*P1_NNOSPLH1*/ |
| 2713 | #define R0900_P1_NNOSPLH1 0xf486 |
| 2714 | #define F0900_P1_NOSPLH_NORMED1 0xf48600ff |
| 2715 | |
| 2716 | /*P1_NNOSPLH0*/ |
| 2717 | #define R0900_P1_NNOSPLH0 0xf487 |
| 2718 | #define F0900_P1_NOSPLH_NORMED0 0xf48700ff |
| 2719 | |
| 2720 | /*P1_NOSDATAT1*/ |
| 2721 | #define R0900_P1_NOSDATAT1 0xf488 |
| 2722 | #define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff |
| 2723 | |
| 2724 | /*P1_NOSDATAT0*/ |
| 2725 | #define R0900_P1_NOSDATAT0 0xf489 |
| 2726 | #define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff |
| 2727 | |
| 2728 | /*P1_NOSDATA1*/ |
| 2729 | #define R0900_P1_NOSDATA1 0xf48a |
| 2730 | #define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff |
| 2731 | |
| 2732 | /*P1_NOSDATA0*/ |
| 2733 | #define R0900_P1_NOSDATA0 0xf48b |
| 2734 | #define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff |
| 2735 | |
| 2736 | /*P1_NOSPLHT1*/ |
| 2737 | #define R0900_P1_NOSPLHT1 0xf48c |
| 2738 | #define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff |
| 2739 | |
| 2740 | /*P1_NOSPLHT0*/ |
| 2741 | #define R0900_P1_NOSPLHT0 0xf48d |
| 2742 | #define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff |
| 2743 | |
| 2744 | /*P1_NOSPLH1*/ |
| 2745 | #define R0900_P1_NOSPLH1 0xf48e |
| 2746 | #define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff |
| 2747 | |
| 2748 | /*P1_NOSPLH0*/ |
| 2749 | #define R0900_P1_NOSPLH0 0xf48f |
| 2750 | #define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff |
| 2751 | |
| 2752 | /*P1_CAR2CFG*/ |
| 2753 | #define R0900_P1_CAR2CFG 0xf490 |
| 2754 | #define F0900_P1_DESCRAMB_OFF 0xf4900080 |
| 2755 | #define F0900_P1_PN4_SELECT 0xf4900040 |
| 2756 | #define F0900_P1_CFR2_STOPDVBS1 0xf4900020 |
| 2757 | #define F0900_P1_STOP_CFR2UPDATE 0xf4900010 |
| 2758 | #define F0900_P1_STOP_NCO2UPDATE 0xf4900008 |
| 2759 | #define F0900_P1_ROTA2ON 0xf4900004 |
| 2760 | #define F0900_P1_PH_DET_ALGO2 0xf4900003 |
| 2761 | |
| 2762 | /*P1_ACLC2*/ |
| 2763 | #define R0900_P1_ACLC2 0xf491 |
| 2764 | #define F0900_P1_CAR2_PUNCT_ADERAT 0xf4910040 |
| 2765 | #define F0900_P1_CAR2_ALPHA_MANT 0xf4910030 |
| 2766 | #define F0900_P1_CAR2_ALPHA_EXP 0xf491000f |
| 2767 | |
| 2768 | /*P1_BCLC2*/ |
| 2769 | #define R0900_P1_BCLC2 0xf492 |
| 2770 | #define F0900_P1_DVBS2_NIP 0xf4920080 |
| 2771 | #define F0900_P1_CAR2_PUNCT_BDERAT 0xf4920040 |
| 2772 | #define F0900_P1_CAR2_BETA_MANT 0xf4920030 |
| 2773 | #define F0900_P1_CAR2_BETA_EXP 0xf492000f |
| 2774 | |
| 2775 | /*P1_CFR22*/ |
| 2776 | #define R0900_P1_CFR22 0xf493 |
| 2777 | #define F0900_P1_CAR2_FREQ2 0xf49301ff |
| 2778 | |
| 2779 | /*P1_CFR21*/ |
| 2780 | #define R0900_P1_CFR21 0xf494 |
| 2781 | #define F0900_P1_CAR2_FREQ1 0xf49400ff |
| 2782 | |
| 2783 | /*P1_CFR20*/ |
| 2784 | #define R0900_P1_CFR20 0xf495 |
| 2785 | #define F0900_P1_CAR2_FREQ0 0xf49500ff |
| 2786 | |
| 2787 | /*P1_ACLC2S2Q*/ |
| 2788 | #define R0900_P1_ACLC2S2Q 0xf497 |
| 2789 | #define F0900_P1_ENAB_SPSKSYMB 0xf4970080 |
| 2790 | #define F0900_P1_CAR2S2_QADERAT 0xf4970040 |
| 2791 | #define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030 |
| 2792 | #define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f |
| 2793 | |
| 2794 | /*P1_ACLC2S28*/ |
| 2795 | #define R0900_P1_ACLC2S28 0xf498 |
| 2796 | #define F0900_P1_OLDI3Q_MODE 0xf4980080 |
| 2797 | #define F0900_P1_CAR2S2_8ADERAT 0xf4980040 |
| 2798 | #define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030 |
| 2799 | #define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f |
| 2800 | |
| 2801 | /*P1_ACLC2S216A*/ |
| 2802 | #define R0900_P1_ACLC2S216A 0xf499 |
| 2803 | #define F0900_P1_CAR2S2_16ADERAT 0xf4990040 |
| 2804 | #define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030 |
| 2805 | #define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f |
| 2806 | |
| 2807 | /*P1_ACLC2S232A*/ |
| 2808 | #define R0900_P1_ACLC2S232A 0xf49a |
| 2809 | #define F0900_P1_CAR2S2_32ADERAT 0xf49a0040 |
| 2810 | #define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030 |
| 2811 | #define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f |
| 2812 | |
| 2813 | /*P1_BCLC2S2Q*/ |
| 2814 | #define R0900_P1_BCLC2S2Q 0xf49c |
| 2815 | #define F0900_P1_DVBS2S2Q_NIP 0xf49c0080 |
| 2816 | #define F0900_P1_CAR2S2_QBDERAT 0xf49c0040 |
| 2817 | #define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030 |
| 2818 | #define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f |
| 2819 | |
| 2820 | /*P1_BCLC2S28*/ |
| 2821 | #define R0900_P1_BCLC2S28 0xf49d |
| 2822 | #define F0900_P1_DVBS2S28_NIP 0xf49d0080 |
| 2823 | #define F0900_P1_CAR2S2_8BDERAT 0xf49d0040 |
| 2824 | #define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030 |
| 2825 | #define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f |
| 2826 | |
| 2827 | /*P1_BCLC2S216A*/ |
| 2828 | #define R0900_P1_BCLC2S216A 0xf49e |
| 2829 | #define F0900_P1_DVBS2S216A_NIP 0xf49e0080 |
| 2830 | #define F0900_P1_CAR2S2_16BDERAT 0xf49e0040 |
| 2831 | #define F0900_P1_CAR2S2_16A_BETA_M 0xf49e0030 |
| 2832 | #define F0900_P1_CAR2S2_16A_BETA_E 0xf49e000f |
| 2833 | |
| 2834 | /*P1_BCLC2S232A*/ |
| 2835 | #define R0900_P1_BCLC2S232A 0xf49f |
| 2836 | #define F0900_P1_DVBS2S232A_NIP 0xf49f0080 |
| 2837 | #define F0900_P1_CAR2S2_32BDERAT 0xf49f0040 |
| 2838 | #define F0900_P1_CAR2S2_32A_BETA_M 0xf49f0030 |
| 2839 | #define F0900_P1_CAR2S2_32A_BETA_E 0xf49f000f |
| 2840 | |
| 2841 | /*P1_PLROOT2*/ |
| 2842 | #define R0900_P1_PLROOT2 0xf4ac |
| 2843 | #define F0900_P1_SHORTFR_DISABLE 0xf4ac0080 |
| 2844 | #define F0900_P1_LONGFR_DISABLE 0xf4ac0040 |
| 2845 | #define F0900_P1_DUMMYPL_DISABLE 0xf4ac0020 |
| 2846 | #define F0900_P1_SHORTFR_AVOID 0xf4ac0010 |
| 2847 | #define F0900_P1_PLSCRAMB_MODE 0xf4ac000c |
| 2848 | #define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003 |
| 2849 | |
| 2850 | /*P1_PLROOT1*/ |
| 2851 | #define R0900_P1_PLROOT1 0xf4ad |
| 2852 | #define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff |
| 2853 | |
| 2854 | /*P1_PLROOT0*/ |
| 2855 | #define R0900_P1_PLROOT0 0xf4ae |
| 2856 | #define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff |
| 2857 | |
| 2858 | /*P1_MODCODLST0*/ |
| 2859 | #define R0900_P1_MODCODLST0 0xf4b0 |
| 2860 | #define F0900_P1_EN_TOKEN31 0xf4b00080 |
| 2861 | #define F0900_P1_SYNCTAG_SELECT 0xf4b00040 |
| 2862 | #define F0900_P1_MODCODRQ_MODE 0xf4b00030 |
| 2863 | |
| 2864 | /*P1_MODCODLST1*/ |
| 2865 | #define R0900_P1_MODCODLST1 0xf4b1 |
| 2866 | #define F0900_P1_DIS_MODCOD29 0xf4b100f0 |
| 2867 | #define F0900_P1_DIS_32PSK_9_10 0xf4b1000f |
| 2868 | |
| 2869 | /*P1_MODCODLST2*/ |
| 2870 | #define R0900_P1_MODCODLST2 0xf4b2 |
| 2871 | #define F0900_P1_DIS_32PSK_8_9 0xf4b200f0 |
| 2872 | #define F0900_P1_DIS_32PSK_5_6 0xf4b2000f |
| 2873 | |
| 2874 | /*P1_MODCODLST3*/ |
| 2875 | #define R0900_P1_MODCODLST3 0xf4b3 |
| 2876 | #define F0900_P1_DIS_32PSK_4_5 0xf4b300f0 |
| 2877 | #define F0900_P1_DIS_32PSK_3_4 0xf4b3000f |
| 2878 | |
| 2879 | /*P1_MODCODLST4*/ |
| 2880 | #define R0900_P1_MODCODLST4 0xf4b4 |
| 2881 | #define F0900_P1_DIS_16PSK_9_10 0xf4b400f0 |
| 2882 | #define F0900_P1_DIS_16PSK_8_9 0xf4b4000f |
| 2883 | |
| 2884 | /*P1_MODCODLST5*/ |
| 2885 | #define R0900_P1_MODCODLST5 0xf4b5 |
| 2886 | #define F0900_P1_DIS_16PSK_5_6 0xf4b500f0 |
| 2887 | #define F0900_P1_DIS_16PSK_4_5 0xf4b5000f |
| 2888 | |
| 2889 | /*P1_MODCODLST6*/ |
| 2890 | #define R0900_P1_MODCODLST6 0xf4b6 |
| 2891 | #define F0900_P1_DIS_16PSK_3_4 0xf4b600f0 |
| 2892 | #define F0900_P1_DIS_16PSK_2_3 0xf4b6000f |
| 2893 | |
| 2894 | /*P1_MODCODLST7*/ |
| 2895 | #define R0900_P1_MODCODLST7 0xf4b7 |
| 2896 | #define F0900_P1_DIS_8P_9_10 0xf4b700f0 |
| 2897 | #define F0900_P1_DIS_8P_8_9 0xf4b7000f |
| 2898 | |
| 2899 | /*P1_MODCODLST8*/ |
| 2900 | #define R0900_P1_MODCODLST8 0xf4b8 |
| 2901 | #define F0900_P1_DIS_8P_5_6 0xf4b800f0 |
| 2902 | #define F0900_P1_DIS_8P_3_4 0xf4b8000f |
| 2903 | |
| 2904 | /*P1_MODCODLST9*/ |
| 2905 | #define R0900_P1_MODCODLST9 0xf4b9 |
| 2906 | #define F0900_P1_DIS_8P_2_3 0xf4b900f0 |
| 2907 | #define F0900_P1_DIS_8P_3_5 0xf4b9000f |
| 2908 | |
| 2909 | /*P1_MODCODLSTA*/ |
| 2910 | #define R0900_P1_MODCODLSTA 0xf4ba |
| 2911 | #define F0900_P1_DIS_QP_9_10 0xf4ba00f0 |
| 2912 | #define F0900_P1_DIS_QP_8_9 0xf4ba000f |
| 2913 | |
| 2914 | /*P1_MODCODLSTB*/ |
| 2915 | #define R0900_P1_MODCODLSTB 0xf4bb |
| 2916 | #define F0900_P1_DIS_QP_5_6 0xf4bb00f0 |
| 2917 | #define F0900_P1_DIS_QP_4_5 0xf4bb000f |
| 2918 | |
| 2919 | /*P1_MODCODLSTC*/ |
| 2920 | #define R0900_P1_MODCODLSTC 0xf4bc |
| 2921 | #define F0900_P1_DIS_QP_3_4 0xf4bc00f0 |
| 2922 | #define F0900_P1_DIS_QP_2_3 0xf4bc000f |
| 2923 | |
| 2924 | /*P1_MODCODLSTD*/ |
| 2925 | #define R0900_P1_MODCODLSTD 0xf4bd |
| 2926 | #define F0900_P1_DIS_QP_3_5 0xf4bd00f0 |
| 2927 | #define F0900_P1_DIS_QP_1_2 0xf4bd000f |
| 2928 | |
| 2929 | /*P1_MODCODLSTE*/ |
| 2930 | #define R0900_P1_MODCODLSTE 0xf4be |
| 2931 | #define F0900_P1_DIS_QP_2_5 0xf4be00f0 |
| 2932 | #define F0900_P1_DIS_QP_1_3 0xf4be000f |
| 2933 | |
| 2934 | /*P1_MODCODLSTF*/ |
| 2935 | #define R0900_P1_MODCODLSTF 0xf4bf |
| 2936 | #define F0900_P1_DIS_QP_1_4 0xf4bf00f0 |
| 2937 | #define F0900_P1_DDEMOD_SET 0xf4bf0002 |
| 2938 | #define F0900_P1_DDEMOD_MASK 0xf4bf0001 |
| 2939 | |
| 2940 | /*P1_DMDRESCFG*/ |
| 2941 | #define R0900_P1_DMDRESCFG 0xf4c6 |
| 2942 | #define F0900_P1_DMDRES_RESET 0xf4c60080 |
| 2943 | #define F0900_P1_DMDRES_NOISESQR 0xf4c60010 |
| 2944 | #define F0900_P1_DMDRES_STRALL 0xf4c60008 |
| 2945 | #define F0900_P1_DMDRES_NEWONLY 0xf4c60004 |
| 2946 | #define F0900_P1_DMDRES_NOSTORE 0xf4c60002 |
| 2947 | #define F0900_P1_DMDRES_AGC2MEM 0xf4c60001 |
| 2948 | |
| 2949 | /*P1_DMDRESADR*/ |
| 2950 | #define R0900_P1_DMDRESADR 0xf4c7 |
| 2951 | #define F0900_P1_SUSP_PREDCANAL 0xf4c70080 |
| 2952 | #define F0900_P1_DMDRES_VALIDCFR 0xf4c70040 |
| 2953 | #define F0900_P1_DMDRES_MEMFULL 0xf4c70030 |
| 2954 | #define F0900_P1_DMDRES_RESNBR 0xf4c7000f |
| 2955 | |
| 2956 | /*P1_DMDRESDATA7*/ |
| 2957 | #define R0900_P1_DMDRESDATA7 0xf4c8 |
| 2958 | #define F0900_P1_DMDRES_DATA7 0xf4c800ff |
| 2959 | |
| 2960 | /*P1_DMDRESDATA6*/ |
| 2961 | #define R0900_P1_DMDRESDATA6 0xf4c9 |
| 2962 | #define F0900_P1_DMDRES_DATA6 0xf4c900ff |
| 2963 | |
| 2964 | /*P1_DMDRESDATA5*/ |
| 2965 | #define R0900_P1_DMDRESDATA5 0xf4ca |
| 2966 | #define F0900_P1_DMDRES_DATA5 0xf4ca00ff |
| 2967 | |
| 2968 | /*P1_DMDRESDATA4*/ |
| 2969 | #define R0900_P1_DMDRESDATA4 0xf4cb |
| 2970 | #define F0900_P1_DMDRES_DATA4 0xf4cb00ff |
| 2971 | |
| 2972 | /*P1_DMDRESDATA3*/ |
| 2973 | #define R0900_P1_DMDRESDATA3 0xf4cc |
| 2974 | #define F0900_P1_DMDRES_DATA3 0xf4cc00ff |
| 2975 | |
| 2976 | /*P1_DMDRESDATA2*/ |
| 2977 | #define R0900_P1_DMDRESDATA2 0xf4cd |
| 2978 | #define F0900_P1_DMDRES_DATA2 0xf4cd00ff |
| 2979 | |
| 2980 | /*P1_DMDRESDATA1*/ |
| 2981 | #define R0900_P1_DMDRESDATA1 0xf4ce |
| 2982 | #define F0900_P1_DMDRES_DATA1 0xf4ce00ff |
| 2983 | |
| 2984 | /*P1_DMDRESDATA0*/ |
| 2985 | #define R0900_P1_DMDRESDATA0 0xf4cf |
| 2986 | #define F0900_P1_DMDRES_DATA0 0xf4cf00ff |
| 2987 | |
| 2988 | /*P1_FFEI1*/ |
| 2989 | #define R0900_P1_FFEI1 0xf4d0 |
| 2990 | #define F0900_P1_FFE_ACCI1 0xf4d001ff |
| 2991 | |
| 2992 | /*P1_FFEQ1*/ |
| 2993 | #define R0900_P1_FFEQ1 0xf4d1 |
| 2994 | #define F0900_P1_FFE_ACCQ1 0xf4d101ff |
| 2995 | |
| 2996 | /*P1_FFEI2*/ |
| 2997 | #define R0900_P1_FFEI2 0xf4d2 |
| 2998 | #define F0900_P1_FFE_ACCI2 0xf4d201ff |
| 2999 | |
| 3000 | /*P1_FFEQ2*/ |
| 3001 | #define R0900_P1_FFEQ2 0xf4d3 |
| 3002 | #define F0900_P1_FFE_ACCQ2 0xf4d301ff |
| 3003 | |
| 3004 | /*P1_FFEI3*/ |
| 3005 | #define R0900_P1_FFEI3 0xf4d4 |
| 3006 | #define F0900_P1_FFE_ACCI3 0xf4d401ff |
| 3007 | |
| 3008 | /*P1_FFEQ3*/ |
| 3009 | #define R0900_P1_FFEQ3 0xf4d5 |
| 3010 | #define F0900_P1_FFE_ACCQ3 0xf4d501ff |
| 3011 | |
| 3012 | /*P1_FFEI4*/ |
| 3013 | #define R0900_P1_FFEI4 0xf4d6 |
| 3014 | #define F0900_P1_FFE_ACCI4 0xf4d601ff |
| 3015 | |
| 3016 | /*P1_FFEQ4*/ |
| 3017 | #define R0900_P1_FFEQ4 0xf4d7 |
| 3018 | #define F0900_P1_FFE_ACCQ4 0xf4d701ff |
| 3019 | |
| 3020 | /*P1_FFECFG*/ |
| 3021 | #define R0900_P1_FFECFG 0xf4d8 |
| 3022 | #define F0900_P1_EQUALFFE_ON 0xf4d80040 |
| 3023 | #define F0900_P1_EQUAL_USEDSYMB 0xf4d80030 |
| 3024 | #define F0900_P1_MU_EQUALFFE 0xf4d80007 |
| 3025 | |
| 3026 | /*P1_TNRCFG*/ |
| 3027 | #define R0900_P1_TNRCFG 0xf4e0 |
| 3028 | #define F0900_P1_TUN_ACKFAIL 0xf4e00080 |
| 3029 | #define F0900_P1_TUN_TYPE 0xf4e00070 |
| 3030 | #define F0900_P1_TUN_SECSTOP 0xf4e00008 |
| 3031 | #define F0900_P1_TUN_VCOSRCH 0xf4e00004 |
| 3032 | #define F0900_P1_TUN_MADDRESS 0xf4e00003 |
| 3033 | |
| 3034 | /*P1_TNRCFG2*/ |
| 3035 | #define R0900_P1_TNRCFG2 0xf4e1 |
| 3036 | #define F0900_P1_TUN_IQSWAP 0xf4e10080 |
| 3037 | #define F0900_P1_STB6110_STEP2MHZ 0xf4e10040 |
| 3038 | #define F0900_P1_STB6120_DBLI2C 0xf4e10020 |
| 3039 | #define F0900_P1_DIS_FCCK 0xf4e10010 |
| 3040 | #define F0900_P1_DIS_LPEN 0xf4e10008 |
| 3041 | #define F0900_P1_DIS_BWCALC 0xf4e10004 |
| 3042 | #define F0900_P1_SHORT_WAITSTATES 0xf4e10002 |
| 3043 | #define F0900_P1_DIS_2BWAGC1 0xf4e10001 |
| 3044 | |
| 3045 | /*P1_TNRXTAL*/ |
| 3046 | #define R0900_P1_TNRXTAL 0xf4e4 |
| 3047 | #define F0900_P1_TUN_MCLKDECIMAL 0xf4e400e0 |
| 3048 | #define F0900_P1_TUN_XTALFREQ 0xf4e4001f |
| 3049 | |
| 3050 | /*P1_TNRSTEPS*/ |
| 3051 | #define R0900_P1_TNRSTEPS 0xf4e7 |
| 3052 | #define F0900_P1_TUNER_BW1P6 0xf4e70080 |
| 3053 | #define F0900_P1_BWINC_OFFSET 0xf4e70070 |
| 3054 | #define F0900_P1_SOFTSTEP_RNG 0xf4e70008 |
| 3055 | #define F0900_P1_TUN_BWOFFSET 0xf4e70107 |
| 3056 | |
| 3057 | /*P1_TNRGAIN*/ |
| 3058 | #define R0900_P1_TNRGAIN 0xf4e8 |
| 3059 | #define F0900_P1_TUN_KDIVEN 0xf4e800c0 |
| 3060 | #define F0900_P1_STB6X00_OCK 0xf4e80030 |
| 3061 | #define F0900_P1_TUN_GAIN 0xf4e8000f |
| 3062 | |
| 3063 | /*P1_TNRRF1*/ |
| 3064 | #define R0900_P1_TNRRF1 0xf4e9 |
| 3065 | #define F0900_P1_TUN_RFFREQ2 0xf4e900ff |
| 3066 | |
| 3067 | /*P1_TNRRF0*/ |
| 3068 | #define R0900_P1_TNRRF0 0xf4ea |
| 3069 | #define F0900_P1_TUN_RFFREQ1 0xf4ea00ff |
| 3070 | |
| 3071 | /*P1_TNRBW*/ |
| 3072 | #define R0900_P1_TNRBW 0xf4eb |
| 3073 | #define F0900_P1_TUN_RFFREQ0 0xf4eb00c0 |
| 3074 | #define F0900_P1_TUN_BW 0xf4eb003f |
| 3075 | |
| 3076 | /*P1_TNRADJ*/ |
| 3077 | #define R0900_P1_TNRADJ 0xf4ec |
| 3078 | #define F0900_P1_STB61X0_RCLK 0xf4ec0080 |
| 3079 | #define F0900_P1_STB61X0_CALTIME 0xf4ec0040 |
| 3080 | #define F0900_P1_STB6X00_DLB 0xf4ec0038 |
| 3081 | #define F0900_P1_STB6000_FCL 0xf4ec0007 |
| 3082 | |
| 3083 | /*P1_TNRCTL2*/ |
| 3084 | #define R0900_P1_TNRCTL2 0xf4ed |
| 3085 | #define F0900_P1_STB61X0_LCP1_RCCKOFF 0xf4ed0080 |
| 3086 | #define F0900_P1_STB61X0_LCP0 0xf4ed0040 |
| 3087 | #define F0900_P1_STB61X0_XTOUT_RFOUTS 0xf4ed0020 |
| 3088 | #define F0900_P1_STB61X0_XTON_MCKDV 0xf4ed0010 |
| 3089 | #define F0900_P1_STB61X0_CALOFF_DCOFF 0xf4ed0008 |
| 3090 | #define F0900_P1_STB6110_LPT 0xf4ed0004 |
| 3091 | #define F0900_P1_STB6110_RX 0xf4ed0002 |
| 3092 | #define F0900_P1_STB6110_SYN 0xf4ed0001 |
| 3093 | |
| 3094 | /*P1_TNRCFG3*/ |
| 3095 | #define R0900_P1_TNRCFG3 0xf4ee |
| 3096 | #define F0900_P1_STB6120_DISCTRL1 0xf4ee0080 |
| 3097 | #define F0900_P1_STB6120_INVORDER 0xf4ee0040 |
| 3098 | #define F0900_P1_STB6120_ENCTRL6 0xf4ee0020 |
| 3099 | #define F0900_P1_TUN_PLLFREQ 0xf4ee001c |
| 3100 | #define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003 |
| 3101 | |
| 3102 | /*P1_TNRLAUNCH*/ |
| 3103 | #define R0900_P1_TNRLAUNCH 0xf4f0 |
| 3104 | |
| 3105 | /*P1_TNRLD*/ |
| 3106 | #define R0900_P1_TNRLD 0xf4f0 |
| 3107 | #define F0900_P1_TUNLD_VCOING 0xf4f00080 |
| 3108 | #define F0900_P1_TUN_REG1FAIL 0xf4f00040 |
| 3109 | #define F0900_P1_TUN_REG2FAIL 0xf4f00020 |
| 3110 | #define F0900_P1_TUN_REG3FAIL 0xf4f00010 |
| 3111 | #define F0900_P1_TUN_REG4FAIL 0xf4f00008 |
| 3112 | #define F0900_P1_TUN_REG5FAIL 0xf4f00004 |
| 3113 | #define F0900_P1_TUN_BWING 0xf4f00002 |
| 3114 | #define F0900_P1_TUN_LOCKED 0xf4f00001 |
| 3115 | |
| 3116 | /*P1_TNROBSL*/ |
| 3117 | #define R0900_P1_TNROBSL 0xf4f6 |
| 3118 | #define F0900_P1_TUN_I2CABORTED 0xf4f60080 |
| 3119 | #define F0900_P1_TUN_LPEN 0xf4f60040 |
| 3120 | #define F0900_P1_TUN_FCCK 0xf4f60020 |
| 3121 | #define F0900_P1_TUN_I2CLOCKED 0xf4f60010 |
| 3122 | #define F0900_P1_TUN_PROGDONE 0xf4f6000c |
| 3123 | #define F0900_P1_TUN_RFRESTE1 0xf4f60003 |
| 3124 | |
| 3125 | /*P1_TNRRESTE*/ |
| 3126 | #define R0900_P1_TNRRESTE 0xf4f7 |
| 3127 | #define F0900_P1_TUN_RFRESTE0 0xf4f700ff |
| 3128 | |
| 3129 | /*P1_SMAPCOEF7*/ |
| 3130 | #define R0900_P1_SMAPCOEF7 0xf500 |
| 3131 | #define F0900_P1_DIS_QSCALE 0xf5000080 |
| 3132 | #define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f |
| 3133 | |
| 3134 | /*P1_SMAPCOEF6*/ |
| 3135 | #define R0900_P1_SMAPCOEF6 0xf501 |
| 3136 | #define F0900_P1_DIS_NEWSCALE 0xf5010008 |
| 3137 | #define F0900_P1_ADJ_8PSKLLR1 0xf5010004 |
| 3138 | #define F0900_P1_OLD_8PSKLLR1 0xf5010002 |
| 3139 | #define F0900_P1_DIS_AB8PSK 0xf5010001 |
| 3140 | |
| 3141 | /*P1_SMAPCOEF5*/ |
| 3142 | #define R0900_P1_SMAPCOEF5 0xf502 |
| 3143 | #define F0900_P1_DIS_8SCALE 0xf5020080 |
| 3144 | #define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f |
| 3145 | |
| 3146 | /*P1_DMDPLHSTAT*/ |
| 3147 | #define R0900_P1_DMDPLHSTAT 0xf520 |
| 3148 | #define F0900_P1_PLH_STATISTIC 0xf52000ff |
| 3149 | |
| 3150 | /*P1_LOCKTIME3*/ |
| 3151 | #define R0900_P1_LOCKTIME3 0xf522 |
| 3152 | #define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff |
| 3153 | |
| 3154 | /*P1_LOCKTIME2*/ |
| 3155 | #define R0900_P1_LOCKTIME2 0xf523 |
| 3156 | #define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff |
| 3157 | |
| 3158 | /*P1_LOCKTIME1*/ |
| 3159 | #define R0900_P1_LOCKTIME1 0xf524 |
| 3160 | #define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff |
| 3161 | |
| 3162 | /*P1_LOCKTIME0*/ |
| 3163 | #define R0900_P1_LOCKTIME0 0xf525 |
| 3164 | #define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff |
| 3165 | |
| 3166 | /*P1_VITSCALE*/ |
| 3167 | #define R0900_P1_VITSCALE 0xf532 |
| 3168 | #define F0900_P1_NVTH_NOSRANGE 0xf5320080 |
| 3169 | #define F0900_P1_VERROR_MAXMODE 0xf5320040 |
| 3170 | #define F0900_P1_KDIV_MODE 0xf5320030 |
| 3171 | #define F0900_P1_NSLOWSN_LOCKED 0xf5320008 |
| 3172 | #define F0900_P1_DELOCK_PRFLOSS 0xf5320004 |
| 3173 | #define F0900_P1_DIS_RSFLOCK 0xf5320002 |
| 3174 | |
| 3175 | /*P1_FECM*/ |
| 3176 | #define R0900_P1_FECM 0xf533 |
| 3177 | #define F0900_P1_DSS_DVB 0xf5330080 |
| 3178 | #define F0900_P1_DEMOD_BYPASS 0xf5330040 |
| 3179 | #define F0900_P1_CMP_SLOWMODE 0xf5330020 |
| 3180 | #define F0900_P1_DSS_SRCH 0xf5330010 |
| 3181 | #define F0900_P1_DIFF_MODEVIT 0xf5330004 |
| 3182 | #define F0900_P1_SYNCVIT 0xf5330002 |
| 3183 | #define F0900_P1_IQINV 0xf5330001 |
| 3184 | |
| 3185 | /*P1_VTH12*/ |
| 3186 | #define R0900_P1_VTH12 0xf534 |
| 3187 | #define F0900_P1_VTH12 0xf53400ff |
| 3188 | |
| 3189 | /*P1_VTH23*/ |
| 3190 | #define R0900_P1_VTH23 0xf535 |
| 3191 | #define F0900_P1_VTH23 0xf53500ff |
| 3192 | |
| 3193 | /*P1_VTH34*/ |
| 3194 | #define R0900_P1_VTH34 0xf536 |
| 3195 | #define F0900_P1_VTH34 0xf53600ff |
| 3196 | |
| 3197 | /*P1_VTH56*/ |
| 3198 | #define R0900_P1_VTH56 0xf537 |
| 3199 | #define F0900_P1_VTH56 0xf53700ff |
| 3200 | |
| 3201 | /*P1_VTH67*/ |
| 3202 | #define R0900_P1_VTH67 0xf538 |
| 3203 | #define F0900_P1_VTH67 0xf53800ff |
| 3204 | |
| 3205 | /*P1_VTH78*/ |
| 3206 | #define R0900_P1_VTH78 0xf539 |
| 3207 | #define F0900_P1_VTH78 0xf53900ff |
| 3208 | |
| 3209 | /*P1_VITCURPUN*/ |
| 3210 | #define R0900_P1_VITCURPUN 0xf53a |
| 3211 | #define F0900_P1_VIT_MAPPING 0xf53a00e0 |
| 3212 | #define F0900_P1_VIT_CURPUN 0xf53a001f |
| 3213 | |
| 3214 | /*P1_VERROR*/ |
| 3215 | #define R0900_P1_VERROR 0xf53b |
| 3216 | #define F0900_P1_REGERR_VIT 0xf53b00ff |
| 3217 | |
| 3218 | /*P1_PRVIT*/ |
| 3219 | #define R0900_P1_PRVIT 0xf53c |
| 3220 | #define F0900_P1_DIS_VTHLOCK 0xf53c0040 |
| 3221 | #define F0900_P1_E7_8VIT 0xf53c0020 |
| 3222 | #define F0900_P1_E6_7VIT 0xf53c0010 |
| 3223 | #define F0900_P1_E5_6VIT 0xf53c0008 |
| 3224 | #define F0900_P1_E3_4VIT 0xf53c0004 |
| 3225 | #define F0900_P1_E2_3VIT 0xf53c0002 |
| 3226 | #define F0900_P1_E1_2VIT 0xf53c0001 |
| 3227 | |
| 3228 | /*P1_VAVSRVIT*/ |
| 3229 | #define R0900_P1_VAVSRVIT 0xf53d |
| 3230 | #define F0900_P1_AMVIT 0xf53d0080 |
| 3231 | #define F0900_P1_FROZENVIT 0xf53d0040 |
| 3232 | #define F0900_P1_SNVIT 0xf53d0030 |
| 3233 | #define F0900_P1_TOVVIT 0xf53d000c |
| 3234 | #define F0900_P1_HYPVIT 0xf53d0003 |
| 3235 | |
| 3236 | /*P1_VSTATUSVIT*/ |
| 3237 | #define R0900_P1_VSTATUSVIT 0xf53e |
| 3238 | #define F0900_P1_VITERBI_ON 0xf53e0080 |
| 3239 | #define F0900_P1_END_LOOPVIT 0xf53e0040 |
| 3240 | #define F0900_P1_VITERBI_DEPRF 0xf53e0020 |
| 3241 | #define F0900_P1_PRFVIT 0xf53e0010 |
| 3242 | #define F0900_P1_LOCKEDVIT 0xf53e0008 |
| 3243 | #define F0900_P1_VITERBI_DELOCK 0xf53e0004 |
| 3244 | #define F0900_P1_VIT_DEMODSEL 0xf53e0002 |
| 3245 | #define F0900_P1_VITERBI_COMPOUT 0xf53e0001 |
| 3246 | |
| 3247 | /*P1_VTHINUSE*/ |
| 3248 | #define R0900_P1_VTHINUSE 0xf53f |
| 3249 | #define F0900_P1_VIT_INUSE 0xf53f00ff |
| 3250 | |
| 3251 | /*P1_KDIV12*/ |
| 3252 | #define R0900_P1_KDIV12 0xf540 |
| 3253 | #define F0900_P1_KDIV12_MANUAL 0xf5400080 |
| 3254 | #define F0900_P1_K_DIVIDER_12 0xf540007f |
| 3255 | |
| 3256 | /*P1_KDIV23*/ |
| 3257 | #define R0900_P1_KDIV23 0xf541 |
| 3258 | #define F0900_P1_KDIV23_MANUAL 0xf5410080 |
| 3259 | #define F0900_P1_K_DIVIDER_23 0xf541007f |
| 3260 | |
| 3261 | /*P1_KDIV34*/ |
| 3262 | #define R0900_P1_KDIV34 0xf542 |
| 3263 | #define F0900_P1_KDIV34_MANUAL 0xf5420080 |
| 3264 | #define F0900_P1_K_DIVIDER_34 0xf542007f |
| 3265 | |
| 3266 | /*P1_KDIV56*/ |
| 3267 | #define R0900_P1_KDIV56 0xf543 |
| 3268 | #define F0900_P1_KDIV56_MANUAL 0xf5430080 |
| 3269 | #define F0900_P1_K_DIVIDER_56 0xf543007f |
| 3270 | |
| 3271 | /*P1_KDIV67*/ |
| 3272 | #define R0900_P1_KDIV67 0xf544 |
| 3273 | #define F0900_P1_KDIV67_MANUAL 0xf5440080 |
| 3274 | #define F0900_P1_K_DIVIDER_67 0xf544007f |
| 3275 | |
| 3276 | /*P1_KDIV78*/ |
| 3277 | #define R0900_P1_KDIV78 0xf545 |
| 3278 | #define F0900_P1_KDIV78_MANUAL 0xf5450080 |
| 3279 | #define F0900_P1_K_DIVIDER_78 0xf545007f |
| 3280 | |
| 3281 | /*P1_PDELCTRL1*/ |
| 3282 | #define R0900_P1_PDELCTRL1 0xf550 |
| 3283 | #define F0900_P1_INV_MISMASK 0xf5500080 |
| 3284 | #define F0900_P1_FORCE_ACCEPTED 0xf5500040 |
| 3285 | #define F0900_P1_FILTER_EN 0xf5500020 |
| 3286 | #define F0900_P1_FORCE_PKTDELINUSE 0xf5500010 |
| 3287 | #define F0900_P1_HYSTEN 0xf5500008 |
| 3288 | #define F0900_P1_HYSTSWRST 0xf5500004 |
| 3289 | #define F0900_P1_EN_MIS00 0xf5500002 |
| 3290 | #define F0900_P1_ALGOSWRST 0xf5500001 |
| 3291 | |
| 3292 | /*P1_PDELCTRL2*/ |
| 3293 | #define R0900_P1_PDELCTRL2 0xf551 |
| 3294 | #define F0900_P1_FORCE_CONTINUOUS 0xf5510080 |
| 3295 | #define F0900_P1_RESET_UPKO_COUNT 0xf5510040 |
| 3296 | #define F0900_P1_USER_PKTDELIN_NB 0xf5510020 |
| 3297 | #define F0900_P1_FORCE_LOCKED 0xf5510010 |
| 3298 | #define F0900_P1_DATA_UNBBSCRAM 0xf5510008 |
| 3299 | #define F0900_P1_FORCE_LONGPKT 0xf5510004 |
| 3300 | #define F0900_P1_FRAME_MODE 0xf5510002 |
| 3301 | |
| 3302 | /*P1_HYSTTHRESH*/ |
| 3303 | #define R0900_P1_HYSTTHRESH 0xf554 |
| 3304 | #define F0900_P1_UNLCK_THRESH 0xf55400f0 |
| 3305 | #define F0900_P1_DELIN_LCK_THRESH 0xf554000f |
| 3306 | |
| 3307 | /*P1_ISIENTRY*/ |
| 3308 | #define R0900_P1_ISIENTRY 0xf55e |
| 3309 | #define F0900_P1_ISI_ENTRY 0xf55e00ff |
| 3310 | |
| 3311 | /*P1_ISIBITENA*/ |
| 3312 | #define R0900_P1_ISIBITENA 0xf55f |
| 3313 | #define F0900_P1_ISI_BIT_EN 0xf55f00ff |
| 3314 | |
| 3315 | /*P1_MATSTR1*/ |
| 3316 | #define R0900_P1_MATSTR1 0xf560 |
| 3317 | #define F0900_P1_MATYPE_CURRENT1 0xf56000ff |
| 3318 | |
| 3319 | /*P1_MATSTR0*/ |
| 3320 | #define R0900_P1_MATSTR0 0xf561 |
| 3321 | #define F0900_P1_MATYPE_CURRENT0 0xf56100ff |
| 3322 | |
| 3323 | /*P1_UPLSTR1*/ |
| 3324 | #define R0900_P1_UPLSTR1 0xf562 |
| 3325 | #define F0900_P1_UPL_CURRENT1 0xf56200ff |
| 3326 | |
| 3327 | /*P1_UPLSTR0*/ |
| 3328 | #define R0900_P1_UPLSTR0 0xf563 |
| 3329 | #define F0900_P1_UPL_CURRENT0 0xf56300ff |
| 3330 | |
| 3331 | /*P1_DFLSTR1*/ |
| 3332 | #define R0900_P1_DFLSTR1 0xf564 |
| 3333 | #define F0900_P1_DFL_CURRENT1 0xf56400ff |
| 3334 | |
| 3335 | /*P1_DFLSTR0*/ |
| 3336 | #define R0900_P1_DFLSTR0 0xf565 |
| 3337 | #define F0900_P1_DFL_CURRENT0 0xf56500ff |
| 3338 | |
| 3339 | /*P1_SYNCSTR*/ |
| 3340 | #define R0900_P1_SYNCSTR 0xf566 |
| 3341 | #define F0900_P1_SYNC_CURRENT 0xf56600ff |
| 3342 | |
| 3343 | /*P1_SYNCDSTR1*/ |
| 3344 | #define R0900_P1_SYNCDSTR1 0xf567 |
| 3345 | #define F0900_P1_SYNCD_CURRENT1 0xf56700ff |
| 3346 | |
| 3347 | /*P1_SYNCDSTR0*/ |
| 3348 | #define R0900_P1_SYNCDSTR0 0xf568 |
| 3349 | #define F0900_P1_SYNCD_CURRENT0 0xf56800ff |
| 3350 | |
| 3351 | /*P1_PDELSTATUS1*/ |
| 3352 | #define R0900_P1_PDELSTATUS1 0xf569 |
| 3353 | #define F0900_P1_PKTDELIN_DELOCK 0xf5690080 |
| 3354 | #define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040 |
| 3355 | #define F0900_P1_CONTINUOUS_STREAM 0xf5690020 |
| 3356 | #define F0900_P1_UNACCEPTED_STREAM 0xf5690010 |
| 3357 | #define F0900_P1_BCH_ERROR_FLAG 0xf5690008 |
| 3358 | #define F0900_P1_BBHCRCKO 0xf5690004 |
| 3359 | #define F0900_P1_PKTDELIN_LOCK 0xf5690002 |
| 3360 | #define F0900_P1_FIRST_LOCK 0xf5690001 |
| 3361 | |
| 3362 | /*P1_PDELSTATUS2*/ |
| 3363 | #define R0900_P1_PDELSTATUS2 0xf56a |
| 3364 | #define F0900_P1_PKTDEL_DEMODSEL 0xf56a0080 |
| 3365 | #define F0900_P1_FRAME_MODCOD 0xf56a007c |
| 3366 | #define F0900_P1_FRAME_TYPE 0xf56a0003 |
| 3367 | |
| 3368 | /*P1_BBFCRCKO1*/ |
| 3369 | #define R0900_P1_BBFCRCKO1 0xf56b |
| 3370 | #define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff |
| 3371 | |
| 3372 | /*P1_BBFCRCKO0*/ |
| 3373 | #define R0900_P1_BBFCRCKO0 0xf56c |
| 3374 | #define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff |
| 3375 | |
| 3376 | /*P1_UPCRCKO1*/ |
| 3377 | #define R0900_P1_UPCRCKO1 0xf56d |
| 3378 | #define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff |
| 3379 | |
| 3380 | /*P1_UPCRCKO0*/ |
| 3381 | #define R0900_P1_UPCRCKO0 0xf56e |
| 3382 | #define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff |
| 3383 | |
| 3384 | /*P1_TSSTATEM*/ |
| 3385 | #define R0900_P1_TSSTATEM 0xf570 |
| 3386 | #define F0900_P1_TSDIL_ON 0xf5700080 |
| 3387 | #define F0900_P1_TSSKIPRS_ON 0xf5700040 |
| 3388 | #define F0900_P1_TSRS_ON 0xf5700020 |
| 3389 | #define F0900_P1_TSDESCRAMB_ON 0xf5700010 |
| 3390 | #define F0900_P1_TSFRAME_MODE 0xf5700008 |
| 3391 | #define F0900_P1_TS_DISABLE 0xf5700004 |
| 3392 | #define F0900_P1_TSACM_MODE 0xf5700002 |
| 3393 | #define F0900_P1_TSOUT_NOSYNC 0xf5700001 |
| 3394 | |
| 3395 | /*P1_TSCFGH*/ |
| 3396 | #define R0900_P1_TSCFGH 0xf572 |
| 3397 | #define F0900_P1_TSFIFO_DVBCI 0xf5720080 |
| 3398 | #define F0900_P1_TSFIFO_SERIAL 0xf5720040 |
| 3399 | #define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020 |
| 3400 | #define F0900_P1_TSFIFO_DUTY50 0xf5720010 |
| 3401 | #define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008 |
| 3402 | #define F0900_P1_TSFIFO_ERRMODE 0xf5720006 |
| 3403 | #define F0900_P1_RST_HWARE 0xf5720001 |
| 3404 | |
| 3405 | /*P1_TSCFGM*/ |
| 3406 | #define R0900_P1_TSCFGM 0xf573 |
| 3407 | #define F0900_P1_TSFIFO_MANSPEED 0xf57300c0 |
| 3408 | #define F0900_P1_TSFIFO_PERMDATA 0xf5730020 |
| 3409 | #define F0900_P1_TSFIFO_NONEWSGNL 0xf5730010 |
| 3410 | #define F0900_P1_TSFIFO_BITSPEED 0xf5730008 |
| 3411 | #define F0900_P1_NPD_SPECDVBS2 0xf5730004 |
| 3412 | #define F0900_P1_TSFIFO_STOPCKDIS 0xf5730002 |
| 3413 | #define F0900_P1_TSFIFO_INVDATA 0xf5730001 |
| 3414 | |
| 3415 | /*P1_TSCFGL*/ |
| 3416 | #define R0900_P1_TSCFGL 0xf574 |
| 3417 | #define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 |
| 3418 | #define F0900_P1_BCHERROR_MODE 0xf5740030 |
| 3419 | #define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008 |
| 3420 | #define F0900_P1_TSFIFO_EMBINDVB 0xf5740004 |
| 3421 | #define F0900_P1_TSFIFO_DPUNACT 0xf5740002 |
| 3422 | #define F0900_P1_TSFIFO_NPDOFF 0xf5740001 |
| 3423 | |
| 3424 | /*P1_TSINSDELH*/ |
| 3425 | #define R0900_P1_TSINSDELH 0xf576 |
| 3426 | #define F0900_P1_TSDEL_SYNCBYTE 0xf5760080 |
| 3427 | #define F0900_P1_TSDEL_XXHEADER 0xf5760040 |
| 3428 | #define F0900_P1_TSDEL_BBHEADER 0xf5760020 |
| 3429 | #define F0900_P1_TSDEL_DATAFIELD 0xf5760010 |
| 3430 | #define F0900_P1_TSINSDEL_ISCR 0xf5760008 |
| 3431 | #define F0900_P1_TSINSDEL_NPD 0xf5760004 |
| 3432 | #define F0900_P1_TSINSDEL_RSPARITY 0xf5760002 |
| 3433 | #define F0900_P1_TSINSDEL_CRC8 0xf5760001 |
| 3434 | |
| 3435 | /*P1_TSSPEED*/ |
| 3436 | #define R0900_P1_TSSPEED 0xf580 |
| 3437 | #define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff |
| 3438 | |
| 3439 | /*P1_TSSTATUS*/ |
| 3440 | #define R0900_P1_TSSTATUS 0xf581 |
| 3441 | #define F0900_P1_TSFIFO_LINEOK 0xf5810080 |
| 3442 | #define F0900_P1_TSFIFO_ERROR 0xf5810040 |
| 3443 | #define F0900_P1_TSFIFO_DATA7 0xf5810020 |
| 3444 | #define F0900_P1_TSFIFO_NOSYNC 0xf5810010 |
| 3445 | #define F0900_P1_ISCR_INITIALIZED 0xf5810008 |
| 3446 | #define F0900_P1_ISCR_UPDATED 0xf5810004 |
| 3447 | #define F0900_P1_SOFFIFO_UNREGUL 0xf5810002 |
| 3448 | #define F0900_P1_DIL_READY 0xf5810001 |
| 3449 | |
| 3450 | /*P1_TSSTATUS2*/ |
| 3451 | #define R0900_P1_TSSTATUS2 0xf582 |
| 3452 | #define F0900_P1_TSFIFO_DEMODSEL 0xf5820080 |
| 3453 | #define F0900_P1_TSFIFOSPEED_STORE 0xf5820040 |
| 3454 | #define F0900_P1_DILXX_RESET 0xf5820020 |
| 3455 | #define F0900_P1_TSSERIAL_IMPOS 0xf5820010 |
| 3456 | #define F0900_P1_TSFIFO_LINENOK 0xf5820008 |
| 3457 | #define F0900_P1_BITSPEED_EVENT 0xf5820004 |
| 3458 | #define F0900_P1_SCRAMBDETECT 0xf5820002 |
| 3459 | #define F0900_P1_ULDTV67_FALSELOCK 0xf5820001 |
| 3460 | |
| 3461 | /*P1_TSBITRATE1*/ |
| 3462 | #define R0900_P1_TSBITRATE1 0xf583 |
| 3463 | #define F0900_P1_TSFIFO_BITRATE1 0xf58300ff |
| 3464 | |
| 3465 | /*P1_TSBITRATE0*/ |
| 3466 | #define R0900_P1_TSBITRATE0 0xf584 |
| 3467 | #define F0900_P1_TSFIFO_BITRATE0 0xf58400ff |
| 3468 | |
| 3469 | /*P1_ERRCTRL1*/ |
| 3470 | #define R0900_P1_ERRCTRL1 0xf598 |
| 3471 | #define F0900_P1_ERR_SOURCE1 0xf59800f0 |
| 3472 | #define F0900_P1_NUM_EVENT1 0xf5980007 |
| 3473 | |
| 3474 | /*P1_ERRCNT12*/ |
| 3475 | #define R0900_P1_ERRCNT12 0xf599 |
| 3476 | #define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080 |
| 3477 | #define F0900_P1_ERR_CNT12 0xf599007f |
| 3478 | |
| 3479 | /*P1_ERRCNT11*/ |
| 3480 | #define R0900_P1_ERRCNT11 0xf59a |
| 3481 | #define F0900_P1_ERR_CNT11 0xf59a00ff |
| 3482 | |
| 3483 | /*P1_ERRCNT10*/ |
| 3484 | #define R0900_P1_ERRCNT10 0xf59b |
| 3485 | #define F0900_P1_ERR_CNT10 0xf59b00ff |
| 3486 | |
| 3487 | /*P1_ERRCTRL2*/ |
| 3488 | #define R0900_P1_ERRCTRL2 0xf59c |
| 3489 | #define F0900_P1_ERR_SOURCE2 0xf59c00f0 |
| 3490 | #define F0900_P1_NUM_EVENT2 0xf59c0007 |
| 3491 | |
| 3492 | /*P1_ERRCNT22*/ |
| 3493 | #define R0900_P1_ERRCNT22 0xf59d |
| 3494 | #define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080 |
| 3495 | #define F0900_P1_ERR_CNT22 0xf59d007f |
| 3496 | |
| 3497 | /*P1_ERRCNT21*/ |
| 3498 | #define R0900_P1_ERRCNT21 0xf59e |
| 3499 | #define F0900_P1_ERR_CNT21 0xf59e00ff |
| 3500 | |
| 3501 | /*P1_ERRCNT20*/ |
| 3502 | #define R0900_P1_ERRCNT20 0xf59f |
| 3503 | #define F0900_P1_ERR_CNT20 0xf59f00ff |
| 3504 | |
| 3505 | /*P1_FECSPY*/ |
| 3506 | #define R0900_P1_FECSPY 0xf5a0 |
| 3507 | #define F0900_P1_SPY_ENABLE 0xf5a00080 |
| 3508 | #define F0900_P1_NO_SYNCBYTE 0xf5a00040 |
| 3509 | #define F0900_P1_SERIAL_MODE 0xf5a00020 |
| 3510 | #define F0900_P1_UNUSUAL_PACKET 0xf5a00010 |
| 3511 | #define F0900_P1_BER_PACKMODE 0xf5a00008 |
| 3512 | #define F0900_P1_BERMETER_LMODE 0xf5a00002 |
| 3513 | #define F0900_P1_BERMETER_RESET 0xf5a00001 |
| 3514 | |
| 3515 | /*P1_FSPYCFG*/ |
| 3516 | #define R0900_P1_FSPYCFG 0xf5a1 |
| 3517 | #define F0900_P1_FECSPY_INPUT 0xf5a100c0 |
| 3518 | #define F0900_P1_RST_ON_ERROR 0xf5a10020 |
| 3519 | #define F0900_P1_ONE_SHOT 0xf5a10010 |
| 3520 | #define F0900_P1_I2C_MODE 0xf5a1000c |
| 3521 | #define F0900_P1_SPY_HYSTERESIS 0xf5a10003 |
| 3522 | |
| 3523 | /*P1_FSPYDATA*/ |
| 3524 | #define R0900_P1_FSPYDATA 0xf5a2 |
| 3525 | #define F0900_P1_SPY_STUFFING 0xf5a20080 |
| 3526 | #define F0900_P1_NOERROR_PKTJITTER 0xf5a20040 |
| 3527 | #define F0900_P1_SPY_CNULLPKT 0xf5a20020 |
| 3528 | #define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f |
| 3529 | |
| 3530 | /*P1_FSPYOUT*/ |
| 3531 | #define R0900_P1_FSPYOUT 0xf5a3 |
| 3532 | #define F0900_P1_FSPY_DIRECT 0xf5a30080 |
| 3533 | #define F0900_P1_SPY_OUTDATA_BUS 0xf5a30038 |
| 3534 | #define F0900_P1_STUFF_MODE 0xf5a30007 |
| 3535 | |
| 3536 | /*P1_FSTATUS*/ |
| 3537 | #define R0900_P1_FSTATUS 0xf5a4 |
| 3538 | #define F0900_P1_SPY_ENDSIM 0xf5a40080 |
| 3539 | #define F0900_P1_VALID_SIM 0xf5a40040 |
| 3540 | #define F0900_P1_FOUND_SIGNAL 0xf5a40020 |
| 3541 | #define F0900_P1_DSS_SYNCBYTE 0xf5a40010 |
| 3542 | #define F0900_P1_RESULT_STATE 0xf5a4000f |
| 3543 | |
| 3544 | /*P1_FBERCPT4*/ |
| 3545 | #define R0900_P1_FBERCPT4 0xf5a8 |
| 3546 | #define F0900_P1_FBERMETER_CPT4 0xf5a800ff |
| 3547 | |
| 3548 | /*P1_FBERCPT3*/ |
| 3549 | #define R0900_P1_FBERCPT3 0xf5a9 |
| 3550 | #define F0900_P1_FBERMETER_CPT3 0xf5a900ff |
| 3551 | |
| 3552 | /*P1_FBERCPT2*/ |
| 3553 | #define R0900_P1_FBERCPT2 0xf5aa |
| 3554 | #define F0900_P1_FBERMETER_CPT2 0xf5aa00ff |
| 3555 | |
| 3556 | /*P1_FBERCPT1*/ |
| 3557 | #define R0900_P1_FBERCPT1 0xf5ab |
| 3558 | #define F0900_P1_FBERMETER_CPT1 0xf5ab00ff |
| 3559 | |
| 3560 | /*P1_FBERCPT0*/ |
| 3561 | #define R0900_P1_FBERCPT0 0xf5ac |
| 3562 | #define F0900_P1_FBERMETER_CPT0 0xf5ac00ff |
| 3563 | |
| 3564 | /*P1_FBERERR2*/ |
| 3565 | #define R0900_P1_FBERERR2 0xf5ad |
| 3566 | #define F0900_P1_FBERMETER_ERR2 0xf5ad00ff |
| 3567 | |
| 3568 | /*P1_FBERERR1*/ |
| 3569 | #define R0900_P1_FBERERR1 0xf5ae |
| 3570 | #define F0900_P1_FBERMETER_ERR1 0xf5ae00ff |
| 3571 | |
| 3572 | /*P1_FBERERR0*/ |
| 3573 | #define R0900_P1_FBERERR0 0xf5af |
| 3574 | #define F0900_P1_FBERMETER_ERR0 0xf5af00ff |
| 3575 | |
| 3576 | /*P1_FSPYBER*/ |
| 3577 | #define R0900_P1_FSPYBER 0xf5b2 |
| 3578 | #define F0900_P1_FSPYOBS_XORREAD 0xf5b20040 |
| 3579 | #define F0900_P1_FSPYBER_OBSMODE 0xf5b20020 |
| 3580 | #define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010 |
| 3581 | #define F0900_P1_FSPYBER_UNSYNC 0xf5b20008 |
| 3582 | #define F0900_P1_FSPYBER_CTIME 0xf5b20007 |
| 3583 | |
| 3584 | /*RCCFGH*/ |
| 3585 | #define R0900_RCCFGH 0xf600 |
| 3586 | #define F0900_TSRCFIFO_DVBCI 0xf6000080 |
| 3587 | #define F0900_TSRCFIFO_SERIAL 0xf6000040 |
| 3588 | #define F0900_TSRCFIFO_DISABLE 0xf6000020 |
| 3589 | #define F0900_TSFIFO_2TORC 0xf6000010 |
| 3590 | #define F0900_TSRCFIFO_HSGNLOUT 0xf6000008 |
| 3591 | #define F0900_TSRCFIFO_ERRMODE 0xf6000006 |
| 3592 | |
| 3593 | /*TSGENERAL*/ |
| 3594 | #define R0900_TSGENERAL 0xf630 |
| 3595 | #define F0900_TSFIFO_BCLK1ALL 0xf6300020 |
| 3596 | #define F0900_MUXSTREAM_OUTMODE 0xf6300008 |
| 3597 | #define F0900_TSFIFO_PERMPARAL 0xf6300006 |
| 3598 | #define F0900_RST_REEDSOLO 0xf6300001 |
| 3599 | |
| 3600 | /*TSGENERAL1X*/ |
| 3601 | #define R0900_TSGENERAL1X 0xf670 |
| 3602 | #define F0900_TSFIFO1X_BCLK1ALL 0xf6700020 |
| 3603 | #define F0900_MUXSTREAM1X_OUTMODE 0xf6700008 |
| 3604 | #define F0900_TSFIFO1X_PERMPARAL 0xf6700006 |
| 3605 | #define F0900_RST1X_REEDSOLO 0xf6700001 |
| 3606 | |
| 3607 | /*NBITER_NF4*/ |
| 3608 | #define R0900_NBITER_NF4 0xfa03 |
| 3609 | #define F0900_NBITER_NF_QP_1_2 0xfa0300ff |
| 3610 | |
| 3611 | /*NBITER_NF5*/ |
| 3612 | #define R0900_NBITER_NF5 0xfa04 |
| 3613 | #define F0900_NBITER_NF_QP_3_5 0xfa0400ff |
| 3614 | |
| 3615 | /*NBITER_NF6*/ |
| 3616 | #define R0900_NBITER_NF6 0xfa05 |
| 3617 | #define F0900_NBITER_NF_QP_2_3 0xfa0500ff |
| 3618 | |
| 3619 | /*NBITER_NF7*/ |
| 3620 | #define R0900_NBITER_NF7 0xfa06 |
| 3621 | #define F0900_NBITER_NF_QP_3_4 0xfa0600ff |
| 3622 | |
| 3623 | /*NBITER_NF8*/ |
| 3624 | #define R0900_NBITER_NF8 0xfa07 |
| 3625 | #define F0900_NBITER_NF_QP_4_5 0xfa0700ff |
| 3626 | |
| 3627 | /*NBITER_NF9*/ |
| 3628 | #define R0900_NBITER_NF9 0xfa08 |
| 3629 | #define F0900_NBITER_NF_QP_5_6 0xfa0800ff |
| 3630 | |
| 3631 | /*NBITER_NF10*/ |
| 3632 | #define R0900_NBITER_NF10 0xfa09 |
| 3633 | #define F0900_NBITER_NF_QP_8_9 0xfa0900ff |
| 3634 | |
| 3635 | /*NBITER_NF11*/ |
| 3636 | #define R0900_NBITER_NF11 0xfa0a |
| 3637 | #define F0900_NBITER_NF_QP_9_10 0xfa0a00ff |
| 3638 | |
| 3639 | /*NBITER_NF12*/ |
| 3640 | #define R0900_NBITER_NF12 0xfa0b |
| 3641 | #define F0900_NBITER_NF_8P_3_5 0xfa0b00ff |
| 3642 | |
| 3643 | /*NBITER_NF13*/ |
| 3644 | #define R0900_NBITER_NF13 0xfa0c |
| 3645 | #define F0900_NBITER_NF_8P_2_3 0xfa0c00ff |
| 3646 | |
| 3647 | /*NBITER_NF14*/ |
| 3648 | #define R0900_NBITER_NF14 0xfa0d |
| 3649 | #define F0900_NBITER_NF_8P_3_4 0xfa0d00ff |
| 3650 | |
| 3651 | /*NBITER_NF15*/ |
| 3652 | #define R0900_NBITER_NF15 0xfa0e |
| 3653 | #define F0900_NBITER_NF_8P_5_6 0xfa0e00ff |
| 3654 | |
| 3655 | /*NBITER_NF16*/ |
| 3656 | #define R0900_NBITER_NF16 0xfa0f |
| 3657 | #define F0900_NBITER_NF_8P_8_9 0xfa0f00ff |
| 3658 | |
| 3659 | /*NBITER_NF17*/ |
| 3660 | #define R0900_NBITER_NF17 0xfa10 |
| 3661 | #define F0900_NBITER_NF_8P_9_10 0xfa1000ff |
| 3662 | |
| 3663 | /*NBITERNOERR*/ |
| 3664 | #define R0900_NBITERNOERR 0xfa3f |
| 3665 | #define F0900_NBITER_STOP_CRIT 0xfa3f000f |
| 3666 | |
| 3667 | /*GAINLLR_NF4*/ |
| 3668 | #define R0900_GAINLLR_NF4 0xfa43 |
| 3669 | #define F0900_GAINLLR_NF_QP_1_2 0xfa43007f |
| 3670 | |
| 3671 | /*GAINLLR_NF5*/ |
| 3672 | #define R0900_GAINLLR_NF5 0xfa44 |
| 3673 | #define F0900_GAINLLR_NF_QP_3_5 0xfa44007f |
| 3674 | |
| 3675 | /*GAINLLR_NF6*/ |
| 3676 | #define R0900_GAINLLR_NF6 0xfa45 |
| 3677 | #define F0900_GAINLLR_NF_QP_2_3 0xfa45007f |
| 3678 | |
| 3679 | /*GAINLLR_NF7*/ |
| 3680 | #define R0900_GAINLLR_NF7 0xfa46 |
| 3681 | #define F0900_GAINLLR_NF_QP_3_4 0xfa46007f |
| 3682 | |
| 3683 | /*GAINLLR_NF8*/ |
| 3684 | #define R0900_GAINLLR_NF8 0xfa47 |
| 3685 | #define F0900_GAINLLR_NF_QP_4_5 0xfa47007f |
| 3686 | |
| 3687 | /*GAINLLR_NF9*/ |
| 3688 | #define R0900_GAINLLR_NF9 0xfa48 |
| 3689 | #define F0900_GAINLLR_NF_QP_5_6 0xfa48007f |
| 3690 | |
| 3691 | /*GAINLLR_NF10*/ |
| 3692 | #define R0900_GAINLLR_NF10 0xfa49 |
| 3693 | #define F0900_GAINLLR_NF_QP_8_9 0xfa49007f |
| 3694 | |
| 3695 | /*GAINLLR_NF11*/ |
| 3696 | #define R0900_GAINLLR_NF11 0xfa4a |
| 3697 | #define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f |
| 3698 | |
| 3699 | /*GAINLLR_NF12*/ |
| 3700 | #define R0900_GAINLLR_NF12 0xfa4b |
| 3701 | #define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f |
| 3702 | |
| 3703 | /*GAINLLR_NF13*/ |
| 3704 | #define R0900_GAINLLR_NF13 0xfa4c |
| 3705 | #define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f |
| 3706 | |
| 3707 | /*GAINLLR_NF14*/ |
| 3708 | #define R0900_GAINLLR_NF14 0xfa4d |
| 3709 | #define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f |
| 3710 | |
| 3711 | /*GAINLLR_NF15*/ |
| 3712 | #define R0900_GAINLLR_NF15 0xfa4e |
| 3713 | #define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f |
| 3714 | |
| 3715 | /*GAINLLR_NF16*/ |
| 3716 | #define R0900_GAINLLR_NF16 0xfa4f |
| 3717 | #define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f |
| 3718 | |
| 3719 | /*GAINLLR_NF17*/ |
| 3720 | #define R0900_GAINLLR_NF17 0xfa50 |
| 3721 | #define F0900_GAINLLR_NF_8P_9_10 0xfa50007f |
| 3722 | |
| 3723 | /*CFGEXT*/ |
| 3724 | #define R0900_CFGEXT 0xfa80 |
| 3725 | #define F0900_STAGMODE 0xfa800080 |
| 3726 | #define F0900_BYPBCH 0xfa800040 |
| 3727 | #define F0900_BYPLDPC 0xfa800020 |
| 3728 | #define F0900_LDPCMODE 0xfa800010 |
| 3729 | #define F0900_INVLLRSIGN 0xfa800008 |
| 3730 | #define F0900_SHORTMULT 0xfa800004 |
| 3731 | #define F0900_EXTERNTX 0xfa800001 |
| 3732 | |
| 3733 | /*GENCFG*/ |
| 3734 | #define R0900_GENCFG 0xfa86 |
| 3735 | #define F0900_BROADCAST 0xfa860010 |
| 3736 | #define F0900_NOSHFRD2 0xfa860008 |
| 3737 | #define F0900_BCHERRFLAG 0xfa860004 |
| 3738 | #define F0900_PRIORITY 0xfa860002 |
| 3739 | #define F0900_DDEMOD 0xfa860001 |
| 3740 | |
| 3741 | /*LDPCERR1*/ |
| 3742 | #define R0900_LDPCERR1 0xfa96 |
| 3743 | #define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff |
| 3744 | |
| 3745 | /*LDPCERR0*/ |
| 3746 | #define R0900_LDPCERR0 0xfa97 |
| 3747 | #define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff |
| 3748 | |
| 3749 | /*BCHERR*/ |
| 3750 | #define R0900_BCHERR 0xfa98 |
| 3751 | #define F0900_ERRORFLAG 0xfa980010 |
| 3752 | #define F0900_BCH_ERRORS_COUNTER 0xfa98000f |
| 3753 | |
| 3754 | /*TSTRES0*/ |
| 3755 | #define R0900_TSTRES0 0xff11 |
| 3756 | #define F0900_FRESFEC 0xff110080 |
| 3757 | #define F0900_FRESTS 0xff110040 |
| 3758 | #define F0900_FRESVIT1 0xff110020 |
| 3759 | #define F0900_FRESVIT2 0xff110010 |
| 3760 | #define F0900_FRESSYM1 0xff110008 |
| 3761 | #define F0900_FRESSYM2 0xff110004 |
| 3762 | #define F0900_FRESMAS 0xff110002 |
| 3763 | #define F0900_FRESINT 0xff110001 |
| 3764 | |
| 3765 | /*P2_TSTDISRX*/ |
| 3766 | #define R0900_P2_TSTDISRX 0xff65 |
| 3767 | #define F0900_P2_EN_DISRX 0xff650080 |
| 3768 | #define F0900_P2_TST_CURRSRC 0xff650040 |
| 3769 | #define F0900_P2_IN_DIGSIGNAL 0xff650020 |
| 3770 | #define F0900_P2_HIZ_CURRENTSRC 0xff650010 |
| 3771 | #define F0900_TST_P2_PIN_SELECT 0xff650008 |
| 3772 | #define F0900_P2_TST_DISRX 0xff650007 |
| 3773 | |
| 3774 | /*P1_TSTDISRX*/ |
| 3775 | #define R0900_P1_TSTDISRX 0xff67 |
| 3776 | #define F0900_P1_EN_DISRX 0xff670080 |
| 3777 | #define F0900_P1_TST_CURRSRC 0xff670040 |
| 3778 | #define F0900_P1_IN_DIGSIGNAL 0xff670020 |
| 3779 | #define F0900_P1_HIZ_CURRENTSRC 0xff670010 |
| 3780 | #define F0900_TST_P1_PIN_SELECT 0xff670008 |
| 3781 | #define F0900_P1_TST_DISRX 0xff670007 |
| 3782 | |
| 3783 | #define STV0900_NBREGS 684 |
| 3784 | #define STV0900_NBFIELDS 1702 |
| 3785 | |
| 3786 | #endif |
| 3787 | |