Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1 | #include "drmP.h" |
| 2 | #include "drm.h" |
| 3 | #include "radeon_drm.h" |
| 4 | #include "radeon.h" |
| 5 | |
| 6 | #include "r600d.h" |
| 7 | #include "r600_blit_shaders.h" |
| 8 | |
| 9 | #define DI_PT_RECTLIST 0x11 |
| 10 | #define DI_INDEX_SIZE_16_BIT 0x0 |
| 11 | #define DI_SRC_SEL_AUTO_INDEX 0x2 |
| 12 | |
| 13 | #define FMT_8 0x1 |
| 14 | #define FMT_5_6_5 0x8 |
| 15 | #define FMT_8_8_8_8 0x1a |
| 16 | #define COLOR_8 0x1 |
| 17 | #define COLOR_5_6_5 0x8 |
| 18 | #define COLOR_8_8_8_8 0x1a |
| 19 | |
| 20 | /* emits 21 on rv770+, 23 on r600 */ |
| 21 | static void |
| 22 | set_render_target(struct radeon_device *rdev, int format, |
| 23 | int w, int h, u64 gpu_addr) |
| 24 | { |
| 25 | u32 cb_color_info; |
| 26 | int pitch, slice; |
| 27 | |
Matt Turner | d964fc5 | 2010-02-25 04:23:31 +0000 | [diff] [blame^] | 28 | h = ALIGN(h, 8); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 29 | if (h < 8) |
| 30 | h = 8; |
| 31 | |
| 32 | cb_color_info = ((format << 2) | (1 << 27)); |
| 33 | pitch = (w / 8) - 1; |
| 34 | slice = ((w * h) / 64) - 1; |
| 35 | |
| 36 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 37 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 38 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 39 | |
| 40 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { |
| 41 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
| 42 | radeon_ring_write(rdev, 2 << 0); |
| 43 | } |
| 44 | |
| 45 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 46 | radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 47 | radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
| 48 | |
| 49 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 50 | radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 51 | radeon_ring_write(rdev, 0); |
| 52 | |
| 53 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 54 | radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 55 | radeon_ring_write(rdev, cb_color_info); |
| 56 | |
| 57 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 58 | radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 59 | radeon_ring_write(rdev, 0); |
| 60 | |
| 61 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 62 | radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 63 | radeon_ring_write(rdev, 0); |
| 64 | |
| 65 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 66 | radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 67 | radeon_ring_write(rdev, 0); |
| 68 | } |
| 69 | |
| 70 | /* emits 5dw */ |
| 71 | static void |
| 72 | cp_set_surface_sync(struct radeon_device *rdev, |
| 73 | u32 sync_type, u32 size, |
| 74 | u64 mc_addr) |
| 75 | { |
| 76 | u32 cp_coher_size; |
| 77 | |
| 78 | if (size == 0xffffffff) |
| 79 | cp_coher_size = 0xffffffff; |
| 80 | else |
| 81 | cp_coher_size = ((size + 255) >> 8); |
| 82 | |
| 83 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 84 | radeon_ring_write(rdev, sync_type); |
| 85 | radeon_ring_write(rdev, cp_coher_size); |
| 86 | radeon_ring_write(rdev, mc_addr >> 8); |
| 87 | radeon_ring_write(rdev, 10); /* poll interval */ |
| 88 | } |
| 89 | |
| 90 | /* emits 21dw + 1 surface sync = 26dw */ |
| 91 | static void |
| 92 | set_shaders(struct radeon_device *rdev) |
| 93 | { |
| 94 | u64 gpu_addr; |
| 95 | u32 sq_pgm_resources; |
| 96 | |
| 97 | /* setup shader regs */ |
| 98 | sq_pgm_resources = (1 << 0); |
| 99 | |
| 100 | /* VS */ |
| 101 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| 102 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 103 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 104 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 105 | |
| 106 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 107 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 108 | radeon_ring_write(rdev, sq_pgm_resources); |
| 109 | |
| 110 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 111 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 112 | radeon_ring_write(rdev, 0); |
| 113 | |
| 114 | /* PS */ |
| 115 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
| 116 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 117 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 118 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 119 | |
| 120 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 121 | radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 122 | radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
| 123 | |
| 124 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 125 | radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 126 | radeon_ring_write(rdev, 2); |
| 127 | |
| 128 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| 129 | radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 130 | radeon_ring_write(rdev, 0); |
| 131 | |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 132 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 133 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
| 134 | } |
| 135 | |
| 136 | /* emits 9 + 1 sync (5) = 14*/ |
| 137 | static void |
| 138 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
| 139 | { |
| 140 | u32 sq_vtx_constant_word2; |
| 141 | |
| 142 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
| 143 | |
| 144 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
| 145 | radeon_ring_write(rdev, 0x460); |
| 146 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); |
| 147 | radeon_ring_write(rdev, 48 - 1); |
| 148 | radeon_ring_write(rdev, sq_vtx_constant_word2); |
| 149 | radeon_ring_write(rdev, 1 << 0); |
| 150 | radeon_ring_write(rdev, 0); |
| 151 | radeon_ring_write(rdev, 0); |
| 152 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
| 153 | |
| 154 | if ((rdev->family == CHIP_RV610) || |
| 155 | (rdev->family == CHIP_RV620) || |
| 156 | (rdev->family == CHIP_RS780) || |
| 157 | (rdev->family == CHIP_RS880) || |
| 158 | (rdev->family == CHIP_RV710)) |
| 159 | cp_set_surface_sync(rdev, |
| 160 | PACKET3_TC_ACTION_ENA, 48, gpu_addr); |
| 161 | else |
| 162 | cp_set_surface_sync(rdev, |
| 163 | PACKET3_VC_ACTION_ENA, 48, gpu_addr); |
| 164 | } |
| 165 | |
| 166 | /* emits 9 */ |
| 167 | static void |
| 168 | set_tex_resource(struct radeon_device *rdev, |
| 169 | int format, int w, int h, int pitch, |
| 170 | u64 gpu_addr) |
| 171 | { |
| 172 | uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; |
| 173 | |
| 174 | if (h < 1) |
| 175 | h = 1; |
| 176 | |
| 177 | sq_tex_resource_word0 = (1 << 0); |
| 178 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | |
| 179 | ((w - 1) << 19)); |
| 180 | |
| 181 | sq_tex_resource_word1 = (format << 26); |
| 182 | sq_tex_resource_word1 |= ((h - 1) << 0); |
| 183 | |
| 184 | sq_tex_resource_word4 = ((1 << 14) | |
| 185 | (0 << 16) | |
| 186 | (1 << 19) | |
| 187 | (2 << 22) | |
| 188 | (3 << 25)); |
| 189 | |
| 190 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
| 191 | radeon_ring_write(rdev, 0); |
| 192 | radeon_ring_write(rdev, sq_tex_resource_word0); |
| 193 | radeon_ring_write(rdev, sq_tex_resource_word1); |
| 194 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 195 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 196 | radeon_ring_write(rdev, sq_tex_resource_word4); |
| 197 | radeon_ring_write(rdev, 0); |
| 198 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); |
| 199 | } |
| 200 | |
| 201 | /* emits 12 */ |
| 202 | static void |
| 203 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
| 204 | int x2, int y2) |
| 205 | { |
| 206 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 207 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 208 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
| 209 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 210 | |
| 211 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 212 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 213 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 214 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 215 | |
| 216 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 217 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| 218 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 219 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 220 | } |
| 221 | |
| 222 | /* emits 10 */ |
| 223 | static void |
| 224 | draw_auto(struct radeon_device *rdev) |
| 225 | { |
| 226 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 227 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 228 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
| 229 | |
| 230 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
| 231 | radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); |
| 232 | |
| 233 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
| 234 | radeon_ring_write(rdev, 1); |
| 235 | |
| 236 | radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
| 237 | radeon_ring_write(rdev, 3); |
| 238 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
| 239 | |
| 240 | } |
| 241 | |
| 242 | /* emits 14 */ |
| 243 | static void |
| 244 | set_default_state(struct radeon_device *rdev) |
| 245 | { |
| 246 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
| 247 | u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
| 248 | int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
| 249 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
| 250 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
| 251 | u64 gpu_addr; |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 252 | int dwords; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 253 | |
| 254 | switch (rdev->family) { |
| 255 | case CHIP_R600: |
| 256 | num_ps_gprs = 192; |
| 257 | num_vs_gprs = 56; |
| 258 | num_temp_gprs = 4; |
| 259 | num_gs_gprs = 0; |
| 260 | num_es_gprs = 0; |
| 261 | num_ps_threads = 136; |
| 262 | num_vs_threads = 48; |
| 263 | num_gs_threads = 4; |
| 264 | num_es_threads = 4; |
| 265 | num_ps_stack_entries = 128; |
| 266 | num_vs_stack_entries = 128; |
| 267 | num_gs_stack_entries = 0; |
| 268 | num_es_stack_entries = 0; |
| 269 | break; |
| 270 | case CHIP_RV630: |
| 271 | case CHIP_RV635: |
| 272 | num_ps_gprs = 84; |
| 273 | num_vs_gprs = 36; |
| 274 | num_temp_gprs = 4; |
| 275 | num_gs_gprs = 0; |
| 276 | num_es_gprs = 0; |
| 277 | num_ps_threads = 144; |
| 278 | num_vs_threads = 40; |
| 279 | num_gs_threads = 4; |
| 280 | num_es_threads = 4; |
| 281 | num_ps_stack_entries = 40; |
| 282 | num_vs_stack_entries = 40; |
| 283 | num_gs_stack_entries = 32; |
| 284 | num_es_stack_entries = 16; |
| 285 | break; |
| 286 | case CHIP_RV610: |
| 287 | case CHIP_RV620: |
| 288 | case CHIP_RS780: |
| 289 | case CHIP_RS880: |
| 290 | default: |
| 291 | num_ps_gprs = 84; |
| 292 | num_vs_gprs = 36; |
| 293 | num_temp_gprs = 4; |
| 294 | num_gs_gprs = 0; |
| 295 | num_es_gprs = 0; |
| 296 | num_ps_threads = 136; |
| 297 | num_vs_threads = 48; |
| 298 | num_gs_threads = 4; |
| 299 | num_es_threads = 4; |
| 300 | num_ps_stack_entries = 40; |
| 301 | num_vs_stack_entries = 40; |
| 302 | num_gs_stack_entries = 32; |
| 303 | num_es_stack_entries = 16; |
| 304 | break; |
| 305 | case CHIP_RV670: |
| 306 | num_ps_gprs = 144; |
| 307 | num_vs_gprs = 40; |
| 308 | num_temp_gprs = 4; |
| 309 | num_gs_gprs = 0; |
| 310 | num_es_gprs = 0; |
| 311 | num_ps_threads = 136; |
| 312 | num_vs_threads = 48; |
| 313 | num_gs_threads = 4; |
| 314 | num_es_threads = 4; |
| 315 | num_ps_stack_entries = 40; |
| 316 | num_vs_stack_entries = 40; |
| 317 | num_gs_stack_entries = 32; |
| 318 | num_es_stack_entries = 16; |
| 319 | break; |
| 320 | case CHIP_RV770: |
| 321 | num_ps_gprs = 192; |
| 322 | num_vs_gprs = 56; |
| 323 | num_temp_gprs = 4; |
| 324 | num_gs_gprs = 0; |
| 325 | num_es_gprs = 0; |
| 326 | num_ps_threads = 188; |
| 327 | num_vs_threads = 60; |
| 328 | num_gs_threads = 0; |
| 329 | num_es_threads = 0; |
| 330 | num_ps_stack_entries = 256; |
| 331 | num_vs_stack_entries = 256; |
| 332 | num_gs_stack_entries = 0; |
| 333 | num_es_stack_entries = 0; |
| 334 | break; |
| 335 | case CHIP_RV730: |
| 336 | case CHIP_RV740: |
| 337 | num_ps_gprs = 84; |
| 338 | num_vs_gprs = 36; |
| 339 | num_temp_gprs = 4; |
| 340 | num_gs_gprs = 0; |
| 341 | num_es_gprs = 0; |
| 342 | num_ps_threads = 188; |
| 343 | num_vs_threads = 60; |
| 344 | num_gs_threads = 0; |
| 345 | num_es_threads = 0; |
| 346 | num_ps_stack_entries = 128; |
| 347 | num_vs_stack_entries = 128; |
| 348 | num_gs_stack_entries = 0; |
| 349 | num_es_stack_entries = 0; |
| 350 | break; |
| 351 | case CHIP_RV710: |
| 352 | num_ps_gprs = 192; |
| 353 | num_vs_gprs = 56; |
| 354 | num_temp_gprs = 4; |
| 355 | num_gs_gprs = 0; |
| 356 | num_es_gprs = 0; |
| 357 | num_ps_threads = 144; |
| 358 | num_vs_threads = 48; |
| 359 | num_gs_threads = 0; |
| 360 | num_es_threads = 0; |
| 361 | num_ps_stack_entries = 128; |
| 362 | num_vs_stack_entries = 128; |
| 363 | num_gs_stack_entries = 0; |
| 364 | num_es_stack_entries = 0; |
| 365 | break; |
| 366 | } |
| 367 | |
| 368 | if ((rdev->family == CHIP_RV610) || |
| 369 | (rdev->family == CHIP_RV620) || |
| 370 | (rdev->family == CHIP_RS780) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 371 | (rdev->family == CHIP_RS880) || |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 372 | (rdev->family == CHIP_RV710)) |
| 373 | sq_config = 0; |
| 374 | else |
| 375 | sq_config = VC_ENABLE; |
| 376 | |
| 377 | sq_config |= (DX9_CONSTS | |
| 378 | ALU_INST_PREFER_VECTOR | |
| 379 | PS_PRIO(0) | |
| 380 | VS_PRIO(1) | |
| 381 | GS_PRIO(2) | |
| 382 | ES_PRIO(3)); |
| 383 | |
| 384 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
| 385 | NUM_VS_GPRS(num_vs_gprs) | |
| 386 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
| 387 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
| 388 | NUM_ES_GPRS(num_es_gprs)); |
| 389 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
| 390 | NUM_VS_THREADS(num_vs_threads) | |
| 391 | NUM_GS_THREADS(num_gs_threads) | |
| 392 | NUM_ES_THREADS(num_es_threads)); |
| 393 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
| 394 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
| 395 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
| 396 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
| 397 | |
| 398 | /* emit an IB pointing at default state */ |
Matt Turner | d964fc5 | 2010-02-25 04:23:31 +0000 | [diff] [blame^] | 399 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 400 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
| 401 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| 402 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
| 403 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 404 | radeon_ring_write(rdev, dwords); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 405 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 406 | /* SQ config */ |
| 407 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
| 408 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 409 | radeon_ring_write(rdev, sq_config); |
| 410 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
| 411 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
| 412 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
| 413 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
| 414 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
| 415 | } |
| 416 | |
| 417 | static inline uint32_t i2f(uint32_t input) |
| 418 | { |
| 419 | u32 result, i, exponent, fraction; |
| 420 | |
| 421 | if ((input & 0x3fff) == 0) |
| 422 | result = 0; /* 0 is a special case */ |
| 423 | else { |
| 424 | exponent = 140; /* exponent biased by 127; */ |
| 425 | fraction = (input & 0x3fff) << 10; /* cheat and only |
| 426 | handle numbers below 2^^15 */ |
| 427 | for (i = 0; i < 14; i++) { |
| 428 | if (fraction & 0x800000) |
| 429 | break; |
| 430 | else { |
| 431 | fraction = fraction << 1; /* keep |
| 432 | shifting left until top bit = 1 */ |
| 433 | exponent = exponent - 1; |
| 434 | } |
| 435 | } |
| 436 | result = exponent << 23 | (fraction & 0x7fffff); /* mask |
| 437 | off top bit; assumed 1 */ |
| 438 | } |
| 439 | return result; |
| 440 | } |
| 441 | |
| 442 | int r600_blit_init(struct radeon_device *rdev) |
| 443 | { |
| 444 | u32 obj_size; |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 445 | int r, dwords; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 446 | void *ptr; |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 447 | u32 packet2s[16]; |
| 448 | int num_packet2s = 0; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 449 | |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 450 | mutex_init(&rdev->r600_blit.mutex); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 451 | rdev->r600_blit.state_offset = 0; |
| 452 | |
| 453 | if (rdev->family >= CHIP_RV770) |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 454 | rdev->r600_blit.state_len = r7xx_default_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 455 | else |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 456 | rdev->r600_blit.state_len = r6xx_default_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 457 | |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 458 | dwords = rdev->r600_blit.state_len; |
| 459 | while (dwords & 0xf) { |
| 460 | packet2s[num_packet2s++] = PACKET2(0); |
| 461 | dwords++; |
| 462 | } |
| 463 | |
| 464 | obj_size = dwords * 4; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 465 | obj_size = ALIGN(obj_size, 256); |
| 466 | |
| 467 | rdev->r600_blit.vs_offset = obj_size; |
| 468 | obj_size += r6xx_vs_size * 4; |
| 469 | obj_size = ALIGN(obj_size, 256); |
| 470 | |
| 471 | rdev->r600_blit.ps_offset = obj_size; |
| 472 | obj_size += r6xx_ps_size * 4; |
| 473 | obj_size = ALIGN(obj_size, 256); |
| 474 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 475 | r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM, |
| 476 | &rdev->r600_blit.shader_obj); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 477 | if (r) { |
| 478 | DRM_ERROR("r600 failed to allocate shader\n"); |
| 479 | return r; |
| 480 | } |
| 481 | |
Dave Airlie | bc1a631 | 2009-09-15 11:07:52 +1000 | [diff] [blame] | 482 | DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", |
| 483 | obj_size, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 484 | rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
| 485 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 486 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 487 | if (unlikely(r != 0)) |
| 488 | return r; |
| 489 | r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 490 | if (r) { |
| 491 | DRM_ERROR("failed to map blit object %d\n", r); |
| 492 | return r; |
| 493 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 494 | if (rdev->family >= CHIP_RV770) |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 495 | memcpy_toio(ptr + rdev->r600_blit.state_offset, |
| 496 | r7xx_default_state, rdev->r600_blit.state_len * 4); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 497 | else |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 498 | memcpy_toio(ptr + rdev->r600_blit.state_offset, |
| 499 | r6xx_default_state, rdev->r600_blit.state_len * 4); |
| 500 | if (num_packet2s) |
| 501 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| 502 | packet2s, num_packet2s * 4); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 503 | memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4); |
| 504 | memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 505 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
| 506 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | void r600_blit_fini(struct radeon_device *rdev) |
| 511 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 512 | int r; |
| 513 | |
Jerome Glisse | 30d2d9a | 2010-01-13 10:29:27 +0100 | [diff] [blame] | 514 | if (rdev->r600_blit.shader_obj == NULL) |
| 515 | return; |
| 516 | /* If we can't reserve the bo, unref should be enough to destroy |
| 517 | * it when it becomes idle. |
| 518 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 519 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
Jerome Glisse | 30d2d9a | 2010-01-13 10:29:27 +0100 | [diff] [blame] | 520 | if (!r) { |
| 521 | radeon_bo_unpin(rdev->r600_blit.shader_obj); |
| 522 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 523 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 524 | radeon_bo_unref(&rdev->r600_blit.shader_obj); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 525 | } |
| 526 | |
| 527 | int r600_vb_ib_get(struct radeon_device *rdev) |
| 528 | { |
| 529 | int r; |
| 530 | r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); |
| 531 | if (r) { |
| 532 | DRM_ERROR("failed to get IB for vertex buffer\n"); |
| 533 | return r; |
| 534 | } |
| 535 | |
| 536 | rdev->r600_blit.vb_total = 64*1024; |
| 537 | rdev->r600_blit.vb_used = 0; |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | void r600_vb_ib_put(struct radeon_device *rdev) |
| 542 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 543 | radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 544 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| 545 | } |
| 546 | |
| 547 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) |
| 548 | { |
| 549 | int r; |
Dave Airlie | 7cbb355 | 2009-09-17 16:11:31 +1000 | [diff] [blame] | 550 | int ring_size, line_size; |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 551 | int max_size; |
Alex Deucher | 1be3405 | 2009-09-11 12:02:03 -0400 | [diff] [blame] | 552 | /* loops of emits 64 + fence emit possible */ |
Dave Airlie | 7cbb355 | 2009-09-17 16:11:31 +1000 | [diff] [blame] | 553 | int dwords_per_loop = 76, num_loops; |
| 554 | |
| 555 | r = r600_vb_ib_get(rdev); |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 556 | if (r) |
| 557 | return r; |
Alex Deucher | 1be3405 | 2009-09-11 12:02:03 -0400 | [diff] [blame] | 558 | |
| 559 | /* set_render_target emits 2 extra dwords on rv6xx */ |
| 560 | if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) |
| 561 | dwords_per_loop += 2; |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 562 | |
| 563 | /* 8 bpp vs 32 bpp for xfer unit */ |
| 564 | if (size_bytes & 3) |
Dave Airlie | 7cbb355 | 2009-09-17 16:11:31 +1000 | [diff] [blame] | 565 | line_size = 8192; |
Alex Deucher | 119e20d | 2009-09-10 02:53:50 -0400 | [diff] [blame] | 566 | else |
Dave Airlie | 7cbb355 | 2009-09-17 16:11:31 +1000 | [diff] [blame] | 567 | line_size = 8192*4; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 568 | |
Dave Airlie | 7cbb355 | 2009-09-17 16:11:31 +1000 | [diff] [blame] | 569 | max_size = 8192 * line_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 570 | |
Dave Airlie | 7cbb355 | 2009-09-17 16:11:31 +1000 | [diff] [blame] | 571 | /* major loops cover the max size transfer */ |
| 572 | num_loops = ((size_bytes + max_size) / max_size); |
| 573 | /* minor loops cover the extra non aligned bits */ |
| 574 | num_loops += ((size_bytes % line_size) ? 1 : 0); |
| 575 | /* calculate number of loops correctly */ |
| 576 | ring_size = num_loops * dwords_per_loop; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 577 | /* set default + shaders */ |
| 578 | ring_size += 40; /* shaders + def state */ |
Alex Deucher | 6ad86c3 | 2010-02-11 10:47:52 -0500 | [diff] [blame] | 579 | ring_size += 10; /* fence emit for VB IB */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 580 | ring_size += 5; /* done copy */ |
Alex Deucher | 6ad86c3 | 2010-02-11 10:47:52 -0500 | [diff] [blame] | 581 | ring_size += 10; /* fence emit for done copy */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 582 | r = radeon_ring_lock(rdev, ring_size); |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 583 | if (r) |
| 584 | return r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 585 | |
| 586 | set_default_state(rdev); /* 14 */ |
| 587 | set_shaders(rdev); /* 26 */ |
| 588 | return 0; |
| 589 | } |
| 590 | |
| 591 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) |
| 592 | { |
| 593 | int r; |
| 594 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 595 | if (rdev->r600_blit.vb_ib) |
| 596 | r600_vb_ib_put(rdev); |
| 597 | |
| 598 | if (fence) |
| 599 | r = radeon_fence_emit(rdev, fence); |
| 600 | |
| 601 | radeon_ring_unlock_commit(rdev); |
| 602 | } |
| 603 | |
| 604 | void r600_kms_blit_copy(struct radeon_device *rdev, |
| 605 | u64 src_gpu_addr, u64 dst_gpu_addr, |
| 606 | int size_bytes) |
| 607 | { |
| 608 | int max_bytes; |
| 609 | u64 vb_gpu_addr; |
| 610 | u32 *vb; |
| 611 | |
| 612 | DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, |
| 613 | size_bytes, rdev->r600_blit.vb_used); |
Dave Airlie | ceeb502 | 2009-10-12 13:54:10 +1000 | [diff] [blame] | 614 | vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 615 | if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { |
| 616 | max_bytes = 8192; |
| 617 | |
| 618 | while (size_bytes) { |
| 619 | int cur_size = size_bytes; |
| 620 | int src_x = src_gpu_addr & 255; |
| 621 | int dst_x = dst_gpu_addr & 255; |
| 622 | int h = 1; |
| 623 | src_gpu_addr = src_gpu_addr & ~255; |
| 624 | dst_gpu_addr = dst_gpu_addr & ~255; |
| 625 | |
| 626 | if (!src_x && !dst_x) { |
| 627 | h = (cur_size / max_bytes); |
| 628 | if (h > 8192) |
| 629 | h = 8192; |
| 630 | if (h == 0) |
| 631 | h = 1; |
| 632 | else |
| 633 | cur_size = max_bytes; |
| 634 | } else { |
| 635 | if (cur_size > max_bytes) |
| 636 | cur_size = max_bytes; |
| 637 | if (cur_size > (max_bytes - dst_x)) |
| 638 | cur_size = (max_bytes - dst_x); |
| 639 | if (cur_size > (max_bytes - src_x)) |
| 640 | cur_size = (max_bytes - src_x); |
| 641 | } |
| 642 | |
| 643 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| 644 | WARN_ON(1); |
| 645 | |
| 646 | #if 0 |
| 647 | r600_vb_ib_put(rdev); |
| 648 | |
| 649 | r600_nomm_put_vb(dev); |
| 650 | r600_nomm_get_vb(dev); |
| 651 | if (!dev_priv->blit_vb) |
| 652 | return; |
| 653 | set_shaders(dev); |
| 654 | vb = r600_nomm_get_vb_ptr(dev); |
| 655 | #endif |
| 656 | } |
| 657 | |
| 658 | vb[0] = i2f(dst_x); |
| 659 | vb[1] = 0; |
| 660 | vb[2] = i2f(src_x); |
| 661 | vb[3] = 0; |
| 662 | |
| 663 | vb[4] = i2f(dst_x); |
| 664 | vb[5] = i2f(h); |
| 665 | vb[6] = i2f(src_x); |
| 666 | vb[7] = i2f(h); |
| 667 | |
| 668 | vb[8] = i2f(dst_x + cur_size); |
| 669 | vb[9] = i2f(h); |
| 670 | vb[10] = i2f(src_x + cur_size); |
| 671 | vb[11] = i2f(h); |
| 672 | |
| 673 | /* src 9 */ |
| 674 | set_tex_resource(rdev, FMT_8, |
| 675 | src_x + cur_size, h, src_x + cur_size, |
| 676 | src_gpu_addr); |
| 677 | |
| 678 | /* 5 */ |
| 679 | cp_set_surface_sync(rdev, |
| 680 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| 681 | |
| 682 | /* dst 23 */ |
| 683 | set_render_target(rdev, COLOR_8, |
| 684 | dst_x + cur_size, h, |
| 685 | dst_gpu_addr); |
| 686 | |
| 687 | /* scissors 12 */ |
| 688 | set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); |
| 689 | |
| 690 | /* 14 */ |
| 691 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| 692 | set_vtx_resource(rdev, vb_gpu_addr); |
| 693 | |
| 694 | /* draw 10 */ |
| 695 | draw_auto(rdev); |
| 696 | |
| 697 | /* 5 */ |
| 698 | cp_set_surface_sync(rdev, |
| 699 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| 700 | cur_size * h, dst_gpu_addr); |
| 701 | |
| 702 | vb += 12; |
| 703 | rdev->r600_blit.vb_used += 12 * 4; |
| 704 | |
| 705 | src_gpu_addr += cur_size * h; |
| 706 | dst_gpu_addr += cur_size * h; |
| 707 | size_bytes -= cur_size * h; |
| 708 | } |
| 709 | } else { |
| 710 | max_bytes = 8192 * 4; |
| 711 | |
| 712 | while (size_bytes) { |
| 713 | int cur_size = size_bytes; |
| 714 | int src_x = (src_gpu_addr & 255); |
| 715 | int dst_x = (dst_gpu_addr & 255); |
| 716 | int h = 1; |
| 717 | src_gpu_addr = src_gpu_addr & ~255; |
| 718 | dst_gpu_addr = dst_gpu_addr & ~255; |
| 719 | |
| 720 | if (!src_x && !dst_x) { |
| 721 | h = (cur_size / max_bytes); |
| 722 | if (h > 8192) |
| 723 | h = 8192; |
| 724 | if (h == 0) |
| 725 | h = 1; |
| 726 | else |
| 727 | cur_size = max_bytes; |
| 728 | } else { |
| 729 | if (cur_size > max_bytes) |
| 730 | cur_size = max_bytes; |
| 731 | if (cur_size > (max_bytes - dst_x)) |
| 732 | cur_size = (max_bytes - dst_x); |
| 733 | if (cur_size > (max_bytes - src_x)) |
| 734 | cur_size = (max_bytes - src_x); |
| 735 | } |
| 736 | |
| 737 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| 738 | WARN_ON(1); |
| 739 | } |
| 740 | #if 0 |
| 741 | if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) { |
| 742 | r600_nomm_put_vb(dev); |
| 743 | r600_nomm_get_vb(dev); |
| 744 | if (!rdev->blit_vb) |
| 745 | return; |
| 746 | |
| 747 | set_shaders(dev); |
| 748 | vb = r600_nomm_get_vb_ptr(dev); |
| 749 | } |
| 750 | #endif |
| 751 | |
| 752 | vb[0] = i2f(dst_x / 4); |
| 753 | vb[1] = 0; |
| 754 | vb[2] = i2f(src_x / 4); |
| 755 | vb[3] = 0; |
| 756 | |
| 757 | vb[4] = i2f(dst_x / 4); |
| 758 | vb[5] = i2f(h); |
| 759 | vb[6] = i2f(src_x / 4); |
| 760 | vb[7] = i2f(h); |
| 761 | |
| 762 | vb[8] = i2f((dst_x + cur_size) / 4); |
| 763 | vb[9] = i2f(h); |
| 764 | vb[10] = i2f((src_x + cur_size) / 4); |
| 765 | vb[11] = i2f(h); |
| 766 | |
| 767 | /* src 9 */ |
| 768 | set_tex_resource(rdev, FMT_8_8_8_8, |
| 769 | (src_x + cur_size) / 4, |
| 770 | h, (src_x + cur_size) / 4, |
| 771 | src_gpu_addr); |
| 772 | /* 5 */ |
| 773 | cp_set_surface_sync(rdev, |
| 774 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| 775 | |
| 776 | /* dst 23 */ |
| 777 | set_render_target(rdev, COLOR_8_8_8_8, |
Andre Maasikas | 5b31aee | 2009-09-21 08:59:41 -0400 | [diff] [blame] | 778 | (dst_x + cur_size) / 4, h, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 779 | dst_gpu_addr); |
| 780 | |
| 781 | /* scissors 12 */ |
| 782 | set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); |
| 783 | |
| 784 | /* Vertex buffer setup 14 */ |
| 785 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| 786 | set_vtx_resource(rdev, vb_gpu_addr); |
| 787 | |
| 788 | /* draw 10 */ |
| 789 | draw_auto(rdev); |
| 790 | |
| 791 | /* 5 */ |
| 792 | cp_set_surface_sync(rdev, |
| 793 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| 794 | cur_size * h, dst_gpu_addr); |
| 795 | |
| 796 | /* 78 ring dwords per loop */ |
| 797 | vb += 12; |
| 798 | rdev->r600_blit.vb_used += 12 * 4; |
| 799 | |
| 800 | src_gpu_addr += cur_size * h; |
| 801 | dst_gpu_addr += cur_size * h; |
| 802 | size_bytes -= cur_size * h; |
| 803 | } |
| 804 | } |
| 805 | } |
| 806 | |