| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | menu "DMA support" |
| 2 | |
| Manuel Lauss | fc467a26 | 2007-05-09 17:36:15 +0900 | [diff] [blame] | 3 | config SH_DMA_API |
| 4 | bool |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | |
| Manuel Lauss | fc467a26 | 2007-05-09 17:36:15 +0900 | [diff] [blame] | 6 | config SH_DMA |
| 7 | bool "SuperH on-chip DMA controller (DMAC) support" |
| Paul Mundt | 3e76783 | 2007-07-20 14:23:04 +0900 | [diff] [blame] | 8 | depends on CPU_SH3 || CPU_SH4 |
| Manuel Lauss | fc467a26 | 2007-05-09 17:36:15 +0900 | [diff] [blame] | 9 | select SH_DMA_API |
| 10 | default n |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | |
| Nobuhiro Iwamatsu | 988f831 | 2009-03-16 03:22:07 +0000 | [diff] [blame] | 12 | config SH_DMA_IRQ_MULTI |
| 13 | bool |
| 14 | depends on SH_DMA |
| 15 | default y if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ |
| 16 | CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ |
| 17 | CPU_SUBTYPE_SH7091 || CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \ |
| 18 | CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 |
| 19 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | config NR_ONCHIP_DMA_CHANNELS |
| Paul Mundt | fc10020 | 2007-07-20 14:24:57 +0900 | [diff] [blame] | 21 | int |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | depends on SH_DMA |
| Nobuhiro Iwamatsu | 71b973a | 2009-03-10 17:26:49 +0900 | [diff] [blame] | 23 | default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S |
| 24 | default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7760 |
| 25 | default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 |
| 26 | default "6" |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | help |
| 28 | This allows you to specify the number of channels that the on-chip |
| 29 | DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the |
| 30 | SH7750R/SH7751R. |
| 31 | |
| 32 | config NR_DMA_CHANNELS_BOOL |
| 33 | depends on SH_DMA |
| 34 | bool "Override default number of maximum DMA channels" |
| 35 | help |
| 36 | This allows you to forcibly update the maximum number of supported |
| 37 | DMA channels for a given board. If this is unset, this will default |
| 38 | to the number of channels that the on-chip DMAC has. |
| 39 | |
| 40 | config NR_DMA_CHANNELS |
| 41 | int "Maximum number of DMA channels" |
| 42 | depends on SH_DMA && NR_DMA_CHANNELS_BOOL |
| 43 | default NR_ONCHIP_DMA_CHANNELS |
| 44 | help |
| 45 | This allows you to specify the maximum number of DMA channels to |
| 46 | support. Setting this to a higher value allows for cascading DMACs |
| 47 | with additional channels. |
| 48 | |
| Manuel Lauss | fc467a26 | 2007-05-09 17:36:15 +0900 | [diff] [blame] | 49 | config SH_DMABRG |
| 50 | bool "SH7760 DMABRG support" |
| 51 | depends on CPU_SUBTYPE_SH7760 |
| 52 | help |
| 53 | The DMABRG does data transfers from main memory to Audio/USB units |
| 54 | of the SH7760. |
| 55 | Say Y if you want to use Audio/USB DMA on your SH7760 board. |
| 56 | |
| Paul Mundt | da62e71 | 2009-03-17 09:30:36 +0900 | [diff] [blame^] | 57 | config PVR2_DMA |
| 58 | tristate "PowerVR 2 DMAC support" |
| 59 | depends on SH_DREAMCAST && SH_DMA |
| 60 | help |
| 61 | Selecting this will enable support for the PVR2 DMA controller. |
| 62 | As this chains off of the on-chip DMAC, that must also be |
| 63 | enabled by default. |
| 64 | |
| 65 | This is primarily used by the pvr2fb framebuffer driver for |
| 66 | certain optimizations, but is not necessary for functionality. |
| 67 | |
| 68 | If in doubt, say N. |
| 69 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | endmenu |