blob: d1513b4a457c208fa65033ff1806799896f46bd9 [file] [log] [blame]
Anton Salnikov7c7e92a2008-02-06 02:57:48 +01001/*
2 * Palmchip bk3710 IDE controller
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * ----------------------------------------------------------------------------
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 * ----------------------------------------------------------------------------
23 *
24 */
25
26#include <linux/types.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/ioport.h>
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010030#include <linux/ide.h>
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/clk.h>
34#include <linux/platform_device.h>
35
36/* Offset of the primary interface registers */
37#define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
38
39/* Primary Control Offset */
40#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
41
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010042#define BK3710_BMICP 0x00
43#define BK3710_BMISP 0x02
44#define BK3710_BMIDTP 0x04
45#define BK3710_BMICS 0x08
46#define BK3710_BMISS 0x0A
47#define BK3710_BMIDTS 0x0C
48#define BK3710_IDETIMP 0x40
49#define BK3710_IDETIMS 0x42
50#define BK3710_SIDETIM 0x44
51#define BK3710_SLEWCTL 0x45
52#define BK3710_IDESTATUS 0x47
53#define BK3710_UDMACTL 0x48
54#define BK3710_UDMATIM 0x4A
55#define BK3710_MISCCTL 0x50
56#define BK3710_REGSTB 0x54
57#define BK3710_REGRCVR 0x58
58#define BK3710_DATSTB 0x5C
59#define BK3710_DATRCVR 0x60
60#define BK3710_DMASTB 0x64
61#define BK3710_DMARCVR 0x68
62#define BK3710_UDMASTB 0x6C
63#define BK3710_UDMATRP 0x70
64#define BK3710_UDMAENV 0x74
65#define BK3710_IORDYTMP 0x78
66#define BK3710_IORDYTMS 0x7C
67
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +020068static unsigned ideclk_period; /* in nanoseconds */
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010069
David Brownelldb2f38c2009-04-22 20:33:40 +020070struct palm_bk3710_udmatiming {
71 unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
72 unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
73 /* tENV is always a minimum of 20 nsec */
74};
75
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010076static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
David Brownelldb2f38c2009-04-22 20:33:40 +020077 {160, 240 / 2,}, /* UDMA Mode 0 */
78 {125, 160 / 2,}, /* UDMA Mode 1 */
79 {100, 120 / 2,}, /* UDMA Mode 2 */
80 {100, 90 / 2,}, /* UDMA Mode 3 */
81 {100, 60 / 2,}, /* UDMA Mode 4 */
82 {85, 40 / 2,}, /* UDMA Mode 5 */
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010083};
84
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010085static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
86 unsigned int mode)
87{
88 u8 tenv, trp, t0;
89 u32 val32;
90 u16 val16;
91
92 /* DMA Data Setup */
Julia Lawall00fe8b72008-04-26 17:36:35 +020093 t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +020094 ideclk_period) - 1;
95 tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
Julia Lawall00fe8b72008-04-26 17:36:35 +020096 trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +020097 ideclk_period) - 1;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010098
99 /* udmatim Register */
100 val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0);
101 val16 |= (mode << (dev ? 4 : 0));
102 writew(val16, base + BK3710_UDMATIM);
103
104 /* udmastb Ultra DMA Access Strobe Width */
105 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
106 val32 |= (t0 << (dev ? 8 : 0));
107 writel(val32, base + BK3710_UDMASTB);
108
109 /* udmatrp Ultra DMA Ready to Pause Time */
110 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
111 val32 |= (trp << (dev ? 8 : 0));
112 writel(val32, base + BK3710_UDMATRP);
113
114 /* udmaenv Ultra DMA envelop Time */
115 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
116 val32 |= (tenv << (dev ? 8 : 0));
117 writel(val32, base + BK3710_UDMAENV);
118
119 /* Enable UDMA for Device */
120 val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
121 writew(val16, base + BK3710_UDMACTL);
122}
123
124static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
125 unsigned short min_cycle,
126 unsigned int mode)
127{
128 u8 td, tkw, t0;
129 u32 val32;
130 u16 val16;
131 struct ide_timing *t;
132 int cycletime;
133
134 t = ide_timing_find_mode(mode);
135 cycletime = max_t(int, t->cycle, min_cycle);
136
137 /* DMA Data Setup */
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200138 t0 = DIV_ROUND_UP(cycletime, ideclk_period);
139 td = DIV_ROUND_UP(t->active, ideclk_period);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100140 tkw = t0 - td - 1;
141 td -= 1;
142
143 val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
144 val32 |= (td << (dev ? 8 : 0));
145 writel(val32, base + BK3710_DMASTB);
146
147 val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
148 val32 |= (tkw << (dev ? 8 : 0));
149 writel(val32, base + BK3710_DMARCVR);
150
151 /* Disable UDMA for Device */
152 val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
153 writew(val16, base + BK3710_UDMACTL);
154}
155
156static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
157 unsigned int dev, unsigned int cycletime,
158 unsigned int mode)
159{
160 u8 t2, t2i, t0;
161 u32 val32;
162 struct ide_timing *t;
163
164 /* PIO Data Setup */
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200165 t0 = DIV_ROUND_UP(cycletime, ideclk_period);
Julia Lawall00fe8b72008-04-26 17:36:35 +0200166 t2 = DIV_ROUND_UP(ide_timing_find_mode(XFER_PIO_0 + mode)->active,
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200167 ideclk_period);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100168
169 t2i = t0 - t2 - 1;
170 t2 -= 1;
171
172 val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
173 val32 |= (t2 << (dev ? 8 : 0));
174 writel(val32, base + BK3710_DATSTB);
175
176 val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
177 val32 |= (t2i << (dev ? 8 : 0));
178 writel(val32, base + BK3710_DATRCVR);
179
Bartlomiej Zolnierkiewicz7e59ea22008-10-10 22:39:26 +0200180 if (mate) {
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100181 u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
182
183 if (mode2 < mode)
184 mode = mode2;
185 }
186
187 /* TASKFILE Setup */
188 t = ide_timing_find_mode(XFER_PIO_0 + mode);
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200189 t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
190 t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100191
192 t2i = t0 - t2 - 1;
193 t2 -= 1;
194
195 val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
196 val32 |= (t2 << (dev ? 8 : 0));
197 writel(val32, base + BK3710_REGSTB);
198
199 val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
200 val32 |= (t2i << (dev ? 8 : 0));
201 writel(val32, base + BK3710_REGRCVR);
202}
203
204static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
205{
206 int is_slave = drive->dn & 1;
207 void __iomem *base = (void *)drive->hwif->dma_base;
208
209 if (xferspeed >= XFER_UDMA_0) {
210 palm_bk3710_setudmamode(base, is_slave,
211 xferspeed - XFER_UDMA_0);
212 } else {
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200213 palm_bk3710_setdmamode(base, is_slave,
214 drive->id[ATA_ID_EIDE_DMA_MIN],
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100215 xferspeed);
216 }
217}
218
219static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
220{
221 unsigned int cycle_time;
222 int is_slave = drive->dn & 1;
223 ide_drive_t *mate;
224 void __iomem *base = (void *)drive->hwif->dma_base;
225
226 /*
227 * Obtain the drive PIO data for tuning the Palm Chip registers
228 */
229 cycle_time = ide_pio_cycle_time(drive, pio);
Bartlomiej Zolnierkiewicz7e59ea22008-10-10 22:39:26 +0200230 mate = ide_get_pair_dev(drive);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100231 palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
232}
233
234static void __devinit palm_bk3710_chipinit(void __iomem *base)
235{
236 /*
237 * enable the reset_en of ATA controller so that when ata signals
238 * are brought out, by writing into device config. at that
239 * time por_n signal should not be 'Z' and have a stable value.
240 */
241 writel(0x0300, base + BK3710_MISCCTL);
242
243 /* wait for some time and deassert the reset of ATA Device. */
244 mdelay(100);
245
246 /* Deassert the Reset */
247 writel(0x0200, base + BK3710_MISCCTL);
248
249 /*
250 * Program the IDETIMP Register Value based on the following assumptions
251 *
252 * (ATA_IDETIMP_IDEEN , ENABLE ) |
253 * (ATA_IDETIMP_SLVTIMEN , DISABLE) |
254 * (ATA_IDETIMP_RDYSMPL , 70NS) |
255 * (ATA_IDETIMP_RDYRCVRY , 50NS) |
256 * (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) |
257 * (ATA_IDETIMP_PREPOST1 , DISABLE) |
258 * (ATA_IDETIMP_RDYSEN1 , DISABLE) |
259 * (ATA_IDETIMP_PIOFTIM1 , DISABLE) |
260 * (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) |
261 * (ATA_IDETIMP_PREPOST0 , DISABLE) |
262 * (ATA_IDETIMP_RDYSEN0 , DISABLE) |
263 * (ATA_IDETIMP_PIOFTIM0 , DISABLE)
264 */
265 writew(0xB388, base + BK3710_IDETIMP);
266
267 /*
268 * Configure SIDETIM Register
269 * (ATA_SIDETIM_RDYSMPS1 ,120NS ) |
270 * (ATA_SIDETIM_RDYRCYS1 ,120NS )
271 */
272 writeb(0, base + BK3710_SIDETIM);
273
274 /*
275 * UDMACTL Ultra-ATA DMA Control
276 * (ATA_UDMACTL_UDMAP1 , 0 ) |
277 * (ATA_UDMACTL_UDMAP0 , 0 )
278 *
279 */
280 writew(0, base + BK3710_UDMACTL);
281
282 /*
283 * MISCCTL Miscellaneous Conrol Register
284 * (ATA_MISCCTL_RSTMODEP , 1) |
285 * (ATA_MISCCTL_RESETP , 0) |
286 * (ATA_MISCCTL_TIMORIDE , 1)
287 */
288 writel(0x201, base + BK3710_MISCCTL);
289
290 /*
291 * IORDYTMP IORDY Timer for Primary Register
292 * (ATA_IORDYTMP_IORDYTMP , 0xffff )
293 */
294 writel(0xFFFF, base + BK3710_IORDYTMP);
295
296 /*
297 * Configure BMISP Register
298 * (ATA_BMISP_DMAEN1 , DISABLE ) |
299 * (ATA_BMISP_DMAEN0 , DISABLE ) |
300 * (ATA_BMISP_IORDYINT , CLEAR) |
301 * (ATA_BMISP_INTRSTAT , CLEAR) |
302 * (ATA_BMISP_DMAERROR , CLEAR)
303 */
304 writew(0, base + BK3710_BMISP);
305
306 palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
307 palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
308}
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100309
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +0200310static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100311{
312 return ATA_CBL_PATA80;
313}
314
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200315static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
316 const struct ide_port_info *d)
317{
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200318 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
319
320 if (ide_allocate_dma_engine(hwif))
321 return -1;
322
Bartlomiej Zolnierkiewicz81e8d5a2008-07-23 19:55:51 +0200323 hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
324
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200325 return 0;
326}
327
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200328static const struct ide_port_ops palm_bk3710_ports_ops = {
329 .set_pio_mode = palm_bk3710_set_pio_mode,
330 .set_dma_mode = palm_bk3710_set_dma_mode,
331 .cable_detect = palm_bk3710_cable_detect,
332};
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100333
Sergei Shtylyova0f403b2008-07-24 22:53:34 +0200334static struct ide_port_info __devinitdata palm_bk3710_port_info = {
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200335 .init_dma = palm_bk3710_init_dma,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200336 .port_ops = &palm_bk3710_ports_ops,
Sergei Shtylyov3f023b02009-01-06 17:21:01 +0100337 .dma_ops = &sff_dma_ops,
Bartlomiej Zolnierkiewiczc5dd43e2008-04-28 23:44:37 +0200338 .host_flags = IDE_HFLAG_MMIO,
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100339 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100340 .mwdma_mask = ATA_MWDMA2,
341};
342
David Brownellbfc2f012008-09-02 20:18:47 +0200343static int __init palm_bk3710_probe(struct platform_device *pdev)
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100344{
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200345 struct clk *clk;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100346 struct resource *mem, *irq;
David Brownellef183f62009-01-19 13:46:57 +0100347 void __iomem *base;
Kevin Hilman13b88602009-01-30 11:59:27 -0800348 unsigned long rate, mem_size;
Bartlomiej Zolnierkiewicz6f904d02008-07-23 19:55:57 +0200349 int i, rc;
Bartlomiej Zolnierkiewiczc97c6ac2008-07-23 19:55:50 +0200350 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100351
Sergei Shtylyova0f403b2008-07-24 22:53:34 +0200352 clk = clk_get(&pdev->dev, "IDECLK");
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200353 if (IS_ERR(clk))
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100354 return -ENODEV;
355
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200356 clk_enable(clk);
357 rate = clk_get_rate(clk);
358 ideclk_period = 1000000000UL / rate;
359
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100360 /* Register the IDE interface with Linux ATA Interface */
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100361 memset(&hw, 0, sizeof(hw));
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100362
363 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
364 if (mem == NULL) {
365 printk(KERN_ERR "failed to get memory region resource\n");
366 return -ENODEV;
367 }
Sergei Shtylyovce42a542008-06-20 20:53:32 +0200368
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100369 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
370 if (irq == NULL) {
371 printk(KERN_ERR "failed to get IRQ resource\n");
372 return -ENODEV;
373 }
374
Kevin Hilman13b88602009-01-30 11:59:27 -0800375 mem_size = mem->end - mem->start + 1;
376 if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) {
Sergei Shtylyovce42a542008-06-20 20:53:32 +0200377 printk(KERN_ERR "failed to request memory region\n");
378 return -EBUSY;
379 }
380
Kevin Hilman13b88602009-01-30 11:59:27 -0800381 base = ioremap(mem->start, mem_size);
382 if (!base) {
383 printk(KERN_ERR "failed to map IO memory\n");
384 release_mem_region(mem->start, mem_size);
385 return -ENOMEM;
386 }
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100387
388 /* Configure the Palm Chip controller */
David Brownellef183f62009-01-19 13:46:57 +0100389 palm_bk3710_chipinit(base);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100390
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100391 for (i = 0; i < IDE_NR_PORTS - 2; i++)
David Brownellef183f62009-01-19 13:46:57 +0100392 hw.io_ports_array[i] = (unsigned long)
393 (base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
394 hw.io_ports.ctl_addr = (unsigned long)
395 (base + IDE_PALM_ATA_PRI_CTL_OFFSET);
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100396 hw.irq = irq->start;
David Brownellbfc2f012008-09-02 20:18:47 +0200397 hw.dev = &pdev->dev;
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100398 hw.chipset = ide_palm3710;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100399
Sergei Shtylyova0f403b2008-07-24 22:53:34 +0200400 palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
401 ATA_UDMA5;
402
Bartlomiej Zolnierkiewicz6f904d02008-07-23 19:55:57 +0200403 rc = ide_host_add(&palm_bk3710_port_info, hws, NULL);
404 if (rc)
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100405 goto out;
406
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100407 return 0;
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100408out:
409 printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
Bartlomiej Zolnierkiewicz6f904d02008-07-23 19:55:57 +0200410 return rc;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100411}
412
Kay Sievers458622f2008-04-18 13:41:57 -0700413/* work with hotplug and coldplug */
414MODULE_ALIAS("platform:palm_bk3710");
415
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100416static struct platform_driver platform_bk_driver = {
417 .driver = {
418 .name = "palm_bk3710",
Kay Sievers458622f2008-04-18 13:41:57 -0700419 .owner = THIS_MODULE,
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100420 },
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100421};
422
423static int __init palm_bk3710_init(void)
424{
David Brownellbfc2f012008-09-02 20:18:47 +0200425 return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100426}
427
428module_init(palm_bk3710_init);
429MODULE_LICENSE("GPL");