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gerrit-public.fairphone.software / kernel / msm-4.9 / dbff2dee9f8561710fcfe7f6623dd272ddca5a27 / . / drivers / gpu / drm / nouveau / nouveau_pm.h
blob: e2ec9c0ed567432d6ded408d6385bce2a53fcbf0 [file] [log] [blame]
Ben Skeggs330c5982010-09-16 15:39:49 +1000[diff] [blame]1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifndef __NOUVEAU_PM_H__
26#define __NOUVEAU_PM_H__
27
Ben Skeggs77145f12012-07-31 16:16:21 +1000[diff] [blame]28#include <subdev/bios/pll.h>
29#include <subdev/clock.h>
30
31struct nouveau_pm_voltage_level {
32 u32 voltage; /* microvolts */
33 u8 vid;
34};
35
36struct nouveau_pm_voltage {
37 bool supported;
38 u8 version;
39 u8 vid_mask;
40
41 struct nouveau_pm_voltage_level *level;
42 int nr_level;
43};
44
45/* Exclusive upper limits */
46#define NV_MEM_CL_DDR2_MAX 8
47#define NV_MEM_WR_DDR2_MAX 9
48#define NV_MEM_CL_DDR3_MAX 17
49#define NV_MEM_WR_DDR3_MAX 17
50#define NV_MEM_CL_GDDR3_MAX 16
51#define NV_MEM_WR_GDDR3_MAX 18
52#define NV_MEM_CL_GDDR5_MAX 21
53#define NV_MEM_WR_GDDR5_MAX 20
54
55struct nouveau_pm_memtiming {
56 int id;
57
58 u32 reg[9];
59 u32 mr[4];
60
61 u8 tCWL;
62
63 u8 odt;
64 u8 drive_strength;
65};
66
67struct nouveau_pm_tbl_header {
68 u8 version;
69 u8 header_len;
70 u8 entry_cnt;
71 u8 entry_len;
72};
73
74struct nouveau_pm_tbl_entry {
75 u8 tWR;
76 u8 tWTR;
77 u8 tCL;
78 u8 tRC;
79 u8 empty_4;
80 u8 tRFC; /* Byte 5 */
81 u8 empty_6;
82 u8 tRAS; /* Byte 7 */
83 u8 empty_8;
84 u8 tRP; /* Byte 9 */
85 u8 tRCDRD;
86 u8 tRCDWR;
87 u8 tRRD;
88 u8 tUNK_13;
89 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
90 u8 empty_15;
91 u8 tUNK_16;
92 u8 empty_17;
93 u8 tUNK_18;
94 u8 tCWL;
95 u8 tUNK_20, tUNK_21;
96};
97
98struct nouveau_pm_profile;
99struct nouveau_pm_profile_func {
100 void (*destroy)(struct nouveau_pm_profile *);
101 void (*init)(struct nouveau_pm_profile *);
102 void (*fini)(struct nouveau_pm_profile *);
103 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
104};
105
106struct nouveau_pm_profile {
107 const struct nouveau_pm_profile_func *func;
108 struct list_head head;
109 char name[8];
110};
111
112#define NOUVEAU_PM_MAX_LEVEL 8
113struct nouveau_pm_level {
114 struct nouveau_pm_profile profile;
115 struct device_attribute dev_attr;
116 char name[32];
117 int id;
118
119 struct nouveau_pm_memtiming timing;
120 u32 memory;
121 u16 memscript;
122
123 u32 core;
124 u32 shader;
125 u32 rop;
126 u32 copy;
127 u32 daemon;
128 u32 vdec;
129 u32 dom6;
130 u32 unka0; /* nva3:nvc0 */
131 u32 hub01; /* nvc0- */
132 u32 hub06; /* nvc0- */
133 u32 hub07; /* nvc0- */
134
135 u32 volt_min; /* microvolts */
136 u32 volt_max;
137 u8 fanspeed;
138};
139
140struct nouveau_pm_temp_sensor_constants {
141 u16 offset_constant;
142 s16 offset_mult;
143 s16 offset_div;
144 s16 slope_mult;
145 s16 slope_div;
146};
147
148struct nouveau_pm_threshold_temp {
149 s16 critical;
150 s16 down_clock;
151 s16 fan_boost;
152};
153
154struct nouveau_pm_fan {
155 u32 percent;
156 u32 min_duty;
157 u32 max_duty;
158 u32 pwm_freq;
159 u32 pwm_divisor;
160};
161
162struct nouveau_pm {
163 struct drm_device *dev;
164
165 struct nouveau_pm_voltage voltage;
166 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
167 int nr_perflvl;
168 struct nouveau_pm_temp_sensor_constants sensor_constants;
169 struct nouveau_pm_threshold_temp threshold_temp;
170 struct nouveau_pm_fan fan;
171
172 struct nouveau_pm_profile *profile_ac;
173 struct nouveau_pm_profile *profile_dc;
174 struct nouveau_pm_profile *profile;
175 struct list_head profiles;
176
177 struct nouveau_pm_level boot;
178 struct nouveau_pm_level *cur;
179
180 struct device *hwmon;
181 struct notifier_block acpi_nb;
182
183 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
184 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
185 int (*clocks_set)(struct drm_device *, void *);
186
187 int (*voltage_get)(struct drm_device *);
188 int (*voltage_set)(struct drm_device *, int voltage);
189 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
190 int (*pwm_set)(struct drm_device *, int line, u32, u32);
191 int (*temp_get)(struct drm_device *);
192};
193
194static inline struct nouveau_pm *
195nouveau_pm(struct drm_device *dev)
196{
197 return nouveau_drm(dev)->pm;
198}
199
Ben Skeggs2d85bc82012-01-23 13:12:09 +1000[diff] [blame]200struct nouveau_mem_exec_func {
201 struct drm_device *dev;
202 void (*precharge)(struct nouveau_mem_exec_func *);
203 void (*refresh)(struct nouveau_mem_exec_func *);
204 void (*refresh_auto)(struct nouveau_mem_exec_func *, bool);
205 void (*refresh_self)(struct nouveau_mem_exec_func *, bool);
206 void (*wait)(struct nouveau_mem_exec_func *, u32 nsec);
207 u32 (*mrg)(struct nouveau_mem_exec_func *, int mr);
208 void (*mrs)(struct nouveau_mem_exec_func *, int mr, u32 data);
209 void (*clock_set)(struct nouveau_mem_exec_func *);
210 void (*timing_set)(struct nouveau_mem_exec_func *);
211 void *priv;
212};
213
214/* nouveau_mem.c */
215int nouveau_mem_exec(struct nouveau_mem_exec_func *,
216 struct nouveau_pm_level *);
217
Ben Skeggs330c5982010-09-16 15:39:49 +1000[diff] [blame]218/* nouveau_pm.c */
219int nouveau_pm_init(struct drm_device *dev);
220void nouveau_pm_fini(struct drm_device *dev);
Ben Skeggs64f1c112010-09-17 13:35:25 +1000[diff] [blame]221void nouveau_pm_resume(struct drm_device *dev);
Ben Skeggs8d7bb402012-01-24 15:59:07 +1000[diff] [blame]222extern const struct nouveau_pm_profile_func nouveau_pm_static_profile_func;
223void nouveau_pm_trigger(struct drm_device *dev);
Ben Skeggs330c5982010-09-16 15:39:49 +1000[diff] [blame]224
225/* nouveau_volt.c */
226void nouveau_volt_init(struct drm_device *);
227void nouveau_volt_fini(struct drm_device *);
228int nouveau_volt_vid_lookup(struct drm_device *, int voltage);
229int nouveau_volt_lvl_lookup(struct drm_device *, int vid);
230int nouveau_voltage_gpio_get(struct drm_device *);
231int nouveau_voltage_gpio_set(struct drm_device *, int voltage);
232
233/* nouveau_perf.c */
234void nouveau_perf_init(struct drm_device *);
235void nouveau_perf_fini(struct drm_device *);
Ben Skeggs27740382012-01-27 10:53:17 +1000[diff] [blame]236u8 *nouveau_perf_rammap(struct drm_device *, u32 freq, u8 *ver,
237 u8 *hdr, u8 *cnt, u8 *len);
Ben Skeggsa9bc2472012-01-24 11:26:40 +1000[diff] [blame]238u8 *nouveau_perf_ramcfg(struct drm_device *, u32 freq, u8 *ver, u8 *len);
Ben Skeggs27740382012-01-27 10:53:17 +1000[diff] [blame]239u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
Ben Skeggs330c5982010-09-16 15:39:49 +1000[diff] [blame]240
Roy Spliet7760fcb2010-09-17 23:17:24 +0200[diff] [blame]241/* nouveau_mem.c */
242void nouveau_mem_timing_init(struct drm_device *);
243void nouveau_mem_timing_fini(struct drm_device *);
244
Ben Skeggs442b6262010-09-16 16:25:26 +1000[diff] [blame]245/* nv04_pm.c */
Ben Skeggs36f13172011-10-27 10:24:12 +1000[diff] [blame]246int nv04_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
247void *nv04_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
248int nv04_pm_clocks_set(struct drm_device *, void *);
Ben Skeggs442b6262010-09-16 16:25:26 +1000[diff] [blame]249
Ben Skeggs1262a202011-07-18 15:15:34 +1000[diff] [blame]250/* nv40_pm.c */
251int nv40_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
252void *nv40_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
Martin Peresdd1da8d2011-07-10 00:08:41 +0200[diff] [blame]253int nv40_pm_clocks_set(struct drm_device *, void *);
Ben Skeggs675aac02011-11-21 21:28:28 +1000[diff] [blame]254int nv40_pm_pwm_get(struct drm_device *, int, u32 *, u32 *);
255int nv40_pm_pwm_set(struct drm_device *, int, u32, u32);
Ben Skeggs1262a202011-07-18 15:15:34 +1000[diff] [blame]256
Ben Skeggs02c30ca2010-09-16 16:17:35 +1000[diff] [blame]257/* nv50_pm.c */
Ben Skeggsf3fbaf32011-10-26 09:11:02 +1000[diff] [blame]258int nv50_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
259void *nv50_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
260int nv50_pm_clocks_set(struct drm_device *, void *);
Ben Skeggs675aac02011-11-21 21:28:28 +1000[diff] [blame]261int nv50_pm_pwm_get(struct drm_device *, int, u32 *, u32 *);
262int nv50_pm_pwm_set(struct drm_device *, int, u32, u32);
Ben Skeggs02c30ca2010-09-16 16:17:35 +1000[diff] [blame]263
Ben Skeggsfade7ad2010-09-27 11:18:14 +1000[diff] [blame]264/* nva3_pm.c */
Ben Skeggsca94a712011-06-17 15:38:48 +1000[diff] [blame]265int nva3_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
266void *nva3_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
Martin Peresdd1da8d2011-07-10 00:08:41 +0200[diff] [blame]267int nva3_pm_clocks_set(struct drm_device *, void *);
Ben Skeggsfade7ad2010-09-27 11:18:14 +1000[diff] [blame]268
Ben Skeggs354d0782011-06-19 01:44:36 +1000[diff] [blame]269/* nvc0_pm.c */
270int nvc0_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
Ben Skeggs045da4e2011-10-29 00:22:49 +1000[diff] [blame]271void *nvc0_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
272int nvc0_pm_clocks_set(struct drm_device *, void *);
Ben Skeggs354d0782011-06-19 01:44:36 +1000[diff] [blame]273
Martin Peres34e9d852010-09-22 20:54:22 +0200[diff] [blame]274/* nouveau_temp.c */
275void nouveau_temp_init(struct drm_device *dev);
276void nouveau_temp_fini(struct drm_device *dev);
277void nouveau_temp_safety_checks(struct drm_device *dev);
Francisco Jerez8155cac2010-09-23 20:58:38 +0200[diff] [blame]278int nv40_temp_get(struct drm_device *dev);
279int nv84_temp_get(struct drm_device *dev);
Martin Peres34e9d852010-09-22 20:54:22 +0200[diff] [blame]280
Ben Skeggs77145f12012-07-31 16:16:21 +1000[diff] [blame]281/* nouveau_mem.c */
282int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
283 struct nouveau_pm_memtiming *);
284void nouveau_mem_timing_read(struct drm_device *,
285 struct nouveau_pm_memtiming *);
286
287static inline int
288nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *pll, u32 freq,
289 int *N, int *fN, int *M, int *P)
290{
291 struct nouveau_device *device = nouveau_dev(dev);
292 struct nouveau_clock *clk = nouveau_clock(device);
293 struct nouveau_pll_vals pv;
294 int ret;
295
296 ret = clk->pll_calc(clk, pll, freq, &pv);
297 *N = pv.N1;
298 *M = pv.M1;
299 *P = pv.log2P;
300 return ret;
301}
302
Ben Skeggs330c5982010-09-16 15:39:49 +1000[diff] [blame]303#endif